1 /* 2 * vfio based device assignment support - PCI devices 3 * 4 * Copyright Red Hat, Inc. 2012-2015 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 */ 12 #ifndef HW_VFIO_VFIO_PCI_H 13 #define HW_VFIO_VFIO_PCI_H 14 15 #include "system/memory.h" 16 #include "hw/pci/pci_device.h" 17 #include "hw/vfio/types.h" 18 #include "hw/vfio/vfio-device.h" 19 #include "hw/vfio/vfio-region.h" 20 #include "qemu/event_notifier.h" 21 #include "qemu/queue.h" 22 #include "qemu/timer.h" 23 #include "qom/object.h" 24 #include "system/kvm.h" 25 #include "vfio-display.h" 26 27 #define PCI_ANY_ID (~0) 28 29 struct VFIOPCIDevice; 30 31 typedef struct VFIOIOEventFD { 32 QLIST_ENTRY(VFIOIOEventFD) next; 33 MemoryRegion *mr; 34 hwaddr addr; 35 unsigned size; 36 uint64_t data; 37 EventNotifier e; 38 VFIORegion *region; 39 hwaddr region_addr; 40 bool dynamic; /* Added runtime, removed on device reset */ 41 bool vfio; 42 } VFIOIOEventFD; 43 44 typedef struct VFIOQuirk { 45 QLIST_ENTRY(VFIOQuirk) next; 46 void *data; 47 QLIST_HEAD(, VFIOIOEventFD) ioeventfds; 48 int nr_mem; 49 MemoryRegion *mem; 50 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk); 51 } VFIOQuirk; 52 53 typedef struct VFIOBAR { 54 VFIORegion region; 55 MemoryRegion *mr; 56 size_t size; 57 uint8_t type; 58 bool ioport; 59 bool mem64; 60 QLIST_HEAD(, VFIOQuirk) quirks; 61 } VFIOBAR; 62 63 typedef struct VFIOVGARegion { 64 MemoryRegion mem; 65 off_t offset; 66 int nr; 67 QLIST_HEAD(, VFIOQuirk) quirks; 68 } VFIOVGARegion; 69 70 typedef struct VFIOVGA { 71 off_t fd_offset; 72 int fd; 73 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS]; 74 } VFIOVGA; 75 76 typedef struct VFIOINTx { 77 bool pending; /* interrupt pending */ 78 bool kvm_accel; /* set when QEMU bypass through KVM enabled */ 79 uint8_t pin; /* which pin to pull for qemu_set_irq */ 80 EventNotifier interrupt; /* eventfd triggered on interrupt */ 81 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */ 82 PCIINTxRoute route; /* routing info for QEMU bypass */ 83 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */ 84 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */ 85 } VFIOINTx; 86 87 typedef struct VFIOMSIVector { 88 /* 89 * Two interrupt paths are configured per vector. The first, is only used 90 * for interrupts injected via QEMU. This is typically the non-accel path, 91 * but may also be used when we want QEMU to handle masking and pending 92 * bits. The KVM path bypasses QEMU and is therefore higher performance, 93 * but requires masking at the device. virq is used to track the MSI route 94 * through KVM, thus kvm_interrupt is only available when virq is set to a 95 * valid (>= 0) value. 96 */ 97 EventNotifier interrupt; 98 EventNotifier kvm_interrupt; 99 struct VFIOPCIDevice *vdev; /* back pointer to device */ 100 int virq; 101 bool use; 102 } VFIOMSIVector; 103 104 enum { 105 VFIO_INT_NONE = 0, 106 VFIO_INT_INTx = 1, 107 VFIO_INT_MSI = 2, 108 VFIO_INT_MSIX = 3, 109 }; 110 111 /* Cache of MSI-X setup */ 112 typedef struct VFIOMSIXInfo { 113 uint8_t table_bar; 114 uint8_t pba_bar; 115 uint16_t entries; 116 uint32_t table_offset; 117 uint32_t pba_offset; 118 unsigned long *pending; 119 bool noresize; 120 MemoryRegion *pba_region; 121 } VFIOMSIXInfo; 122 123 OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI_BASE) 124 125 struct VFIOPCIDevice { 126 PCIDevice pdev; 127 VFIODevice vbasedev; 128 VFIOINTx intx; 129 unsigned int config_size; 130 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */ 131 off_t config_offset; /* Offset of config space region within device fd */ 132 unsigned int rom_size; 133 off_t rom_offset; /* Offset of ROM region within device fd */ 134 void *rom; 135 int msi_cap_size; 136 VFIOMSIVector *msi_vectors; 137 VFIOMSIXInfo *msix; 138 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */ 139 int interrupt; /* Current interrupt type */ 140 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */ 141 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */ 142 void *igd_opregion; 143 PCIHostDeviceAddress host; 144 QemuUUID vf_token; 145 EventNotifier err_notifier; 146 EventNotifier req_notifier; 147 int (*resetfn)(struct VFIOPCIDevice *); 148 uint32_t vendor_id; 149 uint32_t device_id; 150 uint32_t sub_vendor_id; 151 uint32_t sub_device_id; 152 uint32_t class_code; 153 uint32_t features; 154 #define VFIO_FEATURE_ENABLE_VGA_BIT 0 155 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT) 156 #define VFIO_FEATURE_ENABLE_REQ_BIT 1 157 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT) 158 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2 159 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \ 160 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT) 161 #define VFIO_FEATURE_ENABLE_IGD_LPC_BIT 3 162 #define VFIO_FEATURE_ENABLE_IGD_LPC \ 163 (1 << VFIO_FEATURE_ENABLE_IGD_LPC_BIT) 164 OnOffAuto display; 165 uint32_t display_xres; 166 uint32_t display_yres; 167 int32_t bootindex; 168 OnOffAuto igd_legacy_mode; 169 uint32_t igd_gms; 170 OffAutoPCIBAR msix_relo; 171 uint8_t nv_gpudirect_clique; 172 bool pci_aer; 173 bool req_enabled; 174 bool has_flr; 175 bool has_pm_reset; 176 bool rom_read_failed; 177 bool no_kvm_intx; 178 bool no_kvm_msi; 179 bool no_kvm_msix; 180 bool no_geforce_quirks; 181 bool no_kvm_ioeventfd; 182 bool no_vfio_ioeventfd; 183 bool enable_ramfb; 184 bool use_legacy_x86_rom; 185 OnOffAuto ramfb_migrate; 186 bool defer_kvm_irq_routing; 187 bool clear_parent_atomics_on_exit; 188 bool skip_vsc_check; 189 VFIODisplay *dpy; 190 Notifier irqchip_change_notifier; 191 VFIOPCICPR cpr; 192 }; 193 194 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */ 195 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device) 196 { 197 return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) && 198 (device == PCI_ANY_ID || device == vdev->device_id); 199 } 200 201 static inline bool vfio_is_vga(VFIOPCIDevice *vdev) 202 { 203 return (vdev->class_code >> 8) == PCI_CLASS_DISPLAY_VGA; 204 } 205 206 /* MSI/MSI-X/INTx */ 207 void vfio_pci_vector_init(VFIOPCIDevice *vdev, int nr); 208 void vfio_pci_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, 209 int vector_n, bool msix); 210 void vfio_pci_prepare_kvm_msi_virq_batch(VFIOPCIDevice *vdev); 211 void vfio_pci_commit_kvm_msi_virq_batch(VFIOPCIDevice *vdev); 212 bool vfio_pci_intx_enable(VFIOPCIDevice *vdev, Error **errp); 213 void vfio_pci_intx_set_handler(VFIOPCIDevice *vdev, bool enable); 214 void vfio_pci_msix_set_notifiers(VFIOPCIDevice *vdev); 215 void vfio_pci_msi_set_handler(VFIOPCIDevice *vdev, int nr, bool enable); 216 217 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len); 218 void vfio_pci_write_config(PCIDevice *pdev, 219 uint32_t addr, uint32_t val, int len); 220 221 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size); 222 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size); 223 224 void vfio_sub_page_bar_update_mappings(VFIOPCIDevice *vdev); 225 bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev); 226 bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp); 227 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev); 228 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev); 229 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev); 230 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr); 231 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr); 232 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr); 233 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev); 234 bool vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp); 235 void vfio_quirk_reset(VFIOPCIDevice *vdev); 236 VFIOQuirk *vfio_quirk_alloc(int nr_mem); 237 void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr); 238 bool vfio_probe_igd_config_quirk(VFIOPCIDevice *vdev, Error **errp); 239 240 extern const PropertyInfo qdev_prop_nv_gpudirect_clique; 241 242 void vfio_pci_pre_reset(VFIOPCIDevice *vdev); 243 void vfio_pci_post_reset(VFIOPCIDevice *vdev); 244 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name); 245 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev, 246 struct vfio_pci_hot_reset_info **info_p); 247 248 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp); 249 250 void vfio_display_reset(VFIOPCIDevice *vdev); 251 bool vfio_display_probe(VFIOPCIDevice *vdev, Error **errp); 252 void vfio_display_finalize(VFIOPCIDevice *vdev); 253 254 extern const VMStateDescription vfio_display_vmstate; 255 256 void vfio_pci_bars_exit(VFIOPCIDevice *vdev); 257 bool vfio_pci_add_capabilities(VFIOPCIDevice *vdev, Error **errp); 258 void vfio_pci_config_register_vga(VFIOPCIDevice *vdev); 259 bool vfio_pci_config_setup(VFIOPCIDevice *vdev, Error **errp); 260 bool vfio_pci_interrupt_setup(VFIOPCIDevice *vdev, Error **errp); 261 void vfio_pci_intx_eoi(VFIODevice *vbasedev); 262 void vfio_pci_put_device(VFIOPCIDevice *vdev); 263 bool vfio_pci_populate_device(VFIOPCIDevice *vdev, Error **errp); 264 void vfio_pci_register_err_notifier(VFIOPCIDevice *vdev); 265 void vfio_pci_register_req_notifier(VFIOPCIDevice *vdev); 266 void vfio_pci_teardown_msi(VFIOPCIDevice *vdev); 267 268 #endif /* HW_VFIO_VFIO_PCI_H */ 269