1 /* 2 * vfio based device assignment support 3 * 4 * Copyright Red Hat, Inc. 2012 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 * 12 * Based on qemu-kvm device-assignment: 13 * Adapted for KVM by Qumranet. 14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) 15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) 16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) 17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) 18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) 19 */ 20 21 #include "qemu/osdep.h" 22 #include <linux/vfio.h> 23 #include <sys/ioctl.h> 24 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "qemu/error-report.h" 29 #include "qemu/range.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/sysemu.h" 32 #include "pci.h" 33 #include "trace.h" 34 #include "qapi/error.h" 35 36 #define MSIX_CAP_LENGTH 12 37 38 static void vfio_disable_interrupts(VFIOPCIDevice *vdev); 39 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); 40 41 /* 42 * Disabling BAR mmaping can be slow, but toggling it around INTx can 43 * also be a huge overhead. We try to get the best of both worlds by 44 * waiting until an interrupt to disable mmaps (subsequent transitions 45 * to the same state are effectively no overhead). If the interrupt has 46 * been serviced and the time gap is long enough, we re-enable mmaps for 47 * performance. This works well for things like graphics cards, which 48 * may not use their interrupt at all and are penalized to an unusable 49 * level by read/write BAR traps. Other devices, like NICs, have more 50 * regular interrupts and see much better latency by staying in non-mmap 51 * mode. We therefore set the default mmap_timeout such that a ping 52 * is just enough to keep the mmap disabled. Users can experiment with 53 * other options with the x-intx-mmap-timeout-ms parameter (a value of 54 * zero disables the timer). 55 */ 56 static void vfio_intx_mmap_enable(void *opaque) 57 { 58 VFIOPCIDevice *vdev = opaque; 59 60 if (vdev->intx.pending) { 61 timer_mod(vdev->intx.mmap_timer, 62 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 63 return; 64 } 65 66 vfio_mmap_set_enabled(vdev, true); 67 } 68 69 static void vfio_intx_interrupt(void *opaque) 70 { 71 VFIOPCIDevice *vdev = opaque; 72 73 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { 74 return; 75 } 76 77 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); 78 79 vdev->intx.pending = true; 80 pci_irq_assert(&vdev->pdev); 81 vfio_mmap_set_enabled(vdev, false); 82 if (vdev->intx.mmap_timeout) { 83 timer_mod(vdev->intx.mmap_timer, 84 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 85 } 86 } 87 88 static void vfio_intx_eoi(VFIODevice *vbasedev) 89 { 90 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 91 92 if (!vdev->intx.pending) { 93 return; 94 } 95 96 trace_vfio_intx_eoi(vbasedev->name); 97 98 vdev->intx.pending = false; 99 pci_irq_deassert(&vdev->pdev); 100 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 101 } 102 103 static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp) 104 { 105 #ifdef CONFIG_KVM 106 struct kvm_irqfd irqfd = { 107 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 108 .gsi = vdev->intx.route.irq, 109 .flags = KVM_IRQFD_FLAG_RESAMPLE, 110 }; 111 struct vfio_irq_set *irq_set; 112 int ret, argsz; 113 int32_t *pfd; 114 115 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || 116 vdev->intx.route.mode != PCI_INTX_ENABLED || 117 !kvm_resamplefds_enabled()) { 118 return; 119 } 120 121 /* Get to a known interrupt state */ 122 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); 123 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 124 vdev->intx.pending = false; 125 pci_irq_deassert(&vdev->pdev); 126 127 /* Get an eventfd for resample/unmask */ 128 if (event_notifier_init(&vdev->intx.unmask, 0)) { 129 error_setg(errp, "event_notifier_init failed eoi"); 130 goto fail; 131 } 132 133 /* KVM triggers it, VFIO listens for it */ 134 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); 135 136 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 137 error_setg_errno(errp, errno, "failed to setup resample irqfd"); 138 goto fail_irqfd; 139 } 140 141 argsz = sizeof(*irq_set) + sizeof(*pfd); 142 143 irq_set = g_malloc0(argsz); 144 irq_set->argsz = argsz; 145 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; 146 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 147 irq_set->start = 0; 148 irq_set->count = 1; 149 pfd = (int32_t *)&irq_set->data; 150 151 *pfd = irqfd.resamplefd; 152 153 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 154 g_free(irq_set); 155 if (ret) { 156 error_setg_errno(errp, -ret, "failed to setup INTx unmask fd"); 157 goto fail_vfio; 158 } 159 160 /* Let'em rip */ 161 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 162 163 vdev->intx.kvm_accel = true; 164 165 trace_vfio_intx_enable_kvm(vdev->vbasedev.name); 166 167 return; 168 169 fail_vfio: 170 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; 171 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); 172 fail_irqfd: 173 event_notifier_cleanup(&vdev->intx.unmask); 174 fail: 175 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 176 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 177 #endif 178 } 179 180 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) 181 { 182 #ifdef CONFIG_KVM 183 struct kvm_irqfd irqfd = { 184 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 185 .gsi = vdev->intx.route.irq, 186 .flags = KVM_IRQFD_FLAG_DEASSIGN, 187 }; 188 189 if (!vdev->intx.kvm_accel) { 190 return; 191 } 192 193 /* 194 * Get to a known state, hardware masked, QEMU ready to accept new 195 * interrupts, QEMU IRQ de-asserted. 196 */ 197 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 198 vdev->intx.pending = false; 199 pci_irq_deassert(&vdev->pdev); 200 201 /* Tell KVM to stop listening for an INTx irqfd */ 202 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 203 error_report("vfio: Error: Failed to disable INTx irqfd: %m"); 204 } 205 206 /* We only need to close the eventfd for VFIO to cleanup the kernel side */ 207 event_notifier_cleanup(&vdev->intx.unmask); 208 209 /* QEMU starts listening for interrupt events. */ 210 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 211 212 vdev->intx.kvm_accel = false; 213 214 /* If we've missed an event, let it re-fire through QEMU */ 215 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 216 217 trace_vfio_intx_disable_kvm(vdev->vbasedev.name); 218 #endif 219 } 220 221 static void vfio_intx_update(PCIDevice *pdev) 222 { 223 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 224 PCIINTxRoute route; 225 Error *err = NULL; 226 227 if (vdev->interrupt != VFIO_INT_INTx) { 228 return; 229 } 230 231 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); 232 233 if (!pci_intx_route_changed(&vdev->intx.route, &route)) { 234 return; /* Nothing changed */ 235 } 236 237 trace_vfio_intx_update(vdev->vbasedev.name, 238 vdev->intx.route.irq, route.irq); 239 240 vfio_intx_disable_kvm(vdev); 241 242 vdev->intx.route = route; 243 244 if (route.mode != PCI_INTX_ENABLED) { 245 return; 246 } 247 248 vfio_intx_enable_kvm(vdev, &err); 249 if (err) { 250 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); 251 } 252 253 /* Re-enable the interrupt in cased we missed an EOI */ 254 vfio_intx_eoi(&vdev->vbasedev); 255 } 256 257 static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp) 258 { 259 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); 260 int ret, argsz; 261 struct vfio_irq_set *irq_set; 262 int32_t *pfd; 263 Error *err = NULL; 264 265 if (!pin) { 266 return 0; 267 } 268 269 vfio_disable_interrupts(vdev); 270 271 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ 272 pci_config_set_interrupt_pin(vdev->pdev.config, pin); 273 274 #ifdef CONFIG_KVM 275 /* 276 * Only conditional to avoid generating error messages on platforms 277 * where we won't actually use the result anyway. 278 */ 279 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { 280 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, 281 vdev->intx.pin); 282 } 283 #endif 284 285 ret = event_notifier_init(&vdev->intx.interrupt, 0); 286 if (ret) { 287 error_setg_errno(errp, -ret, "event_notifier_init failed"); 288 return ret; 289 } 290 291 argsz = sizeof(*irq_set) + sizeof(*pfd); 292 293 irq_set = g_malloc0(argsz); 294 irq_set->argsz = argsz; 295 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 296 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 297 irq_set->start = 0; 298 irq_set->count = 1; 299 pfd = (int32_t *)&irq_set->data; 300 301 *pfd = event_notifier_get_fd(&vdev->intx.interrupt); 302 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); 303 304 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 305 g_free(irq_set); 306 if (ret) { 307 error_setg_errno(errp, -ret, "failed to setup INTx fd"); 308 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 309 event_notifier_cleanup(&vdev->intx.interrupt); 310 return -errno; 311 } 312 313 vfio_intx_enable_kvm(vdev, &err); 314 if (err) { 315 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); 316 } 317 318 vdev->interrupt = VFIO_INT_INTx; 319 320 trace_vfio_intx_enable(vdev->vbasedev.name); 321 322 return 0; 323 } 324 325 static void vfio_intx_disable(VFIOPCIDevice *vdev) 326 { 327 int fd; 328 329 timer_del(vdev->intx.mmap_timer); 330 vfio_intx_disable_kvm(vdev); 331 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 332 vdev->intx.pending = false; 333 pci_irq_deassert(&vdev->pdev); 334 vfio_mmap_set_enabled(vdev, true); 335 336 fd = event_notifier_get_fd(&vdev->intx.interrupt); 337 qemu_set_fd_handler(fd, NULL, NULL, vdev); 338 event_notifier_cleanup(&vdev->intx.interrupt); 339 340 vdev->interrupt = VFIO_INT_NONE; 341 342 trace_vfio_intx_disable(vdev->vbasedev.name); 343 } 344 345 /* 346 * MSI/X 347 */ 348 static void vfio_msi_interrupt(void *opaque) 349 { 350 VFIOMSIVector *vector = opaque; 351 VFIOPCIDevice *vdev = vector->vdev; 352 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); 353 void (*notify)(PCIDevice *dev, unsigned vector); 354 MSIMessage msg; 355 int nr = vector - vdev->msi_vectors; 356 357 if (!event_notifier_test_and_clear(&vector->interrupt)) { 358 return; 359 } 360 361 if (vdev->interrupt == VFIO_INT_MSIX) { 362 get_msg = msix_get_message; 363 notify = msix_notify; 364 365 /* A masked vector firing needs to use the PBA, enable it */ 366 if (msix_is_masked(&vdev->pdev, nr)) { 367 set_bit(nr, vdev->msix->pending); 368 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); 369 trace_vfio_msix_pba_enable(vdev->vbasedev.name); 370 } 371 } else if (vdev->interrupt == VFIO_INT_MSI) { 372 get_msg = msi_get_message; 373 notify = msi_notify; 374 } else { 375 abort(); 376 } 377 378 msg = get_msg(&vdev->pdev, nr); 379 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); 380 notify(&vdev->pdev, nr); 381 } 382 383 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) 384 { 385 struct vfio_irq_set *irq_set; 386 int ret = 0, i, argsz; 387 int32_t *fds; 388 389 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); 390 391 irq_set = g_malloc0(argsz); 392 irq_set->argsz = argsz; 393 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 394 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; 395 irq_set->start = 0; 396 irq_set->count = vdev->nr_vectors; 397 fds = (int32_t *)&irq_set->data; 398 399 for (i = 0; i < vdev->nr_vectors; i++) { 400 int fd = -1; 401 402 /* 403 * MSI vs MSI-X - The guest has direct access to MSI mask and pending 404 * bits, therefore we always use the KVM signaling path when setup. 405 * MSI-X mask and pending bits are emulated, so we want to use the 406 * KVM signaling path only when configured and unmasked. 407 */ 408 if (vdev->msi_vectors[i].use) { 409 if (vdev->msi_vectors[i].virq < 0 || 410 (msix && msix_is_masked(&vdev->pdev, i))) { 411 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); 412 } else { 413 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); 414 } 415 } 416 417 fds[i] = fd; 418 } 419 420 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 421 422 g_free(irq_set); 423 424 return ret; 425 } 426 427 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, 428 int vector_n, bool msix) 429 { 430 int virq; 431 432 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { 433 return; 434 } 435 436 if (event_notifier_init(&vector->kvm_interrupt, 0)) { 437 return; 438 } 439 440 virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); 441 if (virq < 0) { 442 event_notifier_cleanup(&vector->kvm_interrupt); 443 return; 444 } 445 446 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 447 NULL, virq) < 0) { 448 kvm_irqchip_release_virq(kvm_state, virq); 449 event_notifier_cleanup(&vector->kvm_interrupt); 450 return; 451 } 452 453 vector->virq = virq; 454 } 455 456 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) 457 { 458 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 459 vector->virq); 460 kvm_irqchip_release_virq(kvm_state, vector->virq); 461 vector->virq = -1; 462 event_notifier_cleanup(&vector->kvm_interrupt); 463 } 464 465 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, 466 PCIDevice *pdev) 467 { 468 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); 469 kvm_irqchip_commit_routes(kvm_state); 470 } 471 472 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, 473 MSIMessage *msg, IOHandler *handler) 474 { 475 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 476 VFIOMSIVector *vector; 477 int ret; 478 479 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); 480 481 vector = &vdev->msi_vectors[nr]; 482 483 if (!vector->use) { 484 vector->vdev = vdev; 485 vector->virq = -1; 486 if (event_notifier_init(&vector->interrupt, 0)) { 487 error_report("vfio: Error: event_notifier_init failed"); 488 } 489 vector->use = true; 490 msix_vector_use(pdev, nr); 491 } 492 493 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 494 handler, NULL, vector); 495 496 /* 497 * Attempt to enable route through KVM irqchip, 498 * default to userspace handling if unavailable. 499 */ 500 if (vector->virq >= 0) { 501 if (!msg) { 502 vfio_remove_kvm_msi_virq(vector); 503 } else { 504 vfio_update_kvm_msi_virq(vector, *msg, pdev); 505 } 506 } else { 507 if (msg) { 508 vfio_add_kvm_msi_virq(vdev, vector, nr, true); 509 } 510 } 511 512 /* 513 * We don't want to have the host allocate all possible MSI vectors 514 * for a device if they're not in use, so we shutdown and incrementally 515 * increase them as needed. 516 */ 517 if (vdev->nr_vectors < nr + 1) { 518 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 519 vdev->nr_vectors = nr + 1; 520 ret = vfio_enable_vectors(vdev, true); 521 if (ret) { 522 error_report("vfio: failed to enable vectors, %d", ret); 523 } 524 } else { 525 int argsz; 526 struct vfio_irq_set *irq_set; 527 int32_t *pfd; 528 529 argsz = sizeof(*irq_set) + sizeof(*pfd); 530 531 irq_set = g_malloc0(argsz); 532 irq_set->argsz = argsz; 533 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 534 VFIO_IRQ_SET_ACTION_TRIGGER; 535 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 536 irq_set->start = nr; 537 irq_set->count = 1; 538 pfd = (int32_t *)&irq_set->data; 539 540 if (vector->virq >= 0) { 541 *pfd = event_notifier_get_fd(&vector->kvm_interrupt); 542 } else { 543 *pfd = event_notifier_get_fd(&vector->interrupt); 544 } 545 546 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 547 g_free(irq_set); 548 if (ret) { 549 error_report("vfio: failed to modify vector, %d", ret); 550 } 551 } 552 553 /* Disable PBA emulation when nothing more is pending. */ 554 clear_bit(nr, vdev->msix->pending); 555 if (find_first_bit(vdev->msix->pending, 556 vdev->nr_vectors) == vdev->nr_vectors) { 557 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 558 trace_vfio_msix_pba_disable(vdev->vbasedev.name); 559 } 560 561 return 0; 562 } 563 564 static int vfio_msix_vector_use(PCIDevice *pdev, 565 unsigned int nr, MSIMessage msg) 566 { 567 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); 568 } 569 570 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) 571 { 572 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 573 VFIOMSIVector *vector = &vdev->msi_vectors[nr]; 574 575 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); 576 577 /* 578 * There are still old guests that mask and unmask vectors on every 579 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of 580 * the KVM setup in place, simply switch VFIO to use the non-bypass 581 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X 582 * core will mask the interrupt and set pending bits, allowing it to 583 * be re-asserted on unmask. Nothing to do if already using QEMU mode. 584 */ 585 if (vector->virq >= 0) { 586 int argsz; 587 struct vfio_irq_set *irq_set; 588 int32_t *pfd; 589 590 argsz = sizeof(*irq_set) + sizeof(*pfd); 591 592 irq_set = g_malloc0(argsz); 593 irq_set->argsz = argsz; 594 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 595 VFIO_IRQ_SET_ACTION_TRIGGER; 596 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 597 irq_set->start = nr; 598 irq_set->count = 1; 599 pfd = (int32_t *)&irq_set->data; 600 601 *pfd = event_notifier_get_fd(&vector->interrupt); 602 603 ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 604 605 g_free(irq_set); 606 } 607 } 608 609 static void vfio_msix_enable(VFIOPCIDevice *vdev) 610 { 611 vfio_disable_interrupts(vdev); 612 613 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); 614 615 vdev->interrupt = VFIO_INT_MSIX; 616 617 /* 618 * Some communication channels between VF & PF or PF & fw rely on the 619 * physical state of the device and expect that enabling MSI-X from the 620 * guest enables the same on the host. When our guest is Linux, the 621 * guest driver call to pci_enable_msix() sets the enabling bit in the 622 * MSI-X capability, but leaves the vector table masked. We therefore 623 * can't rely on a vector_use callback (from request_irq() in the guest) 624 * to switch the physical device into MSI-X mode because that may come a 625 * long time after pci_enable_msix(). This code enables vector 0 with 626 * triggering to userspace, then immediately release the vector, leaving 627 * the physical device with no vectors enabled, but MSI-X enabled, just 628 * like the guest view. 629 */ 630 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); 631 vfio_msix_vector_release(&vdev->pdev, 0); 632 633 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, 634 vfio_msix_vector_release, NULL)) { 635 error_report("vfio: msix_set_vector_notifiers failed"); 636 } 637 638 trace_vfio_msix_enable(vdev->vbasedev.name); 639 } 640 641 static void vfio_msi_enable(VFIOPCIDevice *vdev) 642 { 643 int ret, i; 644 645 vfio_disable_interrupts(vdev); 646 647 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); 648 retry: 649 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); 650 651 for (i = 0; i < vdev->nr_vectors; i++) { 652 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 653 654 vector->vdev = vdev; 655 vector->virq = -1; 656 vector->use = true; 657 658 if (event_notifier_init(&vector->interrupt, 0)) { 659 error_report("vfio: Error: event_notifier_init failed"); 660 } 661 662 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 663 vfio_msi_interrupt, NULL, vector); 664 665 /* 666 * Attempt to enable route through KVM irqchip, 667 * default to userspace handling if unavailable. 668 */ 669 vfio_add_kvm_msi_virq(vdev, vector, i, false); 670 } 671 672 /* Set interrupt type prior to possible interrupts */ 673 vdev->interrupt = VFIO_INT_MSI; 674 675 ret = vfio_enable_vectors(vdev, false); 676 if (ret) { 677 if (ret < 0) { 678 error_report("vfio: Error: Failed to setup MSI fds: %m"); 679 } else if (ret != vdev->nr_vectors) { 680 error_report("vfio: Error: Failed to enable %d " 681 "MSI vectors, retry with %d", vdev->nr_vectors, ret); 682 } 683 684 for (i = 0; i < vdev->nr_vectors; i++) { 685 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 686 if (vector->virq >= 0) { 687 vfio_remove_kvm_msi_virq(vector); 688 } 689 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 690 NULL, NULL, NULL); 691 event_notifier_cleanup(&vector->interrupt); 692 } 693 694 g_free(vdev->msi_vectors); 695 696 if (ret > 0 && ret != vdev->nr_vectors) { 697 vdev->nr_vectors = ret; 698 goto retry; 699 } 700 vdev->nr_vectors = 0; 701 702 /* 703 * Failing to setup MSI doesn't really fall within any specification. 704 * Let's try leaving interrupts disabled and hope the guest figures 705 * out to fall back to INTx for this device. 706 */ 707 error_report("vfio: Error: Failed to enable MSI"); 708 vdev->interrupt = VFIO_INT_NONE; 709 710 return; 711 } 712 713 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); 714 } 715 716 static void vfio_msi_disable_common(VFIOPCIDevice *vdev) 717 { 718 Error *err = NULL; 719 int i; 720 721 for (i = 0; i < vdev->nr_vectors; i++) { 722 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 723 if (vdev->msi_vectors[i].use) { 724 if (vector->virq >= 0) { 725 vfio_remove_kvm_msi_virq(vector); 726 } 727 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 728 NULL, NULL, NULL); 729 event_notifier_cleanup(&vector->interrupt); 730 } 731 } 732 733 g_free(vdev->msi_vectors); 734 vdev->msi_vectors = NULL; 735 vdev->nr_vectors = 0; 736 vdev->interrupt = VFIO_INT_NONE; 737 738 vfio_intx_enable(vdev, &err); 739 if (err) { 740 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); 741 } 742 } 743 744 static void vfio_msix_disable(VFIOPCIDevice *vdev) 745 { 746 int i; 747 748 msix_unset_vector_notifiers(&vdev->pdev); 749 750 /* 751 * MSI-X will only release vectors if MSI-X is still enabled on the 752 * device, check through the rest and release it ourselves if necessary. 753 */ 754 for (i = 0; i < vdev->nr_vectors; i++) { 755 if (vdev->msi_vectors[i].use) { 756 vfio_msix_vector_release(&vdev->pdev, i); 757 msix_vector_unuse(&vdev->pdev, i); 758 } 759 } 760 761 if (vdev->nr_vectors) { 762 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 763 } 764 765 vfio_msi_disable_common(vdev); 766 767 memset(vdev->msix->pending, 0, 768 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); 769 770 trace_vfio_msix_disable(vdev->vbasedev.name); 771 } 772 773 static void vfio_msi_disable(VFIOPCIDevice *vdev) 774 { 775 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); 776 vfio_msi_disable_common(vdev); 777 778 trace_vfio_msi_disable(vdev->vbasedev.name); 779 } 780 781 static void vfio_update_msi(VFIOPCIDevice *vdev) 782 { 783 int i; 784 785 for (i = 0; i < vdev->nr_vectors; i++) { 786 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 787 MSIMessage msg; 788 789 if (!vector->use || vector->virq < 0) { 790 continue; 791 } 792 793 msg = msi_get_message(&vdev->pdev, i); 794 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); 795 } 796 } 797 798 static void vfio_pci_load_rom(VFIOPCIDevice *vdev) 799 { 800 struct vfio_region_info *reg_info; 801 uint64_t size; 802 off_t off = 0; 803 ssize_t bytes; 804 805 if (vfio_get_region_info(&vdev->vbasedev, 806 VFIO_PCI_ROM_REGION_INDEX, ®_info)) { 807 error_report("vfio: Error getting ROM info: %m"); 808 return; 809 } 810 811 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, 812 (unsigned long)reg_info->offset, 813 (unsigned long)reg_info->flags); 814 815 vdev->rom_size = size = reg_info->size; 816 vdev->rom_offset = reg_info->offset; 817 818 g_free(reg_info); 819 820 if (!vdev->rom_size) { 821 vdev->rom_read_failed = true; 822 error_report("vfio-pci: Cannot read device rom at " 823 "%s", vdev->vbasedev.name); 824 error_printf("Device option ROM contents are probably invalid " 825 "(check dmesg).\nSkip option ROM probe with rombar=0, " 826 "or load from file with romfile=\n"); 827 return; 828 } 829 830 vdev->rom = g_malloc(size); 831 memset(vdev->rom, 0xff, size); 832 833 while (size) { 834 bytes = pread(vdev->vbasedev.fd, vdev->rom + off, 835 size, vdev->rom_offset + off); 836 if (bytes == 0) { 837 break; 838 } else if (bytes > 0) { 839 off += bytes; 840 size -= bytes; 841 } else { 842 if (errno == EINTR || errno == EAGAIN) { 843 continue; 844 } 845 error_report("vfio: Error reading device ROM: %m"); 846 break; 847 } 848 } 849 850 /* 851 * Test the ROM signature against our device, if the vendor is correct 852 * but the device ID doesn't match, store the correct device ID and 853 * recompute the checksum. Intel IGD devices need this and are known 854 * to have bogus checksums so we can't simply adjust the checksum. 855 */ 856 if (pci_get_word(vdev->rom) == 0xaa55 && 857 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && 858 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { 859 uint16_t vid, did; 860 861 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); 862 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); 863 864 if (vid == vdev->vendor_id && did != vdev->device_id) { 865 int i; 866 uint8_t csum, *data = vdev->rom; 867 868 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, 869 vdev->device_id); 870 data[6] = 0; 871 872 for (csum = 0, i = 0; i < vdev->rom_size; i++) { 873 csum += data[i]; 874 } 875 876 data[6] = -csum; 877 } 878 } 879 } 880 881 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) 882 { 883 VFIOPCIDevice *vdev = opaque; 884 union { 885 uint8_t byte; 886 uint16_t word; 887 uint32_t dword; 888 uint64_t qword; 889 } val; 890 uint64_t data = 0; 891 892 /* Load the ROM lazily when the guest tries to read it */ 893 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { 894 vfio_pci_load_rom(vdev); 895 } 896 897 memcpy(&val, vdev->rom + addr, 898 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); 899 900 switch (size) { 901 case 1: 902 data = val.byte; 903 break; 904 case 2: 905 data = le16_to_cpu(val.word); 906 break; 907 case 4: 908 data = le32_to_cpu(val.dword); 909 break; 910 default: 911 hw_error("vfio: unsupported read size, %d bytes\n", size); 912 break; 913 } 914 915 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); 916 917 return data; 918 } 919 920 static void vfio_rom_write(void *opaque, hwaddr addr, 921 uint64_t data, unsigned size) 922 { 923 } 924 925 static const MemoryRegionOps vfio_rom_ops = { 926 .read = vfio_rom_read, 927 .write = vfio_rom_write, 928 .endianness = DEVICE_LITTLE_ENDIAN, 929 }; 930 931 static void vfio_pci_size_rom(VFIOPCIDevice *vdev) 932 { 933 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); 934 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; 935 DeviceState *dev = DEVICE(vdev); 936 char *name; 937 int fd = vdev->vbasedev.fd; 938 939 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { 940 /* Since pci handles romfile, just print a message and return */ 941 if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { 942 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n", 943 vdev->vbasedev.name); 944 } 945 return; 946 } 947 948 /* 949 * Use the same size ROM BAR as the physical device. The contents 950 * will get filled in later when the guest tries to read it. 951 */ 952 if (pread(fd, &orig, 4, offset) != 4 || 953 pwrite(fd, &size, 4, offset) != 4 || 954 pread(fd, &size, 4, offset) != 4 || 955 pwrite(fd, &orig, 4, offset) != 4) { 956 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); 957 return; 958 } 959 960 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; 961 962 if (!size) { 963 return; 964 } 965 966 if (vfio_blacklist_opt_rom(vdev)) { 967 if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { 968 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n", 969 vdev->vbasedev.name); 970 } else { 971 error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n", 972 vdev->vbasedev.name); 973 return; 974 } 975 } 976 977 trace_vfio_pci_size_rom(vdev->vbasedev.name, size); 978 979 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); 980 981 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), 982 &vfio_rom_ops, vdev, name, size); 983 g_free(name); 984 985 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, 986 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); 987 988 vdev->pdev.has_rom = true; 989 vdev->rom_read_failed = false; 990 } 991 992 void vfio_vga_write(void *opaque, hwaddr addr, 993 uint64_t data, unsigned size) 994 { 995 VFIOVGARegion *region = opaque; 996 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 997 union { 998 uint8_t byte; 999 uint16_t word; 1000 uint32_t dword; 1001 uint64_t qword; 1002 } buf; 1003 off_t offset = vga->fd_offset + region->offset + addr; 1004 1005 switch (size) { 1006 case 1: 1007 buf.byte = data; 1008 break; 1009 case 2: 1010 buf.word = cpu_to_le16(data); 1011 break; 1012 case 4: 1013 buf.dword = cpu_to_le32(data); 1014 break; 1015 default: 1016 hw_error("vfio: unsupported write size, %d bytes", size); 1017 break; 1018 } 1019 1020 if (pwrite(vga->fd, &buf, size, offset) != size) { 1021 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", 1022 __func__, region->offset + addr, data, size); 1023 } 1024 1025 trace_vfio_vga_write(region->offset + addr, data, size); 1026 } 1027 1028 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) 1029 { 1030 VFIOVGARegion *region = opaque; 1031 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1032 union { 1033 uint8_t byte; 1034 uint16_t word; 1035 uint32_t dword; 1036 uint64_t qword; 1037 } buf; 1038 uint64_t data = 0; 1039 off_t offset = vga->fd_offset + region->offset + addr; 1040 1041 if (pread(vga->fd, &buf, size, offset) != size) { 1042 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", 1043 __func__, region->offset + addr, size); 1044 return (uint64_t)-1; 1045 } 1046 1047 switch (size) { 1048 case 1: 1049 data = buf.byte; 1050 break; 1051 case 2: 1052 data = le16_to_cpu(buf.word); 1053 break; 1054 case 4: 1055 data = le32_to_cpu(buf.dword); 1056 break; 1057 default: 1058 hw_error("vfio: unsupported read size, %d bytes", size); 1059 break; 1060 } 1061 1062 trace_vfio_vga_read(region->offset + addr, size, data); 1063 1064 return data; 1065 } 1066 1067 static const MemoryRegionOps vfio_vga_ops = { 1068 .read = vfio_vga_read, 1069 .write = vfio_vga_write, 1070 .endianness = DEVICE_LITTLE_ENDIAN, 1071 }; 1072 1073 /* 1074 * PCI config space 1075 */ 1076 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) 1077 { 1078 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 1079 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; 1080 1081 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); 1082 emu_bits = le32_to_cpu(emu_bits); 1083 1084 if (emu_bits) { 1085 emu_val = pci_default_read_config(pdev, addr, len); 1086 } 1087 1088 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { 1089 ssize_t ret; 1090 1091 ret = pread(vdev->vbasedev.fd, &phys_val, len, 1092 vdev->config_offset + addr); 1093 if (ret != len) { 1094 error_report("%s(%s, 0x%x, 0x%x) failed: %m", 1095 __func__, vdev->vbasedev.name, addr, len); 1096 return -errno; 1097 } 1098 phys_val = le32_to_cpu(phys_val); 1099 } 1100 1101 val = (emu_val & emu_bits) | (phys_val & ~emu_bits); 1102 1103 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); 1104 1105 return val; 1106 } 1107 1108 void vfio_pci_write_config(PCIDevice *pdev, 1109 uint32_t addr, uint32_t val, int len) 1110 { 1111 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 1112 uint32_t val_le = cpu_to_le32(val); 1113 1114 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); 1115 1116 /* Write everything to VFIO, let it filter out what we can't write */ 1117 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) 1118 != len) { 1119 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", 1120 __func__, vdev->vbasedev.name, addr, val, len); 1121 } 1122 1123 /* MSI/MSI-X Enabling/Disabling */ 1124 if (pdev->cap_present & QEMU_PCI_CAP_MSI && 1125 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { 1126 int is_enabled, was_enabled = msi_enabled(pdev); 1127 1128 pci_default_write_config(pdev, addr, val, len); 1129 1130 is_enabled = msi_enabled(pdev); 1131 1132 if (!was_enabled) { 1133 if (is_enabled) { 1134 vfio_msi_enable(vdev); 1135 } 1136 } else { 1137 if (!is_enabled) { 1138 vfio_msi_disable(vdev); 1139 } else { 1140 vfio_update_msi(vdev); 1141 } 1142 } 1143 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && 1144 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { 1145 int is_enabled, was_enabled = msix_enabled(pdev); 1146 1147 pci_default_write_config(pdev, addr, val, len); 1148 1149 is_enabled = msix_enabled(pdev); 1150 1151 if (!was_enabled && is_enabled) { 1152 vfio_msix_enable(vdev); 1153 } else if (was_enabled && !is_enabled) { 1154 vfio_msix_disable(vdev); 1155 } 1156 } else { 1157 /* Write everything to QEMU to keep emulated bits correct */ 1158 pci_default_write_config(pdev, addr, val, len); 1159 } 1160 } 1161 1162 /* 1163 * Interrupt setup 1164 */ 1165 static void vfio_disable_interrupts(VFIOPCIDevice *vdev) 1166 { 1167 /* 1168 * More complicated than it looks. Disabling MSI/X transitions the 1169 * device to INTx mode (if supported). Therefore we need to first 1170 * disable MSI/X and then cleanup by disabling INTx. 1171 */ 1172 if (vdev->interrupt == VFIO_INT_MSIX) { 1173 vfio_msix_disable(vdev); 1174 } else if (vdev->interrupt == VFIO_INT_MSI) { 1175 vfio_msi_disable(vdev); 1176 } 1177 1178 if (vdev->interrupt == VFIO_INT_INTx) { 1179 vfio_intx_disable(vdev); 1180 } 1181 } 1182 1183 static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1184 { 1185 uint16_t ctrl; 1186 bool msi_64bit, msi_maskbit; 1187 int ret, entries; 1188 Error *err = NULL; 1189 1190 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), 1191 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { 1192 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); 1193 return -errno; 1194 } 1195 ctrl = le16_to_cpu(ctrl); 1196 1197 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); 1198 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); 1199 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); 1200 1201 trace_vfio_msi_setup(vdev->vbasedev.name, pos); 1202 1203 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err); 1204 if (ret < 0) { 1205 if (ret == -ENOTSUP) { 1206 return 0; 1207 } 1208 error_prepend(&err, "msi_init failed: "); 1209 error_propagate(errp, err); 1210 return ret; 1211 } 1212 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); 1213 1214 return 0; 1215 } 1216 1217 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) 1218 { 1219 off_t start, end; 1220 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; 1221 1222 /* 1223 * We expect to find a single mmap covering the whole BAR, anything else 1224 * means it's either unsupported or already setup. 1225 */ 1226 if (region->nr_mmaps != 1 || region->mmaps[0].offset || 1227 region->size != region->mmaps[0].size) { 1228 return; 1229 } 1230 1231 /* MSI-X table start and end aligned to host page size */ 1232 start = vdev->msix->table_offset & qemu_real_host_page_mask; 1233 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + 1234 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); 1235 1236 /* 1237 * Does the MSI-X table cover the beginning of the BAR? The whole BAR? 1238 * NB - Host page size is necessarily a power of two and so is the PCI 1239 * BAR (not counting EA yet), therefore if we have host page aligned 1240 * @start and @end, then any remainder of the BAR before or after those 1241 * must be at least host page sized and therefore mmap'able. 1242 */ 1243 if (!start) { 1244 if (end >= region->size) { 1245 region->nr_mmaps = 0; 1246 g_free(region->mmaps); 1247 region->mmaps = NULL; 1248 trace_vfio_msix_fixup(vdev->vbasedev.name, 1249 vdev->msix->table_bar, 0, 0); 1250 } else { 1251 region->mmaps[0].offset = end; 1252 region->mmaps[0].size = region->size - end; 1253 trace_vfio_msix_fixup(vdev->vbasedev.name, 1254 vdev->msix->table_bar, region->mmaps[0].offset, 1255 region->mmaps[0].offset + region->mmaps[0].size); 1256 } 1257 1258 /* Maybe it's aligned at the end of the BAR */ 1259 } else if (end >= region->size) { 1260 region->mmaps[0].size = start; 1261 trace_vfio_msix_fixup(vdev->vbasedev.name, 1262 vdev->msix->table_bar, region->mmaps[0].offset, 1263 region->mmaps[0].offset + region->mmaps[0].size); 1264 1265 /* Otherwise it must split the BAR */ 1266 } else { 1267 region->nr_mmaps = 2; 1268 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); 1269 1270 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); 1271 1272 region->mmaps[0].size = start; 1273 trace_vfio_msix_fixup(vdev->vbasedev.name, 1274 vdev->msix->table_bar, region->mmaps[0].offset, 1275 region->mmaps[0].offset + region->mmaps[0].size); 1276 1277 region->mmaps[1].offset = end; 1278 region->mmaps[1].size = region->size - end; 1279 trace_vfio_msix_fixup(vdev->vbasedev.name, 1280 vdev->msix->table_bar, region->mmaps[1].offset, 1281 region->mmaps[1].offset + region->mmaps[1].size); 1282 } 1283 } 1284 1285 /* 1286 * We don't have any control over how pci_add_capability() inserts 1287 * capabilities into the chain. In order to setup MSI-X we need a 1288 * MemoryRegion for the BAR. In order to setup the BAR and not 1289 * attempt to mmap the MSI-X table area, which VFIO won't allow, we 1290 * need to first look for where the MSI-X table lives. So we 1291 * unfortunately split MSI-X setup across two functions. 1292 */ 1293 static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) 1294 { 1295 uint8_t pos; 1296 uint16_t ctrl; 1297 uint32_t table, pba; 1298 int fd = vdev->vbasedev.fd; 1299 VFIOMSIXInfo *msix; 1300 1301 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); 1302 if (!pos) { 1303 return; 1304 } 1305 1306 if (pread(fd, &ctrl, sizeof(ctrl), 1307 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { 1308 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS"); 1309 return; 1310 } 1311 1312 if (pread(fd, &table, sizeof(table), 1313 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { 1314 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE"); 1315 return; 1316 } 1317 1318 if (pread(fd, &pba, sizeof(pba), 1319 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { 1320 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA"); 1321 return; 1322 } 1323 1324 ctrl = le16_to_cpu(ctrl); 1325 table = le32_to_cpu(table); 1326 pba = le32_to_cpu(pba); 1327 1328 msix = g_malloc0(sizeof(*msix)); 1329 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 1330 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 1331 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 1332 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 1333 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 1334 1335 /* 1336 * Test the size of the pba_offset variable and catch if it extends outside 1337 * of the specified BAR. If it is the case, we need to apply a hardware 1338 * specific quirk if the device is known or we have a broken configuration. 1339 */ 1340 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { 1341 /* 1342 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 1343 * adapters. The T5 hardware returns an incorrect value of 0x8000 for 1344 * the VF PBA offset while the BAR itself is only 8k. The correct value 1345 * is 0x1000, so we hard code that here. 1346 */ 1347 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && 1348 (vdev->device_id & 0xff00) == 0x5800) { 1349 msix->pba_offset = 0x1000; 1350 } else { 1351 error_setg(errp, "hardware reports invalid configuration, " 1352 "MSIX PBA outside of specified BAR"); 1353 g_free(msix); 1354 return; 1355 } 1356 } 1357 1358 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, 1359 msix->table_offset, msix->entries); 1360 vdev->msix = msix; 1361 1362 vfio_pci_fixup_msix_region(vdev); 1363 } 1364 1365 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1366 { 1367 int ret; 1368 1369 vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * 1370 sizeof(unsigned long)); 1371 ret = msix_init(&vdev->pdev, vdev->msix->entries, 1372 vdev->bars[vdev->msix->table_bar].region.mem, 1373 vdev->msix->table_bar, vdev->msix->table_offset, 1374 vdev->bars[vdev->msix->pba_bar].region.mem, 1375 vdev->msix->pba_bar, vdev->msix->pba_offset, pos); 1376 if (ret < 0) { 1377 if (ret == -ENOTSUP) { 1378 return 0; 1379 } 1380 error_setg(errp, "msix_init failed"); 1381 return ret; 1382 } 1383 1384 /* 1385 * The PCI spec suggests that devices provide additional alignment for 1386 * MSI-X structures and avoid overlapping non-MSI-X related registers. 1387 * For an assigned device, this hopefully means that emulation of MSI-X 1388 * structures does not affect the performance of the device. If devices 1389 * fail to provide that alignment, a significant performance penalty may 1390 * result, for instance Mellanox MT27500 VFs: 1391 * http://www.spinics.net/lists/kvm/msg125881.html 1392 * 1393 * The PBA is simply not that important for such a serious regression and 1394 * most drivers do not appear to look at it. The solution for this is to 1395 * disable the PBA MemoryRegion unless it's being used. We disable it 1396 * here and only enable it if a masked vector fires through QEMU. As the 1397 * vector-use notifier is called, which occurs on unmask, we test whether 1398 * PBA emulation is needed and again disable if not. 1399 */ 1400 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 1401 1402 return 0; 1403 } 1404 1405 static void vfio_teardown_msi(VFIOPCIDevice *vdev) 1406 { 1407 msi_uninit(&vdev->pdev); 1408 1409 if (vdev->msix) { 1410 msix_uninit(&vdev->pdev, 1411 vdev->bars[vdev->msix->table_bar].region.mem, 1412 vdev->bars[vdev->msix->pba_bar].region.mem); 1413 g_free(vdev->msix->pending); 1414 } 1415 } 1416 1417 /* 1418 * Resource setup 1419 */ 1420 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) 1421 { 1422 int i; 1423 1424 for (i = 0; i < PCI_ROM_SLOT; i++) { 1425 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); 1426 } 1427 } 1428 1429 static void vfio_bar_setup(VFIOPCIDevice *vdev, int nr) 1430 { 1431 VFIOBAR *bar = &vdev->bars[nr]; 1432 1433 uint32_t pci_bar; 1434 uint8_t type; 1435 int ret; 1436 1437 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ 1438 if (!bar->region.size) { 1439 return; 1440 } 1441 1442 /* Determine what type of BAR this is for registration */ 1443 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), 1444 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); 1445 if (ret != sizeof(pci_bar)) { 1446 error_report("vfio: Failed to read BAR %d (%m)", nr); 1447 return; 1448 } 1449 1450 pci_bar = le32_to_cpu(pci_bar); 1451 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); 1452 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); 1453 type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : 1454 ~PCI_BASE_ADDRESS_MEM_MASK); 1455 1456 if (vfio_region_mmap(&bar->region)) { 1457 error_report("Failed to mmap %s BAR %d. Performance may be slow", 1458 vdev->vbasedev.name, nr); 1459 } 1460 1461 pci_register_bar(&vdev->pdev, nr, type, bar->region.mem); 1462 } 1463 1464 static void vfio_bars_setup(VFIOPCIDevice *vdev) 1465 { 1466 int i; 1467 1468 for (i = 0; i < PCI_ROM_SLOT; i++) { 1469 vfio_bar_setup(vdev, i); 1470 } 1471 } 1472 1473 static void vfio_bars_exit(VFIOPCIDevice *vdev) 1474 { 1475 int i; 1476 1477 for (i = 0; i < PCI_ROM_SLOT; i++) { 1478 vfio_bar_quirk_exit(vdev, i); 1479 vfio_region_exit(&vdev->bars[i].region); 1480 } 1481 1482 if (vdev->vga) { 1483 pci_unregister_vga(&vdev->pdev); 1484 vfio_vga_quirk_exit(vdev); 1485 } 1486 } 1487 1488 static void vfio_bars_finalize(VFIOPCIDevice *vdev) 1489 { 1490 int i; 1491 1492 for (i = 0; i < PCI_ROM_SLOT; i++) { 1493 vfio_bar_quirk_finalize(vdev, i); 1494 vfio_region_finalize(&vdev->bars[i].region); 1495 } 1496 1497 if (vdev->vga) { 1498 vfio_vga_quirk_finalize(vdev); 1499 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { 1500 object_unparent(OBJECT(&vdev->vga->region[i].mem)); 1501 } 1502 g_free(vdev->vga); 1503 } 1504 } 1505 1506 /* 1507 * General setup 1508 */ 1509 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) 1510 { 1511 uint8_t tmp; 1512 uint16_t next = PCI_CONFIG_SPACE_SIZE; 1513 1514 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; 1515 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { 1516 if (tmp > pos && tmp < next) { 1517 next = tmp; 1518 } 1519 } 1520 1521 return next - pos; 1522 } 1523 1524 1525 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) 1526 { 1527 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; 1528 1529 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; 1530 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { 1531 if (tmp > pos && tmp < next) { 1532 next = tmp; 1533 } 1534 } 1535 1536 return next - pos; 1537 } 1538 1539 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) 1540 { 1541 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); 1542 } 1543 1544 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, 1545 uint16_t val, uint16_t mask) 1546 { 1547 vfio_set_word_bits(vdev->pdev.config + pos, val, mask); 1548 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); 1549 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); 1550 } 1551 1552 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) 1553 { 1554 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); 1555 } 1556 1557 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, 1558 uint32_t val, uint32_t mask) 1559 { 1560 vfio_set_long_bits(vdev->pdev.config + pos, val, mask); 1561 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); 1562 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); 1563 } 1564 1565 static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1566 Error **errp) 1567 { 1568 uint16_t flags; 1569 uint8_t type; 1570 1571 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); 1572 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; 1573 1574 if (type != PCI_EXP_TYPE_ENDPOINT && 1575 type != PCI_EXP_TYPE_LEG_END && 1576 type != PCI_EXP_TYPE_RC_END) { 1577 1578 error_setg(errp, "assignment of PCIe type 0x%x " 1579 "devices is not currently supported", type); 1580 return -EINVAL; 1581 } 1582 1583 if (!pci_bus_is_express(vdev->pdev.bus)) { 1584 PCIBus *bus = vdev->pdev.bus; 1585 PCIDevice *bridge; 1586 1587 /* 1588 * Traditionally PCI device assignment exposes the PCIe capability 1589 * as-is on non-express buses. The reason being that some drivers 1590 * simply assume that it's there, for example tg3. However when 1591 * we're running on a native PCIe machine type, like Q35, we need 1592 * to hide the PCIe capability. The reason for this is twofold; 1593 * first Windows guests get a Code 10 error when the PCIe capability 1594 * is exposed in this configuration. Therefore express devices won't 1595 * work at all unless they're attached to express buses in the VM. 1596 * Second, a native PCIe machine introduces the possibility of fine 1597 * granularity IOMMUs supporting both translation and isolation. 1598 * Guest code to discover the IOMMU visibility of a device, such as 1599 * IOMMU grouping code on Linux, is very aware of device types and 1600 * valid transitions between bus types. An express device on a non- 1601 * express bus is not a valid combination on bare metal systems. 1602 * 1603 * Drivers that require a PCIe capability to make the device 1604 * functional are simply going to need to have their devices placed 1605 * on a PCIe bus in the VM. 1606 */ 1607 while (!pci_bus_is_root(bus)) { 1608 bridge = pci_bridge_get_device(bus); 1609 bus = bridge->bus; 1610 } 1611 1612 if (pci_bus_is_express(bus)) { 1613 return 0; 1614 } 1615 1616 } else if (pci_bus_is_root(vdev->pdev.bus)) { 1617 /* 1618 * On a Root Complex bus Endpoints become Root Complex Integrated 1619 * Endpoints, which changes the type and clears the LNK & LNK2 fields. 1620 */ 1621 if (type == PCI_EXP_TYPE_ENDPOINT) { 1622 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1623 PCI_EXP_TYPE_RC_END << 4, 1624 PCI_EXP_FLAGS_TYPE); 1625 1626 /* Link Capabilities, Status, and Control goes away */ 1627 if (size > PCI_EXP_LNKCTL) { 1628 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); 1629 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1630 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); 1631 1632 #ifndef PCI_EXP_LNKCAP2 1633 #define PCI_EXP_LNKCAP2 44 1634 #endif 1635 #ifndef PCI_EXP_LNKSTA2 1636 #define PCI_EXP_LNKSTA2 50 1637 #endif 1638 /* Link 2 Capabilities, Status, and Control goes away */ 1639 if (size > PCI_EXP_LNKCAP2) { 1640 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); 1641 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); 1642 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); 1643 } 1644 } 1645 1646 } else if (type == PCI_EXP_TYPE_LEG_END) { 1647 /* 1648 * Legacy endpoints don't belong on the root complex. Windows 1649 * seems to be happier with devices if we skip the capability. 1650 */ 1651 return 0; 1652 } 1653 1654 } else { 1655 /* 1656 * Convert Root Complex Integrated Endpoints to regular endpoints. 1657 * These devices don't support LNK/LNK2 capabilities, so make them up. 1658 */ 1659 if (type == PCI_EXP_TYPE_RC_END) { 1660 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1661 PCI_EXP_TYPE_ENDPOINT << 4, 1662 PCI_EXP_FLAGS_TYPE); 1663 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 1664 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); 1665 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1666 } 1667 1668 /* Mark the Link Status bits as emulated to allow virtual negotiation */ 1669 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 1670 pci_get_word(vdev->pdev.config + pos + 1671 PCI_EXP_LNKSTA), 1672 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 1673 } 1674 1675 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size); 1676 if (pos >= 0) { 1677 vdev->pdev.exp.exp_cap = pos; 1678 } 1679 1680 return pos; 1681 } 1682 1683 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) 1684 { 1685 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); 1686 1687 if (cap & PCI_EXP_DEVCAP_FLR) { 1688 trace_vfio_check_pcie_flr(vdev->vbasedev.name); 1689 vdev->has_flr = true; 1690 } 1691 } 1692 1693 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) 1694 { 1695 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); 1696 1697 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { 1698 trace_vfio_check_pm_reset(vdev->vbasedev.name); 1699 vdev->has_pm_reset = true; 1700 } 1701 } 1702 1703 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) 1704 { 1705 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); 1706 1707 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { 1708 trace_vfio_check_af_flr(vdev->vbasedev.name); 1709 vdev->has_flr = true; 1710 } 1711 } 1712 1713 static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) 1714 { 1715 PCIDevice *pdev = &vdev->pdev; 1716 uint8_t cap_id, next, size; 1717 int ret; 1718 1719 cap_id = pdev->config[pos]; 1720 next = pdev->config[pos + PCI_CAP_LIST_NEXT]; 1721 1722 /* 1723 * If it becomes important to configure capabilities to their actual 1724 * size, use this as the default when it's something we don't recognize. 1725 * Since QEMU doesn't actually handle many of the config accesses, 1726 * exact size doesn't seem worthwhile. 1727 */ 1728 size = vfio_std_cap_max_size(pdev, pos); 1729 1730 /* 1731 * pci_add_capability always inserts the new capability at the head 1732 * of the chain. Therefore to end up with a chain that matches the 1733 * physical device, we insert from the end by making this recursive. 1734 * This is also why we pre-calculate size above as cached config space 1735 * will be changed as we unwind the stack. 1736 */ 1737 if (next) { 1738 ret = vfio_add_std_cap(vdev, next, errp); 1739 if (ret) { 1740 goto out; 1741 } 1742 } else { 1743 /* Begin the rebuild, use QEMU emulated list bits */ 1744 pdev->config[PCI_CAPABILITY_LIST] = 0; 1745 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; 1746 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 1747 } 1748 1749 /* Use emulated next pointer to allow dropping caps */ 1750 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); 1751 1752 switch (cap_id) { 1753 case PCI_CAP_ID_MSI: 1754 ret = vfio_msi_setup(vdev, pos, errp); 1755 break; 1756 case PCI_CAP_ID_EXP: 1757 vfio_check_pcie_flr(vdev, pos); 1758 ret = vfio_setup_pcie_cap(vdev, pos, size, errp); 1759 break; 1760 case PCI_CAP_ID_MSIX: 1761 ret = vfio_msix_setup(vdev, pos, errp); 1762 break; 1763 case PCI_CAP_ID_PM: 1764 vfio_check_pm_reset(vdev, pos); 1765 vdev->pm_cap = pos; 1766 ret = pci_add_capability2(pdev, cap_id, pos, size, errp); 1767 break; 1768 case PCI_CAP_ID_AF: 1769 vfio_check_af_flr(vdev, pos); 1770 ret = pci_add_capability2(pdev, cap_id, pos, size, errp); 1771 break; 1772 default: 1773 ret = pci_add_capability2(pdev, cap_id, pos, size, errp); 1774 break; 1775 } 1776 out: 1777 if (ret < 0) { 1778 error_prepend(errp, 1779 "failed to add PCI capability 0x%x[0x%x]@0x%x: ", 1780 cap_id, size, pos); 1781 return ret; 1782 } 1783 1784 return 0; 1785 } 1786 1787 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) 1788 { 1789 PCIDevice *pdev = &vdev->pdev; 1790 uint32_t header; 1791 uint16_t cap_id, next, size; 1792 uint8_t cap_ver; 1793 uint8_t *config; 1794 1795 /* Only add extended caps if we have them and the guest can see them */ 1796 if (!pci_is_express(pdev) || !pci_bus_is_express(pdev->bus) || 1797 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { 1798 return; 1799 } 1800 1801 /* 1802 * pcie_add_capability always inserts the new capability at the tail 1803 * of the chain. Therefore to end up with a chain that matches the 1804 * physical device, we cache the config space to avoid overwriting 1805 * the original config space when we parse the extended capabilities. 1806 */ 1807 config = g_memdup(pdev->config, vdev->config_size); 1808 1809 /* 1810 * Extended capabilities are chained with each pointing to the next, so we 1811 * can drop anything other than the head of the chain simply by modifying 1812 * the previous next pointer. For the head of the chain, we can modify the 1813 * capability ID to something that cannot match a valid capability. ID 1814 * 0 is reserved for this since absence of capabilities is indicated by 1815 * 0 for the ID, version, AND next pointer. However, pcie_add_capability() 1816 * uses ID 0 as reserved for list management and will incorrectly match and 1817 * assert if we attempt to pre-load the head of the chain with with this 1818 * ID. Use ID 0xFFFF temporarily since it is also seems to be reserved in 1819 * part for identifying absence of capabilities in a root complex register 1820 * block. If the ID still exists after adding capabilities, switch back to 1821 * zero. We'll mark this entire first dword as emulated for this purpose. 1822 */ 1823 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, 1824 PCI_EXT_CAP(0xFFFF, 0, 0)); 1825 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 1826 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); 1827 1828 for (next = PCI_CONFIG_SPACE_SIZE; next; 1829 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { 1830 header = pci_get_long(config + next); 1831 cap_id = PCI_EXT_CAP_ID(header); 1832 cap_ver = PCI_EXT_CAP_VER(header); 1833 1834 /* 1835 * If it becomes important to configure extended capabilities to their 1836 * actual size, use this as the default when it's something we don't 1837 * recognize. Since QEMU doesn't actually handle many of the config 1838 * accesses, exact size doesn't seem worthwhile. 1839 */ 1840 size = vfio_ext_cap_max_size(config, next); 1841 1842 /* Use emulated next pointer to allow dropping extended caps */ 1843 pci_long_test_and_set_mask(vdev->emulated_config_bits + next, 1844 PCI_EXT_CAP_NEXT_MASK); 1845 1846 switch (cap_id) { 1847 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ 1848 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */ 1849 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); 1850 break; 1851 default: 1852 pcie_add_capability(pdev, cap_id, cap_ver, next, size); 1853 } 1854 1855 } 1856 1857 /* Cleanup chain head ID if necessary */ 1858 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { 1859 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); 1860 } 1861 1862 g_free(config); 1863 return; 1864 } 1865 1866 static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp) 1867 { 1868 PCIDevice *pdev = &vdev->pdev; 1869 int ret; 1870 1871 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || 1872 !pdev->config[PCI_CAPABILITY_LIST]) { 1873 return 0; /* Nothing to add */ 1874 } 1875 1876 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp); 1877 if (ret) { 1878 return ret; 1879 } 1880 1881 vfio_add_ext_cap(vdev); 1882 return 0; 1883 } 1884 1885 static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) 1886 { 1887 PCIDevice *pdev = &vdev->pdev; 1888 uint16_t cmd; 1889 1890 vfio_disable_interrupts(vdev); 1891 1892 /* Make sure the device is in D0 */ 1893 if (vdev->pm_cap) { 1894 uint16_t pmcsr; 1895 uint8_t state; 1896 1897 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 1898 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 1899 if (state) { 1900 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 1901 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); 1902 /* vfio handles the necessary delay here */ 1903 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 1904 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 1905 if (state) { 1906 error_report("vfio: Unable to power on device, stuck in D%d", 1907 state); 1908 } 1909 } 1910 } 1911 1912 /* 1913 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. 1914 * Also put INTx Disable in known state. 1915 */ 1916 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); 1917 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 1918 PCI_COMMAND_INTX_DISABLE); 1919 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); 1920 } 1921 1922 static void vfio_pci_post_reset(VFIOPCIDevice *vdev) 1923 { 1924 Error *err = NULL; 1925 1926 vfio_intx_enable(vdev, &err); 1927 if (err) { 1928 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); 1929 } 1930 } 1931 1932 static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) 1933 { 1934 char tmp[13]; 1935 1936 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, 1937 addr->bus, addr->slot, addr->function); 1938 1939 return (strcmp(tmp, name) == 0); 1940 } 1941 1942 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) 1943 { 1944 VFIOGroup *group; 1945 struct vfio_pci_hot_reset_info *info; 1946 struct vfio_pci_dependent_device *devices; 1947 struct vfio_pci_hot_reset *reset; 1948 int32_t *fds; 1949 int ret, i, count; 1950 bool multi = false; 1951 1952 trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); 1953 1954 if (!single) { 1955 vfio_pci_pre_reset(vdev); 1956 } 1957 vdev->vbasedev.needs_reset = false; 1958 1959 info = g_malloc0(sizeof(*info)); 1960 info->argsz = sizeof(*info); 1961 1962 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 1963 if (ret && errno != ENOSPC) { 1964 ret = -errno; 1965 if (!vdev->has_pm_reset) { 1966 error_report("vfio: Cannot reset device %s, " 1967 "no available reset mechanism.", vdev->vbasedev.name); 1968 } 1969 goto out_single; 1970 } 1971 1972 count = info->count; 1973 info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); 1974 info->argsz = sizeof(*info) + (count * sizeof(*devices)); 1975 devices = &info->devices[0]; 1976 1977 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 1978 if (ret) { 1979 ret = -errno; 1980 error_report("vfio: hot reset info failed: %m"); 1981 goto out_single; 1982 } 1983 1984 trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); 1985 1986 /* Verify that we have all the groups required */ 1987 for (i = 0; i < info->count; i++) { 1988 PCIHostDeviceAddress host; 1989 VFIOPCIDevice *tmp; 1990 VFIODevice *vbasedev_iter; 1991 1992 host.domain = devices[i].segment; 1993 host.bus = devices[i].bus; 1994 host.slot = PCI_SLOT(devices[i].devfn); 1995 host.function = PCI_FUNC(devices[i].devfn); 1996 1997 trace_vfio_pci_hot_reset_dep_devices(host.domain, 1998 host.bus, host.slot, host.function, devices[i].group_id); 1999 2000 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2001 continue; 2002 } 2003 2004 QLIST_FOREACH(group, &vfio_group_list, next) { 2005 if (group->groupid == devices[i].group_id) { 2006 break; 2007 } 2008 } 2009 2010 if (!group) { 2011 if (!vdev->has_pm_reset) { 2012 error_report("vfio: Cannot reset device %s, " 2013 "depends on group %d which is not owned.", 2014 vdev->vbasedev.name, devices[i].group_id); 2015 } 2016 ret = -EPERM; 2017 goto out; 2018 } 2019 2020 /* Prep dependent devices for reset and clear our marker. */ 2021 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2022 if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2023 continue; 2024 } 2025 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2026 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2027 if (single) { 2028 ret = -EINVAL; 2029 goto out_single; 2030 } 2031 vfio_pci_pre_reset(tmp); 2032 tmp->vbasedev.needs_reset = false; 2033 multi = true; 2034 break; 2035 } 2036 } 2037 } 2038 2039 if (!single && !multi) { 2040 ret = -EINVAL; 2041 goto out_single; 2042 } 2043 2044 /* Determine how many group fds need to be passed */ 2045 count = 0; 2046 QLIST_FOREACH(group, &vfio_group_list, next) { 2047 for (i = 0; i < info->count; i++) { 2048 if (group->groupid == devices[i].group_id) { 2049 count++; 2050 break; 2051 } 2052 } 2053 } 2054 2055 reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); 2056 reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); 2057 fds = &reset->group_fds[0]; 2058 2059 /* Fill in group fds */ 2060 QLIST_FOREACH(group, &vfio_group_list, next) { 2061 for (i = 0; i < info->count; i++) { 2062 if (group->groupid == devices[i].group_id) { 2063 fds[reset->count++] = group->fd; 2064 break; 2065 } 2066 } 2067 } 2068 2069 /* Bus reset! */ 2070 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); 2071 g_free(reset); 2072 2073 trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, 2074 ret ? "%m" : "Success"); 2075 2076 out: 2077 /* Re-enable INTx on affected devices */ 2078 for (i = 0; i < info->count; i++) { 2079 PCIHostDeviceAddress host; 2080 VFIOPCIDevice *tmp; 2081 VFIODevice *vbasedev_iter; 2082 2083 host.domain = devices[i].segment; 2084 host.bus = devices[i].bus; 2085 host.slot = PCI_SLOT(devices[i].devfn); 2086 host.function = PCI_FUNC(devices[i].devfn); 2087 2088 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2089 continue; 2090 } 2091 2092 QLIST_FOREACH(group, &vfio_group_list, next) { 2093 if (group->groupid == devices[i].group_id) { 2094 break; 2095 } 2096 } 2097 2098 if (!group) { 2099 break; 2100 } 2101 2102 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2103 if (vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2104 continue; 2105 } 2106 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2107 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2108 vfio_pci_post_reset(tmp); 2109 break; 2110 } 2111 } 2112 } 2113 out_single: 2114 if (!single) { 2115 vfio_pci_post_reset(vdev); 2116 } 2117 g_free(info); 2118 2119 return ret; 2120 } 2121 2122 /* 2123 * We want to differentiate hot reset of mulitple in-use devices vs hot reset 2124 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case 2125 * of doing hot resets when there is only a single device per bus. The in-use 2126 * here refers to how many VFIODevices are affected. A hot reset that affects 2127 * multiple devices, but only a single in-use device, means that we can call 2128 * it from our bus ->reset() callback since the extent is effectively a single 2129 * device. This allows us to make use of it in the hotplug path. When there 2130 * are multiple in-use devices, we can only trigger the hot reset during a 2131 * system reset and thus from our reset handler. We separate _one vs _multi 2132 * here so that we don't overlap and do a double reset on the system reset 2133 * path where both our reset handler and ->reset() callback are used. Calling 2134 * _one() will only do a hot reset for the one in-use devices case, calling 2135 * _multi() will do nothing if a _one() would have been sufficient. 2136 */ 2137 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) 2138 { 2139 return vfio_pci_hot_reset(vdev, true); 2140 } 2141 2142 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) 2143 { 2144 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2145 return vfio_pci_hot_reset(vdev, false); 2146 } 2147 2148 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) 2149 { 2150 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2151 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { 2152 vbasedev->needs_reset = true; 2153 } 2154 } 2155 2156 static VFIODeviceOps vfio_pci_ops = { 2157 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, 2158 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, 2159 .vfio_eoi = vfio_intx_eoi, 2160 }; 2161 2162 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) 2163 { 2164 VFIODevice *vbasedev = &vdev->vbasedev; 2165 struct vfio_region_info *reg_info; 2166 int ret; 2167 2168 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); 2169 if (ret) { 2170 error_setg_errno(errp, -ret, 2171 "failed getting region info for VGA region index %d", 2172 VFIO_PCI_VGA_REGION_INDEX); 2173 return ret; 2174 } 2175 2176 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || 2177 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || 2178 reg_info->size < 0xbffff + 1) { 2179 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx", 2180 (unsigned long)reg_info->flags, 2181 (unsigned long)reg_info->size); 2182 g_free(reg_info); 2183 return -EINVAL; 2184 } 2185 2186 vdev->vga = g_new0(VFIOVGA, 1); 2187 2188 vdev->vga->fd_offset = reg_info->offset; 2189 vdev->vga->fd = vdev->vbasedev.fd; 2190 2191 g_free(reg_info); 2192 2193 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; 2194 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; 2195 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); 2196 2197 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2198 OBJECT(vdev), &vfio_vga_ops, 2199 &vdev->vga->region[QEMU_PCI_VGA_MEM], 2200 "vfio-vga-mmio@0xa0000", 2201 QEMU_PCI_VGA_MEM_SIZE); 2202 2203 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; 2204 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; 2205 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); 2206 2207 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2208 OBJECT(vdev), &vfio_vga_ops, 2209 &vdev->vga->region[QEMU_PCI_VGA_IO_LO], 2210 "vfio-vga-io@0x3b0", 2211 QEMU_PCI_VGA_IO_LO_SIZE); 2212 2213 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; 2214 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; 2215 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); 2216 2217 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, 2218 OBJECT(vdev), &vfio_vga_ops, 2219 &vdev->vga->region[QEMU_PCI_VGA_IO_HI], 2220 "vfio-vga-io@0x3c0", 2221 QEMU_PCI_VGA_IO_HI_SIZE); 2222 2223 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2224 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2225 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); 2226 2227 return 0; 2228 } 2229 2230 static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp) 2231 { 2232 VFIODevice *vbasedev = &vdev->vbasedev; 2233 struct vfio_region_info *reg_info; 2234 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; 2235 int i, ret = -1; 2236 2237 /* Sanity check device */ 2238 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { 2239 error_setg(errp, "this isn't a PCI device"); 2240 return; 2241 } 2242 2243 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { 2244 error_setg(errp, "unexpected number of io regions %u", 2245 vbasedev->num_regions); 2246 return; 2247 } 2248 2249 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { 2250 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs); 2251 return; 2252 } 2253 2254 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { 2255 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); 2256 2257 ret = vfio_region_setup(OBJECT(vdev), vbasedev, 2258 &vdev->bars[i].region, i, name); 2259 g_free(name); 2260 2261 if (ret) { 2262 error_setg_errno(errp, -ret, "failed to get region %d info", i); 2263 return; 2264 } 2265 2266 QLIST_INIT(&vdev->bars[i].quirks); 2267 } 2268 2269 ret = vfio_get_region_info(vbasedev, 2270 VFIO_PCI_CONFIG_REGION_INDEX, ®_info); 2271 if (ret) { 2272 error_setg_errno(errp, -ret, "failed to get config info"); 2273 return; 2274 } 2275 2276 trace_vfio_populate_device_config(vdev->vbasedev.name, 2277 (unsigned long)reg_info->size, 2278 (unsigned long)reg_info->offset, 2279 (unsigned long)reg_info->flags); 2280 2281 vdev->config_size = reg_info->size; 2282 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { 2283 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; 2284 } 2285 vdev->config_offset = reg_info->offset; 2286 2287 g_free(reg_info); 2288 2289 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { 2290 ret = vfio_populate_vga(vdev, errp); 2291 if (ret) { 2292 error_append_hint(errp, "device does not support " 2293 "requested feature x-vga\n"); 2294 return; 2295 } 2296 } 2297 2298 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; 2299 2300 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); 2301 if (ret) { 2302 /* This can fail for an old kernel or legacy PCI dev */ 2303 trace_vfio_populate_device_get_irq_info_failure(); 2304 } else if (irq_info.count == 1) { 2305 vdev->pci_aer = true; 2306 } else { 2307 error_report(WARN_PREFIX 2308 "Could not enable error recovery for the device", 2309 vbasedev->name); 2310 } 2311 } 2312 2313 static void vfio_put_device(VFIOPCIDevice *vdev) 2314 { 2315 g_free(vdev->vbasedev.name); 2316 g_free(vdev->msix); 2317 2318 vfio_put_base_device(&vdev->vbasedev); 2319 } 2320 2321 static void vfio_err_notifier_handler(void *opaque) 2322 { 2323 VFIOPCIDevice *vdev = opaque; 2324 2325 if (!event_notifier_test_and_clear(&vdev->err_notifier)) { 2326 return; 2327 } 2328 2329 /* 2330 * TBD. Retrieve the error details and decide what action 2331 * needs to be taken. One of the actions could be to pass 2332 * the error to the guest and have the guest driver recover 2333 * from the error. This requires that PCIe capabilities be 2334 * exposed to the guest. For now, we just terminate the 2335 * guest to contain the error. 2336 */ 2337 2338 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); 2339 2340 vm_stop(RUN_STATE_INTERNAL_ERROR); 2341 } 2342 2343 /* 2344 * Registers error notifier for devices supporting error recovery. 2345 * If we encounter a failure in this function, we report an error 2346 * and continue after disabling error recovery support for the 2347 * device. 2348 */ 2349 static void vfio_register_err_notifier(VFIOPCIDevice *vdev) 2350 { 2351 int ret; 2352 int argsz; 2353 struct vfio_irq_set *irq_set; 2354 int32_t *pfd; 2355 2356 if (!vdev->pci_aer) { 2357 return; 2358 } 2359 2360 if (event_notifier_init(&vdev->err_notifier, 0)) { 2361 error_report("vfio: Unable to init event notifier for error detection"); 2362 vdev->pci_aer = false; 2363 return; 2364 } 2365 2366 argsz = sizeof(*irq_set) + sizeof(*pfd); 2367 2368 irq_set = g_malloc0(argsz); 2369 irq_set->argsz = argsz; 2370 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2371 VFIO_IRQ_SET_ACTION_TRIGGER; 2372 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2373 irq_set->start = 0; 2374 irq_set->count = 1; 2375 pfd = (int32_t *)&irq_set->data; 2376 2377 *pfd = event_notifier_get_fd(&vdev->err_notifier); 2378 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); 2379 2380 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2381 if (ret) { 2382 error_report("vfio: Failed to set up error notification"); 2383 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2384 event_notifier_cleanup(&vdev->err_notifier); 2385 vdev->pci_aer = false; 2386 } 2387 g_free(irq_set); 2388 } 2389 2390 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) 2391 { 2392 int argsz; 2393 struct vfio_irq_set *irq_set; 2394 int32_t *pfd; 2395 int ret; 2396 2397 if (!vdev->pci_aer) { 2398 return; 2399 } 2400 2401 argsz = sizeof(*irq_set) + sizeof(*pfd); 2402 2403 irq_set = g_malloc0(argsz); 2404 irq_set->argsz = argsz; 2405 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2406 VFIO_IRQ_SET_ACTION_TRIGGER; 2407 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2408 irq_set->start = 0; 2409 irq_set->count = 1; 2410 pfd = (int32_t *)&irq_set->data; 2411 *pfd = -1; 2412 2413 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2414 if (ret) { 2415 error_report("vfio: Failed to de-assign error fd: %m"); 2416 } 2417 g_free(irq_set); 2418 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), 2419 NULL, NULL, vdev); 2420 event_notifier_cleanup(&vdev->err_notifier); 2421 } 2422 2423 static void vfio_req_notifier_handler(void *opaque) 2424 { 2425 VFIOPCIDevice *vdev = opaque; 2426 2427 if (!event_notifier_test_and_clear(&vdev->req_notifier)) { 2428 return; 2429 } 2430 2431 qdev_unplug(&vdev->pdev.qdev, NULL); 2432 } 2433 2434 static void vfio_register_req_notifier(VFIOPCIDevice *vdev) 2435 { 2436 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), 2437 .index = VFIO_PCI_REQ_IRQ_INDEX }; 2438 int argsz; 2439 struct vfio_irq_set *irq_set; 2440 int32_t *pfd; 2441 2442 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { 2443 return; 2444 } 2445 2446 if (ioctl(vdev->vbasedev.fd, 2447 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { 2448 return; 2449 } 2450 2451 if (event_notifier_init(&vdev->req_notifier, 0)) { 2452 error_report("vfio: Unable to init event notifier for device request"); 2453 return; 2454 } 2455 2456 argsz = sizeof(*irq_set) + sizeof(*pfd); 2457 2458 irq_set = g_malloc0(argsz); 2459 irq_set->argsz = argsz; 2460 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2461 VFIO_IRQ_SET_ACTION_TRIGGER; 2462 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2463 irq_set->start = 0; 2464 irq_set->count = 1; 2465 pfd = (int32_t *)&irq_set->data; 2466 2467 *pfd = event_notifier_get_fd(&vdev->req_notifier); 2468 qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); 2469 2470 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2471 error_report("vfio: Failed to set up device request notification"); 2472 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2473 event_notifier_cleanup(&vdev->req_notifier); 2474 } else { 2475 vdev->req_enabled = true; 2476 } 2477 2478 g_free(irq_set); 2479 } 2480 2481 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) 2482 { 2483 int argsz; 2484 struct vfio_irq_set *irq_set; 2485 int32_t *pfd; 2486 2487 if (!vdev->req_enabled) { 2488 return; 2489 } 2490 2491 argsz = sizeof(*irq_set) + sizeof(*pfd); 2492 2493 irq_set = g_malloc0(argsz); 2494 irq_set->argsz = argsz; 2495 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2496 VFIO_IRQ_SET_ACTION_TRIGGER; 2497 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2498 irq_set->start = 0; 2499 irq_set->count = 1; 2500 pfd = (int32_t *)&irq_set->data; 2501 *pfd = -1; 2502 2503 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2504 error_report("vfio: Failed to de-assign device request fd: %m"); 2505 } 2506 g_free(irq_set); 2507 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), 2508 NULL, NULL, vdev); 2509 event_notifier_cleanup(&vdev->req_notifier); 2510 2511 vdev->req_enabled = false; 2512 } 2513 2514 static void vfio_realize(PCIDevice *pdev, Error **errp) 2515 { 2516 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2517 VFIODevice *vbasedev_iter; 2518 VFIOGroup *group; 2519 char *tmp, group_path[PATH_MAX], *group_name; 2520 Error *err = NULL; 2521 ssize_t len; 2522 struct stat st; 2523 int groupid; 2524 int i, ret; 2525 2526 if (!vdev->vbasedev.sysfsdev) { 2527 if (!(~vdev->host.domain || ~vdev->host.bus || 2528 ~vdev->host.slot || ~vdev->host.function)) { 2529 error_setg(errp, "No provided host device"); 2530 error_append_hint(errp, "Use -vfio-pci,host=DDDD:BB:DD.F " 2531 "or -vfio-pci,sysfsdev=PATH_TO_DEVICE\n"); 2532 return; 2533 } 2534 vdev->vbasedev.sysfsdev = 2535 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", 2536 vdev->host.domain, vdev->host.bus, 2537 vdev->host.slot, vdev->host.function); 2538 } 2539 2540 if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { 2541 error_setg_errno(errp, errno, "no such host device"); 2542 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.sysfsdev); 2543 return; 2544 } 2545 2546 vdev->vbasedev.name = g_strdup(basename(vdev->vbasedev.sysfsdev)); 2547 vdev->vbasedev.ops = &vfio_pci_ops; 2548 vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; 2549 2550 tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); 2551 len = readlink(tmp, group_path, sizeof(group_path)); 2552 g_free(tmp); 2553 2554 if (len <= 0 || len >= sizeof(group_path)) { 2555 error_setg_errno(errp, len < 0 ? errno : ENAMETOOLONG, 2556 "no iommu_group found"); 2557 goto error; 2558 } 2559 2560 group_path[len] = 0; 2561 2562 group_name = basename(group_path); 2563 if (sscanf(group_name, "%d", &groupid) != 1) { 2564 error_setg_errno(errp, errno, "failed to read %s", group_path); 2565 goto error; 2566 } 2567 2568 trace_vfio_realize(vdev->vbasedev.name, groupid); 2569 2570 group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev), errp); 2571 if (!group) { 2572 goto error; 2573 } 2574 2575 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2576 if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { 2577 error_setg(errp, "device is already attached"); 2578 vfio_put_group(group); 2579 goto error; 2580 } 2581 } 2582 2583 ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev, errp); 2584 if (ret) { 2585 vfio_put_group(group); 2586 goto error; 2587 } 2588 2589 vfio_populate_device(vdev, &err); 2590 if (err) { 2591 error_propagate(errp, err); 2592 goto error; 2593 } 2594 2595 /* Get a copy of config space */ 2596 ret = pread(vdev->vbasedev.fd, vdev->pdev.config, 2597 MIN(pci_config_size(&vdev->pdev), vdev->config_size), 2598 vdev->config_offset); 2599 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { 2600 ret = ret < 0 ? -errno : -EFAULT; 2601 error_setg_errno(errp, -ret, "failed to read device config space"); 2602 goto error; 2603 } 2604 2605 /* vfio emulates a lot for us, but some bits need extra love */ 2606 vdev->emulated_config_bits = g_malloc0(vdev->config_size); 2607 2608 /* QEMU can choose to expose the ROM or not */ 2609 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); 2610 2611 /* 2612 * The PCI spec reserves vendor ID 0xffff as an invalid value. The 2613 * device ID is managed by the vendor and need only be a 16-bit value. 2614 * Allow any 16-bit value for subsystem so they can be hidden or changed. 2615 */ 2616 if (vdev->vendor_id != PCI_ANY_ID) { 2617 if (vdev->vendor_id >= 0xffff) { 2618 error_setg(errp, "invalid PCI vendor ID provided"); 2619 goto error; 2620 } 2621 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); 2622 trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); 2623 } else { 2624 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2625 } 2626 2627 if (vdev->device_id != PCI_ANY_ID) { 2628 if (vdev->device_id > 0xffff) { 2629 error_setg(errp, "invalid PCI device ID provided"); 2630 goto error; 2631 } 2632 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); 2633 trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); 2634 } else { 2635 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2636 } 2637 2638 if (vdev->sub_vendor_id != PCI_ANY_ID) { 2639 if (vdev->sub_vendor_id > 0xffff) { 2640 error_setg(errp, "invalid PCI subsystem vendor ID provided"); 2641 goto error; 2642 } 2643 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, 2644 vdev->sub_vendor_id, ~0); 2645 trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, 2646 vdev->sub_vendor_id); 2647 } 2648 2649 if (vdev->sub_device_id != PCI_ANY_ID) { 2650 if (vdev->sub_device_id > 0xffff) { 2651 error_setg(errp, "invalid PCI subsystem device ID provided"); 2652 goto error; 2653 } 2654 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); 2655 trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, 2656 vdev->sub_device_id); 2657 } 2658 2659 /* QEMU can change multi-function devices to single function, or reverse */ 2660 vdev->emulated_config_bits[PCI_HEADER_TYPE] = 2661 PCI_HEADER_TYPE_MULTI_FUNCTION; 2662 2663 /* Restore or clear multifunction, this is always controlled by QEMU */ 2664 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 2665 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 2666 } else { 2667 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; 2668 } 2669 2670 /* 2671 * Clear host resource mapping info. If we choose not to register a 2672 * BAR, such as might be the case with the option ROM, we can get 2673 * confusing, unwritable, residual addresses from the host here. 2674 */ 2675 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); 2676 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); 2677 2678 vfio_pci_size_rom(vdev); 2679 2680 vfio_msix_early_setup(vdev, &err); 2681 if (err) { 2682 error_propagate(errp, err); 2683 goto error; 2684 } 2685 2686 vfio_bars_setup(vdev); 2687 2688 ret = vfio_add_capabilities(vdev, errp); 2689 if (ret) { 2690 goto out_teardown; 2691 } 2692 2693 if (vdev->vga) { 2694 vfio_vga_quirk_setup(vdev); 2695 } 2696 2697 for (i = 0; i < PCI_ROM_SLOT; i++) { 2698 vfio_bar_quirk_setup(vdev, i); 2699 } 2700 2701 if (!vdev->igd_opregion && 2702 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { 2703 struct vfio_region_info *opregion; 2704 2705 if (vdev->pdev.qdev.hotplugged) { 2706 error_setg(errp, 2707 "cannot support IGD OpRegion feature on hotplugged " 2708 "device"); 2709 goto out_teardown; 2710 } 2711 2712 ret = vfio_get_dev_region_info(&vdev->vbasedev, 2713 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 2714 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 2715 if (ret) { 2716 error_setg_errno(errp, -ret, 2717 "does not support requested IGD OpRegion feature"); 2718 goto out_teardown; 2719 } 2720 2721 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp); 2722 g_free(opregion); 2723 if (ret) { 2724 goto out_teardown; 2725 } 2726 } 2727 2728 /* QEMU emulates all of MSI & MSIX */ 2729 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { 2730 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, 2731 MSIX_CAP_LENGTH); 2732 } 2733 2734 if (pdev->cap_present & QEMU_PCI_CAP_MSI) { 2735 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, 2736 vdev->msi_cap_size); 2737 } 2738 2739 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { 2740 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 2741 vfio_intx_mmap_enable, vdev); 2742 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); 2743 ret = vfio_intx_enable(vdev, errp); 2744 if (ret) { 2745 goto out_teardown; 2746 } 2747 } 2748 2749 vfio_register_err_notifier(vdev); 2750 vfio_register_req_notifier(vdev); 2751 vfio_setup_resetfn_quirk(vdev); 2752 2753 return; 2754 2755 out_teardown: 2756 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 2757 vfio_teardown_msi(vdev); 2758 vfio_bars_exit(vdev); 2759 error: 2760 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.name); 2761 } 2762 2763 static void vfio_instance_finalize(Object *obj) 2764 { 2765 PCIDevice *pci_dev = PCI_DEVICE(obj); 2766 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev); 2767 VFIOGroup *group = vdev->vbasedev.group; 2768 2769 vfio_bars_finalize(vdev); 2770 g_free(vdev->emulated_config_bits); 2771 g_free(vdev->rom); 2772 /* 2773 * XXX Leaking igd_opregion is not an oversight, we can't remove the 2774 * fw_cfg entry therefore leaking this allocation seems like the safest 2775 * option. 2776 * 2777 * g_free(vdev->igd_opregion); 2778 */ 2779 vfio_put_device(vdev); 2780 vfio_put_group(group); 2781 } 2782 2783 static void vfio_exitfn(PCIDevice *pdev) 2784 { 2785 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2786 2787 vfio_unregister_req_notifier(vdev); 2788 vfio_unregister_err_notifier(vdev); 2789 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 2790 vfio_disable_interrupts(vdev); 2791 if (vdev->intx.mmap_timer) { 2792 timer_free(vdev->intx.mmap_timer); 2793 } 2794 vfio_teardown_msi(vdev); 2795 vfio_bars_exit(vdev); 2796 } 2797 2798 static void vfio_pci_reset(DeviceState *dev) 2799 { 2800 PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev); 2801 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2802 2803 trace_vfio_pci_reset(vdev->vbasedev.name); 2804 2805 vfio_pci_pre_reset(vdev); 2806 2807 if (vdev->resetfn && !vdev->resetfn(vdev)) { 2808 goto post_reset; 2809 } 2810 2811 if (vdev->vbasedev.reset_works && 2812 (vdev->has_flr || !vdev->has_pm_reset) && 2813 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 2814 trace_vfio_pci_reset_flr(vdev->vbasedev.name); 2815 goto post_reset; 2816 } 2817 2818 /* See if we can do our own bus reset */ 2819 if (!vfio_pci_hot_reset_one(vdev)) { 2820 goto post_reset; 2821 } 2822 2823 /* If nothing else works and the device supports PM reset, use it */ 2824 if (vdev->vbasedev.reset_works && vdev->has_pm_reset && 2825 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 2826 trace_vfio_pci_reset_pm(vdev->vbasedev.name); 2827 goto post_reset; 2828 } 2829 2830 post_reset: 2831 vfio_pci_post_reset(vdev); 2832 } 2833 2834 static void vfio_instance_init(Object *obj) 2835 { 2836 PCIDevice *pci_dev = PCI_DEVICE(obj); 2837 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj)); 2838 2839 device_add_bootindex_property(obj, &vdev->bootindex, 2840 "bootindex", NULL, 2841 &pci_dev->qdev, NULL); 2842 vdev->host.domain = ~0U; 2843 vdev->host.bus = ~0U; 2844 vdev->host.slot = ~0U; 2845 vdev->host.function = ~0U; 2846 } 2847 2848 static Property vfio_pci_dev_properties[] = { 2849 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), 2850 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), 2851 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, 2852 intx.mmap_timeout, 1100), 2853 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, 2854 VFIO_FEATURE_ENABLE_VGA_BIT, false), 2855 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, 2856 VFIO_FEATURE_ENABLE_REQ_BIT, true), 2857 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, 2858 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), 2859 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), 2860 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), 2861 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), 2862 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), 2863 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), 2864 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), 2865 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, 2866 sub_vendor_id, PCI_ANY_ID), 2867 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, 2868 sub_device_id, PCI_ANY_ID), 2869 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), 2870 /* 2871 * TODO - support passed fds... is this necessary? 2872 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), 2873 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), 2874 */ 2875 DEFINE_PROP_END_OF_LIST(), 2876 }; 2877 2878 static const VMStateDescription vfio_pci_vmstate = { 2879 .name = "vfio-pci", 2880 .unmigratable = 1, 2881 }; 2882 2883 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) 2884 { 2885 DeviceClass *dc = DEVICE_CLASS(klass); 2886 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); 2887 2888 dc->reset = vfio_pci_reset; 2889 dc->props = vfio_pci_dev_properties; 2890 dc->vmsd = &vfio_pci_vmstate; 2891 dc->desc = "VFIO-based PCI device assignment"; 2892 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 2893 pdc->realize = vfio_realize; 2894 pdc->exit = vfio_exitfn; 2895 pdc->config_read = vfio_pci_read_config; 2896 pdc->config_write = vfio_pci_write_config; 2897 pdc->is_express = 1; /* We might be */ 2898 } 2899 2900 static const TypeInfo vfio_pci_dev_info = { 2901 .name = "vfio-pci", 2902 .parent = TYPE_PCI_DEVICE, 2903 .instance_size = sizeof(VFIOPCIDevice), 2904 .class_init = vfio_pci_dev_class_init, 2905 .instance_init = vfio_instance_init, 2906 .instance_finalize = vfio_instance_finalize, 2907 }; 2908 2909 static void register_vfio_pci_dev_type(void) 2910 { 2911 type_register_static(&vfio_pci_dev_info); 2912 } 2913 2914 type_init(register_vfio_pci_dev_type) 2915