1 /* 2 * vfio based device assignment support 3 * 4 * Copyright Red Hat, Inc. 2012 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 * 12 * Based on qemu-kvm device-assignment: 13 * Adapted for KVM by Qumranet. 14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) 15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) 16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) 17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) 18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) 19 */ 20 21 #include "qemu/osdep.h" 22 #include <linux/vfio.h> 23 #include <sys/ioctl.h> 24 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "qemu/error-report.h" 29 #include "qemu/range.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/sysemu.h" 32 #include "pci.h" 33 #include "trace.h" 34 #include "qapi/error.h" 35 36 #define MSIX_CAP_LENGTH 12 37 38 static void vfio_disable_interrupts(VFIOPCIDevice *vdev); 39 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); 40 41 /* 42 * Disabling BAR mmaping can be slow, but toggling it around INTx can 43 * also be a huge overhead. We try to get the best of both worlds by 44 * waiting until an interrupt to disable mmaps (subsequent transitions 45 * to the same state are effectively no overhead). If the interrupt has 46 * been serviced and the time gap is long enough, we re-enable mmaps for 47 * performance. This works well for things like graphics cards, which 48 * may not use their interrupt at all and are penalized to an unusable 49 * level by read/write BAR traps. Other devices, like NICs, have more 50 * regular interrupts and see much better latency by staying in non-mmap 51 * mode. We therefore set the default mmap_timeout such that a ping 52 * is just enough to keep the mmap disabled. Users can experiment with 53 * other options with the x-intx-mmap-timeout-ms parameter (a value of 54 * zero disables the timer). 55 */ 56 static void vfio_intx_mmap_enable(void *opaque) 57 { 58 VFIOPCIDevice *vdev = opaque; 59 60 if (vdev->intx.pending) { 61 timer_mod(vdev->intx.mmap_timer, 62 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 63 return; 64 } 65 66 vfio_mmap_set_enabled(vdev, true); 67 } 68 69 static void vfio_intx_interrupt(void *opaque) 70 { 71 VFIOPCIDevice *vdev = opaque; 72 73 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { 74 return; 75 } 76 77 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); 78 79 vdev->intx.pending = true; 80 pci_irq_assert(&vdev->pdev); 81 vfio_mmap_set_enabled(vdev, false); 82 if (vdev->intx.mmap_timeout) { 83 timer_mod(vdev->intx.mmap_timer, 84 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 85 } 86 } 87 88 static void vfio_intx_eoi(VFIODevice *vbasedev) 89 { 90 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 91 92 if (!vdev->intx.pending) { 93 return; 94 } 95 96 trace_vfio_intx_eoi(vbasedev->name); 97 98 vdev->intx.pending = false; 99 pci_irq_deassert(&vdev->pdev); 100 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 101 } 102 103 static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp) 104 { 105 #ifdef CONFIG_KVM 106 struct kvm_irqfd irqfd = { 107 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 108 .gsi = vdev->intx.route.irq, 109 .flags = KVM_IRQFD_FLAG_RESAMPLE, 110 }; 111 struct vfio_irq_set *irq_set; 112 int ret, argsz; 113 int32_t *pfd; 114 115 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || 116 vdev->intx.route.mode != PCI_INTX_ENABLED || 117 !kvm_resamplefds_enabled()) { 118 return; 119 } 120 121 /* Get to a known interrupt state */ 122 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); 123 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 124 vdev->intx.pending = false; 125 pci_irq_deassert(&vdev->pdev); 126 127 /* Get an eventfd for resample/unmask */ 128 if (event_notifier_init(&vdev->intx.unmask, 0)) { 129 error_setg(errp, "event_notifier_init failed eoi"); 130 goto fail; 131 } 132 133 /* KVM triggers it, VFIO listens for it */ 134 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); 135 136 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 137 error_setg_errno(errp, errno, "failed to setup resample irqfd"); 138 goto fail_irqfd; 139 } 140 141 argsz = sizeof(*irq_set) + sizeof(*pfd); 142 143 irq_set = g_malloc0(argsz); 144 irq_set->argsz = argsz; 145 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; 146 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 147 irq_set->start = 0; 148 irq_set->count = 1; 149 pfd = (int32_t *)&irq_set->data; 150 151 *pfd = irqfd.resamplefd; 152 153 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 154 g_free(irq_set); 155 if (ret) { 156 error_setg_errno(errp, -ret, "failed to setup INTx unmask fd"); 157 goto fail_vfio; 158 } 159 160 /* Let'em rip */ 161 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 162 163 vdev->intx.kvm_accel = true; 164 165 trace_vfio_intx_enable_kvm(vdev->vbasedev.name); 166 167 return; 168 169 fail_vfio: 170 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; 171 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); 172 fail_irqfd: 173 event_notifier_cleanup(&vdev->intx.unmask); 174 fail: 175 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 176 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 177 #endif 178 } 179 180 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) 181 { 182 #ifdef CONFIG_KVM 183 struct kvm_irqfd irqfd = { 184 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 185 .gsi = vdev->intx.route.irq, 186 .flags = KVM_IRQFD_FLAG_DEASSIGN, 187 }; 188 189 if (!vdev->intx.kvm_accel) { 190 return; 191 } 192 193 /* 194 * Get to a known state, hardware masked, QEMU ready to accept new 195 * interrupts, QEMU IRQ de-asserted. 196 */ 197 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 198 vdev->intx.pending = false; 199 pci_irq_deassert(&vdev->pdev); 200 201 /* Tell KVM to stop listening for an INTx irqfd */ 202 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 203 error_report("vfio: Error: Failed to disable INTx irqfd: %m"); 204 } 205 206 /* We only need to close the eventfd for VFIO to cleanup the kernel side */ 207 event_notifier_cleanup(&vdev->intx.unmask); 208 209 /* QEMU starts listening for interrupt events. */ 210 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 211 212 vdev->intx.kvm_accel = false; 213 214 /* If we've missed an event, let it re-fire through QEMU */ 215 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 216 217 trace_vfio_intx_disable_kvm(vdev->vbasedev.name); 218 #endif 219 } 220 221 static void vfio_intx_update(PCIDevice *pdev) 222 { 223 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 224 PCIINTxRoute route; 225 Error *err = NULL; 226 227 if (vdev->interrupt != VFIO_INT_INTx) { 228 return; 229 } 230 231 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); 232 233 if (!pci_intx_route_changed(&vdev->intx.route, &route)) { 234 return; /* Nothing changed */ 235 } 236 237 trace_vfio_intx_update(vdev->vbasedev.name, 238 vdev->intx.route.irq, route.irq); 239 240 vfio_intx_disable_kvm(vdev); 241 242 vdev->intx.route = route; 243 244 if (route.mode != PCI_INTX_ENABLED) { 245 return; 246 } 247 248 vfio_intx_enable_kvm(vdev, &err); 249 if (err) { 250 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); 251 } 252 253 /* Re-enable the interrupt in cased we missed an EOI */ 254 vfio_intx_eoi(&vdev->vbasedev); 255 } 256 257 static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp) 258 { 259 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); 260 int ret, argsz, retval = 0; 261 struct vfio_irq_set *irq_set; 262 int32_t *pfd; 263 Error *err = NULL; 264 265 if (!pin) { 266 return 0; 267 } 268 269 vfio_disable_interrupts(vdev); 270 271 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ 272 pci_config_set_interrupt_pin(vdev->pdev.config, pin); 273 274 #ifdef CONFIG_KVM 275 /* 276 * Only conditional to avoid generating error messages on platforms 277 * where we won't actually use the result anyway. 278 */ 279 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { 280 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, 281 vdev->intx.pin); 282 } 283 #endif 284 285 ret = event_notifier_init(&vdev->intx.interrupt, 0); 286 if (ret) { 287 error_setg_errno(errp, -ret, "event_notifier_init failed"); 288 return ret; 289 } 290 291 argsz = sizeof(*irq_set) + sizeof(*pfd); 292 293 irq_set = g_malloc0(argsz); 294 irq_set->argsz = argsz; 295 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 296 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 297 irq_set->start = 0; 298 irq_set->count = 1; 299 pfd = (int32_t *)&irq_set->data; 300 301 *pfd = event_notifier_get_fd(&vdev->intx.interrupt); 302 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); 303 304 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 305 if (ret) { 306 error_setg_errno(errp, -ret, "failed to setup INTx fd"); 307 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 308 event_notifier_cleanup(&vdev->intx.interrupt); 309 retval = -errno; 310 goto cleanup; 311 } 312 313 vfio_intx_enable_kvm(vdev, &err); 314 if (err) { 315 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); 316 } 317 318 vdev->interrupt = VFIO_INT_INTx; 319 320 trace_vfio_intx_enable(vdev->vbasedev.name); 321 322 cleanup: 323 g_free(irq_set); 324 325 return retval; 326 } 327 328 static void vfio_intx_disable(VFIOPCIDevice *vdev) 329 { 330 int fd; 331 332 timer_del(vdev->intx.mmap_timer); 333 vfio_intx_disable_kvm(vdev); 334 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 335 vdev->intx.pending = false; 336 pci_irq_deassert(&vdev->pdev); 337 vfio_mmap_set_enabled(vdev, true); 338 339 fd = event_notifier_get_fd(&vdev->intx.interrupt); 340 qemu_set_fd_handler(fd, NULL, NULL, vdev); 341 event_notifier_cleanup(&vdev->intx.interrupt); 342 343 vdev->interrupt = VFIO_INT_NONE; 344 345 trace_vfio_intx_disable(vdev->vbasedev.name); 346 } 347 348 /* 349 * MSI/X 350 */ 351 static void vfio_msi_interrupt(void *opaque) 352 { 353 VFIOMSIVector *vector = opaque; 354 VFIOPCIDevice *vdev = vector->vdev; 355 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); 356 void (*notify)(PCIDevice *dev, unsigned vector); 357 MSIMessage msg; 358 int nr = vector - vdev->msi_vectors; 359 360 if (!event_notifier_test_and_clear(&vector->interrupt)) { 361 return; 362 } 363 364 if (vdev->interrupt == VFIO_INT_MSIX) { 365 get_msg = msix_get_message; 366 notify = msix_notify; 367 368 /* A masked vector firing needs to use the PBA, enable it */ 369 if (msix_is_masked(&vdev->pdev, nr)) { 370 set_bit(nr, vdev->msix->pending); 371 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); 372 trace_vfio_msix_pba_enable(vdev->vbasedev.name); 373 } 374 } else if (vdev->interrupt == VFIO_INT_MSI) { 375 get_msg = msi_get_message; 376 notify = msi_notify; 377 } else { 378 abort(); 379 } 380 381 msg = get_msg(&vdev->pdev, nr); 382 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); 383 notify(&vdev->pdev, nr); 384 } 385 386 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) 387 { 388 struct vfio_irq_set *irq_set; 389 int ret = 0, i, argsz; 390 int32_t *fds; 391 392 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); 393 394 irq_set = g_malloc0(argsz); 395 irq_set->argsz = argsz; 396 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 397 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; 398 irq_set->start = 0; 399 irq_set->count = vdev->nr_vectors; 400 fds = (int32_t *)&irq_set->data; 401 402 for (i = 0; i < vdev->nr_vectors; i++) { 403 int fd = -1; 404 405 /* 406 * MSI vs MSI-X - The guest has direct access to MSI mask and pending 407 * bits, therefore we always use the KVM signaling path when setup. 408 * MSI-X mask and pending bits are emulated, so we want to use the 409 * KVM signaling path only when configured and unmasked. 410 */ 411 if (vdev->msi_vectors[i].use) { 412 if (vdev->msi_vectors[i].virq < 0 || 413 (msix && msix_is_masked(&vdev->pdev, i))) { 414 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); 415 } else { 416 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); 417 } 418 } 419 420 fds[i] = fd; 421 } 422 423 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 424 425 g_free(irq_set); 426 427 return ret; 428 } 429 430 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, 431 int vector_n, bool msix) 432 { 433 int virq; 434 435 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { 436 return; 437 } 438 439 if (event_notifier_init(&vector->kvm_interrupt, 0)) { 440 return; 441 } 442 443 virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); 444 if (virq < 0) { 445 event_notifier_cleanup(&vector->kvm_interrupt); 446 return; 447 } 448 449 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 450 NULL, virq) < 0) { 451 kvm_irqchip_release_virq(kvm_state, virq); 452 event_notifier_cleanup(&vector->kvm_interrupt); 453 return; 454 } 455 456 vector->virq = virq; 457 } 458 459 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) 460 { 461 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 462 vector->virq); 463 kvm_irqchip_release_virq(kvm_state, vector->virq); 464 vector->virq = -1; 465 event_notifier_cleanup(&vector->kvm_interrupt); 466 } 467 468 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, 469 PCIDevice *pdev) 470 { 471 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); 472 kvm_irqchip_commit_routes(kvm_state); 473 } 474 475 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, 476 MSIMessage *msg, IOHandler *handler) 477 { 478 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 479 VFIOMSIVector *vector; 480 int ret; 481 482 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); 483 484 vector = &vdev->msi_vectors[nr]; 485 486 if (!vector->use) { 487 vector->vdev = vdev; 488 vector->virq = -1; 489 if (event_notifier_init(&vector->interrupt, 0)) { 490 error_report("vfio: Error: event_notifier_init failed"); 491 } 492 vector->use = true; 493 msix_vector_use(pdev, nr); 494 } 495 496 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 497 handler, NULL, vector); 498 499 /* 500 * Attempt to enable route through KVM irqchip, 501 * default to userspace handling if unavailable. 502 */ 503 if (vector->virq >= 0) { 504 if (!msg) { 505 vfio_remove_kvm_msi_virq(vector); 506 } else { 507 vfio_update_kvm_msi_virq(vector, *msg, pdev); 508 } 509 } else { 510 if (msg) { 511 vfio_add_kvm_msi_virq(vdev, vector, nr, true); 512 } 513 } 514 515 /* 516 * We don't want to have the host allocate all possible MSI vectors 517 * for a device if they're not in use, so we shutdown and incrementally 518 * increase them as needed. 519 */ 520 if (vdev->nr_vectors < nr + 1) { 521 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 522 vdev->nr_vectors = nr + 1; 523 ret = vfio_enable_vectors(vdev, true); 524 if (ret) { 525 error_report("vfio: failed to enable vectors, %d", ret); 526 } 527 } else { 528 int argsz; 529 struct vfio_irq_set *irq_set; 530 int32_t *pfd; 531 532 argsz = sizeof(*irq_set) + sizeof(*pfd); 533 534 irq_set = g_malloc0(argsz); 535 irq_set->argsz = argsz; 536 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 537 VFIO_IRQ_SET_ACTION_TRIGGER; 538 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 539 irq_set->start = nr; 540 irq_set->count = 1; 541 pfd = (int32_t *)&irq_set->data; 542 543 if (vector->virq >= 0) { 544 *pfd = event_notifier_get_fd(&vector->kvm_interrupt); 545 } else { 546 *pfd = event_notifier_get_fd(&vector->interrupt); 547 } 548 549 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 550 g_free(irq_set); 551 if (ret) { 552 error_report("vfio: failed to modify vector, %d", ret); 553 } 554 } 555 556 /* Disable PBA emulation when nothing more is pending. */ 557 clear_bit(nr, vdev->msix->pending); 558 if (find_first_bit(vdev->msix->pending, 559 vdev->nr_vectors) == vdev->nr_vectors) { 560 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 561 trace_vfio_msix_pba_disable(vdev->vbasedev.name); 562 } 563 564 return 0; 565 } 566 567 static int vfio_msix_vector_use(PCIDevice *pdev, 568 unsigned int nr, MSIMessage msg) 569 { 570 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); 571 } 572 573 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) 574 { 575 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 576 VFIOMSIVector *vector = &vdev->msi_vectors[nr]; 577 578 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); 579 580 /* 581 * There are still old guests that mask and unmask vectors on every 582 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of 583 * the KVM setup in place, simply switch VFIO to use the non-bypass 584 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X 585 * core will mask the interrupt and set pending bits, allowing it to 586 * be re-asserted on unmask. Nothing to do if already using QEMU mode. 587 */ 588 if (vector->virq >= 0) { 589 int argsz; 590 struct vfio_irq_set *irq_set; 591 int32_t *pfd; 592 593 argsz = sizeof(*irq_set) + sizeof(*pfd); 594 595 irq_set = g_malloc0(argsz); 596 irq_set->argsz = argsz; 597 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 598 VFIO_IRQ_SET_ACTION_TRIGGER; 599 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 600 irq_set->start = nr; 601 irq_set->count = 1; 602 pfd = (int32_t *)&irq_set->data; 603 604 *pfd = event_notifier_get_fd(&vector->interrupt); 605 606 ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 607 608 g_free(irq_set); 609 } 610 } 611 612 static void vfio_msix_enable(VFIOPCIDevice *vdev) 613 { 614 vfio_disable_interrupts(vdev); 615 616 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); 617 618 vdev->interrupt = VFIO_INT_MSIX; 619 620 /* 621 * Some communication channels between VF & PF or PF & fw rely on the 622 * physical state of the device and expect that enabling MSI-X from the 623 * guest enables the same on the host. When our guest is Linux, the 624 * guest driver call to pci_enable_msix() sets the enabling bit in the 625 * MSI-X capability, but leaves the vector table masked. We therefore 626 * can't rely on a vector_use callback (from request_irq() in the guest) 627 * to switch the physical device into MSI-X mode because that may come a 628 * long time after pci_enable_msix(). This code enables vector 0 with 629 * triggering to userspace, then immediately release the vector, leaving 630 * the physical device with no vectors enabled, but MSI-X enabled, just 631 * like the guest view. 632 */ 633 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); 634 vfio_msix_vector_release(&vdev->pdev, 0); 635 636 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, 637 vfio_msix_vector_release, NULL)) { 638 error_report("vfio: msix_set_vector_notifiers failed"); 639 } 640 641 trace_vfio_msix_enable(vdev->vbasedev.name); 642 } 643 644 static void vfio_msi_enable(VFIOPCIDevice *vdev) 645 { 646 int ret, i; 647 648 vfio_disable_interrupts(vdev); 649 650 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); 651 retry: 652 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); 653 654 for (i = 0; i < vdev->nr_vectors; i++) { 655 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 656 657 vector->vdev = vdev; 658 vector->virq = -1; 659 vector->use = true; 660 661 if (event_notifier_init(&vector->interrupt, 0)) { 662 error_report("vfio: Error: event_notifier_init failed"); 663 } 664 665 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 666 vfio_msi_interrupt, NULL, vector); 667 668 /* 669 * Attempt to enable route through KVM irqchip, 670 * default to userspace handling if unavailable. 671 */ 672 vfio_add_kvm_msi_virq(vdev, vector, i, false); 673 } 674 675 /* Set interrupt type prior to possible interrupts */ 676 vdev->interrupt = VFIO_INT_MSI; 677 678 ret = vfio_enable_vectors(vdev, false); 679 if (ret) { 680 if (ret < 0) { 681 error_report("vfio: Error: Failed to setup MSI fds: %m"); 682 } else if (ret != vdev->nr_vectors) { 683 error_report("vfio: Error: Failed to enable %d " 684 "MSI vectors, retry with %d", vdev->nr_vectors, ret); 685 } 686 687 for (i = 0; i < vdev->nr_vectors; i++) { 688 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 689 if (vector->virq >= 0) { 690 vfio_remove_kvm_msi_virq(vector); 691 } 692 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 693 NULL, NULL, NULL); 694 event_notifier_cleanup(&vector->interrupt); 695 } 696 697 g_free(vdev->msi_vectors); 698 699 if (ret > 0 && ret != vdev->nr_vectors) { 700 vdev->nr_vectors = ret; 701 goto retry; 702 } 703 vdev->nr_vectors = 0; 704 705 /* 706 * Failing to setup MSI doesn't really fall within any specification. 707 * Let's try leaving interrupts disabled and hope the guest figures 708 * out to fall back to INTx for this device. 709 */ 710 error_report("vfio: Error: Failed to enable MSI"); 711 vdev->interrupt = VFIO_INT_NONE; 712 713 return; 714 } 715 716 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); 717 } 718 719 static void vfio_msi_disable_common(VFIOPCIDevice *vdev) 720 { 721 Error *err = NULL; 722 int i; 723 724 for (i = 0; i < vdev->nr_vectors; i++) { 725 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 726 if (vdev->msi_vectors[i].use) { 727 if (vector->virq >= 0) { 728 vfio_remove_kvm_msi_virq(vector); 729 } 730 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 731 NULL, NULL, NULL); 732 event_notifier_cleanup(&vector->interrupt); 733 } 734 } 735 736 g_free(vdev->msi_vectors); 737 vdev->msi_vectors = NULL; 738 vdev->nr_vectors = 0; 739 vdev->interrupt = VFIO_INT_NONE; 740 741 vfio_intx_enable(vdev, &err); 742 if (err) { 743 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); 744 } 745 } 746 747 static void vfio_msix_disable(VFIOPCIDevice *vdev) 748 { 749 int i; 750 751 msix_unset_vector_notifiers(&vdev->pdev); 752 753 /* 754 * MSI-X will only release vectors if MSI-X is still enabled on the 755 * device, check through the rest and release it ourselves if necessary. 756 */ 757 for (i = 0; i < vdev->nr_vectors; i++) { 758 if (vdev->msi_vectors[i].use) { 759 vfio_msix_vector_release(&vdev->pdev, i); 760 msix_vector_unuse(&vdev->pdev, i); 761 } 762 } 763 764 if (vdev->nr_vectors) { 765 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 766 } 767 768 vfio_msi_disable_common(vdev); 769 770 memset(vdev->msix->pending, 0, 771 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); 772 773 trace_vfio_msix_disable(vdev->vbasedev.name); 774 } 775 776 static void vfio_msi_disable(VFIOPCIDevice *vdev) 777 { 778 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); 779 vfio_msi_disable_common(vdev); 780 781 trace_vfio_msi_disable(vdev->vbasedev.name); 782 } 783 784 static void vfio_update_msi(VFIOPCIDevice *vdev) 785 { 786 int i; 787 788 for (i = 0; i < vdev->nr_vectors; i++) { 789 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 790 MSIMessage msg; 791 792 if (!vector->use || vector->virq < 0) { 793 continue; 794 } 795 796 msg = msi_get_message(&vdev->pdev, i); 797 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); 798 } 799 } 800 801 static void vfio_pci_load_rom(VFIOPCIDevice *vdev) 802 { 803 struct vfio_region_info *reg_info; 804 uint64_t size; 805 off_t off = 0; 806 ssize_t bytes; 807 808 if (vfio_get_region_info(&vdev->vbasedev, 809 VFIO_PCI_ROM_REGION_INDEX, ®_info)) { 810 error_report("vfio: Error getting ROM info: %m"); 811 return; 812 } 813 814 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, 815 (unsigned long)reg_info->offset, 816 (unsigned long)reg_info->flags); 817 818 vdev->rom_size = size = reg_info->size; 819 vdev->rom_offset = reg_info->offset; 820 821 g_free(reg_info); 822 823 if (!vdev->rom_size) { 824 vdev->rom_read_failed = true; 825 error_report("vfio-pci: Cannot read device rom at " 826 "%s", vdev->vbasedev.name); 827 error_printf("Device option ROM contents are probably invalid " 828 "(check dmesg).\nSkip option ROM probe with rombar=0, " 829 "or load from file with romfile=\n"); 830 return; 831 } 832 833 vdev->rom = g_malloc(size); 834 memset(vdev->rom, 0xff, size); 835 836 while (size) { 837 bytes = pread(vdev->vbasedev.fd, vdev->rom + off, 838 size, vdev->rom_offset + off); 839 if (bytes == 0) { 840 break; 841 } else if (bytes > 0) { 842 off += bytes; 843 size -= bytes; 844 } else { 845 if (errno == EINTR || errno == EAGAIN) { 846 continue; 847 } 848 error_report("vfio: Error reading device ROM: %m"); 849 break; 850 } 851 } 852 853 /* 854 * Test the ROM signature against our device, if the vendor is correct 855 * but the device ID doesn't match, store the correct device ID and 856 * recompute the checksum. Intel IGD devices need this and are known 857 * to have bogus checksums so we can't simply adjust the checksum. 858 */ 859 if (pci_get_word(vdev->rom) == 0xaa55 && 860 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && 861 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { 862 uint16_t vid, did; 863 864 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); 865 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); 866 867 if (vid == vdev->vendor_id && did != vdev->device_id) { 868 int i; 869 uint8_t csum, *data = vdev->rom; 870 871 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, 872 vdev->device_id); 873 data[6] = 0; 874 875 for (csum = 0, i = 0; i < vdev->rom_size; i++) { 876 csum += data[i]; 877 } 878 879 data[6] = -csum; 880 } 881 } 882 } 883 884 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) 885 { 886 VFIOPCIDevice *vdev = opaque; 887 union { 888 uint8_t byte; 889 uint16_t word; 890 uint32_t dword; 891 uint64_t qword; 892 } val; 893 uint64_t data = 0; 894 895 /* Load the ROM lazily when the guest tries to read it */ 896 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { 897 vfio_pci_load_rom(vdev); 898 } 899 900 memcpy(&val, vdev->rom + addr, 901 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); 902 903 switch (size) { 904 case 1: 905 data = val.byte; 906 break; 907 case 2: 908 data = le16_to_cpu(val.word); 909 break; 910 case 4: 911 data = le32_to_cpu(val.dword); 912 break; 913 default: 914 hw_error("vfio: unsupported read size, %d bytes\n", size); 915 break; 916 } 917 918 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); 919 920 return data; 921 } 922 923 static void vfio_rom_write(void *opaque, hwaddr addr, 924 uint64_t data, unsigned size) 925 { 926 } 927 928 static const MemoryRegionOps vfio_rom_ops = { 929 .read = vfio_rom_read, 930 .write = vfio_rom_write, 931 .endianness = DEVICE_LITTLE_ENDIAN, 932 }; 933 934 static void vfio_pci_size_rom(VFIOPCIDevice *vdev) 935 { 936 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); 937 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; 938 DeviceState *dev = DEVICE(vdev); 939 char *name; 940 int fd = vdev->vbasedev.fd; 941 942 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { 943 /* Since pci handles romfile, just print a message and return */ 944 if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { 945 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n", 946 vdev->vbasedev.name); 947 } 948 return; 949 } 950 951 /* 952 * Use the same size ROM BAR as the physical device. The contents 953 * will get filled in later when the guest tries to read it. 954 */ 955 if (pread(fd, &orig, 4, offset) != 4 || 956 pwrite(fd, &size, 4, offset) != 4 || 957 pread(fd, &size, 4, offset) != 4 || 958 pwrite(fd, &orig, 4, offset) != 4) { 959 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); 960 return; 961 } 962 963 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; 964 965 if (!size) { 966 return; 967 } 968 969 if (vfio_blacklist_opt_rom(vdev)) { 970 if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { 971 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n", 972 vdev->vbasedev.name); 973 } else { 974 error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n", 975 vdev->vbasedev.name); 976 return; 977 } 978 } 979 980 trace_vfio_pci_size_rom(vdev->vbasedev.name, size); 981 982 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); 983 984 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), 985 &vfio_rom_ops, vdev, name, size); 986 g_free(name); 987 988 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, 989 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); 990 991 vdev->pdev.has_rom = true; 992 vdev->rom_read_failed = false; 993 } 994 995 void vfio_vga_write(void *opaque, hwaddr addr, 996 uint64_t data, unsigned size) 997 { 998 VFIOVGARegion *region = opaque; 999 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1000 union { 1001 uint8_t byte; 1002 uint16_t word; 1003 uint32_t dword; 1004 uint64_t qword; 1005 } buf; 1006 off_t offset = vga->fd_offset + region->offset + addr; 1007 1008 switch (size) { 1009 case 1: 1010 buf.byte = data; 1011 break; 1012 case 2: 1013 buf.word = cpu_to_le16(data); 1014 break; 1015 case 4: 1016 buf.dword = cpu_to_le32(data); 1017 break; 1018 default: 1019 hw_error("vfio: unsupported write size, %d bytes", size); 1020 break; 1021 } 1022 1023 if (pwrite(vga->fd, &buf, size, offset) != size) { 1024 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", 1025 __func__, region->offset + addr, data, size); 1026 } 1027 1028 trace_vfio_vga_write(region->offset + addr, data, size); 1029 } 1030 1031 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) 1032 { 1033 VFIOVGARegion *region = opaque; 1034 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1035 union { 1036 uint8_t byte; 1037 uint16_t word; 1038 uint32_t dword; 1039 uint64_t qword; 1040 } buf; 1041 uint64_t data = 0; 1042 off_t offset = vga->fd_offset + region->offset + addr; 1043 1044 if (pread(vga->fd, &buf, size, offset) != size) { 1045 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", 1046 __func__, region->offset + addr, size); 1047 return (uint64_t)-1; 1048 } 1049 1050 switch (size) { 1051 case 1: 1052 data = buf.byte; 1053 break; 1054 case 2: 1055 data = le16_to_cpu(buf.word); 1056 break; 1057 case 4: 1058 data = le32_to_cpu(buf.dword); 1059 break; 1060 default: 1061 hw_error("vfio: unsupported read size, %d bytes", size); 1062 break; 1063 } 1064 1065 trace_vfio_vga_read(region->offset + addr, size, data); 1066 1067 return data; 1068 } 1069 1070 static const MemoryRegionOps vfio_vga_ops = { 1071 .read = vfio_vga_read, 1072 .write = vfio_vga_write, 1073 .endianness = DEVICE_LITTLE_ENDIAN, 1074 }; 1075 1076 /* 1077 * Expand memory region of sub-page(size < PAGE_SIZE) MMIO BAR to page 1078 * size if the BAR is in an exclusive page in host so that we could map 1079 * this BAR to guest. But this sub-page BAR may not occupy an exclusive 1080 * page in guest. So we should set the priority of the expanded memory 1081 * region to zero in case of overlap with BARs which share the same page 1082 * with the sub-page BAR in guest. Besides, we should also recover the 1083 * size of this sub-page BAR when its base address is changed in guest 1084 * and not page aligned any more. 1085 */ 1086 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar) 1087 { 1088 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 1089 VFIORegion *region = &vdev->bars[bar].region; 1090 MemoryRegion *mmap_mr, *region_mr, *base_mr; 1091 PCIIORegion *r; 1092 pcibus_t bar_addr; 1093 uint64_t size = region->size; 1094 1095 /* Make sure that the whole region is allowed to be mmapped */ 1096 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap || 1097 region->mmaps[0].size != region->size) { 1098 return; 1099 } 1100 1101 r = &pdev->io_regions[bar]; 1102 bar_addr = r->addr; 1103 base_mr = vdev->bars[bar].mr; 1104 region_mr = region->mem; 1105 mmap_mr = ®ion->mmaps[0].mem; 1106 1107 /* If BAR is mapped and page aligned, update to fill PAGE_SIZE */ 1108 if (bar_addr != PCI_BAR_UNMAPPED && 1109 !(bar_addr & ~qemu_real_host_page_mask)) { 1110 size = qemu_real_host_page_size; 1111 } 1112 1113 memory_region_transaction_begin(); 1114 1115 if (vdev->bars[bar].size < size) { 1116 memory_region_set_size(base_mr, size); 1117 } 1118 memory_region_set_size(region_mr, size); 1119 memory_region_set_size(mmap_mr, size); 1120 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) { 1121 memory_region_del_subregion(r->address_space, base_mr); 1122 memory_region_add_subregion_overlap(r->address_space, 1123 bar_addr, base_mr, 0); 1124 } 1125 1126 memory_region_transaction_commit(); 1127 } 1128 1129 /* 1130 * PCI config space 1131 */ 1132 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) 1133 { 1134 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 1135 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; 1136 1137 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); 1138 emu_bits = le32_to_cpu(emu_bits); 1139 1140 if (emu_bits) { 1141 emu_val = pci_default_read_config(pdev, addr, len); 1142 } 1143 1144 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { 1145 ssize_t ret; 1146 1147 ret = pread(vdev->vbasedev.fd, &phys_val, len, 1148 vdev->config_offset + addr); 1149 if (ret != len) { 1150 error_report("%s(%s, 0x%x, 0x%x) failed: %m", 1151 __func__, vdev->vbasedev.name, addr, len); 1152 return -errno; 1153 } 1154 phys_val = le32_to_cpu(phys_val); 1155 } 1156 1157 val = (emu_val & emu_bits) | (phys_val & ~emu_bits); 1158 1159 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); 1160 1161 return val; 1162 } 1163 1164 void vfio_pci_write_config(PCIDevice *pdev, 1165 uint32_t addr, uint32_t val, int len) 1166 { 1167 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 1168 uint32_t val_le = cpu_to_le32(val); 1169 1170 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); 1171 1172 /* Write everything to VFIO, let it filter out what we can't write */ 1173 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) 1174 != len) { 1175 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", 1176 __func__, vdev->vbasedev.name, addr, val, len); 1177 } 1178 1179 /* MSI/MSI-X Enabling/Disabling */ 1180 if (pdev->cap_present & QEMU_PCI_CAP_MSI && 1181 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { 1182 int is_enabled, was_enabled = msi_enabled(pdev); 1183 1184 pci_default_write_config(pdev, addr, val, len); 1185 1186 is_enabled = msi_enabled(pdev); 1187 1188 if (!was_enabled) { 1189 if (is_enabled) { 1190 vfio_msi_enable(vdev); 1191 } 1192 } else { 1193 if (!is_enabled) { 1194 vfio_msi_disable(vdev); 1195 } else { 1196 vfio_update_msi(vdev); 1197 } 1198 } 1199 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && 1200 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { 1201 int is_enabled, was_enabled = msix_enabled(pdev); 1202 1203 pci_default_write_config(pdev, addr, val, len); 1204 1205 is_enabled = msix_enabled(pdev); 1206 1207 if (!was_enabled && is_enabled) { 1208 vfio_msix_enable(vdev); 1209 } else if (was_enabled && !is_enabled) { 1210 vfio_msix_disable(vdev); 1211 } 1212 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) || 1213 range_covers_byte(addr, len, PCI_COMMAND)) { 1214 pcibus_t old_addr[PCI_NUM_REGIONS - 1]; 1215 int bar; 1216 1217 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1218 old_addr[bar] = pdev->io_regions[bar].addr; 1219 } 1220 1221 pci_default_write_config(pdev, addr, val, len); 1222 1223 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1224 if (old_addr[bar] != pdev->io_regions[bar].addr && 1225 vdev->bars[bar].region.size > 0 && 1226 vdev->bars[bar].region.size < qemu_real_host_page_size) { 1227 vfio_sub_page_bar_update_mapping(pdev, bar); 1228 } 1229 } 1230 } else { 1231 /* Write everything to QEMU to keep emulated bits correct */ 1232 pci_default_write_config(pdev, addr, val, len); 1233 } 1234 } 1235 1236 /* 1237 * Interrupt setup 1238 */ 1239 static void vfio_disable_interrupts(VFIOPCIDevice *vdev) 1240 { 1241 /* 1242 * More complicated than it looks. Disabling MSI/X transitions the 1243 * device to INTx mode (if supported). Therefore we need to first 1244 * disable MSI/X and then cleanup by disabling INTx. 1245 */ 1246 if (vdev->interrupt == VFIO_INT_MSIX) { 1247 vfio_msix_disable(vdev); 1248 } else if (vdev->interrupt == VFIO_INT_MSI) { 1249 vfio_msi_disable(vdev); 1250 } 1251 1252 if (vdev->interrupt == VFIO_INT_INTx) { 1253 vfio_intx_disable(vdev); 1254 } 1255 } 1256 1257 static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1258 { 1259 uint16_t ctrl; 1260 bool msi_64bit, msi_maskbit; 1261 int ret, entries; 1262 Error *err = NULL; 1263 1264 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), 1265 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { 1266 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); 1267 return -errno; 1268 } 1269 ctrl = le16_to_cpu(ctrl); 1270 1271 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); 1272 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); 1273 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); 1274 1275 trace_vfio_msi_setup(vdev->vbasedev.name, pos); 1276 1277 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err); 1278 if (ret < 0) { 1279 if (ret == -ENOTSUP) { 1280 return 0; 1281 } 1282 error_prepend(&err, "msi_init failed: "); 1283 error_propagate(errp, err); 1284 return ret; 1285 } 1286 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); 1287 1288 return 0; 1289 } 1290 1291 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) 1292 { 1293 off_t start, end; 1294 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; 1295 1296 /* 1297 * We expect to find a single mmap covering the whole BAR, anything else 1298 * means it's either unsupported or already setup. 1299 */ 1300 if (region->nr_mmaps != 1 || region->mmaps[0].offset || 1301 region->size != region->mmaps[0].size) { 1302 return; 1303 } 1304 1305 /* MSI-X table start and end aligned to host page size */ 1306 start = vdev->msix->table_offset & qemu_real_host_page_mask; 1307 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + 1308 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); 1309 1310 /* 1311 * Does the MSI-X table cover the beginning of the BAR? The whole BAR? 1312 * NB - Host page size is necessarily a power of two and so is the PCI 1313 * BAR (not counting EA yet), therefore if we have host page aligned 1314 * @start and @end, then any remainder of the BAR before or after those 1315 * must be at least host page sized and therefore mmap'able. 1316 */ 1317 if (!start) { 1318 if (end >= region->size) { 1319 region->nr_mmaps = 0; 1320 g_free(region->mmaps); 1321 region->mmaps = NULL; 1322 trace_vfio_msix_fixup(vdev->vbasedev.name, 1323 vdev->msix->table_bar, 0, 0); 1324 } else { 1325 region->mmaps[0].offset = end; 1326 region->mmaps[0].size = region->size - end; 1327 trace_vfio_msix_fixup(vdev->vbasedev.name, 1328 vdev->msix->table_bar, region->mmaps[0].offset, 1329 region->mmaps[0].offset + region->mmaps[0].size); 1330 } 1331 1332 /* Maybe it's aligned at the end of the BAR */ 1333 } else if (end >= region->size) { 1334 region->mmaps[0].size = start; 1335 trace_vfio_msix_fixup(vdev->vbasedev.name, 1336 vdev->msix->table_bar, region->mmaps[0].offset, 1337 region->mmaps[0].offset + region->mmaps[0].size); 1338 1339 /* Otherwise it must split the BAR */ 1340 } else { 1341 region->nr_mmaps = 2; 1342 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); 1343 1344 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); 1345 1346 region->mmaps[0].size = start; 1347 trace_vfio_msix_fixup(vdev->vbasedev.name, 1348 vdev->msix->table_bar, region->mmaps[0].offset, 1349 region->mmaps[0].offset + region->mmaps[0].size); 1350 1351 region->mmaps[1].offset = end; 1352 region->mmaps[1].size = region->size - end; 1353 trace_vfio_msix_fixup(vdev->vbasedev.name, 1354 vdev->msix->table_bar, region->mmaps[1].offset, 1355 region->mmaps[1].offset + region->mmaps[1].size); 1356 } 1357 } 1358 1359 /* 1360 * We don't have any control over how pci_add_capability() inserts 1361 * capabilities into the chain. In order to setup MSI-X we need a 1362 * MemoryRegion for the BAR. In order to setup the BAR and not 1363 * attempt to mmap the MSI-X table area, which VFIO won't allow, we 1364 * need to first look for where the MSI-X table lives. So we 1365 * unfortunately split MSI-X setup across two functions. 1366 */ 1367 static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) 1368 { 1369 uint8_t pos; 1370 uint16_t ctrl; 1371 uint32_t table, pba; 1372 int fd = vdev->vbasedev.fd; 1373 VFIOMSIXInfo *msix; 1374 1375 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); 1376 if (!pos) { 1377 return; 1378 } 1379 1380 if (pread(fd, &ctrl, sizeof(ctrl), 1381 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { 1382 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS"); 1383 return; 1384 } 1385 1386 if (pread(fd, &table, sizeof(table), 1387 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { 1388 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE"); 1389 return; 1390 } 1391 1392 if (pread(fd, &pba, sizeof(pba), 1393 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { 1394 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA"); 1395 return; 1396 } 1397 1398 ctrl = le16_to_cpu(ctrl); 1399 table = le32_to_cpu(table); 1400 pba = le32_to_cpu(pba); 1401 1402 msix = g_malloc0(sizeof(*msix)); 1403 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 1404 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 1405 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 1406 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 1407 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 1408 1409 /* 1410 * Test the size of the pba_offset variable and catch if it extends outside 1411 * of the specified BAR. If it is the case, we need to apply a hardware 1412 * specific quirk if the device is known or we have a broken configuration. 1413 */ 1414 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { 1415 /* 1416 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 1417 * adapters. The T5 hardware returns an incorrect value of 0x8000 for 1418 * the VF PBA offset while the BAR itself is only 8k. The correct value 1419 * is 0x1000, so we hard code that here. 1420 */ 1421 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && 1422 (vdev->device_id & 0xff00) == 0x5800) { 1423 msix->pba_offset = 0x1000; 1424 } else { 1425 error_setg(errp, "hardware reports invalid configuration, " 1426 "MSIX PBA outside of specified BAR"); 1427 g_free(msix); 1428 return; 1429 } 1430 } 1431 1432 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, 1433 msix->table_offset, msix->entries); 1434 vdev->msix = msix; 1435 1436 vfio_pci_fixup_msix_region(vdev); 1437 } 1438 1439 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1440 { 1441 int ret; 1442 Error *err = NULL; 1443 1444 vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * 1445 sizeof(unsigned long)); 1446 ret = msix_init(&vdev->pdev, vdev->msix->entries, 1447 vdev->bars[vdev->msix->table_bar].mr, 1448 vdev->msix->table_bar, vdev->msix->table_offset, 1449 vdev->bars[vdev->msix->pba_bar].mr, 1450 vdev->msix->pba_bar, vdev->msix->pba_offset, pos, 1451 &err); 1452 if (ret < 0) { 1453 if (ret == -ENOTSUP) { 1454 error_report_err(err); 1455 return 0; 1456 } 1457 1458 error_propagate(errp, err); 1459 return ret; 1460 } 1461 1462 /* 1463 * The PCI spec suggests that devices provide additional alignment for 1464 * MSI-X structures and avoid overlapping non-MSI-X related registers. 1465 * For an assigned device, this hopefully means that emulation of MSI-X 1466 * structures does not affect the performance of the device. If devices 1467 * fail to provide that alignment, a significant performance penalty may 1468 * result, for instance Mellanox MT27500 VFs: 1469 * http://www.spinics.net/lists/kvm/msg125881.html 1470 * 1471 * The PBA is simply not that important for such a serious regression and 1472 * most drivers do not appear to look at it. The solution for this is to 1473 * disable the PBA MemoryRegion unless it's being used. We disable it 1474 * here and only enable it if a masked vector fires through QEMU. As the 1475 * vector-use notifier is called, which occurs on unmask, we test whether 1476 * PBA emulation is needed and again disable if not. 1477 */ 1478 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 1479 1480 return 0; 1481 } 1482 1483 static void vfio_teardown_msi(VFIOPCIDevice *vdev) 1484 { 1485 msi_uninit(&vdev->pdev); 1486 1487 if (vdev->msix) { 1488 msix_uninit(&vdev->pdev, 1489 vdev->bars[vdev->msix->table_bar].mr, 1490 vdev->bars[vdev->msix->pba_bar].mr); 1491 g_free(vdev->msix->pending); 1492 } 1493 } 1494 1495 /* 1496 * Resource setup 1497 */ 1498 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) 1499 { 1500 int i; 1501 1502 for (i = 0; i < PCI_ROM_SLOT; i++) { 1503 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); 1504 } 1505 } 1506 1507 static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr) 1508 { 1509 VFIOBAR *bar = &vdev->bars[nr]; 1510 1511 uint32_t pci_bar; 1512 int ret; 1513 1514 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ 1515 if (!bar->region.size) { 1516 return; 1517 } 1518 1519 /* Determine what type of BAR this is for registration */ 1520 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), 1521 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); 1522 if (ret != sizeof(pci_bar)) { 1523 error_report("vfio: Failed to read BAR %d (%m)", nr); 1524 return; 1525 } 1526 1527 pci_bar = le32_to_cpu(pci_bar); 1528 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); 1529 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); 1530 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : 1531 ~PCI_BASE_ADDRESS_MEM_MASK); 1532 bar->size = bar->region.size; 1533 } 1534 1535 static void vfio_bars_prepare(VFIOPCIDevice *vdev) 1536 { 1537 int i; 1538 1539 for (i = 0; i < PCI_ROM_SLOT; i++) { 1540 vfio_bar_prepare(vdev, i); 1541 } 1542 } 1543 1544 static void vfio_bar_register(VFIOPCIDevice *vdev, int nr) 1545 { 1546 VFIOBAR *bar = &vdev->bars[nr]; 1547 char *name; 1548 1549 if (!bar->size) { 1550 return; 1551 } 1552 1553 bar->mr = g_new0(MemoryRegion, 1); 1554 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr); 1555 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size); 1556 g_free(name); 1557 1558 if (bar->region.size) { 1559 memory_region_add_subregion(bar->mr, 0, bar->region.mem); 1560 1561 if (vfio_region_mmap(&bar->region)) { 1562 error_report("Failed to mmap %s BAR %d. Performance may be slow", 1563 vdev->vbasedev.name, nr); 1564 } 1565 } 1566 1567 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr); 1568 } 1569 1570 static void vfio_bars_register(VFIOPCIDevice *vdev) 1571 { 1572 int i; 1573 1574 for (i = 0; i < PCI_ROM_SLOT; i++) { 1575 vfio_bar_register(vdev, i); 1576 } 1577 } 1578 1579 static void vfio_bars_exit(VFIOPCIDevice *vdev) 1580 { 1581 int i; 1582 1583 for (i = 0; i < PCI_ROM_SLOT; i++) { 1584 VFIOBAR *bar = &vdev->bars[i]; 1585 1586 vfio_bar_quirk_exit(vdev, i); 1587 vfio_region_exit(&bar->region); 1588 if (bar->region.size) { 1589 memory_region_del_subregion(bar->mr, bar->region.mem); 1590 } 1591 } 1592 1593 if (vdev->vga) { 1594 pci_unregister_vga(&vdev->pdev); 1595 vfio_vga_quirk_exit(vdev); 1596 } 1597 } 1598 1599 static void vfio_bars_finalize(VFIOPCIDevice *vdev) 1600 { 1601 int i; 1602 1603 for (i = 0; i < PCI_ROM_SLOT; i++) { 1604 VFIOBAR *bar = &vdev->bars[i]; 1605 1606 vfio_bar_quirk_finalize(vdev, i); 1607 vfio_region_finalize(&bar->region); 1608 if (bar->size) { 1609 object_unparent(OBJECT(bar->mr)); 1610 g_free(bar->mr); 1611 } 1612 } 1613 1614 if (vdev->vga) { 1615 vfio_vga_quirk_finalize(vdev); 1616 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { 1617 object_unparent(OBJECT(&vdev->vga->region[i].mem)); 1618 } 1619 g_free(vdev->vga); 1620 } 1621 } 1622 1623 /* 1624 * General setup 1625 */ 1626 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) 1627 { 1628 uint8_t tmp; 1629 uint16_t next = PCI_CONFIG_SPACE_SIZE; 1630 1631 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; 1632 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { 1633 if (tmp > pos && tmp < next) { 1634 next = tmp; 1635 } 1636 } 1637 1638 return next - pos; 1639 } 1640 1641 1642 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) 1643 { 1644 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; 1645 1646 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; 1647 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { 1648 if (tmp > pos && tmp < next) { 1649 next = tmp; 1650 } 1651 } 1652 1653 return next - pos; 1654 } 1655 1656 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) 1657 { 1658 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); 1659 } 1660 1661 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, 1662 uint16_t val, uint16_t mask) 1663 { 1664 vfio_set_word_bits(vdev->pdev.config + pos, val, mask); 1665 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); 1666 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); 1667 } 1668 1669 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) 1670 { 1671 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); 1672 } 1673 1674 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, 1675 uint32_t val, uint32_t mask) 1676 { 1677 vfio_set_long_bits(vdev->pdev.config + pos, val, mask); 1678 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); 1679 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); 1680 } 1681 1682 static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1683 Error **errp) 1684 { 1685 uint16_t flags; 1686 uint8_t type; 1687 1688 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); 1689 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; 1690 1691 if (type != PCI_EXP_TYPE_ENDPOINT && 1692 type != PCI_EXP_TYPE_LEG_END && 1693 type != PCI_EXP_TYPE_RC_END) { 1694 1695 error_setg(errp, "assignment of PCIe type 0x%x " 1696 "devices is not currently supported", type); 1697 return -EINVAL; 1698 } 1699 1700 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) { 1701 PCIBus *bus = pci_get_bus(&vdev->pdev); 1702 PCIDevice *bridge; 1703 1704 /* 1705 * Traditionally PCI device assignment exposes the PCIe capability 1706 * as-is on non-express buses. The reason being that some drivers 1707 * simply assume that it's there, for example tg3. However when 1708 * we're running on a native PCIe machine type, like Q35, we need 1709 * to hide the PCIe capability. The reason for this is twofold; 1710 * first Windows guests get a Code 10 error when the PCIe capability 1711 * is exposed in this configuration. Therefore express devices won't 1712 * work at all unless they're attached to express buses in the VM. 1713 * Second, a native PCIe machine introduces the possibility of fine 1714 * granularity IOMMUs supporting both translation and isolation. 1715 * Guest code to discover the IOMMU visibility of a device, such as 1716 * IOMMU grouping code on Linux, is very aware of device types and 1717 * valid transitions between bus types. An express device on a non- 1718 * express bus is not a valid combination on bare metal systems. 1719 * 1720 * Drivers that require a PCIe capability to make the device 1721 * functional are simply going to need to have their devices placed 1722 * on a PCIe bus in the VM. 1723 */ 1724 while (!pci_bus_is_root(bus)) { 1725 bridge = pci_bridge_get_device(bus); 1726 bus = pci_get_bus(bridge); 1727 } 1728 1729 if (pci_bus_is_express(bus)) { 1730 return 0; 1731 } 1732 1733 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) { 1734 /* 1735 * On a Root Complex bus Endpoints become Root Complex Integrated 1736 * Endpoints, which changes the type and clears the LNK & LNK2 fields. 1737 */ 1738 if (type == PCI_EXP_TYPE_ENDPOINT) { 1739 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1740 PCI_EXP_TYPE_RC_END << 4, 1741 PCI_EXP_FLAGS_TYPE); 1742 1743 /* Link Capabilities, Status, and Control goes away */ 1744 if (size > PCI_EXP_LNKCTL) { 1745 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); 1746 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1747 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); 1748 1749 #ifndef PCI_EXP_LNKCAP2 1750 #define PCI_EXP_LNKCAP2 44 1751 #endif 1752 #ifndef PCI_EXP_LNKSTA2 1753 #define PCI_EXP_LNKSTA2 50 1754 #endif 1755 /* Link 2 Capabilities, Status, and Control goes away */ 1756 if (size > PCI_EXP_LNKCAP2) { 1757 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); 1758 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); 1759 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); 1760 } 1761 } 1762 1763 } else if (type == PCI_EXP_TYPE_LEG_END) { 1764 /* 1765 * Legacy endpoints don't belong on the root complex. Windows 1766 * seems to be happier with devices if we skip the capability. 1767 */ 1768 return 0; 1769 } 1770 1771 } else { 1772 /* 1773 * Convert Root Complex Integrated Endpoints to regular endpoints. 1774 * These devices don't support LNK/LNK2 capabilities, so make them up. 1775 */ 1776 if (type == PCI_EXP_TYPE_RC_END) { 1777 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1778 PCI_EXP_TYPE_ENDPOINT << 4, 1779 PCI_EXP_FLAGS_TYPE); 1780 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 1781 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); 1782 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1783 } 1784 1785 /* Mark the Link Status bits as emulated to allow virtual negotiation */ 1786 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 1787 pci_get_word(vdev->pdev.config + pos + 1788 PCI_EXP_LNKSTA), 1789 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 1790 } 1791 1792 /* 1793 * Intel 82599 SR-IOV VFs report an invalid PCIe capability version 0 1794 * (Niantic errate #35) causing Windows to error with a Code 10 for the 1795 * device on Q35. Fixup any such devices to report version 1. If we 1796 * were to remove the capability entirely the guest would lose extended 1797 * config space. 1798 */ 1799 if ((flags & PCI_EXP_FLAGS_VERS) == 0) { 1800 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1801 1, PCI_EXP_FLAGS_VERS); 1802 } 1803 1804 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, 1805 errp); 1806 if (pos < 0) { 1807 return pos; 1808 } 1809 1810 vdev->pdev.exp.exp_cap = pos; 1811 1812 return pos; 1813 } 1814 1815 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) 1816 { 1817 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); 1818 1819 if (cap & PCI_EXP_DEVCAP_FLR) { 1820 trace_vfio_check_pcie_flr(vdev->vbasedev.name); 1821 vdev->has_flr = true; 1822 } 1823 } 1824 1825 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) 1826 { 1827 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); 1828 1829 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { 1830 trace_vfio_check_pm_reset(vdev->vbasedev.name); 1831 vdev->has_pm_reset = true; 1832 } 1833 } 1834 1835 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) 1836 { 1837 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); 1838 1839 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { 1840 trace_vfio_check_af_flr(vdev->vbasedev.name); 1841 vdev->has_flr = true; 1842 } 1843 } 1844 1845 static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) 1846 { 1847 PCIDevice *pdev = &vdev->pdev; 1848 uint8_t cap_id, next, size; 1849 int ret; 1850 1851 cap_id = pdev->config[pos]; 1852 next = pdev->config[pos + PCI_CAP_LIST_NEXT]; 1853 1854 /* 1855 * If it becomes important to configure capabilities to their actual 1856 * size, use this as the default when it's something we don't recognize. 1857 * Since QEMU doesn't actually handle many of the config accesses, 1858 * exact size doesn't seem worthwhile. 1859 */ 1860 size = vfio_std_cap_max_size(pdev, pos); 1861 1862 /* 1863 * pci_add_capability always inserts the new capability at the head 1864 * of the chain. Therefore to end up with a chain that matches the 1865 * physical device, we insert from the end by making this recursive. 1866 * This is also why we pre-calculate size above as cached config space 1867 * will be changed as we unwind the stack. 1868 */ 1869 if (next) { 1870 ret = vfio_add_std_cap(vdev, next, errp); 1871 if (ret) { 1872 return ret; 1873 } 1874 } else { 1875 /* Begin the rebuild, use QEMU emulated list bits */ 1876 pdev->config[PCI_CAPABILITY_LIST] = 0; 1877 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; 1878 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 1879 1880 ret = vfio_add_virt_caps(vdev, errp); 1881 if (ret) { 1882 return ret; 1883 } 1884 } 1885 1886 /* Scale down size, esp in case virt caps were added above */ 1887 size = MIN(size, vfio_std_cap_max_size(pdev, pos)); 1888 1889 /* Use emulated next pointer to allow dropping caps */ 1890 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); 1891 1892 switch (cap_id) { 1893 case PCI_CAP_ID_MSI: 1894 ret = vfio_msi_setup(vdev, pos, errp); 1895 break; 1896 case PCI_CAP_ID_EXP: 1897 vfio_check_pcie_flr(vdev, pos); 1898 ret = vfio_setup_pcie_cap(vdev, pos, size, errp); 1899 break; 1900 case PCI_CAP_ID_MSIX: 1901 ret = vfio_msix_setup(vdev, pos, errp); 1902 break; 1903 case PCI_CAP_ID_PM: 1904 vfio_check_pm_reset(vdev, pos); 1905 vdev->pm_cap = pos; 1906 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 1907 break; 1908 case PCI_CAP_ID_AF: 1909 vfio_check_af_flr(vdev, pos); 1910 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 1911 break; 1912 default: 1913 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 1914 break; 1915 } 1916 1917 if (ret < 0) { 1918 error_prepend(errp, 1919 "failed to add PCI capability 0x%x[0x%x]@0x%x: ", 1920 cap_id, size, pos); 1921 return ret; 1922 } 1923 1924 return 0; 1925 } 1926 1927 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) 1928 { 1929 PCIDevice *pdev = &vdev->pdev; 1930 uint32_t header; 1931 uint16_t cap_id, next, size; 1932 uint8_t cap_ver; 1933 uint8_t *config; 1934 1935 /* Only add extended caps if we have them and the guest can see them */ 1936 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) || 1937 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { 1938 return; 1939 } 1940 1941 /* 1942 * pcie_add_capability always inserts the new capability at the tail 1943 * of the chain. Therefore to end up with a chain that matches the 1944 * physical device, we cache the config space to avoid overwriting 1945 * the original config space when we parse the extended capabilities. 1946 */ 1947 config = g_memdup(pdev->config, vdev->config_size); 1948 1949 /* 1950 * Extended capabilities are chained with each pointing to the next, so we 1951 * can drop anything other than the head of the chain simply by modifying 1952 * the previous next pointer. Seed the head of the chain here such that 1953 * we can simply skip any capabilities we want to drop below, regardless 1954 * of their position in the chain. If this stub capability still exists 1955 * after we add the capabilities we want to expose, update the capability 1956 * ID to zero. Note that we cannot seed with the capability header being 1957 * zero as this conflicts with definition of an absent capability chain 1958 * and prevents capabilities beyond the head of the list from being added. 1959 * By replacing the dummy capability ID with zero after walking the device 1960 * chain, we also transparently mark extended capabilities as absent if 1961 * no capabilities were added. Note that the PCIe spec defines an absence 1962 * of extended capabilities to be determined by a value of zero for the 1963 * capability ID, version, AND next pointer. A non-zero next pointer 1964 * should be sufficient to indicate additional capabilities are present, 1965 * which will occur if we call pcie_add_capability() below. The entire 1966 * first dword is emulated to support this. 1967 * 1968 * NB. The kernel side does similar masking, so be prepared that our 1969 * view of the device may also contain a capability ID zero in the head 1970 * of the chain. Skip it for the same reason that we cannot seed the 1971 * chain with a zero capability. 1972 */ 1973 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, 1974 PCI_EXT_CAP(0xFFFF, 0, 0)); 1975 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 1976 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); 1977 1978 for (next = PCI_CONFIG_SPACE_SIZE; next; 1979 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { 1980 header = pci_get_long(config + next); 1981 cap_id = PCI_EXT_CAP_ID(header); 1982 cap_ver = PCI_EXT_CAP_VER(header); 1983 1984 /* 1985 * If it becomes important to configure extended capabilities to their 1986 * actual size, use this as the default when it's something we don't 1987 * recognize. Since QEMU doesn't actually handle many of the config 1988 * accesses, exact size doesn't seem worthwhile. 1989 */ 1990 size = vfio_ext_cap_max_size(config, next); 1991 1992 /* Use emulated next pointer to allow dropping extended caps */ 1993 pci_long_test_and_set_mask(vdev->emulated_config_bits + next, 1994 PCI_EXT_CAP_NEXT_MASK); 1995 1996 switch (cap_id) { 1997 case 0: /* kernel masked capability */ 1998 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ 1999 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */ 2000 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); 2001 break; 2002 default: 2003 pcie_add_capability(pdev, cap_id, cap_ver, next, size); 2004 } 2005 2006 } 2007 2008 /* Cleanup chain head ID if necessary */ 2009 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { 2010 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); 2011 } 2012 2013 g_free(config); 2014 return; 2015 } 2016 2017 static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp) 2018 { 2019 PCIDevice *pdev = &vdev->pdev; 2020 int ret; 2021 2022 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || 2023 !pdev->config[PCI_CAPABILITY_LIST]) { 2024 return 0; /* Nothing to add */ 2025 } 2026 2027 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp); 2028 if (ret) { 2029 return ret; 2030 } 2031 2032 vfio_add_ext_cap(vdev); 2033 return 0; 2034 } 2035 2036 static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) 2037 { 2038 PCIDevice *pdev = &vdev->pdev; 2039 uint16_t cmd; 2040 2041 vfio_disable_interrupts(vdev); 2042 2043 /* Make sure the device is in D0 */ 2044 if (vdev->pm_cap) { 2045 uint16_t pmcsr; 2046 uint8_t state; 2047 2048 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2049 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2050 if (state) { 2051 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 2052 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); 2053 /* vfio handles the necessary delay here */ 2054 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2055 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2056 if (state) { 2057 error_report("vfio: Unable to power on device, stuck in D%d", 2058 state); 2059 } 2060 } 2061 } 2062 2063 /* 2064 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. 2065 * Also put INTx Disable in known state. 2066 */ 2067 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); 2068 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 2069 PCI_COMMAND_INTX_DISABLE); 2070 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); 2071 } 2072 2073 static void vfio_pci_post_reset(VFIOPCIDevice *vdev) 2074 { 2075 Error *err = NULL; 2076 int nr; 2077 2078 vfio_intx_enable(vdev, &err); 2079 if (err) { 2080 error_reportf_err(err, ERR_PREFIX, vdev->vbasedev.name); 2081 } 2082 2083 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) { 2084 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr); 2085 uint32_t val = 0; 2086 uint32_t len = sizeof(val); 2087 2088 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) { 2089 error_report("%s(%s) reset bar %d failed: %m", __func__, 2090 vdev->vbasedev.name, nr); 2091 } 2092 } 2093 } 2094 2095 static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) 2096 { 2097 char tmp[13]; 2098 2099 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, 2100 addr->bus, addr->slot, addr->function); 2101 2102 return (strcmp(tmp, name) == 0); 2103 } 2104 2105 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) 2106 { 2107 VFIOGroup *group; 2108 struct vfio_pci_hot_reset_info *info; 2109 struct vfio_pci_dependent_device *devices; 2110 struct vfio_pci_hot_reset *reset; 2111 int32_t *fds; 2112 int ret, i, count; 2113 bool multi = false; 2114 2115 trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); 2116 2117 if (!single) { 2118 vfio_pci_pre_reset(vdev); 2119 } 2120 vdev->vbasedev.needs_reset = false; 2121 2122 info = g_malloc0(sizeof(*info)); 2123 info->argsz = sizeof(*info); 2124 2125 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2126 if (ret && errno != ENOSPC) { 2127 ret = -errno; 2128 if (!vdev->has_pm_reset) { 2129 error_report("vfio: Cannot reset device %s, " 2130 "no available reset mechanism.", vdev->vbasedev.name); 2131 } 2132 goto out_single; 2133 } 2134 2135 count = info->count; 2136 info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); 2137 info->argsz = sizeof(*info) + (count * sizeof(*devices)); 2138 devices = &info->devices[0]; 2139 2140 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2141 if (ret) { 2142 ret = -errno; 2143 error_report("vfio: hot reset info failed: %m"); 2144 goto out_single; 2145 } 2146 2147 trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); 2148 2149 /* Verify that we have all the groups required */ 2150 for (i = 0; i < info->count; i++) { 2151 PCIHostDeviceAddress host; 2152 VFIOPCIDevice *tmp; 2153 VFIODevice *vbasedev_iter; 2154 2155 host.domain = devices[i].segment; 2156 host.bus = devices[i].bus; 2157 host.slot = PCI_SLOT(devices[i].devfn); 2158 host.function = PCI_FUNC(devices[i].devfn); 2159 2160 trace_vfio_pci_hot_reset_dep_devices(host.domain, 2161 host.bus, host.slot, host.function, devices[i].group_id); 2162 2163 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2164 continue; 2165 } 2166 2167 QLIST_FOREACH(group, &vfio_group_list, next) { 2168 if (group->groupid == devices[i].group_id) { 2169 break; 2170 } 2171 } 2172 2173 if (!group) { 2174 if (!vdev->has_pm_reset) { 2175 error_report("vfio: Cannot reset device %s, " 2176 "depends on group %d which is not owned.", 2177 vdev->vbasedev.name, devices[i].group_id); 2178 } 2179 ret = -EPERM; 2180 goto out; 2181 } 2182 2183 /* Prep dependent devices for reset and clear our marker. */ 2184 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2185 if (!vbasedev_iter->dev->realized || 2186 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2187 continue; 2188 } 2189 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2190 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2191 if (single) { 2192 ret = -EINVAL; 2193 goto out_single; 2194 } 2195 vfio_pci_pre_reset(tmp); 2196 tmp->vbasedev.needs_reset = false; 2197 multi = true; 2198 break; 2199 } 2200 } 2201 } 2202 2203 if (!single && !multi) { 2204 ret = -EINVAL; 2205 goto out_single; 2206 } 2207 2208 /* Determine how many group fds need to be passed */ 2209 count = 0; 2210 QLIST_FOREACH(group, &vfio_group_list, next) { 2211 for (i = 0; i < info->count; i++) { 2212 if (group->groupid == devices[i].group_id) { 2213 count++; 2214 break; 2215 } 2216 } 2217 } 2218 2219 reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); 2220 reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); 2221 fds = &reset->group_fds[0]; 2222 2223 /* Fill in group fds */ 2224 QLIST_FOREACH(group, &vfio_group_list, next) { 2225 for (i = 0; i < info->count; i++) { 2226 if (group->groupid == devices[i].group_id) { 2227 fds[reset->count++] = group->fd; 2228 break; 2229 } 2230 } 2231 } 2232 2233 /* Bus reset! */ 2234 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); 2235 g_free(reset); 2236 2237 trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, 2238 ret ? "%m" : "Success"); 2239 2240 out: 2241 /* Re-enable INTx on affected devices */ 2242 for (i = 0; i < info->count; i++) { 2243 PCIHostDeviceAddress host; 2244 VFIOPCIDevice *tmp; 2245 VFIODevice *vbasedev_iter; 2246 2247 host.domain = devices[i].segment; 2248 host.bus = devices[i].bus; 2249 host.slot = PCI_SLOT(devices[i].devfn); 2250 host.function = PCI_FUNC(devices[i].devfn); 2251 2252 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2253 continue; 2254 } 2255 2256 QLIST_FOREACH(group, &vfio_group_list, next) { 2257 if (group->groupid == devices[i].group_id) { 2258 break; 2259 } 2260 } 2261 2262 if (!group) { 2263 break; 2264 } 2265 2266 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2267 if (!vbasedev_iter->dev->realized || 2268 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2269 continue; 2270 } 2271 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2272 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2273 vfio_pci_post_reset(tmp); 2274 break; 2275 } 2276 } 2277 } 2278 out_single: 2279 if (!single) { 2280 vfio_pci_post_reset(vdev); 2281 } 2282 g_free(info); 2283 2284 return ret; 2285 } 2286 2287 /* 2288 * We want to differentiate hot reset of mulitple in-use devices vs hot reset 2289 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case 2290 * of doing hot resets when there is only a single device per bus. The in-use 2291 * here refers to how many VFIODevices are affected. A hot reset that affects 2292 * multiple devices, but only a single in-use device, means that we can call 2293 * it from our bus ->reset() callback since the extent is effectively a single 2294 * device. This allows us to make use of it in the hotplug path. When there 2295 * are multiple in-use devices, we can only trigger the hot reset during a 2296 * system reset and thus from our reset handler. We separate _one vs _multi 2297 * here so that we don't overlap and do a double reset on the system reset 2298 * path where both our reset handler and ->reset() callback are used. Calling 2299 * _one() will only do a hot reset for the one in-use devices case, calling 2300 * _multi() will do nothing if a _one() would have been sufficient. 2301 */ 2302 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) 2303 { 2304 return vfio_pci_hot_reset(vdev, true); 2305 } 2306 2307 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) 2308 { 2309 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2310 return vfio_pci_hot_reset(vdev, false); 2311 } 2312 2313 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) 2314 { 2315 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2316 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { 2317 vbasedev->needs_reset = true; 2318 } 2319 } 2320 2321 static VFIODeviceOps vfio_pci_ops = { 2322 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, 2323 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, 2324 .vfio_eoi = vfio_intx_eoi, 2325 }; 2326 2327 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) 2328 { 2329 VFIODevice *vbasedev = &vdev->vbasedev; 2330 struct vfio_region_info *reg_info; 2331 int ret; 2332 2333 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); 2334 if (ret) { 2335 error_setg_errno(errp, -ret, 2336 "failed getting region info for VGA region index %d", 2337 VFIO_PCI_VGA_REGION_INDEX); 2338 return ret; 2339 } 2340 2341 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || 2342 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || 2343 reg_info->size < 0xbffff + 1) { 2344 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx", 2345 (unsigned long)reg_info->flags, 2346 (unsigned long)reg_info->size); 2347 g_free(reg_info); 2348 return -EINVAL; 2349 } 2350 2351 vdev->vga = g_new0(VFIOVGA, 1); 2352 2353 vdev->vga->fd_offset = reg_info->offset; 2354 vdev->vga->fd = vdev->vbasedev.fd; 2355 2356 g_free(reg_info); 2357 2358 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; 2359 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; 2360 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); 2361 2362 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2363 OBJECT(vdev), &vfio_vga_ops, 2364 &vdev->vga->region[QEMU_PCI_VGA_MEM], 2365 "vfio-vga-mmio@0xa0000", 2366 QEMU_PCI_VGA_MEM_SIZE); 2367 2368 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; 2369 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; 2370 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); 2371 2372 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2373 OBJECT(vdev), &vfio_vga_ops, 2374 &vdev->vga->region[QEMU_PCI_VGA_IO_LO], 2375 "vfio-vga-io@0x3b0", 2376 QEMU_PCI_VGA_IO_LO_SIZE); 2377 2378 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; 2379 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; 2380 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); 2381 2382 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, 2383 OBJECT(vdev), &vfio_vga_ops, 2384 &vdev->vga->region[QEMU_PCI_VGA_IO_HI], 2385 "vfio-vga-io@0x3c0", 2386 QEMU_PCI_VGA_IO_HI_SIZE); 2387 2388 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2389 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2390 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); 2391 2392 return 0; 2393 } 2394 2395 static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp) 2396 { 2397 VFIODevice *vbasedev = &vdev->vbasedev; 2398 struct vfio_region_info *reg_info; 2399 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; 2400 int i, ret = -1; 2401 2402 /* Sanity check device */ 2403 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { 2404 error_setg(errp, "this isn't a PCI device"); 2405 return; 2406 } 2407 2408 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { 2409 error_setg(errp, "unexpected number of io regions %u", 2410 vbasedev->num_regions); 2411 return; 2412 } 2413 2414 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { 2415 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs); 2416 return; 2417 } 2418 2419 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { 2420 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); 2421 2422 ret = vfio_region_setup(OBJECT(vdev), vbasedev, 2423 &vdev->bars[i].region, i, name); 2424 g_free(name); 2425 2426 if (ret) { 2427 error_setg_errno(errp, -ret, "failed to get region %d info", i); 2428 return; 2429 } 2430 2431 QLIST_INIT(&vdev->bars[i].quirks); 2432 } 2433 2434 ret = vfio_get_region_info(vbasedev, 2435 VFIO_PCI_CONFIG_REGION_INDEX, ®_info); 2436 if (ret) { 2437 error_setg_errno(errp, -ret, "failed to get config info"); 2438 return; 2439 } 2440 2441 trace_vfio_populate_device_config(vdev->vbasedev.name, 2442 (unsigned long)reg_info->size, 2443 (unsigned long)reg_info->offset, 2444 (unsigned long)reg_info->flags); 2445 2446 vdev->config_size = reg_info->size; 2447 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { 2448 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; 2449 } 2450 vdev->config_offset = reg_info->offset; 2451 2452 g_free(reg_info); 2453 2454 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { 2455 ret = vfio_populate_vga(vdev, errp); 2456 if (ret) { 2457 error_append_hint(errp, "device does not support " 2458 "requested feature x-vga\n"); 2459 return; 2460 } 2461 } 2462 2463 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; 2464 2465 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); 2466 if (ret) { 2467 /* This can fail for an old kernel or legacy PCI dev */ 2468 trace_vfio_populate_device_get_irq_info_failure(); 2469 } else if (irq_info.count == 1) { 2470 vdev->pci_aer = true; 2471 } else { 2472 error_report(WARN_PREFIX 2473 "Could not enable error recovery for the device", 2474 vbasedev->name); 2475 } 2476 } 2477 2478 static void vfio_put_device(VFIOPCIDevice *vdev) 2479 { 2480 g_free(vdev->vbasedev.name); 2481 g_free(vdev->msix); 2482 2483 vfio_put_base_device(&vdev->vbasedev); 2484 } 2485 2486 static void vfio_err_notifier_handler(void *opaque) 2487 { 2488 VFIOPCIDevice *vdev = opaque; 2489 2490 if (!event_notifier_test_and_clear(&vdev->err_notifier)) { 2491 return; 2492 } 2493 2494 /* 2495 * TBD. Retrieve the error details and decide what action 2496 * needs to be taken. One of the actions could be to pass 2497 * the error to the guest and have the guest driver recover 2498 * from the error. This requires that PCIe capabilities be 2499 * exposed to the guest. For now, we just terminate the 2500 * guest to contain the error. 2501 */ 2502 2503 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); 2504 2505 vm_stop(RUN_STATE_INTERNAL_ERROR); 2506 } 2507 2508 /* 2509 * Registers error notifier for devices supporting error recovery. 2510 * If we encounter a failure in this function, we report an error 2511 * and continue after disabling error recovery support for the 2512 * device. 2513 */ 2514 static void vfio_register_err_notifier(VFIOPCIDevice *vdev) 2515 { 2516 int ret; 2517 int argsz; 2518 struct vfio_irq_set *irq_set; 2519 int32_t *pfd; 2520 2521 if (!vdev->pci_aer) { 2522 return; 2523 } 2524 2525 if (event_notifier_init(&vdev->err_notifier, 0)) { 2526 error_report("vfio: Unable to init event notifier for error detection"); 2527 vdev->pci_aer = false; 2528 return; 2529 } 2530 2531 argsz = sizeof(*irq_set) + sizeof(*pfd); 2532 2533 irq_set = g_malloc0(argsz); 2534 irq_set->argsz = argsz; 2535 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2536 VFIO_IRQ_SET_ACTION_TRIGGER; 2537 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2538 irq_set->start = 0; 2539 irq_set->count = 1; 2540 pfd = (int32_t *)&irq_set->data; 2541 2542 *pfd = event_notifier_get_fd(&vdev->err_notifier); 2543 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); 2544 2545 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2546 if (ret) { 2547 error_report("vfio: Failed to set up error notification"); 2548 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2549 event_notifier_cleanup(&vdev->err_notifier); 2550 vdev->pci_aer = false; 2551 } 2552 g_free(irq_set); 2553 } 2554 2555 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) 2556 { 2557 int argsz; 2558 struct vfio_irq_set *irq_set; 2559 int32_t *pfd; 2560 int ret; 2561 2562 if (!vdev->pci_aer) { 2563 return; 2564 } 2565 2566 argsz = sizeof(*irq_set) + sizeof(*pfd); 2567 2568 irq_set = g_malloc0(argsz); 2569 irq_set->argsz = argsz; 2570 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2571 VFIO_IRQ_SET_ACTION_TRIGGER; 2572 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2573 irq_set->start = 0; 2574 irq_set->count = 1; 2575 pfd = (int32_t *)&irq_set->data; 2576 *pfd = -1; 2577 2578 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2579 if (ret) { 2580 error_report("vfio: Failed to de-assign error fd: %m"); 2581 } 2582 g_free(irq_set); 2583 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), 2584 NULL, NULL, vdev); 2585 event_notifier_cleanup(&vdev->err_notifier); 2586 } 2587 2588 static void vfio_req_notifier_handler(void *opaque) 2589 { 2590 VFIOPCIDevice *vdev = opaque; 2591 Error *err = NULL; 2592 2593 if (!event_notifier_test_and_clear(&vdev->req_notifier)) { 2594 return; 2595 } 2596 2597 qdev_unplug(&vdev->pdev.qdev, &err); 2598 if (err) { 2599 error_reportf_err(err, WARN_PREFIX, vdev->vbasedev.name); 2600 } 2601 } 2602 2603 static void vfio_register_req_notifier(VFIOPCIDevice *vdev) 2604 { 2605 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), 2606 .index = VFIO_PCI_REQ_IRQ_INDEX }; 2607 int argsz; 2608 struct vfio_irq_set *irq_set; 2609 int32_t *pfd; 2610 2611 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { 2612 return; 2613 } 2614 2615 if (ioctl(vdev->vbasedev.fd, 2616 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { 2617 return; 2618 } 2619 2620 if (event_notifier_init(&vdev->req_notifier, 0)) { 2621 error_report("vfio: Unable to init event notifier for device request"); 2622 return; 2623 } 2624 2625 argsz = sizeof(*irq_set) + sizeof(*pfd); 2626 2627 irq_set = g_malloc0(argsz); 2628 irq_set->argsz = argsz; 2629 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2630 VFIO_IRQ_SET_ACTION_TRIGGER; 2631 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2632 irq_set->start = 0; 2633 irq_set->count = 1; 2634 pfd = (int32_t *)&irq_set->data; 2635 2636 *pfd = event_notifier_get_fd(&vdev->req_notifier); 2637 qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); 2638 2639 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2640 error_report("vfio: Failed to set up device request notification"); 2641 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2642 event_notifier_cleanup(&vdev->req_notifier); 2643 } else { 2644 vdev->req_enabled = true; 2645 } 2646 2647 g_free(irq_set); 2648 } 2649 2650 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) 2651 { 2652 int argsz; 2653 struct vfio_irq_set *irq_set; 2654 int32_t *pfd; 2655 2656 if (!vdev->req_enabled) { 2657 return; 2658 } 2659 2660 argsz = sizeof(*irq_set) + sizeof(*pfd); 2661 2662 irq_set = g_malloc0(argsz); 2663 irq_set->argsz = argsz; 2664 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2665 VFIO_IRQ_SET_ACTION_TRIGGER; 2666 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2667 irq_set->start = 0; 2668 irq_set->count = 1; 2669 pfd = (int32_t *)&irq_set->data; 2670 *pfd = -1; 2671 2672 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2673 error_report("vfio: Failed to de-assign device request fd: %m"); 2674 } 2675 g_free(irq_set); 2676 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), 2677 NULL, NULL, vdev); 2678 event_notifier_cleanup(&vdev->req_notifier); 2679 2680 vdev->req_enabled = false; 2681 } 2682 2683 static void vfio_realize(PCIDevice *pdev, Error **errp) 2684 { 2685 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2686 VFIODevice *vbasedev_iter; 2687 VFIOGroup *group; 2688 char *tmp, group_path[PATH_MAX], *group_name; 2689 Error *err = NULL; 2690 ssize_t len; 2691 struct stat st; 2692 int groupid; 2693 int i, ret; 2694 2695 if (!vdev->vbasedev.sysfsdev) { 2696 if (!(~vdev->host.domain || ~vdev->host.bus || 2697 ~vdev->host.slot || ~vdev->host.function)) { 2698 error_setg(errp, "No provided host device"); 2699 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F " 2700 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n"); 2701 return; 2702 } 2703 vdev->vbasedev.sysfsdev = 2704 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", 2705 vdev->host.domain, vdev->host.bus, 2706 vdev->host.slot, vdev->host.function); 2707 } 2708 2709 if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { 2710 error_setg_errno(errp, errno, "no such host device"); 2711 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.sysfsdev); 2712 return; 2713 } 2714 2715 vdev->vbasedev.name = g_strdup(basename(vdev->vbasedev.sysfsdev)); 2716 vdev->vbasedev.ops = &vfio_pci_ops; 2717 vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; 2718 vdev->vbasedev.dev = &vdev->pdev.qdev; 2719 2720 tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); 2721 len = readlink(tmp, group_path, sizeof(group_path)); 2722 g_free(tmp); 2723 2724 if (len <= 0 || len >= sizeof(group_path)) { 2725 error_setg_errno(errp, len < 0 ? errno : ENAMETOOLONG, 2726 "no iommu_group found"); 2727 goto error; 2728 } 2729 2730 group_path[len] = 0; 2731 2732 group_name = basename(group_path); 2733 if (sscanf(group_name, "%d", &groupid) != 1) { 2734 error_setg_errno(errp, errno, "failed to read %s", group_path); 2735 goto error; 2736 } 2737 2738 trace_vfio_realize(vdev->vbasedev.name, groupid); 2739 2740 group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev), errp); 2741 if (!group) { 2742 goto error; 2743 } 2744 2745 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2746 if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { 2747 error_setg(errp, "device is already attached"); 2748 vfio_put_group(group); 2749 goto error; 2750 } 2751 } 2752 2753 ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev, errp); 2754 if (ret) { 2755 vfio_put_group(group); 2756 goto error; 2757 } 2758 2759 vfio_populate_device(vdev, &err); 2760 if (err) { 2761 error_propagate(errp, err); 2762 goto error; 2763 } 2764 2765 /* Get a copy of config space */ 2766 ret = pread(vdev->vbasedev.fd, vdev->pdev.config, 2767 MIN(pci_config_size(&vdev->pdev), vdev->config_size), 2768 vdev->config_offset); 2769 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { 2770 ret = ret < 0 ? -errno : -EFAULT; 2771 error_setg_errno(errp, -ret, "failed to read device config space"); 2772 goto error; 2773 } 2774 2775 /* vfio emulates a lot for us, but some bits need extra love */ 2776 vdev->emulated_config_bits = g_malloc0(vdev->config_size); 2777 2778 /* QEMU can choose to expose the ROM or not */ 2779 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); 2780 /* QEMU can also add or extend BARs */ 2781 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4); 2782 2783 /* 2784 * The PCI spec reserves vendor ID 0xffff as an invalid value. The 2785 * device ID is managed by the vendor and need only be a 16-bit value. 2786 * Allow any 16-bit value for subsystem so they can be hidden or changed. 2787 */ 2788 if (vdev->vendor_id != PCI_ANY_ID) { 2789 if (vdev->vendor_id >= 0xffff) { 2790 error_setg(errp, "invalid PCI vendor ID provided"); 2791 goto error; 2792 } 2793 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); 2794 trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); 2795 } else { 2796 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2797 } 2798 2799 if (vdev->device_id != PCI_ANY_ID) { 2800 if (vdev->device_id > 0xffff) { 2801 error_setg(errp, "invalid PCI device ID provided"); 2802 goto error; 2803 } 2804 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); 2805 trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); 2806 } else { 2807 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2808 } 2809 2810 if (vdev->sub_vendor_id != PCI_ANY_ID) { 2811 if (vdev->sub_vendor_id > 0xffff) { 2812 error_setg(errp, "invalid PCI subsystem vendor ID provided"); 2813 goto error; 2814 } 2815 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, 2816 vdev->sub_vendor_id, ~0); 2817 trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, 2818 vdev->sub_vendor_id); 2819 } 2820 2821 if (vdev->sub_device_id != PCI_ANY_ID) { 2822 if (vdev->sub_device_id > 0xffff) { 2823 error_setg(errp, "invalid PCI subsystem device ID provided"); 2824 goto error; 2825 } 2826 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); 2827 trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, 2828 vdev->sub_device_id); 2829 } 2830 2831 /* QEMU can change multi-function devices to single function, or reverse */ 2832 vdev->emulated_config_bits[PCI_HEADER_TYPE] = 2833 PCI_HEADER_TYPE_MULTI_FUNCTION; 2834 2835 /* Restore or clear multifunction, this is always controlled by QEMU */ 2836 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 2837 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 2838 } else { 2839 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; 2840 } 2841 2842 /* 2843 * Clear host resource mapping info. If we choose not to register a 2844 * BAR, such as might be the case with the option ROM, we can get 2845 * confusing, unwritable, residual addresses from the host here. 2846 */ 2847 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); 2848 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); 2849 2850 vfio_pci_size_rom(vdev); 2851 2852 vfio_msix_early_setup(vdev, &err); 2853 if (err) { 2854 error_propagate(errp, err); 2855 goto error; 2856 } 2857 2858 vfio_bars_prepare(vdev); 2859 vfio_bars_register(vdev); 2860 2861 ret = vfio_add_capabilities(vdev, errp); 2862 if (ret) { 2863 goto out_teardown; 2864 } 2865 2866 if (vdev->vga) { 2867 vfio_vga_quirk_setup(vdev); 2868 } 2869 2870 for (i = 0; i < PCI_ROM_SLOT; i++) { 2871 vfio_bar_quirk_setup(vdev, i); 2872 } 2873 2874 if (!vdev->igd_opregion && 2875 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { 2876 struct vfio_region_info *opregion; 2877 2878 if (vdev->pdev.qdev.hotplugged) { 2879 error_setg(errp, 2880 "cannot support IGD OpRegion feature on hotplugged " 2881 "device"); 2882 goto out_teardown; 2883 } 2884 2885 ret = vfio_get_dev_region_info(&vdev->vbasedev, 2886 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 2887 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 2888 if (ret) { 2889 error_setg_errno(errp, -ret, 2890 "does not support requested IGD OpRegion feature"); 2891 goto out_teardown; 2892 } 2893 2894 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp); 2895 g_free(opregion); 2896 if (ret) { 2897 goto out_teardown; 2898 } 2899 } 2900 2901 /* QEMU emulates all of MSI & MSIX */ 2902 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { 2903 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, 2904 MSIX_CAP_LENGTH); 2905 } 2906 2907 if (pdev->cap_present & QEMU_PCI_CAP_MSI) { 2908 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, 2909 vdev->msi_cap_size); 2910 } 2911 2912 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { 2913 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 2914 vfio_intx_mmap_enable, vdev); 2915 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); 2916 ret = vfio_intx_enable(vdev, errp); 2917 if (ret) { 2918 goto out_teardown; 2919 } 2920 } 2921 2922 vfio_register_err_notifier(vdev); 2923 vfio_register_req_notifier(vdev); 2924 vfio_setup_resetfn_quirk(vdev); 2925 2926 return; 2927 2928 out_teardown: 2929 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 2930 vfio_teardown_msi(vdev); 2931 vfio_bars_exit(vdev); 2932 error: 2933 error_prepend(errp, ERR_PREFIX, vdev->vbasedev.name); 2934 } 2935 2936 static void vfio_instance_finalize(Object *obj) 2937 { 2938 PCIDevice *pci_dev = PCI_DEVICE(obj); 2939 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pci_dev); 2940 VFIOGroup *group = vdev->vbasedev.group; 2941 2942 vfio_bars_finalize(vdev); 2943 g_free(vdev->emulated_config_bits); 2944 g_free(vdev->rom); 2945 /* 2946 * XXX Leaking igd_opregion is not an oversight, we can't remove the 2947 * fw_cfg entry therefore leaking this allocation seems like the safest 2948 * option. 2949 * 2950 * g_free(vdev->igd_opregion); 2951 */ 2952 vfio_put_device(vdev); 2953 vfio_put_group(group); 2954 } 2955 2956 static void vfio_exitfn(PCIDevice *pdev) 2957 { 2958 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2959 2960 vfio_unregister_req_notifier(vdev); 2961 vfio_unregister_err_notifier(vdev); 2962 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 2963 vfio_disable_interrupts(vdev); 2964 if (vdev->intx.mmap_timer) { 2965 timer_free(vdev->intx.mmap_timer); 2966 } 2967 vfio_teardown_msi(vdev); 2968 vfio_bars_exit(vdev); 2969 } 2970 2971 static void vfio_pci_reset(DeviceState *dev) 2972 { 2973 PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev); 2974 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, pdev); 2975 2976 trace_vfio_pci_reset(vdev->vbasedev.name); 2977 2978 vfio_pci_pre_reset(vdev); 2979 2980 if (vdev->resetfn && !vdev->resetfn(vdev)) { 2981 goto post_reset; 2982 } 2983 2984 if (vdev->vbasedev.reset_works && 2985 (vdev->has_flr || !vdev->has_pm_reset) && 2986 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 2987 trace_vfio_pci_reset_flr(vdev->vbasedev.name); 2988 goto post_reset; 2989 } 2990 2991 /* See if we can do our own bus reset */ 2992 if (!vfio_pci_hot_reset_one(vdev)) { 2993 goto post_reset; 2994 } 2995 2996 /* If nothing else works and the device supports PM reset, use it */ 2997 if (vdev->vbasedev.reset_works && vdev->has_pm_reset && 2998 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 2999 trace_vfio_pci_reset_pm(vdev->vbasedev.name); 3000 goto post_reset; 3001 } 3002 3003 post_reset: 3004 vfio_pci_post_reset(vdev); 3005 } 3006 3007 static void vfio_instance_init(Object *obj) 3008 { 3009 PCIDevice *pci_dev = PCI_DEVICE(obj); 3010 VFIOPCIDevice *vdev = DO_UPCAST(VFIOPCIDevice, pdev, PCI_DEVICE(obj)); 3011 3012 device_add_bootindex_property(obj, &vdev->bootindex, 3013 "bootindex", NULL, 3014 &pci_dev->qdev, NULL); 3015 vdev->host.domain = ~0U; 3016 vdev->host.bus = ~0U; 3017 vdev->host.slot = ~0U; 3018 vdev->host.function = ~0U; 3019 3020 vdev->nv_gpudirect_clique = 0xFF; 3021 } 3022 3023 static Property vfio_pci_dev_properties[] = { 3024 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), 3025 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), 3026 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, 3027 intx.mmap_timeout, 1100), 3028 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, 3029 VFIO_FEATURE_ENABLE_VGA_BIT, false), 3030 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, 3031 VFIO_FEATURE_ENABLE_REQ_BIT, true), 3032 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, 3033 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), 3034 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), 3035 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), 3036 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), 3037 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), 3038 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), 3039 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), 3040 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, 3041 sub_vendor_id, PCI_ANY_ID), 3042 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, 3043 sub_device_id, PCI_ANY_ID), 3044 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), 3045 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice, 3046 nv_gpudirect_clique, 3047 qdev_prop_nv_gpudirect_clique, uint8_t), 3048 /* 3049 * TODO - support passed fds... is this necessary? 3050 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), 3051 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), 3052 */ 3053 DEFINE_PROP_END_OF_LIST(), 3054 }; 3055 3056 static const VMStateDescription vfio_pci_vmstate = { 3057 .name = "vfio-pci", 3058 .unmigratable = 1, 3059 }; 3060 3061 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) 3062 { 3063 DeviceClass *dc = DEVICE_CLASS(klass); 3064 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); 3065 3066 dc->reset = vfio_pci_reset; 3067 dc->props = vfio_pci_dev_properties; 3068 dc->vmsd = &vfio_pci_vmstate; 3069 dc->desc = "VFIO-based PCI device assignment"; 3070 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3071 pdc->realize = vfio_realize; 3072 pdc->exit = vfio_exitfn; 3073 pdc->config_read = vfio_pci_read_config; 3074 pdc->config_write = vfio_pci_write_config; 3075 pdc->is_express = 1; /* We might be */ 3076 } 3077 3078 static const TypeInfo vfio_pci_dev_info = { 3079 .name = "vfio-pci", 3080 .parent = TYPE_PCI_DEVICE, 3081 .instance_size = sizeof(VFIOPCIDevice), 3082 .class_init = vfio_pci_dev_class_init, 3083 .instance_init = vfio_instance_init, 3084 .instance_finalize = vfio_instance_finalize, 3085 .interfaces = (InterfaceInfo[]) { 3086 { INTERFACE_PCIE_DEVICE }, 3087 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3088 { } 3089 }, 3090 }; 3091 3092 static void register_vfio_pci_dev_type(void) 3093 { 3094 type_register_static(&vfio_pci_dev_info); 3095 } 3096 3097 type_init(register_vfio_pci_dev_type) 3098