1 /* 2 * vfio based device assignment support 3 * 4 * Copyright Red Hat, Inc. 2012 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 * 12 * Based on qemu-kvm device-assignment: 13 * Adapted for KVM by Qumranet. 14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) 15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) 16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) 17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) 18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) 19 */ 20 21 #include "qemu/osdep.h" 22 #include <linux/vfio.h> 23 #include <sys/ioctl.h> 24 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "qemu/error-report.h" 29 #include "qemu/option.h" 30 #include "qemu/range.h" 31 #include "qemu/units.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/sysemu.h" 34 #include "pci.h" 35 #include "trace.h" 36 #include "qapi/error.h" 37 38 #define MSIX_CAP_LENGTH 12 39 40 #define TYPE_VFIO_PCI "vfio-pci" 41 #define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI) 42 43 static void vfio_disable_interrupts(VFIOPCIDevice *vdev); 44 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); 45 46 /* 47 * Disabling BAR mmaping can be slow, but toggling it around INTx can 48 * also be a huge overhead. We try to get the best of both worlds by 49 * waiting until an interrupt to disable mmaps (subsequent transitions 50 * to the same state are effectively no overhead). If the interrupt has 51 * been serviced and the time gap is long enough, we re-enable mmaps for 52 * performance. This works well for things like graphics cards, which 53 * may not use their interrupt at all and are penalized to an unusable 54 * level by read/write BAR traps. Other devices, like NICs, have more 55 * regular interrupts and see much better latency by staying in non-mmap 56 * mode. We therefore set the default mmap_timeout such that a ping 57 * is just enough to keep the mmap disabled. Users can experiment with 58 * other options with the x-intx-mmap-timeout-ms parameter (a value of 59 * zero disables the timer). 60 */ 61 static void vfio_intx_mmap_enable(void *opaque) 62 { 63 VFIOPCIDevice *vdev = opaque; 64 65 if (vdev->intx.pending) { 66 timer_mod(vdev->intx.mmap_timer, 67 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 68 return; 69 } 70 71 vfio_mmap_set_enabled(vdev, true); 72 } 73 74 static void vfio_intx_interrupt(void *opaque) 75 { 76 VFIOPCIDevice *vdev = opaque; 77 78 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { 79 return; 80 } 81 82 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); 83 84 vdev->intx.pending = true; 85 pci_irq_assert(&vdev->pdev); 86 vfio_mmap_set_enabled(vdev, false); 87 if (vdev->intx.mmap_timeout) { 88 timer_mod(vdev->intx.mmap_timer, 89 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 90 } 91 } 92 93 static void vfio_intx_eoi(VFIODevice *vbasedev) 94 { 95 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 96 97 if (!vdev->intx.pending) { 98 return; 99 } 100 101 trace_vfio_intx_eoi(vbasedev->name); 102 103 vdev->intx.pending = false; 104 pci_irq_deassert(&vdev->pdev); 105 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 106 } 107 108 static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp) 109 { 110 #ifdef CONFIG_KVM 111 struct kvm_irqfd irqfd = { 112 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 113 .gsi = vdev->intx.route.irq, 114 .flags = KVM_IRQFD_FLAG_RESAMPLE, 115 }; 116 struct vfio_irq_set *irq_set; 117 int ret, argsz; 118 int32_t *pfd; 119 120 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || 121 vdev->intx.route.mode != PCI_INTX_ENABLED || 122 !kvm_resamplefds_enabled()) { 123 return; 124 } 125 126 /* Get to a known interrupt state */ 127 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); 128 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 129 vdev->intx.pending = false; 130 pci_irq_deassert(&vdev->pdev); 131 132 /* Get an eventfd for resample/unmask */ 133 if (event_notifier_init(&vdev->intx.unmask, 0)) { 134 error_setg(errp, "event_notifier_init failed eoi"); 135 goto fail; 136 } 137 138 /* KVM triggers it, VFIO listens for it */ 139 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); 140 141 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 142 error_setg_errno(errp, errno, "failed to setup resample irqfd"); 143 goto fail_irqfd; 144 } 145 146 argsz = sizeof(*irq_set) + sizeof(*pfd); 147 148 irq_set = g_malloc0(argsz); 149 irq_set->argsz = argsz; 150 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; 151 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 152 irq_set->start = 0; 153 irq_set->count = 1; 154 pfd = (int32_t *)&irq_set->data; 155 156 *pfd = irqfd.resamplefd; 157 158 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 159 g_free(irq_set); 160 if (ret) { 161 error_setg_errno(errp, -ret, "failed to setup INTx unmask fd"); 162 goto fail_vfio; 163 } 164 165 /* Let'em rip */ 166 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 167 168 vdev->intx.kvm_accel = true; 169 170 trace_vfio_intx_enable_kvm(vdev->vbasedev.name); 171 172 return; 173 174 fail_vfio: 175 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; 176 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); 177 fail_irqfd: 178 event_notifier_cleanup(&vdev->intx.unmask); 179 fail: 180 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 181 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 182 #endif 183 } 184 185 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) 186 { 187 #ifdef CONFIG_KVM 188 struct kvm_irqfd irqfd = { 189 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 190 .gsi = vdev->intx.route.irq, 191 .flags = KVM_IRQFD_FLAG_DEASSIGN, 192 }; 193 194 if (!vdev->intx.kvm_accel) { 195 return; 196 } 197 198 /* 199 * Get to a known state, hardware masked, QEMU ready to accept new 200 * interrupts, QEMU IRQ de-asserted. 201 */ 202 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 203 vdev->intx.pending = false; 204 pci_irq_deassert(&vdev->pdev); 205 206 /* Tell KVM to stop listening for an INTx irqfd */ 207 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 208 error_report("vfio: Error: Failed to disable INTx irqfd: %m"); 209 } 210 211 /* We only need to close the eventfd for VFIO to cleanup the kernel side */ 212 event_notifier_cleanup(&vdev->intx.unmask); 213 214 /* QEMU starts listening for interrupt events. */ 215 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 216 217 vdev->intx.kvm_accel = false; 218 219 /* If we've missed an event, let it re-fire through QEMU */ 220 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 221 222 trace_vfio_intx_disable_kvm(vdev->vbasedev.name); 223 #endif 224 } 225 226 static void vfio_intx_update(PCIDevice *pdev) 227 { 228 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 229 PCIINTxRoute route; 230 Error *err = NULL; 231 232 if (vdev->interrupt != VFIO_INT_INTx) { 233 return; 234 } 235 236 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); 237 238 if (!pci_intx_route_changed(&vdev->intx.route, &route)) { 239 return; /* Nothing changed */ 240 } 241 242 trace_vfio_intx_update(vdev->vbasedev.name, 243 vdev->intx.route.irq, route.irq); 244 245 vfio_intx_disable_kvm(vdev); 246 247 vdev->intx.route = route; 248 249 if (route.mode != PCI_INTX_ENABLED) { 250 return; 251 } 252 253 vfio_intx_enable_kvm(vdev, &err); 254 if (err) { 255 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 256 } 257 258 /* Re-enable the interrupt in cased we missed an EOI */ 259 vfio_intx_eoi(&vdev->vbasedev); 260 } 261 262 static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp) 263 { 264 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); 265 int ret, argsz, retval = 0; 266 struct vfio_irq_set *irq_set; 267 int32_t *pfd; 268 Error *err = NULL; 269 270 if (!pin) { 271 return 0; 272 } 273 274 vfio_disable_interrupts(vdev); 275 276 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ 277 pci_config_set_interrupt_pin(vdev->pdev.config, pin); 278 279 #ifdef CONFIG_KVM 280 /* 281 * Only conditional to avoid generating error messages on platforms 282 * where we won't actually use the result anyway. 283 */ 284 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { 285 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, 286 vdev->intx.pin); 287 } 288 #endif 289 290 ret = event_notifier_init(&vdev->intx.interrupt, 0); 291 if (ret) { 292 error_setg_errno(errp, -ret, "event_notifier_init failed"); 293 return ret; 294 } 295 296 argsz = sizeof(*irq_set) + sizeof(*pfd); 297 298 irq_set = g_malloc0(argsz); 299 irq_set->argsz = argsz; 300 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 301 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 302 irq_set->start = 0; 303 irq_set->count = 1; 304 pfd = (int32_t *)&irq_set->data; 305 306 *pfd = event_notifier_get_fd(&vdev->intx.interrupt); 307 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); 308 309 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 310 if (ret) { 311 error_setg_errno(errp, -ret, "failed to setup INTx fd"); 312 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 313 event_notifier_cleanup(&vdev->intx.interrupt); 314 retval = -errno; 315 goto cleanup; 316 } 317 318 vfio_intx_enable_kvm(vdev, &err); 319 if (err) { 320 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 321 } 322 323 vdev->interrupt = VFIO_INT_INTx; 324 325 trace_vfio_intx_enable(vdev->vbasedev.name); 326 327 cleanup: 328 g_free(irq_set); 329 330 return retval; 331 } 332 333 static void vfio_intx_disable(VFIOPCIDevice *vdev) 334 { 335 int fd; 336 337 timer_del(vdev->intx.mmap_timer); 338 vfio_intx_disable_kvm(vdev); 339 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 340 vdev->intx.pending = false; 341 pci_irq_deassert(&vdev->pdev); 342 vfio_mmap_set_enabled(vdev, true); 343 344 fd = event_notifier_get_fd(&vdev->intx.interrupt); 345 qemu_set_fd_handler(fd, NULL, NULL, vdev); 346 event_notifier_cleanup(&vdev->intx.interrupt); 347 348 vdev->interrupt = VFIO_INT_NONE; 349 350 trace_vfio_intx_disable(vdev->vbasedev.name); 351 } 352 353 /* 354 * MSI/X 355 */ 356 static void vfio_msi_interrupt(void *opaque) 357 { 358 VFIOMSIVector *vector = opaque; 359 VFIOPCIDevice *vdev = vector->vdev; 360 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); 361 void (*notify)(PCIDevice *dev, unsigned vector); 362 MSIMessage msg; 363 int nr = vector - vdev->msi_vectors; 364 365 if (!event_notifier_test_and_clear(&vector->interrupt)) { 366 return; 367 } 368 369 if (vdev->interrupt == VFIO_INT_MSIX) { 370 get_msg = msix_get_message; 371 notify = msix_notify; 372 373 /* A masked vector firing needs to use the PBA, enable it */ 374 if (msix_is_masked(&vdev->pdev, nr)) { 375 set_bit(nr, vdev->msix->pending); 376 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); 377 trace_vfio_msix_pba_enable(vdev->vbasedev.name); 378 } 379 } else if (vdev->interrupt == VFIO_INT_MSI) { 380 get_msg = msi_get_message; 381 notify = msi_notify; 382 } else { 383 abort(); 384 } 385 386 msg = get_msg(&vdev->pdev, nr); 387 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); 388 notify(&vdev->pdev, nr); 389 } 390 391 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) 392 { 393 struct vfio_irq_set *irq_set; 394 int ret = 0, i, argsz; 395 int32_t *fds; 396 397 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); 398 399 irq_set = g_malloc0(argsz); 400 irq_set->argsz = argsz; 401 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 402 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; 403 irq_set->start = 0; 404 irq_set->count = vdev->nr_vectors; 405 fds = (int32_t *)&irq_set->data; 406 407 for (i = 0; i < vdev->nr_vectors; i++) { 408 int fd = -1; 409 410 /* 411 * MSI vs MSI-X - The guest has direct access to MSI mask and pending 412 * bits, therefore we always use the KVM signaling path when setup. 413 * MSI-X mask and pending bits are emulated, so we want to use the 414 * KVM signaling path only when configured and unmasked. 415 */ 416 if (vdev->msi_vectors[i].use) { 417 if (vdev->msi_vectors[i].virq < 0 || 418 (msix && msix_is_masked(&vdev->pdev, i))) { 419 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); 420 } else { 421 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); 422 } 423 } 424 425 fds[i] = fd; 426 } 427 428 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 429 430 g_free(irq_set); 431 432 return ret; 433 } 434 435 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, 436 int vector_n, bool msix) 437 { 438 int virq; 439 440 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { 441 return; 442 } 443 444 if (event_notifier_init(&vector->kvm_interrupt, 0)) { 445 return; 446 } 447 448 virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); 449 if (virq < 0) { 450 event_notifier_cleanup(&vector->kvm_interrupt); 451 return; 452 } 453 454 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 455 NULL, virq) < 0) { 456 kvm_irqchip_release_virq(kvm_state, virq); 457 event_notifier_cleanup(&vector->kvm_interrupt); 458 return; 459 } 460 461 vector->virq = virq; 462 } 463 464 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) 465 { 466 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 467 vector->virq); 468 kvm_irqchip_release_virq(kvm_state, vector->virq); 469 vector->virq = -1; 470 event_notifier_cleanup(&vector->kvm_interrupt); 471 } 472 473 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, 474 PCIDevice *pdev) 475 { 476 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); 477 kvm_irqchip_commit_routes(kvm_state); 478 } 479 480 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, 481 MSIMessage *msg, IOHandler *handler) 482 { 483 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 484 VFIOMSIVector *vector; 485 int ret; 486 487 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); 488 489 vector = &vdev->msi_vectors[nr]; 490 491 if (!vector->use) { 492 vector->vdev = vdev; 493 vector->virq = -1; 494 if (event_notifier_init(&vector->interrupt, 0)) { 495 error_report("vfio: Error: event_notifier_init failed"); 496 } 497 vector->use = true; 498 msix_vector_use(pdev, nr); 499 } 500 501 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 502 handler, NULL, vector); 503 504 /* 505 * Attempt to enable route through KVM irqchip, 506 * default to userspace handling if unavailable. 507 */ 508 if (vector->virq >= 0) { 509 if (!msg) { 510 vfio_remove_kvm_msi_virq(vector); 511 } else { 512 vfio_update_kvm_msi_virq(vector, *msg, pdev); 513 } 514 } else { 515 if (msg) { 516 vfio_add_kvm_msi_virq(vdev, vector, nr, true); 517 } 518 } 519 520 /* 521 * We don't want to have the host allocate all possible MSI vectors 522 * for a device if they're not in use, so we shutdown and incrementally 523 * increase them as needed. 524 */ 525 if (vdev->nr_vectors < nr + 1) { 526 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 527 vdev->nr_vectors = nr + 1; 528 ret = vfio_enable_vectors(vdev, true); 529 if (ret) { 530 error_report("vfio: failed to enable vectors, %d", ret); 531 } 532 } else { 533 int argsz; 534 struct vfio_irq_set *irq_set; 535 int32_t *pfd; 536 537 argsz = sizeof(*irq_set) + sizeof(*pfd); 538 539 irq_set = g_malloc0(argsz); 540 irq_set->argsz = argsz; 541 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 542 VFIO_IRQ_SET_ACTION_TRIGGER; 543 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 544 irq_set->start = nr; 545 irq_set->count = 1; 546 pfd = (int32_t *)&irq_set->data; 547 548 if (vector->virq >= 0) { 549 *pfd = event_notifier_get_fd(&vector->kvm_interrupt); 550 } else { 551 *pfd = event_notifier_get_fd(&vector->interrupt); 552 } 553 554 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 555 g_free(irq_set); 556 if (ret) { 557 error_report("vfio: failed to modify vector, %d", ret); 558 } 559 } 560 561 /* Disable PBA emulation when nothing more is pending. */ 562 clear_bit(nr, vdev->msix->pending); 563 if (find_first_bit(vdev->msix->pending, 564 vdev->nr_vectors) == vdev->nr_vectors) { 565 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 566 trace_vfio_msix_pba_disable(vdev->vbasedev.name); 567 } 568 569 return 0; 570 } 571 572 static int vfio_msix_vector_use(PCIDevice *pdev, 573 unsigned int nr, MSIMessage msg) 574 { 575 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); 576 } 577 578 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) 579 { 580 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 581 VFIOMSIVector *vector = &vdev->msi_vectors[nr]; 582 583 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); 584 585 /* 586 * There are still old guests that mask and unmask vectors on every 587 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of 588 * the KVM setup in place, simply switch VFIO to use the non-bypass 589 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X 590 * core will mask the interrupt and set pending bits, allowing it to 591 * be re-asserted on unmask. Nothing to do if already using QEMU mode. 592 */ 593 if (vector->virq >= 0) { 594 int argsz; 595 struct vfio_irq_set *irq_set; 596 int32_t *pfd; 597 598 argsz = sizeof(*irq_set) + sizeof(*pfd); 599 600 irq_set = g_malloc0(argsz); 601 irq_set->argsz = argsz; 602 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 603 VFIO_IRQ_SET_ACTION_TRIGGER; 604 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 605 irq_set->start = nr; 606 irq_set->count = 1; 607 pfd = (int32_t *)&irq_set->data; 608 609 *pfd = event_notifier_get_fd(&vector->interrupt); 610 611 ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 612 613 g_free(irq_set); 614 } 615 } 616 617 static void vfio_msix_enable(VFIOPCIDevice *vdev) 618 { 619 vfio_disable_interrupts(vdev); 620 621 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); 622 623 vdev->interrupt = VFIO_INT_MSIX; 624 625 /* 626 * Some communication channels between VF & PF or PF & fw rely on the 627 * physical state of the device and expect that enabling MSI-X from the 628 * guest enables the same on the host. When our guest is Linux, the 629 * guest driver call to pci_enable_msix() sets the enabling bit in the 630 * MSI-X capability, but leaves the vector table masked. We therefore 631 * can't rely on a vector_use callback (from request_irq() in the guest) 632 * to switch the physical device into MSI-X mode because that may come a 633 * long time after pci_enable_msix(). This code enables vector 0 with 634 * triggering to userspace, then immediately release the vector, leaving 635 * the physical device with no vectors enabled, but MSI-X enabled, just 636 * like the guest view. 637 */ 638 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); 639 vfio_msix_vector_release(&vdev->pdev, 0); 640 641 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, 642 vfio_msix_vector_release, NULL)) { 643 error_report("vfio: msix_set_vector_notifiers failed"); 644 } 645 646 trace_vfio_msix_enable(vdev->vbasedev.name); 647 } 648 649 static void vfio_msi_enable(VFIOPCIDevice *vdev) 650 { 651 int ret, i; 652 653 vfio_disable_interrupts(vdev); 654 655 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); 656 retry: 657 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); 658 659 for (i = 0; i < vdev->nr_vectors; i++) { 660 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 661 662 vector->vdev = vdev; 663 vector->virq = -1; 664 vector->use = true; 665 666 if (event_notifier_init(&vector->interrupt, 0)) { 667 error_report("vfio: Error: event_notifier_init failed"); 668 } 669 670 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 671 vfio_msi_interrupt, NULL, vector); 672 673 /* 674 * Attempt to enable route through KVM irqchip, 675 * default to userspace handling if unavailable. 676 */ 677 vfio_add_kvm_msi_virq(vdev, vector, i, false); 678 } 679 680 /* Set interrupt type prior to possible interrupts */ 681 vdev->interrupt = VFIO_INT_MSI; 682 683 ret = vfio_enable_vectors(vdev, false); 684 if (ret) { 685 if (ret < 0) { 686 error_report("vfio: Error: Failed to setup MSI fds: %m"); 687 } else if (ret != vdev->nr_vectors) { 688 error_report("vfio: Error: Failed to enable %d " 689 "MSI vectors, retry with %d", vdev->nr_vectors, ret); 690 } 691 692 for (i = 0; i < vdev->nr_vectors; i++) { 693 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 694 if (vector->virq >= 0) { 695 vfio_remove_kvm_msi_virq(vector); 696 } 697 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 698 NULL, NULL, NULL); 699 event_notifier_cleanup(&vector->interrupt); 700 } 701 702 g_free(vdev->msi_vectors); 703 704 if (ret > 0 && ret != vdev->nr_vectors) { 705 vdev->nr_vectors = ret; 706 goto retry; 707 } 708 vdev->nr_vectors = 0; 709 710 /* 711 * Failing to setup MSI doesn't really fall within any specification. 712 * Let's try leaving interrupts disabled and hope the guest figures 713 * out to fall back to INTx for this device. 714 */ 715 error_report("vfio: Error: Failed to enable MSI"); 716 vdev->interrupt = VFIO_INT_NONE; 717 718 return; 719 } 720 721 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); 722 } 723 724 static void vfio_msi_disable_common(VFIOPCIDevice *vdev) 725 { 726 Error *err = NULL; 727 int i; 728 729 for (i = 0; i < vdev->nr_vectors; i++) { 730 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 731 if (vdev->msi_vectors[i].use) { 732 if (vector->virq >= 0) { 733 vfio_remove_kvm_msi_virq(vector); 734 } 735 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 736 NULL, NULL, NULL); 737 event_notifier_cleanup(&vector->interrupt); 738 } 739 } 740 741 g_free(vdev->msi_vectors); 742 vdev->msi_vectors = NULL; 743 vdev->nr_vectors = 0; 744 vdev->interrupt = VFIO_INT_NONE; 745 746 vfio_intx_enable(vdev, &err); 747 if (err) { 748 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 749 } 750 } 751 752 static void vfio_msix_disable(VFIOPCIDevice *vdev) 753 { 754 int i; 755 756 msix_unset_vector_notifiers(&vdev->pdev); 757 758 /* 759 * MSI-X will only release vectors if MSI-X is still enabled on the 760 * device, check through the rest and release it ourselves if necessary. 761 */ 762 for (i = 0; i < vdev->nr_vectors; i++) { 763 if (vdev->msi_vectors[i].use) { 764 vfio_msix_vector_release(&vdev->pdev, i); 765 msix_vector_unuse(&vdev->pdev, i); 766 } 767 } 768 769 if (vdev->nr_vectors) { 770 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 771 } 772 773 vfio_msi_disable_common(vdev); 774 775 memset(vdev->msix->pending, 0, 776 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); 777 778 trace_vfio_msix_disable(vdev->vbasedev.name); 779 } 780 781 static void vfio_msi_disable(VFIOPCIDevice *vdev) 782 { 783 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); 784 vfio_msi_disable_common(vdev); 785 786 trace_vfio_msi_disable(vdev->vbasedev.name); 787 } 788 789 static void vfio_update_msi(VFIOPCIDevice *vdev) 790 { 791 int i; 792 793 for (i = 0; i < vdev->nr_vectors; i++) { 794 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 795 MSIMessage msg; 796 797 if (!vector->use || vector->virq < 0) { 798 continue; 799 } 800 801 msg = msi_get_message(&vdev->pdev, i); 802 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); 803 } 804 } 805 806 static void vfio_pci_load_rom(VFIOPCIDevice *vdev) 807 { 808 struct vfio_region_info *reg_info; 809 uint64_t size; 810 off_t off = 0; 811 ssize_t bytes; 812 813 if (vfio_get_region_info(&vdev->vbasedev, 814 VFIO_PCI_ROM_REGION_INDEX, ®_info)) { 815 error_report("vfio: Error getting ROM info: %m"); 816 return; 817 } 818 819 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, 820 (unsigned long)reg_info->offset, 821 (unsigned long)reg_info->flags); 822 823 vdev->rom_size = size = reg_info->size; 824 vdev->rom_offset = reg_info->offset; 825 826 g_free(reg_info); 827 828 if (!vdev->rom_size) { 829 vdev->rom_read_failed = true; 830 error_report("vfio-pci: Cannot read device rom at " 831 "%s", vdev->vbasedev.name); 832 error_printf("Device option ROM contents are probably invalid " 833 "(check dmesg).\nSkip option ROM probe with rombar=0, " 834 "or load from file with romfile=\n"); 835 return; 836 } 837 838 vdev->rom = g_malloc(size); 839 memset(vdev->rom, 0xff, size); 840 841 while (size) { 842 bytes = pread(vdev->vbasedev.fd, vdev->rom + off, 843 size, vdev->rom_offset + off); 844 if (bytes == 0) { 845 break; 846 } else if (bytes > 0) { 847 off += bytes; 848 size -= bytes; 849 } else { 850 if (errno == EINTR || errno == EAGAIN) { 851 continue; 852 } 853 error_report("vfio: Error reading device ROM: %m"); 854 break; 855 } 856 } 857 858 /* 859 * Test the ROM signature against our device, if the vendor is correct 860 * but the device ID doesn't match, store the correct device ID and 861 * recompute the checksum. Intel IGD devices need this and are known 862 * to have bogus checksums so we can't simply adjust the checksum. 863 */ 864 if (pci_get_word(vdev->rom) == 0xaa55 && 865 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && 866 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { 867 uint16_t vid, did; 868 869 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); 870 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); 871 872 if (vid == vdev->vendor_id && did != vdev->device_id) { 873 int i; 874 uint8_t csum, *data = vdev->rom; 875 876 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, 877 vdev->device_id); 878 data[6] = 0; 879 880 for (csum = 0, i = 0; i < vdev->rom_size; i++) { 881 csum += data[i]; 882 } 883 884 data[6] = -csum; 885 } 886 } 887 } 888 889 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) 890 { 891 VFIOPCIDevice *vdev = opaque; 892 union { 893 uint8_t byte; 894 uint16_t word; 895 uint32_t dword; 896 uint64_t qword; 897 } val; 898 uint64_t data = 0; 899 900 /* Load the ROM lazily when the guest tries to read it */ 901 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { 902 vfio_pci_load_rom(vdev); 903 } 904 905 memcpy(&val, vdev->rom + addr, 906 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); 907 908 switch (size) { 909 case 1: 910 data = val.byte; 911 break; 912 case 2: 913 data = le16_to_cpu(val.word); 914 break; 915 case 4: 916 data = le32_to_cpu(val.dword); 917 break; 918 default: 919 hw_error("vfio: unsupported read size, %d bytes\n", size); 920 break; 921 } 922 923 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); 924 925 return data; 926 } 927 928 static void vfio_rom_write(void *opaque, hwaddr addr, 929 uint64_t data, unsigned size) 930 { 931 } 932 933 static const MemoryRegionOps vfio_rom_ops = { 934 .read = vfio_rom_read, 935 .write = vfio_rom_write, 936 .endianness = DEVICE_LITTLE_ENDIAN, 937 }; 938 939 static void vfio_pci_size_rom(VFIOPCIDevice *vdev) 940 { 941 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); 942 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; 943 DeviceState *dev = DEVICE(vdev); 944 char *name; 945 int fd = vdev->vbasedev.fd; 946 947 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { 948 /* Since pci handles romfile, just print a message and return */ 949 if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { 950 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified romfile\n", 951 vdev->vbasedev.name); 952 } 953 return; 954 } 955 956 /* 957 * Use the same size ROM BAR as the physical device. The contents 958 * will get filled in later when the guest tries to read it. 959 */ 960 if (pread(fd, &orig, 4, offset) != 4 || 961 pwrite(fd, &size, 4, offset) != 4 || 962 pread(fd, &size, 4, offset) != 4 || 963 pwrite(fd, &orig, 4, offset) != 4) { 964 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); 965 return; 966 } 967 968 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; 969 970 if (!size) { 971 return; 972 } 973 974 if (vfio_blacklist_opt_rom(vdev)) { 975 if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { 976 error_printf("Warning : Device at %s is known to cause system instability issues during option rom execution. Proceeding anyway since user specified non zero value for rombar\n", 977 vdev->vbasedev.name); 978 } else { 979 error_printf("Warning : Rom loading for device at %s has been disabled due to system instability issues. Specify rombar=1 or romfile to force\n", 980 vdev->vbasedev.name); 981 return; 982 } 983 } 984 985 trace_vfio_pci_size_rom(vdev->vbasedev.name, size); 986 987 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); 988 989 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), 990 &vfio_rom_ops, vdev, name, size); 991 g_free(name); 992 993 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, 994 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); 995 996 vdev->rom_read_failed = false; 997 } 998 999 void vfio_vga_write(void *opaque, hwaddr addr, 1000 uint64_t data, unsigned size) 1001 { 1002 VFIOVGARegion *region = opaque; 1003 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1004 union { 1005 uint8_t byte; 1006 uint16_t word; 1007 uint32_t dword; 1008 uint64_t qword; 1009 } buf; 1010 off_t offset = vga->fd_offset + region->offset + addr; 1011 1012 switch (size) { 1013 case 1: 1014 buf.byte = data; 1015 break; 1016 case 2: 1017 buf.word = cpu_to_le16(data); 1018 break; 1019 case 4: 1020 buf.dword = cpu_to_le32(data); 1021 break; 1022 default: 1023 hw_error("vfio: unsupported write size, %d bytes", size); 1024 break; 1025 } 1026 1027 if (pwrite(vga->fd, &buf, size, offset) != size) { 1028 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", 1029 __func__, region->offset + addr, data, size); 1030 } 1031 1032 trace_vfio_vga_write(region->offset + addr, data, size); 1033 } 1034 1035 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) 1036 { 1037 VFIOVGARegion *region = opaque; 1038 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1039 union { 1040 uint8_t byte; 1041 uint16_t word; 1042 uint32_t dword; 1043 uint64_t qword; 1044 } buf; 1045 uint64_t data = 0; 1046 off_t offset = vga->fd_offset + region->offset + addr; 1047 1048 if (pread(vga->fd, &buf, size, offset) != size) { 1049 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", 1050 __func__, region->offset + addr, size); 1051 return (uint64_t)-1; 1052 } 1053 1054 switch (size) { 1055 case 1: 1056 data = buf.byte; 1057 break; 1058 case 2: 1059 data = le16_to_cpu(buf.word); 1060 break; 1061 case 4: 1062 data = le32_to_cpu(buf.dword); 1063 break; 1064 default: 1065 hw_error("vfio: unsupported read size, %d bytes", size); 1066 break; 1067 } 1068 1069 trace_vfio_vga_read(region->offset + addr, size, data); 1070 1071 return data; 1072 } 1073 1074 static const MemoryRegionOps vfio_vga_ops = { 1075 .read = vfio_vga_read, 1076 .write = vfio_vga_write, 1077 .endianness = DEVICE_LITTLE_ENDIAN, 1078 }; 1079 1080 /* 1081 * Expand memory region of sub-page(size < PAGE_SIZE) MMIO BAR to page 1082 * size if the BAR is in an exclusive page in host so that we could map 1083 * this BAR to guest. But this sub-page BAR may not occupy an exclusive 1084 * page in guest. So we should set the priority of the expanded memory 1085 * region to zero in case of overlap with BARs which share the same page 1086 * with the sub-page BAR in guest. Besides, we should also recover the 1087 * size of this sub-page BAR when its base address is changed in guest 1088 * and not page aligned any more. 1089 */ 1090 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar) 1091 { 1092 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1093 VFIORegion *region = &vdev->bars[bar].region; 1094 MemoryRegion *mmap_mr, *region_mr, *base_mr; 1095 PCIIORegion *r; 1096 pcibus_t bar_addr; 1097 uint64_t size = region->size; 1098 1099 /* Make sure that the whole region is allowed to be mmapped */ 1100 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap || 1101 region->mmaps[0].size != region->size) { 1102 return; 1103 } 1104 1105 r = &pdev->io_regions[bar]; 1106 bar_addr = r->addr; 1107 base_mr = vdev->bars[bar].mr; 1108 region_mr = region->mem; 1109 mmap_mr = ®ion->mmaps[0].mem; 1110 1111 /* If BAR is mapped and page aligned, update to fill PAGE_SIZE */ 1112 if (bar_addr != PCI_BAR_UNMAPPED && 1113 !(bar_addr & ~qemu_real_host_page_mask)) { 1114 size = qemu_real_host_page_size; 1115 } 1116 1117 memory_region_transaction_begin(); 1118 1119 if (vdev->bars[bar].size < size) { 1120 memory_region_set_size(base_mr, size); 1121 } 1122 memory_region_set_size(region_mr, size); 1123 memory_region_set_size(mmap_mr, size); 1124 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) { 1125 memory_region_del_subregion(r->address_space, base_mr); 1126 memory_region_add_subregion_overlap(r->address_space, 1127 bar_addr, base_mr, 0); 1128 } 1129 1130 memory_region_transaction_commit(); 1131 } 1132 1133 /* 1134 * PCI config space 1135 */ 1136 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) 1137 { 1138 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1139 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; 1140 1141 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); 1142 emu_bits = le32_to_cpu(emu_bits); 1143 1144 if (emu_bits) { 1145 emu_val = pci_default_read_config(pdev, addr, len); 1146 } 1147 1148 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { 1149 ssize_t ret; 1150 1151 ret = pread(vdev->vbasedev.fd, &phys_val, len, 1152 vdev->config_offset + addr); 1153 if (ret != len) { 1154 error_report("%s(%s, 0x%x, 0x%x) failed: %m", 1155 __func__, vdev->vbasedev.name, addr, len); 1156 return -errno; 1157 } 1158 phys_val = le32_to_cpu(phys_val); 1159 } 1160 1161 val = (emu_val & emu_bits) | (phys_val & ~emu_bits); 1162 1163 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); 1164 1165 return val; 1166 } 1167 1168 void vfio_pci_write_config(PCIDevice *pdev, 1169 uint32_t addr, uint32_t val, int len) 1170 { 1171 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1172 uint32_t val_le = cpu_to_le32(val); 1173 1174 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); 1175 1176 /* Write everything to VFIO, let it filter out what we can't write */ 1177 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) 1178 != len) { 1179 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", 1180 __func__, vdev->vbasedev.name, addr, val, len); 1181 } 1182 1183 /* MSI/MSI-X Enabling/Disabling */ 1184 if (pdev->cap_present & QEMU_PCI_CAP_MSI && 1185 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { 1186 int is_enabled, was_enabled = msi_enabled(pdev); 1187 1188 pci_default_write_config(pdev, addr, val, len); 1189 1190 is_enabled = msi_enabled(pdev); 1191 1192 if (!was_enabled) { 1193 if (is_enabled) { 1194 vfio_msi_enable(vdev); 1195 } 1196 } else { 1197 if (!is_enabled) { 1198 vfio_msi_disable(vdev); 1199 } else { 1200 vfio_update_msi(vdev); 1201 } 1202 } 1203 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && 1204 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { 1205 int is_enabled, was_enabled = msix_enabled(pdev); 1206 1207 pci_default_write_config(pdev, addr, val, len); 1208 1209 is_enabled = msix_enabled(pdev); 1210 1211 if (!was_enabled && is_enabled) { 1212 vfio_msix_enable(vdev); 1213 } else if (was_enabled && !is_enabled) { 1214 vfio_msix_disable(vdev); 1215 } 1216 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) || 1217 range_covers_byte(addr, len, PCI_COMMAND)) { 1218 pcibus_t old_addr[PCI_NUM_REGIONS - 1]; 1219 int bar; 1220 1221 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1222 old_addr[bar] = pdev->io_regions[bar].addr; 1223 } 1224 1225 pci_default_write_config(pdev, addr, val, len); 1226 1227 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1228 if (old_addr[bar] != pdev->io_regions[bar].addr && 1229 vdev->bars[bar].region.size > 0 && 1230 vdev->bars[bar].region.size < qemu_real_host_page_size) { 1231 vfio_sub_page_bar_update_mapping(pdev, bar); 1232 } 1233 } 1234 } else { 1235 /* Write everything to QEMU to keep emulated bits correct */ 1236 pci_default_write_config(pdev, addr, val, len); 1237 } 1238 } 1239 1240 /* 1241 * Interrupt setup 1242 */ 1243 static void vfio_disable_interrupts(VFIOPCIDevice *vdev) 1244 { 1245 /* 1246 * More complicated than it looks. Disabling MSI/X transitions the 1247 * device to INTx mode (if supported). Therefore we need to first 1248 * disable MSI/X and then cleanup by disabling INTx. 1249 */ 1250 if (vdev->interrupt == VFIO_INT_MSIX) { 1251 vfio_msix_disable(vdev); 1252 } else if (vdev->interrupt == VFIO_INT_MSI) { 1253 vfio_msi_disable(vdev); 1254 } 1255 1256 if (vdev->interrupt == VFIO_INT_INTx) { 1257 vfio_intx_disable(vdev); 1258 } 1259 } 1260 1261 static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1262 { 1263 uint16_t ctrl; 1264 bool msi_64bit, msi_maskbit; 1265 int ret, entries; 1266 Error *err = NULL; 1267 1268 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), 1269 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { 1270 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); 1271 return -errno; 1272 } 1273 ctrl = le16_to_cpu(ctrl); 1274 1275 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); 1276 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); 1277 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); 1278 1279 trace_vfio_msi_setup(vdev->vbasedev.name, pos); 1280 1281 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err); 1282 if (ret < 0) { 1283 if (ret == -ENOTSUP) { 1284 return 0; 1285 } 1286 error_propagate_prepend(errp, err, "msi_init failed: "); 1287 return ret; 1288 } 1289 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); 1290 1291 return 0; 1292 } 1293 1294 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) 1295 { 1296 off_t start, end; 1297 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; 1298 1299 /* 1300 * If the host driver allows mapping of a MSIX data, we are going to 1301 * do map the entire BAR and emulate MSIX table on top of that. 1302 */ 1303 if (vfio_has_region_cap(&vdev->vbasedev, region->nr, 1304 VFIO_REGION_INFO_CAP_MSIX_MAPPABLE)) { 1305 return; 1306 } 1307 1308 /* 1309 * We expect to find a single mmap covering the whole BAR, anything else 1310 * means it's either unsupported or already setup. 1311 */ 1312 if (region->nr_mmaps != 1 || region->mmaps[0].offset || 1313 region->size != region->mmaps[0].size) { 1314 return; 1315 } 1316 1317 /* MSI-X table start and end aligned to host page size */ 1318 start = vdev->msix->table_offset & qemu_real_host_page_mask; 1319 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + 1320 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); 1321 1322 /* 1323 * Does the MSI-X table cover the beginning of the BAR? The whole BAR? 1324 * NB - Host page size is necessarily a power of two and so is the PCI 1325 * BAR (not counting EA yet), therefore if we have host page aligned 1326 * @start and @end, then any remainder of the BAR before or after those 1327 * must be at least host page sized and therefore mmap'able. 1328 */ 1329 if (!start) { 1330 if (end >= region->size) { 1331 region->nr_mmaps = 0; 1332 g_free(region->mmaps); 1333 region->mmaps = NULL; 1334 trace_vfio_msix_fixup(vdev->vbasedev.name, 1335 vdev->msix->table_bar, 0, 0); 1336 } else { 1337 region->mmaps[0].offset = end; 1338 region->mmaps[0].size = region->size - end; 1339 trace_vfio_msix_fixup(vdev->vbasedev.name, 1340 vdev->msix->table_bar, region->mmaps[0].offset, 1341 region->mmaps[0].offset + region->mmaps[0].size); 1342 } 1343 1344 /* Maybe it's aligned at the end of the BAR */ 1345 } else if (end >= region->size) { 1346 region->mmaps[0].size = start; 1347 trace_vfio_msix_fixup(vdev->vbasedev.name, 1348 vdev->msix->table_bar, region->mmaps[0].offset, 1349 region->mmaps[0].offset + region->mmaps[0].size); 1350 1351 /* Otherwise it must split the BAR */ 1352 } else { 1353 region->nr_mmaps = 2; 1354 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); 1355 1356 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); 1357 1358 region->mmaps[0].size = start; 1359 trace_vfio_msix_fixup(vdev->vbasedev.name, 1360 vdev->msix->table_bar, region->mmaps[0].offset, 1361 region->mmaps[0].offset + region->mmaps[0].size); 1362 1363 region->mmaps[1].offset = end; 1364 region->mmaps[1].size = region->size - end; 1365 trace_vfio_msix_fixup(vdev->vbasedev.name, 1366 vdev->msix->table_bar, region->mmaps[1].offset, 1367 region->mmaps[1].offset + region->mmaps[1].size); 1368 } 1369 } 1370 1371 static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp) 1372 { 1373 int target_bar = -1; 1374 size_t msix_sz; 1375 1376 if (!vdev->msix || vdev->msix_relo == OFF_AUTOPCIBAR_OFF) { 1377 return; 1378 } 1379 1380 /* The actual minimum size of MSI-X structures */ 1381 msix_sz = (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) + 1382 (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8); 1383 /* Round up to host pages, we don't want to share a page */ 1384 msix_sz = REAL_HOST_PAGE_ALIGN(msix_sz); 1385 /* PCI BARs must be a power of 2 */ 1386 msix_sz = pow2ceil(msix_sz); 1387 1388 if (vdev->msix_relo == OFF_AUTOPCIBAR_AUTO) { 1389 /* 1390 * TODO: Lookup table for known devices. 1391 * 1392 * Logically we might use an algorithm here to select the BAR adding 1393 * the least additional MMIO space, but we cannot programatically 1394 * predict the driver dependency on BAR ordering or sizing, therefore 1395 * 'auto' becomes a lookup for combinations reported to work. 1396 */ 1397 if (target_bar < 0) { 1398 error_setg(errp, "No automatic MSI-X relocation available for " 1399 "device %04x:%04x", vdev->vendor_id, vdev->device_id); 1400 return; 1401 } 1402 } else { 1403 target_bar = (int)(vdev->msix_relo - OFF_AUTOPCIBAR_BAR0); 1404 } 1405 1406 /* I/O port BARs cannot host MSI-X structures */ 1407 if (vdev->bars[target_bar].ioport) { 1408 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1409 "I/O port BAR", target_bar); 1410 return; 1411 } 1412 1413 /* Cannot use a BAR in the "shadow" of a 64-bit BAR */ 1414 if (!vdev->bars[target_bar].size && 1415 target_bar > 0 && vdev->bars[target_bar - 1].mem64) { 1416 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1417 "consumed by 64-bit BAR %d", target_bar, target_bar - 1); 1418 return; 1419 } 1420 1421 /* 2GB max size for 32-bit BARs, cannot double if already > 1G */ 1422 if (vdev->bars[target_bar].size > 1 * GiB && 1423 !vdev->bars[target_bar].mem64) { 1424 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1425 "no space to extend 32-bit BAR", target_bar); 1426 return; 1427 } 1428 1429 /* 1430 * If adding a new BAR, test if we can make it 64bit. We make it 1431 * prefetchable since QEMU MSI-X emulation has no read side effects 1432 * and doing so makes mapping more flexible. 1433 */ 1434 if (!vdev->bars[target_bar].size) { 1435 if (target_bar < (PCI_ROM_SLOT - 1) && 1436 !vdev->bars[target_bar + 1].size) { 1437 vdev->bars[target_bar].mem64 = true; 1438 vdev->bars[target_bar].type = PCI_BASE_ADDRESS_MEM_TYPE_64; 1439 } 1440 vdev->bars[target_bar].type |= PCI_BASE_ADDRESS_MEM_PREFETCH; 1441 vdev->bars[target_bar].size = msix_sz; 1442 vdev->msix->table_offset = 0; 1443 } else { 1444 vdev->bars[target_bar].size = MAX(vdev->bars[target_bar].size * 2, 1445 msix_sz * 2); 1446 /* 1447 * Due to above size calc, MSI-X always starts halfway into the BAR, 1448 * which will always be a separate host page. 1449 */ 1450 vdev->msix->table_offset = vdev->bars[target_bar].size / 2; 1451 } 1452 1453 vdev->msix->table_bar = target_bar; 1454 vdev->msix->pba_bar = target_bar; 1455 /* Requires 8-byte alignment, but PCI_MSIX_ENTRY_SIZE guarantees that */ 1456 vdev->msix->pba_offset = vdev->msix->table_offset + 1457 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE); 1458 1459 trace_vfio_msix_relo(vdev->vbasedev.name, 1460 vdev->msix->table_bar, vdev->msix->table_offset); 1461 } 1462 1463 /* 1464 * We don't have any control over how pci_add_capability() inserts 1465 * capabilities into the chain. In order to setup MSI-X we need a 1466 * MemoryRegion for the BAR. In order to setup the BAR and not 1467 * attempt to mmap the MSI-X table area, which VFIO won't allow, we 1468 * need to first look for where the MSI-X table lives. So we 1469 * unfortunately split MSI-X setup across two functions. 1470 */ 1471 static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) 1472 { 1473 uint8_t pos; 1474 uint16_t ctrl; 1475 uint32_t table, pba; 1476 int fd = vdev->vbasedev.fd; 1477 VFIOMSIXInfo *msix; 1478 1479 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); 1480 if (!pos) { 1481 return; 1482 } 1483 1484 if (pread(fd, &ctrl, sizeof(ctrl), 1485 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { 1486 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS"); 1487 return; 1488 } 1489 1490 if (pread(fd, &table, sizeof(table), 1491 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { 1492 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE"); 1493 return; 1494 } 1495 1496 if (pread(fd, &pba, sizeof(pba), 1497 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { 1498 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA"); 1499 return; 1500 } 1501 1502 ctrl = le16_to_cpu(ctrl); 1503 table = le32_to_cpu(table); 1504 pba = le32_to_cpu(pba); 1505 1506 msix = g_malloc0(sizeof(*msix)); 1507 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 1508 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 1509 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 1510 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 1511 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 1512 1513 /* 1514 * Test the size of the pba_offset variable and catch if it extends outside 1515 * of the specified BAR. If it is the case, we need to apply a hardware 1516 * specific quirk if the device is known or we have a broken configuration. 1517 */ 1518 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { 1519 /* 1520 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 1521 * adapters. The T5 hardware returns an incorrect value of 0x8000 for 1522 * the VF PBA offset while the BAR itself is only 8k. The correct value 1523 * is 0x1000, so we hard code that here. 1524 */ 1525 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && 1526 (vdev->device_id & 0xff00) == 0x5800) { 1527 msix->pba_offset = 0x1000; 1528 } else { 1529 error_setg(errp, "hardware reports invalid configuration, " 1530 "MSIX PBA outside of specified BAR"); 1531 g_free(msix); 1532 return; 1533 } 1534 } 1535 1536 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, 1537 msix->table_offset, msix->entries); 1538 vdev->msix = msix; 1539 1540 vfio_pci_fixup_msix_region(vdev); 1541 1542 vfio_pci_relocate_msix(vdev, errp); 1543 } 1544 1545 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1546 { 1547 int ret; 1548 Error *err = NULL; 1549 1550 vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * 1551 sizeof(unsigned long)); 1552 ret = msix_init(&vdev->pdev, vdev->msix->entries, 1553 vdev->bars[vdev->msix->table_bar].mr, 1554 vdev->msix->table_bar, vdev->msix->table_offset, 1555 vdev->bars[vdev->msix->pba_bar].mr, 1556 vdev->msix->pba_bar, vdev->msix->pba_offset, pos, 1557 &err); 1558 if (ret < 0) { 1559 if (ret == -ENOTSUP) { 1560 warn_report_err(err); 1561 return 0; 1562 } 1563 1564 error_propagate(errp, err); 1565 return ret; 1566 } 1567 1568 /* 1569 * The PCI spec suggests that devices provide additional alignment for 1570 * MSI-X structures and avoid overlapping non-MSI-X related registers. 1571 * For an assigned device, this hopefully means that emulation of MSI-X 1572 * structures does not affect the performance of the device. If devices 1573 * fail to provide that alignment, a significant performance penalty may 1574 * result, for instance Mellanox MT27500 VFs: 1575 * http://www.spinics.net/lists/kvm/msg125881.html 1576 * 1577 * The PBA is simply not that important for such a serious regression and 1578 * most drivers do not appear to look at it. The solution for this is to 1579 * disable the PBA MemoryRegion unless it's being used. We disable it 1580 * here and only enable it if a masked vector fires through QEMU. As the 1581 * vector-use notifier is called, which occurs on unmask, we test whether 1582 * PBA emulation is needed and again disable if not. 1583 */ 1584 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 1585 1586 /* 1587 * The emulated machine may provide a paravirt interface for MSIX setup 1588 * so it is not strictly necessary to emulate MSIX here. This becomes 1589 * helpful when frequently accessed MMIO registers are located in 1590 * subpages adjacent to the MSIX table but the MSIX data containing page 1591 * cannot be mapped because of a host page size bigger than the MSIX table 1592 * alignment. 1593 */ 1594 if (object_property_get_bool(OBJECT(qdev_get_machine()), 1595 "vfio-no-msix-emulation", NULL)) { 1596 memory_region_set_enabled(&vdev->pdev.msix_table_mmio, false); 1597 } 1598 1599 return 0; 1600 } 1601 1602 static void vfio_teardown_msi(VFIOPCIDevice *vdev) 1603 { 1604 msi_uninit(&vdev->pdev); 1605 1606 if (vdev->msix) { 1607 msix_uninit(&vdev->pdev, 1608 vdev->bars[vdev->msix->table_bar].mr, 1609 vdev->bars[vdev->msix->pba_bar].mr); 1610 g_free(vdev->msix->pending); 1611 } 1612 } 1613 1614 /* 1615 * Resource setup 1616 */ 1617 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) 1618 { 1619 int i; 1620 1621 for (i = 0; i < PCI_ROM_SLOT; i++) { 1622 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); 1623 } 1624 } 1625 1626 static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr) 1627 { 1628 VFIOBAR *bar = &vdev->bars[nr]; 1629 1630 uint32_t pci_bar; 1631 int ret; 1632 1633 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ 1634 if (!bar->region.size) { 1635 return; 1636 } 1637 1638 /* Determine what type of BAR this is for registration */ 1639 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), 1640 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); 1641 if (ret != sizeof(pci_bar)) { 1642 error_report("vfio: Failed to read BAR %d (%m)", nr); 1643 return; 1644 } 1645 1646 pci_bar = le32_to_cpu(pci_bar); 1647 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); 1648 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); 1649 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : 1650 ~PCI_BASE_ADDRESS_MEM_MASK); 1651 bar->size = bar->region.size; 1652 } 1653 1654 static void vfio_bars_prepare(VFIOPCIDevice *vdev) 1655 { 1656 int i; 1657 1658 for (i = 0; i < PCI_ROM_SLOT; i++) { 1659 vfio_bar_prepare(vdev, i); 1660 } 1661 } 1662 1663 static void vfio_bar_register(VFIOPCIDevice *vdev, int nr) 1664 { 1665 VFIOBAR *bar = &vdev->bars[nr]; 1666 char *name; 1667 1668 if (!bar->size) { 1669 return; 1670 } 1671 1672 bar->mr = g_new0(MemoryRegion, 1); 1673 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr); 1674 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size); 1675 g_free(name); 1676 1677 if (bar->region.size) { 1678 memory_region_add_subregion(bar->mr, 0, bar->region.mem); 1679 1680 if (vfio_region_mmap(&bar->region)) { 1681 error_report("Failed to mmap %s BAR %d. Performance may be slow", 1682 vdev->vbasedev.name, nr); 1683 } 1684 } 1685 1686 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr); 1687 } 1688 1689 static void vfio_bars_register(VFIOPCIDevice *vdev) 1690 { 1691 int i; 1692 1693 for (i = 0; i < PCI_ROM_SLOT; i++) { 1694 vfio_bar_register(vdev, i); 1695 } 1696 } 1697 1698 static void vfio_bars_exit(VFIOPCIDevice *vdev) 1699 { 1700 int i; 1701 1702 for (i = 0; i < PCI_ROM_SLOT; i++) { 1703 VFIOBAR *bar = &vdev->bars[i]; 1704 1705 vfio_bar_quirk_exit(vdev, i); 1706 vfio_region_exit(&bar->region); 1707 if (bar->region.size) { 1708 memory_region_del_subregion(bar->mr, bar->region.mem); 1709 } 1710 } 1711 1712 if (vdev->vga) { 1713 pci_unregister_vga(&vdev->pdev); 1714 vfio_vga_quirk_exit(vdev); 1715 } 1716 } 1717 1718 static void vfio_bars_finalize(VFIOPCIDevice *vdev) 1719 { 1720 int i; 1721 1722 for (i = 0; i < PCI_ROM_SLOT; i++) { 1723 VFIOBAR *bar = &vdev->bars[i]; 1724 1725 vfio_bar_quirk_finalize(vdev, i); 1726 vfio_region_finalize(&bar->region); 1727 if (bar->size) { 1728 object_unparent(OBJECT(bar->mr)); 1729 g_free(bar->mr); 1730 } 1731 } 1732 1733 if (vdev->vga) { 1734 vfio_vga_quirk_finalize(vdev); 1735 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { 1736 object_unparent(OBJECT(&vdev->vga->region[i].mem)); 1737 } 1738 g_free(vdev->vga); 1739 } 1740 } 1741 1742 /* 1743 * General setup 1744 */ 1745 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) 1746 { 1747 uint8_t tmp; 1748 uint16_t next = PCI_CONFIG_SPACE_SIZE; 1749 1750 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; 1751 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { 1752 if (tmp > pos && tmp < next) { 1753 next = tmp; 1754 } 1755 } 1756 1757 return next - pos; 1758 } 1759 1760 1761 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) 1762 { 1763 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; 1764 1765 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; 1766 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { 1767 if (tmp > pos && tmp < next) { 1768 next = tmp; 1769 } 1770 } 1771 1772 return next - pos; 1773 } 1774 1775 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) 1776 { 1777 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); 1778 } 1779 1780 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, 1781 uint16_t val, uint16_t mask) 1782 { 1783 vfio_set_word_bits(vdev->pdev.config + pos, val, mask); 1784 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); 1785 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); 1786 } 1787 1788 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) 1789 { 1790 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); 1791 } 1792 1793 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, 1794 uint32_t val, uint32_t mask) 1795 { 1796 vfio_set_long_bits(vdev->pdev.config + pos, val, mask); 1797 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); 1798 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); 1799 } 1800 1801 static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1802 Error **errp) 1803 { 1804 uint16_t flags; 1805 uint8_t type; 1806 1807 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); 1808 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; 1809 1810 if (type != PCI_EXP_TYPE_ENDPOINT && 1811 type != PCI_EXP_TYPE_LEG_END && 1812 type != PCI_EXP_TYPE_RC_END) { 1813 1814 error_setg(errp, "assignment of PCIe type 0x%x " 1815 "devices is not currently supported", type); 1816 return -EINVAL; 1817 } 1818 1819 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) { 1820 PCIBus *bus = pci_get_bus(&vdev->pdev); 1821 PCIDevice *bridge; 1822 1823 /* 1824 * Traditionally PCI device assignment exposes the PCIe capability 1825 * as-is on non-express buses. The reason being that some drivers 1826 * simply assume that it's there, for example tg3. However when 1827 * we're running on a native PCIe machine type, like Q35, we need 1828 * to hide the PCIe capability. The reason for this is twofold; 1829 * first Windows guests get a Code 10 error when the PCIe capability 1830 * is exposed in this configuration. Therefore express devices won't 1831 * work at all unless they're attached to express buses in the VM. 1832 * Second, a native PCIe machine introduces the possibility of fine 1833 * granularity IOMMUs supporting both translation and isolation. 1834 * Guest code to discover the IOMMU visibility of a device, such as 1835 * IOMMU grouping code on Linux, is very aware of device types and 1836 * valid transitions between bus types. An express device on a non- 1837 * express bus is not a valid combination on bare metal systems. 1838 * 1839 * Drivers that require a PCIe capability to make the device 1840 * functional are simply going to need to have their devices placed 1841 * on a PCIe bus in the VM. 1842 */ 1843 while (!pci_bus_is_root(bus)) { 1844 bridge = pci_bridge_get_device(bus); 1845 bus = pci_get_bus(bridge); 1846 } 1847 1848 if (pci_bus_is_express(bus)) { 1849 return 0; 1850 } 1851 1852 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) { 1853 /* 1854 * On a Root Complex bus Endpoints become Root Complex Integrated 1855 * Endpoints, which changes the type and clears the LNK & LNK2 fields. 1856 */ 1857 if (type == PCI_EXP_TYPE_ENDPOINT) { 1858 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1859 PCI_EXP_TYPE_RC_END << 4, 1860 PCI_EXP_FLAGS_TYPE); 1861 1862 /* Link Capabilities, Status, and Control goes away */ 1863 if (size > PCI_EXP_LNKCTL) { 1864 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); 1865 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1866 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); 1867 1868 #ifndef PCI_EXP_LNKCAP2 1869 #define PCI_EXP_LNKCAP2 44 1870 #endif 1871 #ifndef PCI_EXP_LNKSTA2 1872 #define PCI_EXP_LNKSTA2 50 1873 #endif 1874 /* Link 2 Capabilities, Status, and Control goes away */ 1875 if (size > PCI_EXP_LNKCAP2) { 1876 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); 1877 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); 1878 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); 1879 } 1880 } 1881 1882 } else if (type == PCI_EXP_TYPE_LEG_END) { 1883 /* 1884 * Legacy endpoints don't belong on the root complex. Windows 1885 * seems to be happier with devices if we skip the capability. 1886 */ 1887 return 0; 1888 } 1889 1890 } else { 1891 /* 1892 * Convert Root Complex Integrated Endpoints to regular endpoints. 1893 * These devices don't support LNK/LNK2 capabilities, so make them up. 1894 */ 1895 if (type == PCI_EXP_TYPE_RC_END) { 1896 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1897 PCI_EXP_TYPE_ENDPOINT << 4, 1898 PCI_EXP_FLAGS_TYPE); 1899 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 1900 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25, ~0); 1901 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1902 } 1903 1904 /* Mark the Link Status bits as emulated to allow virtual negotiation */ 1905 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 1906 pci_get_word(vdev->pdev.config + pos + 1907 PCI_EXP_LNKSTA), 1908 PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); 1909 } 1910 1911 /* 1912 * Intel 82599 SR-IOV VFs report an invalid PCIe capability version 0 1913 * (Niantic errate #35) causing Windows to error with a Code 10 for the 1914 * device on Q35. Fixup any such devices to report version 1. If we 1915 * were to remove the capability entirely the guest would lose extended 1916 * config space. 1917 */ 1918 if ((flags & PCI_EXP_FLAGS_VERS) == 0) { 1919 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1920 1, PCI_EXP_FLAGS_VERS); 1921 } 1922 1923 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, 1924 errp); 1925 if (pos < 0) { 1926 return pos; 1927 } 1928 1929 vdev->pdev.exp.exp_cap = pos; 1930 1931 return pos; 1932 } 1933 1934 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) 1935 { 1936 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); 1937 1938 if (cap & PCI_EXP_DEVCAP_FLR) { 1939 trace_vfio_check_pcie_flr(vdev->vbasedev.name); 1940 vdev->has_flr = true; 1941 } 1942 } 1943 1944 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) 1945 { 1946 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); 1947 1948 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { 1949 trace_vfio_check_pm_reset(vdev->vbasedev.name); 1950 vdev->has_pm_reset = true; 1951 } 1952 } 1953 1954 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) 1955 { 1956 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); 1957 1958 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { 1959 trace_vfio_check_af_flr(vdev->vbasedev.name); 1960 vdev->has_flr = true; 1961 } 1962 } 1963 1964 static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) 1965 { 1966 PCIDevice *pdev = &vdev->pdev; 1967 uint8_t cap_id, next, size; 1968 int ret; 1969 1970 cap_id = pdev->config[pos]; 1971 next = pdev->config[pos + PCI_CAP_LIST_NEXT]; 1972 1973 /* 1974 * If it becomes important to configure capabilities to their actual 1975 * size, use this as the default when it's something we don't recognize. 1976 * Since QEMU doesn't actually handle many of the config accesses, 1977 * exact size doesn't seem worthwhile. 1978 */ 1979 size = vfio_std_cap_max_size(pdev, pos); 1980 1981 /* 1982 * pci_add_capability always inserts the new capability at the head 1983 * of the chain. Therefore to end up with a chain that matches the 1984 * physical device, we insert from the end by making this recursive. 1985 * This is also why we pre-calculate size above as cached config space 1986 * will be changed as we unwind the stack. 1987 */ 1988 if (next) { 1989 ret = vfio_add_std_cap(vdev, next, errp); 1990 if (ret) { 1991 return ret; 1992 } 1993 } else { 1994 /* Begin the rebuild, use QEMU emulated list bits */ 1995 pdev->config[PCI_CAPABILITY_LIST] = 0; 1996 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; 1997 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 1998 1999 ret = vfio_add_virt_caps(vdev, errp); 2000 if (ret) { 2001 return ret; 2002 } 2003 } 2004 2005 /* Scale down size, esp in case virt caps were added above */ 2006 size = MIN(size, vfio_std_cap_max_size(pdev, pos)); 2007 2008 /* Use emulated next pointer to allow dropping caps */ 2009 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); 2010 2011 switch (cap_id) { 2012 case PCI_CAP_ID_MSI: 2013 ret = vfio_msi_setup(vdev, pos, errp); 2014 break; 2015 case PCI_CAP_ID_EXP: 2016 vfio_check_pcie_flr(vdev, pos); 2017 ret = vfio_setup_pcie_cap(vdev, pos, size, errp); 2018 break; 2019 case PCI_CAP_ID_MSIX: 2020 ret = vfio_msix_setup(vdev, pos, errp); 2021 break; 2022 case PCI_CAP_ID_PM: 2023 vfio_check_pm_reset(vdev, pos); 2024 vdev->pm_cap = pos; 2025 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2026 break; 2027 case PCI_CAP_ID_AF: 2028 vfio_check_af_flr(vdev, pos); 2029 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2030 break; 2031 default: 2032 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2033 break; 2034 } 2035 2036 if (ret < 0) { 2037 error_prepend(errp, 2038 "failed to add PCI capability 0x%x[0x%x]@0x%x: ", 2039 cap_id, size, pos); 2040 return ret; 2041 } 2042 2043 return 0; 2044 } 2045 2046 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) 2047 { 2048 PCIDevice *pdev = &vdev->pdev; 2049 uint32_t header; 2050 uint16_t cap_id, next, size; 2051 uint8_t cap_ver; 2052 uint8_t *config; 2053 2054 /* Only add extended caps if we have them and the guest can see them */ 2055 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) || 2056 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { 2057 return; 2058 } 2059 2060 /* 2061 * pcie_add_capability always inserts the new capability at the tail 2062 * of the chain. Therefore to end up with a chain that matches the 2063 * physical device, we cache the config space to avoid overwriting 2064 * the original config space when we parse the extended capabilities. 2065 */ 2066 config = g_memdup(pdev->config, vdev->config_size); 2067 2068 /* 2069 * Extended capabilities are chained with each pointing to the next, so we 2070 * can drop anything other than the head of the chain simply by modifying 2071 * the previous next pointer. Seed the head of the chain here such that 2072 * we can simply skip any capabilities we want to drop below, regardless 2073 * of their position in the chain. If this stub capability still exists 2074 * after we add the capabilities we want to expose, update the capability 2075 * ID to zero. Note that we cannot seed with the capability header being 2076 * zero as this conflicts with definition of an absent capability chain 2077 * and prevents capabilities beyond the head of the list from being added. 2078 * By replacing the dummy capability ID with zero after walking the device 2079 * chain, we also transparently mark extended capabilities as absent if 2080 * no capabilities were added. Note that the PCIe spec defines an absence 2081 * of extended capabilities to be determined by a value of zero for the 2082 * capability ID, version, AND next pointer. A non-zero next pointer 2083 * should be sufficient to indicate additional capabilities are present, 2084 * which will occur if we call pcie_add_capability() below. The entire 2085 * first dword is emulated to support this. 2086 * 2087 * NB. The kernel side does similar masking, so be prepared that our 2088 * view of the device may also contain a capability ID zero in the head 2089 * of the chain. Skip it for the same reason that we cannot seed the 2090 * chain with a zero capability. 2091 */ 2092 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, 2093 PCI_EXT_CAP(0xFFFF, 0, 0)); 2094 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 2095 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); 2096 2097 for (next = PCI_CONFIG_SPACE_SIZE; next; 2098 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { 2099 header = pci_get_long(config + next); 2100 cap_id = PCI_EXT_CAP_ID(header); 2101 cap_ver = PCI_EXT_CAP_VER(header); 2102 2103 /* 2104 * If it becomes important to configure extended capabilities to their 2105 * actual size, use this as the default when it's something we don't 2106 * recognize. Since QEMU doesn't actually handle many of the config 2107 * accesses, exact size doesn't seem worthwhile. 2108 */ 2109 size = vfio_ext_cap_max_size(config, next); 2110 2111 /* Use emulated next pointer to allow dropping extended caps */ 2112 pci_long_test_and_set_mask(vdev->emulated_config_bits + next, 2113 PCI_EXT_CAP_NEXT_MASK); 2114 2115 switch (cap_id) { 2116 case 0: /* kernel masked capability */ 2117 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ 2118 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */ 2119 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); 2120 break; 2121 default: 2122 pcie_add_capability(pdev, cap_id, cap_ver, next, size); 2123 } 2124 2125 } 2126 2127 /* Cleanup chain head ID if necessary */ 2128 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { 2129 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); 2130 } 2131 2132 g_free(config); 2133 return; 2134 } 2135 2136 static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp) 2137 { 2138 PCIDevice *pdev = &vdev->pdev; 2139 int ret; 2140 2141 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || 2142 !pdev->config[PCI_CAPABILITY_LIST]) { 2143 return 0; /* Nothing to add */ 2144 } 2145 2146 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp); 2147 if (ret) { 2148 return ret; 2149 } 2150 2151 vfio_add_ext_cap(vdev); 2152 return 0; 2153 } 2154 2155 static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) 2156 { 2157 PCIDevice *pdev = &vdev->pdev; 2158 uint16_t cmd; 2159 2160 vfio_disable_interrupts(vdev); 2161 2162 /* Make sure the device is in D0 */ 2163 if (vdev->pm_cap) { 2164 uint16_t pmcsr; 2165 uint8_t state; 2166 2167 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2168 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2169 if (state) { 2170 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 2171 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); 2172 /* vfio handles the necessary delay here */ 2173 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2174 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2175 if (state) { 2176 error_report("vfio: Unable to power on device, stuck in D%d", 2177 state); 2178 } 2179 } 2180 } 2181 2182 /* 2183 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. 2184 * Also put INTx Disable in known state. 2185 */ 2186 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); 2187 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 2188 PCI_COMMAND_INTX_DISABLE); 2189 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); 2190 } 2191 2192 static void vfio_pci_post_reset(VFIOPCIDevice *vdev) 2193 { 2194 Error *err = NULL; 2195 int nr; 2196 2197 vfio_intx_enable(vdev, &err); 2198 if (err) { 2199 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 2200 } 2201 2202 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) { 2203 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr); 2204 uint32_t val = 0; 2205 uint32_t len = sizeof(val); 2206 2207 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) { 2208 error_report("%s(%s) reset bar %d failed: %m", __func__, 2209 vdev->vbasedev.name, nr); 2210 } 2211 } 2212 2213 vfio_quirk_reset(vdev); 2214 } 2215 2216 static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) 2217 { 2218 char tmp[13]; 2219 2220 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, 2221 addr->bus, addr->slot, addr->function); 2222 2223 return (strcmp(tmp, name) == 0); 2224 } 2225 2226 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) 2227 { 2228 VFIOGroup *group; 2229 struct vfio_pci_hot_reset_info *info; 2230 struct vfio_pci_dependent_device *devices; 2231 struct vfio_pci_hot_reset *reset; 2232 int32_t *fds; 2233 int ret, i, count; 2234 bool multi = false; 2235 2236 trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); 2237 2238 if (!single) { 2239 vfio_pci_pre_reset(vdev); 2240 } 2241 vdev->vbasedev.needs_reset = false; 2242 2243 info = g_malloc0(sizeof(*info)); 2244 info->argsz = sizeof(*info); 2245 2246 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2247 if (ret && errno != ENOSPC) { 2248 ret = -errno; 2249 if (!vdev->has_pm_reset) { 2250 error_report("vfio: Cannot reset device %s, " 2251 "no available reset mechanism.", vdev->vbasedev.name); 2252 } 2253 goto out_single; 2254 } 2255 2256 count = info->count; 2257 info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); 2258 info->argsz = sizeof(*info) + (count * sizeof(*devices)); 2259 devices = &info->devices[0]; 2260 2261 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2262 if (ret) { 2263 ret = -errno; 2264 error_report("vfio: hot reset info failed: %m"); 2265 goto out_single; 2266 } 2267 2268 trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); 2269 2270 /* Verify that we have all the groups required */ 2271 for (i = 0; i < info->count; i++) { 2272 PCIHostDeviceAddress host; 2273 VFIOPCIDevice *tmp; 2274 VFIODevice *vbasedev_iter; 2275 2276 host.domain = devices[i].segment; 2277 host.bus = devices[i].bus; 2278 host.slot = PCI_SLOT(devices[i].devfn); 2279 host.function = PCI_FUNC(devices[i].devfn); 2280 2281 trace_vfio_pci_hot_reset_dep_devices(host.domain, 2282 host.bus, host.slot, host.function, devices[i].group_id); 2283 2284 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2285 continue; 2286 } 2287 2288 QLIST_FOREACH(group, &vfio_group_list, next) { 2289 if (group->groupid == devices[i].group_id) { 2290 break; 2291 } 2292 } 2293 2294 if (!group) { 2295 if (!vdev->has_pm_reset) { 2296 error_report("vfio: Cannot reset device %s, " 2297 "depends on group %d which is not owned.", 2298 vdev->vbasedev.name, devices[i].group_id); 2299 } 2300 ret = -EPERM; 2301 goto out; 2302 } 2303 2304 /* Prep dependent devices for reset and clear our marker. */ 2305 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2306 if (!vbasedev_iter->dev->realized || 2307 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2308 continue; 2309 } 2310 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2311 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2312 if (single) { 2313 ret = -EINVAL; 2314 goto out_single; 2315 } 2316 vfio_pci_pre_reset(tmp); 2317 tmp->vbasedev.needs_reset = false; 2318 multi = true; 2319 break; 2320 } 2321 } 2322 } 2323 2324 if (!single && !multi) { 2325 ret = -EINVAL; 2326 goto out_single; 2327 } 2328 2329 /* Determine how many group fds need to be passed */ 2330 count = 0; 2331 QLIST_FOREACH(group, &vfio_group_list, next) { 2332 for (i = 0; i < info->count; i++) { 2333 if (group->groupid == devices[i].group_id) { 2334 count++; 2335 break; 2336 } 2337 } 2338 } 2339 2340 reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); 2341 reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); 2342 fds = &reset->group_fds[0]; 2343 2344 /* Fill in group fds */ 2345 QLIST_FOREACH(group, &vfio_group_list, next) { 2346 for (i = 0; i < info->count; i++) { 2347 if (group->groupid == devices[i].group_id) { 2348 fds[reset->count++] = group->fd; 2349 break; 2350 } 2351 } 2352 } 2353 2354 /* Bus reset! */ 2355 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); 2356 g_free(reset); 2357 2358 trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, 2359 ret ? "%m" : "Success"); 2360 2361 out: 2362 /* Re-enable INTx on affected devices */ 2363 for (i = 0; i < info->count; i++) { 2364 PCIHostDeviceAddress host; 2365 VFIOPCIDevice *tmp; 2366 VFIODevice *vbasedev_iter; 2367 2368 host.domain = devices[i].segment; 2369 host.bus = devices[i].bus; 2370 host.slot = PCI_SLOT(devices[i].devfn); 2371 host.function = PCI_FUNC(devices[i].devfn); 2372 2373 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2374 continue; 2375 } 2376 2377 QLIST_FOREACH(group, &vfio_group_list, next) { 2378 if (group->groupid == devices[i].group_id) { 2379 break; 2380 } 2381 } 2382 2383 if (!group) { 2384 break; 2385 } 2386 2387 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2388 if (!vbasedev_iter->dev->realized || 2389 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2390 continue; 2391 } 2392 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2393 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2394 vfio_pci_post_reset(tmp); 2395 break; 2396 } 2397 } 2398 } 2399 out_single: 2400 if (!single) { 2401 vfio_pci_post_reset(vdev); 2402 } 2403 g_free(info); 2404 2405 return ret; 2406 } 2407 2408 /* 2409 * We want to differentiate hot reset of mulitple in-use devices vs hot reset 2410 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case 2411 * of doing hot resets when there is only a single device per bus. The in-use 2412 * here refers to how many VFIODevices are affected. A hot reset that affects 2413 * multiple devices, but only a single in-use device, means that we can call 2414 * it from our bus ->reset() callback since the extent is effectively a single 2415 * device. This allows us to make use of it in the hotplug path. When there 2416 * are multiple in-use devices, we can only trigger the hot reset during a 2417 * system reset and thus from our reset handler. We separate _one vs _multi 2418 * here so that we don't overlap and do a double reset on the system reset 2419 * path where both our reset handler and ->reset() callback are used. Calling 2420 * _one() will only do a hot reset for the one in-use devices case, calling 2421 * _multi() will do nothing if a _one() would have been sufficient. 2422 */ 2423 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) 2424 { 2425 return vfio_pci_hot_reset(vdev, true); 2426 } 2427 2428 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) 2429 { 2430 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2431 return vfio_pci_hot_reset(vdev, false); 2432 } 2433 2434 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) 2435 { 2436 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2437 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { 2438 vbasedev->needs_reset = true; 2439 } 2440 } 2441 2442 static VFIODeviceOps vfio_pci_ops = { 2443 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, 2444 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, 2445 .vfio_eoi = vfio_intx_eoi, 2446 }; 2447 2448 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) 2449 { 2450 VFIODevice *vbasedev = &vdev->vbasedev; 2451 struct vfio_region_info *reg_info; 2452 int ret; 2453 2454 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); 2455 if (ret) { 2456 error_setg_errno(errp, -ret, 2457 "failed getting region info for VGA region index %d", 2458 VFIO_PCI_VGA_REGION_INDEX); 2459 return ret; 2460 } 2461 2462 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || 2463 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || 2464 reg_info->size < 0xbffff + 1) { 2465 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx", 2466 (unsigned long)reg_info->flags, 2467 (unsigned long)reg_info->size); 2468 g_free(reg_info); 2469 return -EINVAL; 2470 } 2471 2472 vdev->vga = g_new0(VFIOVGA, 1); 2473 2474 vdev->vga->fd_offset = reg_info->offset; 2475 vdev->vga->fd = vdev->vbasedev.fd; 2476 2477 g_free(reg_info); 2478 2479 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; 2480 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; 2481 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); 2482 2483 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2484 OBJECT(vdev), &vfio_vga_ops, 2485 &vdev->vga->region[QEMU_PCI_VGA_MEM], 2486 "vfio-vga-mmio@0xa0000", 2487 QEMU_PCI_VGA_MEM_SIZE); 2488 2489 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; 2490 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; 2491 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); 2492 2493 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2494 OBJECT(vdev), &vfio_vga_ops, 2495 &vdev->vga->region[QEMU_PCI_VGA_IO_LO], 2496 "vfio-vga-io@0x3b0", 2497 QEMU_PCI_VGA_IO_LO_SIZE); 2498 2499 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; 2500 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; 2501 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); 2502 2503 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, 2504 OBJECT(vdev), &vfio_vga_ops, 2505 &vdev->vga->region[QEMU_PCI_VGA_IO_HI], 2506 "vfio-vga-io@0x3c0", 2507 QEMU_PCI_VGA_IO_HI_SIZE); 2508 2509 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2510 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2511 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); 2512 2513 return 0; 2514 } 2515 2516 static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp) 2517 { 2518 VFIODevice *vbasedev = &vdev->vbasedev; 2519 struct vfio_region_info *reg_info; 2520 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; 2521 int i, ret = -1; 2522 2523 /* Sanity check device */ 2524 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { 2525 error_setg(errp, "this isn't a PCI device"); 2526 return; 2527 } 2528 2529 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { 2530 error_setg(errp, "unexpected number of io regions %u", 2531 vbasedev->num_regions); 2532 return; 2533 } 2534 2535 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { 2536 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs); 2537 return; 2538 } 2539 2540 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { 2541 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); 2542 2543 ret = vfio_region_setup(OBJECT(vdev), vbasedev, 2544 &vdev->bars[i].region, i, name); 2545 g_free(name); 2546 2547 if (ret) { 2548 error_setg_errno(errp, -ret, "failed to get region %d info", i); 2549 return; 2550 } 2551 2552 QLIST_INIT(&vdev->bars[i].quirks); 2553 } 2554 2555 ret = vfio_get_region_info(vbasedev, 2556 VFIO_PCI_CONFIG_REGION_INDEX, ®_info); 2557 if (ret) { 2558 error_setg_errno(errp, -ret, "failed to get config info"); 2559 return; 2560 } 2561 2562 trace_vfio_populate_device_config(vdev->vbasedev.name, 2563 (unsigned long)reg_info->size, 2564 (unsigned long)reg_info->offset, 2565 (unsigned long)reg_info->flags); 2566 2567 vdev->config_size = reg_info->size; 2568 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { 2569 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; 2570 } 2571 vdev->config_offset = reg_info->offset; 2572 2573 g_free(reg_info); 2574 2575 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { 2576 ret = vfio_populate_vga(vdev, errp); 2577 if (ret) { 2578 error_append_hint(errp, "device does not support " 2579 "requested feature x-vga\n"); 2580 return; 2581 } 2582 } 2583 2584 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; 2585 2586 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); 2587 if (ret) { 2588 /* This can fail for an old kernel or legacy PCI dev */ 2589 trace_vfio_populate_device_get_irq_info_failure(); 2590 } else if (irq_info.count == 1) { 2591 vdev->pci_aer = true; 2592 } else { 2593 warn_report(VFIO_MSG_PREFIX 2594 "Could not enable error recovery for the device", 2595 vbasedev->name); 2596 } 2597 } 2598 2599 static void vfio_put_device(VFIOPCIDevice *vdev) 2600 { 2601 g_free(vdev->vbasedev.name); 2602 g_free(vdev->msix); 2603 2604 vfio_put_base_device(&vdev->vbasedev); 2605 } 2606 2607 static void vfio_err_notifier_handler(void *opaque) 2608 { 2609 VFIOPCIDevice *vdev = opaque; 2610 2611 if (!event_notifier_test_and_clear(&vdev->err_notifier)) { 2612 return; 2613 } 2614 2615 /* 2616 * TBD. Retrieve the error details and decide what action 2617 * needs to be taken. One of the actions could be to pass 2618 * the error to the guest and have the guest driver recover 2619 * from the error. This requires that PCIe capabilities be 2620 * exposed to the guest. For now, we just terminate the 2621 * guest to contain the error. 2622 */ 2623 2624 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); 2625 2626 vm_stop(RUN_STATE_INTERNAL_ERROR); 2627 } 2628 2629 /* 2630 * Registers error notifier for devices supporting error recovery. 2631 * If we encounter a failure in this function, we report an error 2632 * and continue after disabling error recovery support for the 2633 * device. 2634 */ 2635 static void vfio_register_err_notifier(VFIOPCIDevice *vdev) 2636 { 2637 int ret; 2638 int argsz; 2639 struct vfio_irq_set *irq_set; 2640 int32_t *pfd; 2641 2642 if (!vdev->pci_aer) { 2643 return; 2644 } 2645 2646 if (event_notifier_init(&vdev->err_notifier, 0)) { 2647 error_report("vfio: Unable to init event notifier for error detection"); 2648 vdev->pci_aer = false; 2649 return; 2650 } 2651 2652 argsz = sizeof(*irq_set) + sizeof(*pfd); 2653 2654 irq_set = g_malloc0(argsz); 2655 irq_set->argsz = argsz; 2656 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2657 VFIO_IRQ_SET_ACTION_TRIGGER; 2658 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2659 irq_set->start = 0; 2660 irq_set->count = 1; 2661 pfd = (int32_t *)&irq_set->data; 2662 2663 *pfd = event_notifier_get_fd(&vdev->err_notifier); 2664 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); 2665 2666 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2667 if (ret) { 2668 error_report("vfio: Failed to set up error notification"); 2669 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2670 event_notifier_cleanup(&vdev->err_notifier); 2671 vdev->pci_aer = false; 2672 } 2673 g_free(irq_set); 2674 } 2675 2676 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) 2677 { 2678 int argsz; 2679 struct vfio_irq_set *irq_set; 2680 int32_t *pfd; 2681 int ret; 2682 2683 if (!vdev->pci_aer) { 2684 return; 2685 } 2686 2687 argsz = sizeof(*irq_set) + sizeof(*pfd); 2688 2689 irq_set = g_malloc0(argsz); 2690 irq_set->argsz = argsz; 2691 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2692 VFIO_IRQ_SET_ACTION_TRIGGER; 2693 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2694 irq_set->start = 0; 2695 irq_set->count = 1; 2696 pfd = (int32_t *)&irq_set->data; 2697 *pfd = -1; 2698 2699 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2700 if (ret) { 2701 error_report("vfio: Failed to de-assign error fd: %m"); 2702 } 2703 g_free(irq_set); 2704 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), 2705 NULL, NULL, vdev); 2706 event_notifier_cleanup(&vdev->err_notifier); 2707 } 2708 2709 static void vfio_req_notifier_handler(void *opaque) 2710 { 2711 VFIOPCIDevice *vdev = opaque; 2712 Error *err = NULL; 2713 2714 if (!event_notifier_test_and_clear(&vdev->req_notifier)) { 2715 return; 2716 } 2717 2718 qdev_unplug(&vdev->pdev.qdev, &err); 2719 if (err) { 2720 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 2721 } 2722 } 2723 2724 static void vfio_register_req_notifier(VFIOPCIDevice *vdev) 2725 { 2726 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), 2727 .index = VFIO_PCI_REQ_IRQ_INDEX }; 2728 int argsz; 2729 struct vfio_irq_set *irq_set; 2730 int32_t *pfd; 2731 2732 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { 2733 return; 2734 } 2735 2736 if (ioctl(vdev->vbasedev.fd, 2737 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { 2738 return; 2739 } 2740 2741 if (event_notifier_init(&vdev->req_notifier, 0)) { 2742 error_report("vfio: Unable to init event notifier for device request"); 2743 return; 2744 } 2745 2746 argsz = sizeof(*irq_set) + sizeof(*pfd); 2747 2748 irq_set = g_malloc0(argsz); 2749 irq_set->argsz = argsz; 2750 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2751 VFIO_IRQ_SET_ACTION_TRIGGER; 2752 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2753 irq_set->start = 0; 2754 irq_set->count = 1; 2755 pfd = (int32_t *)&irq_set->data; 2756 2757 *pfd = event_notifier_get_fd(&vdev->req_notifier); 2758 qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); 2759 2760 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2761 error_report("vfio: Failed to set up device request notification"); 2762 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2763 event_notifier_cleanup(&vdev->req_notifier); 2764 } else { 2765 vdev->req_enabled = true; 2766 } 2767 2768 g_free(irq_set); 2769 } 2770 2771 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) 2772 { 2773 int argsz; 2774 struct vfio_irq_set *irq_set; 2775 int32_t *pfd; 2776 2777 if (!vdev->req_enabled) { 2778 return; 2779 } 2780 2781 argsz = sizeof(*irq_set) + sizeof(*pfd); 2782 2783 irq_set = g_malloc0(argsz); 2784 irq_set->argsz = argsz; 2785 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2786 VFIO_IRQ_SET_ACTION_TRIGGER; 2787 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2788 irq_set->start = 0; 2789 irq_set->count = 1; 2790 pfd = (int32_t *)&irq_set->data; 2791 *pfd = -1; 2792 2793 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2794 error_report("vfio: Failed to de-assign device request fd: %m"); 2795 } 2796 g_free(irq_set); 2797 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), 2798 NULL, NULL, vdev); 2799 event_notifier_cleanup(&vdev->req_notifier); 2800 2801 vdev->req_enabled = false; 2802 } 2803 2804 static void vfio_realize(PCIDevice *pdev, Error **errp) 2805 { 2806 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 2807 VFIODevice *vbasedev_iter; 2808 VFIOGroup *group; 2809 char *tmp, *subsys, group_path[PATH_MAX], *group_name; 2810 Error *err = NULL; 2811 ssize_t len; 2812 struct stat st; 2813 int groupid; 2814 int i, ret; 2815 bool is_mdev; 2816 2817 if (!vdev->vbasedev.sysfsdev) { 2818 if (!(~vdev->host.domain || ~vdev->host.bus || 2819 ~vdev->host.slot || ~vdev->host.function)) { 2820 error_setg(errp, "No provided host device"); 2821 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F " 2822 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n"); 2823 return; 2824 } 2825 vdev->vbasedev.sysfsdev = 2826 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", 2827 vdev->host.domain, vdev->host.bus, 2828 vdev->host.slot, vdev->host.function); 2829 } 2830 2831 if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { 2832 error_setg_errno(errp, errno, "no such host device"); 2833 error_prepend(errp, VFIO_MSG_PREFIX, vdev->vbasedev.sysfsdev); 2834 return; 2835 } 2836 2837 vdev->vbasedev.name = g_path_get_basename(vdev->vbasedev.sysfsdev); 2838 vdev->vbasedev.ops = &vfio_pci_ops; 2839 vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; 2840 vdev->vbasedev.dev = &vdev->pdev.qdev; 2841 2842 tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); 2843 len = readlink(tmp, group_path, sizeof(group_path)); 2844 g_free(tmp); 2845 2846 if (len <= 0 || len >= sizeof(group_path)) { 2847 error_setg_errno(errp, len < 0 ? errno : ENAMETOOLONG, 2848 "no iommu_group found"); 2849 goto error; 2850 } 2851 2852 group_path[len] = 0; 2853 2854 group_name = basename(group_path); 2855 if (sscanf(group_name, "%d", &groupid) != 1) { 2856 error_setg_errno(errp, errno, "failed to read %s", group_path); 2857 goto error; 2858 } 2859 2860 trace_vfio_realize(vdev->vbasedev.name, groupid); 2861 2862 group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev), errp); 2863 if (!group) { 2864 goto error; 2865 } 2866 2867 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2868 if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { 2869 error_setg(errp, "device is already attached"); 2870 vfio_put_group(group); 2871 goto error; 2872 } 2873 } 2874 2875 /* 2876 * Mediated devices *might* operate compatibly with memory ballooning, but 2877 * we cannot know for certain, it depends on whether the mdev vendor driver 2878 * stays in sync with the active working set of the guest driver. Prevent 2879 * the x-balloon-allowed option unless this is minimally an mdev device. 2880 */ 2881 tmp = g_strdup_printf("%s/subsystem", vdev->vbasedev.sysfsdev); 2882 subsys = realpath(tmp, NULL); 2883 g_free(tmp); 2884 is_mdev = subsys && (strcmp(subsys, "/sys/bus/mdev") == 0); 2885 free(subsys); 2886 2887 trace_vfio_mdev(vdev->vbasedev.name, is_mdev); 2888 2889 if (vdev->vbasedev.balloon_allowed && !is_mdev) { 2890 error_setg(errp, "x-balloon-allowed only potentially compatible " 2891 "with mdev devices"); 2892 vfio_put_group(group); 2893 goto error; 2894 } 2895 2896 ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev, errp); 2897 if (ret) { 2898 vfio_put_group(group); 2899 goto error; 2900 } 2901 2902 vfio_populate_device(vdev, &err); 2903 if (err) { 2904 error_propagate(errp, err); 2905 goto error; 2906 } 2907 2908 /* Get a copy of config space */ 2909 ret = pread(vdev->vbasedev.fd, vdev->pdev.config, 2910 MIN(pci_config_size(&vdev->pdev), vdev->config_size), 2911 vdev->config_offset); 2912 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { 2913 ret = ret < 0 ? -errno : -EFAULT; 2914 error_setg_errno(errp, -ret, "failed to read device config space"); 2915 goto error; 2916 } 2917 2918 /* vfio emulates a lot for us, but some bits need extra love */ 2919 vdev->emulated_config_bits = g_malloc0(vdev->config_size); 2920 2921 /* QEMU can choose to expose the ROM or not */ 2922 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); 2923 /* QEMU can also add or extend BARs */ 2924 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4); 2925 2926 /* 2927 * The PCI spec reserves vendor ID 0xffff as an invalid value. The 2928 * device ID is managed by the vendor and need only be a 16-bit value. 2929 * Allow any 16-bit value for subsystem so they can be hidden or changed. 2930 */ 2931 if (vdev->vendor_id != PCI_ANY_ID) { 2932 if (vdev->vendor_id >= 0xffff) { 2933 error_setg(errp, "invalid PCI vendor ID provided"); 2934 goto error; 2935 } 2936 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); 2937 trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); 2938 } else { 2939 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2940 } 2941 2942 if (vdev->device_id != PCI_ANY_ID) { 2943 if (vdev->device_id > 0xffff) { 2944 error_setg(errp, "invalid PCI device ID provided"); 2945 goto error; 2946 } 2947 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); 2948 trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); 2949 } else { 2950 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2951 } 2952 2953 if (vdev->sub_vendor_id != PCI_ANY_ID) { 2954 if (vdev->sub_vendor_id > 0xffff) { 2955 error_setg(errp, "invalid PCI subsystem vendor ID provided"); 2956 goto error; 2957 } 2958 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, 2959 vdev->sub_vendor_id, ~0); 2960 trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, 2961 vdev->sub_vendor_id); 2962 } 2963 2964 if (vdev->sub_device_id != PCI_ANY_ID) { 2965 if (vdev->sub_device_id > 0xffff) { 2966 error_setg(errp, "invalid PCI subsystem device ID provided"); 2967 goto error; 2968 } 2969 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); 2970 trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, 2971 vdev->sub_device_id); 2972 } 2973 2974 /* QEMU can change multi-function devices to single function, or reverse */ 2975 vdev->emulated_config_bits[PCI_HEADER_TYPE] = 2976 PCI_HEADER_TYPE_MULTI_FUNCTION; 2977 2978 /* Restore or clear multifunction, this is always controlled by QEMU */ 2979 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 2980 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 2981 } else { 2982 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; 2983 } 2984 2985 /* 2986 * Clear host resource mapping info. If we choose not to register a 2987 * BAR, such as might be the case with the option ROM, we can get 2988 * confusing, unwritable, residual addresses from the host here. 2989 */ 2990 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); 2991 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); 2992 2993 vfio_pci_size_rom(vdev); 2994 2995 vfio_bars_prepare(vdev); 2996 2997 vfio_msix_early_setup(vdev, &err); 2998 if (err) { 2999 error_propagate(errp, err); 3000 goto error; 3001 } 3002 3003 vfio_bars_register(vdev); 3004 3005 ret = vfio_add_capabilities(vdev, errp); 3006 if (ret) { 3007 goto out_teardown; 3008 } 3009 3010 if (vdev->vga) { 3011 vfio_vga_quirk_setup(vdev); 3012 } 3013 3014 for (i = 0; i < PCI_ROM_SLOT; i++) { 3015 vfio_bar_quirk_setup(vdev, i); 3016 } 3017 3018 if (!vdev->igd_opregion && 3019 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { 3020 struct vfio_region_info *opregion; 3021 3022 if (vdev->pdev.qdev.hotplugged) { 3023 error_setg(errp, 3024 "cannot support IGD OpRegion feature on hotplugged " 3025 "device"); 3026 goto out_teardown; 3027 } 3028 3029 ret = vfio_get_dev_region_info(&vdev->vbasedev, 3030 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 3031 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 3032 if (ret) { 3033 error_setg_errno(errp, -ret, 3034 "does not support requested IGD OpRegion feature"); 3035 goto out_teardown; 3036 } 3037 3038 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp); 3039 g_free(opregion); 3040 if (ret) { 3041 goto out_teardown; 3042 } 3043 } 3044 3045 /* QEMU emulates all of MSI & MSIX */ 3046 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { 3047 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, 3048 MSIX_CAP_LENGTH); 3049 } 3050 3051 if (pdev->cap_present & QEMU_PCI_CAP_MSI) { 3052 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, 3053 vdev->msi_cap_size); 3054 } 3055 3056 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { 3057 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3058 vfio_intx_mmap_enable, vdev); 3059 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); 3060 ret = vfio_intx_enable(vdev, errp); 3061 if (ret) { 3062 goto out_teardown; 3063 } 3064 } 3065 3066 if (vdev->display != ON_OFF_AUTO_OFF) { 3067 ret = vfio_display_probe(vdev, errp); 3068 if (ret) { 3069 goto out_teardown; 3070 } 3071 } 3072 if (vdev->enable_ramfb && vdev->dpy == NULL) { 3073 error_setg(errp, "ramfb=on requires display=on"); 3074 goto out_teardown; 3075 } 3076 3077 vfio_register_err_notifier(vdev); 3078 vfio_register_req_notifier(vdev); 3079 vfio_setup_resetfn_quirk(vdev); 3080 3081 return; 3082 3083 out_teardown: 3084 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 3085 vfio_teardown_msi(vdev); 3086 vfio_bars_exit(vdev); 3087 error: 3088 error_prepend(errp, VFIO_MSG_PREFIX, vdev->vbasedev.name); 3089 } 3090 3091 static void vfio_instance_finalize(Object *obj) 3092 { 3093 VFIOPCIDevice *vdev = PCI_VFIO(obj); 3094 VFIOGroup *group = vdev->vbasedev.group; 3095 3096 vfio_display_finalize(vdev); 3097 vfio_bars_finalize(vdev); 3098 g_free(vdev->emulated_config_bits); 3099 g_free(vdev->rom); 3100 /* 3101 * XXX Leaking igd_opregion is not an oversight, we can't remove the 3102 * fw_cfg entry therefore leaking this allocation seems like the safest 3103 * option. 3104 * 3105 * g_free(vdev->igd_opregion); 3106 */ 3107 vfio_put_device(vdev); 3108 vfio_put_group(group); 3109 } 3110 3111 static void vfio_exitfn(PCIDevice *pdev) 3112 { 3113 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 3114 3115 vfio_unregister_req_notifier(vdev); 3116 vfio_unregister_err_notifier(vdev); 3117 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 3118 vfio_disable_interrupts(vdev); 3119 if (vdev->intx.mmap_timer) { 3120 timer_free(vdev->intx.mmap_timer); 3121 } 3122 vfio_teardown_msi(vdev); 3123 vfio_bars_exit(vdev); 3124 } 3125 3126 static void vfio_pci_reset(DeviceState *dev) 3127 { 3128 VFIOPCIDevice *vdev = PCI_VFIO(dev); 3129 3130 trace_vfio_pci_reset(vdev->vbasedev.name); 3131 3132 vfio_pci_pre_reset(vdev); 3133 3134 if (vdev->display != ON_OFF_AUTO_OFF) { 3135 vfio_display_reset(vdev); 3136 } 3137 3138 if (vdev->resetfn && !vdev->resetfn(vdev)) { 3139 goto post_reset; 3140 } 3141 3142 if (vdev->vbasedev.reset_works && 3143 (vdev->has_flr || !vdev->has_pm_reset) && 3144 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 3145 trace_vfio_pci_reset_flr(vdev->vbasedev.name); 3146 goto post_reset; 3147 } 3148 3149 /* See if we can do our own bus reset */ 3150 if (!vfio_pci_hot_reset_one(vdev)) { 3151 goto post_reset; 3152 } 3153 3154 /* If nothing else works and the device supports PM reset, use it */ 3155 if (vdev->vbasedev.reset_works && vdev->has_pm_reset && 3156 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 3157 trace_vfio_pci_reset_pm(vdev->vbasedev.name); 3158 goto post_reset; 3159 } 3160 3161 post_reset: 3162 vfio_pci_post_reset(vdev); 3163 } 3164 3165 static void vfio_instance_init(Object *obj) 3166 { 3167 PCIDevice *pci_dev = PCI_DEVICE(obj); 3168 VFIOPCIDevice *vdev = PCI_VFIO(obj); 3169 3170 device_add_bootindex_property(obj, &vdev->bootindex, 3171 "bootindex", NULL, 3172 &pci_dev->qdev, NULL); 3173 vdev->host.domain = ~0U; 3174 vdev->host.bus = ~0U; 3175 vdev->host.slot = ~0U; 3176 vdev->host.function = ~0U; 3177 3178 vdev->nv_gpudirect_clique = 0xFF; 3179 3180 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 3181 * line, therefore, no need to wait to realize like other devices */ 3182 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 3183 } 3184 3185 static Property vfio_pci_dev_properties[] = { 3186 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), 3187 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), 3188 DEFINE_PROP_ON_OFF_AUTO("display", VFIOPCIDevice, 3189 display, ON_OFF_AUTO_OFF), 3190 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, 3191 intx.mmap_timeout, 1100), 3192 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, 3193 VFIO_FEATURE_ENABLE_VGA_BIT, false), 3194 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, 3195 VFIO_FEATURE_ENABLE_REQ_BIT, true), 3196 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, 3197 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), 3198 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), 3199 DEFINE_PROP_BOOL("x-balloon-allowed", VFIOPCIDevice, 3200 vbasedev.balloon_allowed, false), 3201 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), 3202 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), 3203 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), 3204 DEFINE_PROP_BOOL("x-no-geforce-quirks", VFIOPCIDevice, 3205 no_geforce_quirks, false), 3206 DEFINE_PROP_BOOL("x-no-kvm-ioeventfd", VFIOPCIDevice, no_kvm_ioeventfd, 3207 false), 3208 DEFINE_PROP_BOOL("x-no-vfio-ioeventfd", VFIOPCIDevice, no_vfio_ioeventfd, 3209 false), 3210 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), 3211 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), 3212 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, 3213 sub_vendor_id, PCI_ANY_ID), 3214 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, 3215 sub_device_id, PCI_ANY_ID), 3216 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), 3217 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice, 3218 nv_gpudirect_clique, 3219 qdev_prop_nv_gpudirect_clique, uint8_t), 3220 DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_relo, 3221 OFF_AUTOPCIBAR_OFF), 3222 /* 3223 * TODO - support passed fds... is this necessary? 3224 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), 3225 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), 3226 */ 3227 DEFINE_PROP_END_OF_LIST(), 3228 }; 3229 3230 static const VMStateDescription vfio_pci_vmstate = { 3231 .name = "vfio-pci", 3232 .unmigratable = 1, 3233 }; 3234 3235 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) 3236 { 3237 DeviceClass *dc = DEVICE_CLASS(klass); 3238 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); 3239 3240 dc->reset = vfio_pci_reset; 3241 dc->props = vfio_pci_dev_properties; 3242 dc->vmsd = &vfio_pci_vmstate; 3243 dc->desc = "VFIO-based PCI device assignment"; 3244 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3245 pdc->realize = vfio_realize; 3246 pdc->exit = vfio_exitfn; 3247 pdc->config_read = vfio_pci_read_config; 3248 pdc->config_write = vfio_pci_write_config; 3249 } 3250 3251 static const TypeInfo vfio_pci_dev_info = { 3252 .name = TYPE_VFIO_PCI, 3253 .parent = TYPE_PCI_DEVICE, 3254 .instance_size = sizeof(VFIOPCIDevice), 3255 .class_init = vfio_pci_dev_class_init, 3256 .instance_init = vfio_instance_init, 3257 .instance_finalize = vfio_instance_finalize, 3258 .interfaces = (InterfaceInfo[]) { 3259 { INTERFACE_PCIE_DEVICE }, 3260 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3261 { } 3262 }, 3263 }; 3264 3265 static Property vfio_pci_dev_nohotplug_properties[] = { 3266 DEFINE_PROP_BOOL("ramfb", VFIOPCIDevice, enable_ramfb, false), 3267 DEFINE_PROP_END_OF_LIST(), 3268 }; 3269 3270 static void vfio_pci_nohotplug_dev_class_init(ObjectClass *klass, void *data) 3271 { 3272 DeviceClass *dc = DEVICE_CLASS(klass); 3273 3274 dc->props = vfio_pci_dev_nohotplug_properties; 3275 dc->hotpluggable = false; 3276 } 3277 3278 static const TypeInfo vfio_pci_nohotplug_dev_info = { 3279 .name = "vfio-pci-nohotplug", 3280 .parent = "vfio-pci", 3281 .instance_size = sizeof(VFIOPCIDevice), 3282 .class_init = vfio_pci_nohotplug_dev_class_init, 3283 }; 3284 3285 static void register_vfio_pci_dev_type(void) 3286 { 3287 type_register_static(&vfio_pci_dev_info); 3288 type_register_static(&vfio_pci_nohotplug_dev_info); 3289 } 3290 3291 type_init(register_vfio_pci_dev_type) 3292