1 /* 2 * vfio based device assignment support 3 * 4 * Copyright Red Hat, Inc. 2012 5 * 6 * Authors: 7 * Alex Williamson <alex.williamson@redhat.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2. See 10 * the COPYING file in the top-level directory. 11 * 12 * Based on qemu-kvm device-assignment: 13 * Adapted for KVM by Qumranet. 14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com) 15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com) 16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com) 17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com) 18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com) 19 */ 20 21 #include "qemu/osdep.h" 22 #include <linux/vfio.h> 23 #include <sys/ioctl.h> 24 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "hw/pci/pci_bridge.h" 28 #include "qemu/error-report.h" 29 #include "qemu/option.h" 30 #include "qemu/range.h" 31 #include "qemu/units.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/sysemu.h" 34 #include "pci.h" 35 #include "trace.h" 36 #include "qapi/error.h" 37 38 #define MSIX_CAP_LENGTH 12 39 40 #define TYPE_VFIO_PCI "vfio-pci" 41 #define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI) 42 43 static void vfio_disable_interrupts(VFIOPCIDevice *vdev); 44 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled); 45 46 /* 47 * Disabling BAR mmaping can be slow, but toggling it around INTx can 48 * also be a huge overhead. We try to get the best of both worlds by 49 * waiting until an interrupt to disable mmaps (subsequent transitions 50 * to the same state are effectively no overhead). If the interrupt has 51 * been serviced and the time gap is long enough, we re-enable mmaps for 52 * performance. This works well for things like graphics cards, which 53 * may not use their interrupt at all and are penalized to an unusable 54 * level by read/write BAR traps. Other devices, like NICs, have more 55 * regular interrupts and see much better latency by staying in non-mmap 56 * mode. We therefore set the default mmap_timeout such that a ping 57 * is just enough to keep the mmap disabled. Users can experiment with 58 * other options with the x-intx-mmap-timeout-ms parameter (a value of 59 * zero disables the timer). 60 */ 61 static void vfio_intx_mmap_enable(void *opaque) 62 { 63 VFIOPCIDevice *vdev = opaque; 64 65 if (vdev->intx.pending) { 66 timer_mod(vdev->intx.mmap_timer, 67 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 68 return; 69 } 70 71 vfio_mmap_set_enabled(vdev, true); 72 } 73 74 static void vfio_intx_interrupt(void *opaque) 75 { 76 VFIOPCIDevice *vdev = opaque; 77 78 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) { 79 return; 80 } 81 82 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin); 83 84 vdev->intx.pending = true; 85 pci_irq_assert(&vdev->pdev); 86 vfio_mmap_set_enabled(vdev, false); 87 if (vdev->intx.mmap_timeout) { 88 timer_mod(vdev->intx.mmap_timer, 89 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout); 90 } 91 } 92 93 static void vfio_intx_eoi(VFIODevice *vbasedev) 94 { 95 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 96 97 if (!vdev->intx.pending) { 98 return; 99 } 100 101 trace_vfio_intx_eoi(vbasedev->name); 102 103 vdev->intx.pending = false; 104 pci_irq_deassert(&vdev->pdev); 105 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 106 } 107 108 static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp) 109 { 110 #ifdef CONFIG_KVM 111 struct kvm_irqfd irqfd = { 112 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 113 .gsi = vdev->intx.route.irq, 114 .flags = KVM_IRQFD_FLAG_RESAMPLE, 115 }; 116 struct vfio_irq_set *irq_set; 117 int ret, argsz; 118 int32_t *pfd; 119 120 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() || 121 vdev->intx.route.mode != PCI_INTX_ENABLED || 122 !kvm_resamplefds_enabled()) { 123 return; 124 } 125 126 /* Get to a known interrupt state */ 127 qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev); 128 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 129 vdev->intx.pending = false; 130 pci_irq_deassert(&vdev->pdev); 131 132 /* Get an eventfd for resample/unmask */ 133 if (event_notifier_init(&vdev->intx.unmask, 0)) { 134 error_setg(errp, "event_notifier_init failed eoi"); 135 goto fail; 136 } 137 138 /* KVM triggers it, VFIO listens for it */ 139 irqfd.resamplefd = event_notifier_get_fd(&vdev->intx.unmask); 140 141 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 142 error_setg_errno(errp, errno, "failed to setup resample irqfd"); 143 goto fail_irqfd; 144 } 145 146 argsz = sizeof(*irq_set) + sizeof(*pfd); 147 148 irq_set = g_malloc0(argsz); 149 irq_set->argsz = argsz; 150 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_UNMASK; 151 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 152 irq_set->start = 0; 153 irq_set->count = 1; 154 pfd = (int32_t *)&irq_set->data; 155 156 *pfd = irqfd.resamplefd; 157 158 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 159 g_free(irq_set); 160 if (ret) { 161 error_setg_errno(errp, -ret, "failed to setup INTx unmask fd"); 162 goto fail_vfio; 163 } 164 165 /* Let'em rip */ 166 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 167 168 vdev->intx.kvm_accel = true; 169 170 trace_vfio_intx_enable_kvm(vdev->vbasedev.name); 171 172 return; 173 174 fail_vfio: 175 irqfd.flags = KVM_IRQFD_FLAG_DEASSIGN; 176 kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd); 177 fail_irqfd: 178 event_notifier_cleanup(&vdev->intx.unmask); 179 fail: 180 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 181 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 182 #endif 183 } 184 185 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev) 186 { 187 #ifdef CONFIG_KVM 188 struct kvm_irqfd irqfd = { 189 .fd = event_notifier_get_fd(&vdev->intx.interrupt), 190 .gsi = vdev->intx.route.irq, 191 .flags = KVM_IRQFD_FLAG_DEASSIGN, 192 }; 193 194 if (!vdev->intx.kvm_accel) { 195 return; 196 } 197 198 /* 199 * Get to a known state, hardware masked, QEMU ready to accept new 200 * interrupts, QEMU IRQ de-asserted. 201 */ 202 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 203 vdev->intx.pending = false; 204 pci_irq_deassert(&vdev->pdev); 205 206 /* Tell KVM to stop listening for an INTx irqfd */ 207 if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) { 208 error_report("vfio: Error: Failed to disable INTx irqfd: %m"); 209 } 210 211 /* We only need to close the eventfd for VFIO to cleanup the kernel side */ 212 event_notifier_cleanup(&vdev->intx.unmask); 213 214 /* QEMU starts listening for interrupt events. */ 215 qemu_set_fd_handler(irqfd.fd, vfio_intx_interrupt, NULL, vdev); 216 217 vdev->intx.kvm_accel = false; 218 219 /* If we've missed an event, let it re-fire through QEMU */ 220 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 221 222 trace_vfio_intx_disable_kvm(vdev->vbasedev.name); 223 #endif 224 } 225 226 static void vfio_intx_update(PCIDevice *pdev) 227 { 228 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 229 PCIINTxRoute route; 230 Error *err = NULL; 231 232 if (vdev->interrupt != VFIO_INT_INTx) { 233 return; 234 } 235 236 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin); 237 238 if (!pci_intx_route_changed(&vdev->intx.route, &route)) { 239 return; /* Nothing changed */ 240 } 241 242 trace_vfio_intx_update(vdev->vbasedev.name, 243 vdev->intx.route.irq, route.irq); 244 245 vfio_intx_disable_kvm(vdev); 246 247 vdev->intx.route = route; 248 249 if (route.mode != PCI_INTX_ENABLED) { 250 return; 251 } 252 253 vfio_intx_enable_kvm(vdev, &err); 254 if (err) { 255 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 256 } 257 258 /* Re-enable the interrupt in cased we missed an EOI */ 259 vfio_intx_eoi(&vdev->vbasedev); 260 } 261 262 static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp) 263 { 264 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1); 265 int ret, argsz, retval = 0; 266 struct vfio_irq_set *irq_set; 267 int32_t *pfd; 268 Error *err = NULL; 269 270 if (!pin) { 271 return 0; 272 } 273 274 vfio_disable_interrupts(vdev); 275 276 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */ 277 pci_config_set_interrupt_pin(vdev->pdev.config, pin); 278 279 #ifdef CONFIG_KVM 280 /* 281 * Only conditional to avoid generating error messages on platforms 282 * where we won't actually use the result anyway. 283 */ 284 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) { 285 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev, 286 vdev->intx.pin); 287 } 288 #endif 289 290 ret = event_notifier_init(&vdev->intx.interrupt, 0); 291 if (ret) { 292 error_setg_errno(errp, -ret, "event_notifier_init failed"); 293 return ret; 294 } 295 296 argsz = sizeof(*irq_set) + sizeof(*pfd); 297 298 irq_set = g_malloc0(argsz); 299 irq_set->argsz = argsz; 300 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 301 irq_set->index = VFIO_PCI_INTX_IRQ_INDEX; 302 irq_set->start = 0; 303 irq_set->count = 1; 304 pfd = (int32_t *)&irq_set->data; 305 306 *pfd = event_notifier_get_fd(&vdev->intx.interrupt); 307 qemu_set_fd_handler(*pfd, vfio_intx_interrupt, NULL, vdev); 308 309 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 310 if (ret) { 311 error_setg_errno(errp, -ret, "failed to setup INTx fd"); 312 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 313 event_notifier_cleanup(&vdev->intx.interrupt); 314 retval = -errno; 315 goto cleanup; 316 } 317 318 vfio_intx_enable_kvm(vdev, &err); 319 if (err) { 320 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 321 } 322 323 vdev->interrupt = VFIO_INT_INTx; 324 325 trace_vfio_intx_enable(vdev->vbasedev.name); 326 327 cleanup: 328 g_free(irq_set); 329 330 return retval; 331 } 332 333 static void vfio_intx_disable(VFIOPCIDevice *vdev) 334 { 335 int fd; 336 337 timer_del(vdev->intx.mmap_timer); 338 vfio_intx_disable_kvm(vdev); 339 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX); 340 vdev->intx.pending = false; 341 pci_irq_deassert(&vdev->pdev); 342 vfio_mmap_set_enabled(vdev, true); 343 344 fd = event_notifier_get_fd(&vdev->intx.interrupt); 345 qemu_set_fd_handler(fd, NULL, NULL, vdev); 346 event_notifier_cleanup(&vdev->intx.interrupt); 347 348 vdev->interrupt = VFIO_INT_NONE; 349 350 trace_vfio_intx_disable(vdev->vbasedev.name); 351 } 352 353 /* 354 * MSI/X 355 */ 356 static void vfio_msi_interrupt(void *opaque) 357 { 358 VFIOMSIVector *vector = opaque; 359 VFIOPCIDevice *vdev = vector->vdev; 360 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector); 361 void (*notify)(PCIDevice *dev, unsigned vector); 362 MSIMessage msg; 363 int nr = vector - vdev->msi_vectors; 364 365 if (!event_notifier_test_and_clear(&vector->interrupt)) { 366 return; 367 } 368 369 if (vdev->interrupt == VFIO_INT_MSIX) { 370 get_msg = msix_get_message; 371 notify = msix_notify; 372 373 /* A masked vector firing needs to use the PBA, enable it */ 374 if (msix_is_masked(&vdev->pdev, nr)) { 375 set_bit(nr, vdev->msix->pending); 376 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true); 377 trace_vfio_msix_pba_enable(vdev->vbasedev.name); 378 } 379 } else if (vdev->interrupt == VFIO_INT_MSI) { 380 get_msg = msi_get_message; 381 notify = msi_notify; 382 } else { 383 abort(); 384 } 385 386 msg = get_msg(&vdev->pdev, nr); 387 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data); 388 notify(&vdev->pdev, nr); 389 } 390 391 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix) 392 { 393 struct vfio_irq_set *irq_set; 394 int ret = 0, i, argsz; 395 int32_t *fds; 396 397 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds)); 398 399 irq_set = g_malloc0(argsz); 400 irq_set->argsz = argsz; 401 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER; 402 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX; 403 irq_set->start = 0; 404 irq_set->count = vdev->nr_vectors; 405 fds = (int32_t *)&irq_set->data; 406 407 for (i = 0; i < vdev->nr_vectors; i++) { 408 int fd = -1; 409 410 /* 411 * MSI vs MSI-X - The guest has direct access to MSI mask and pending 412 * bits, therefore we always use the KVM signaling path when setup. 413 * MSI-X mask and pending bits are emulated, so we want to use the 414 * KVM signaling path only when configured and unmasked. 415 */ 416 if (vdev->msi_vectors[i].use) { 417 if (vdev->msi_vectors[i].virq < 0 || 418 (msix && msix_is_masked(&vdev->pdev, i))) { 419 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt); 420 } else { 421 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt); 422 } 423 } 424 425 fds[i] = fd; 426 } 427 428 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 429 430 g_free(irq_set); 431 432 return ret; 433 } 434 435 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector, 436 int vector_n, bool msix) 437 { 438 int virq; 439 440 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) { 441 return; 442 } 443 444 if (event_notifier_init(&vector->kvm_interrupt, 0)) { 445 return; 446 } 447 448 virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev); 449 if (virq < 0) { 450 event_notifier_cleanup(&vector->kvm_interrupt); 451 return; 452 } 453 454 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 455 NULL, virq) < 0) { 456 kvm_irqchip_release_virq(kvm_state, virq); 457 event_notifier_cleanup(&vector->kvm_interrupt); 458 return; 459 } 460 461 vector->virq = virq; 462 } 463 464 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector) 465 { 466 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt, 467 vector->virq); 468 kvm_irqchip_release_virq(kvm_state, vector->virq); 469 vector->virq = -1; 470 event_notifier_cleanup(&vector->kvm_interrupt); 471 } 472 473 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg, 474 PCIDevice *pdev) 475 { 476 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev); 477 kvm_irqchip_commit_routes(kvm_state); 478 } 479 480 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr, 481 MSIMessage *msg, IOHandler *handler) 482 { 483 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 484 VFIOMSIVector *vector; 485 int ret; 486 487 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr); 488 489 vector = &vdev->msi_vectors[nr]; 490 491 if (!vector->use) { 492 vector->vdev = vdev; 493 vector->virq = -1; 494 if (event_notifier_init(&vector->interrupt, 0)) { 495 error_report("vfio: Error: event_notifier_init failed"); 496 } 497 vector->use = true; 498 msix_vector_use(pdev, nr); 499 } 500 501 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 502 handler, NULL, vector); 503 504 /* 505 * Attempt to enable route through KVM irqchip, 506 * default to userspace handling if unavailable. 507 */ 508 if (vector->virq >= 0) { 509 if (!msg) { 510 vfio_remove_kvm_msi_virq(vector); 511 } else { 512 vfio_update_kvm_msi_virq(vector, *msg, pdev); 513 } 514 } else { 515 if (msg) { 516 vfio_add_kvm_msi_virq(vdev, vector, nr, true); 517 } 518 } 519 520 /* 521 * We don't want to have the host allocate all possible MSI vectors 522 * for a device if they're not in use, so we shutdown and incrementally 523 * increase them as needed. 524 */ 525 if (vdev->nr_vectors < nr + 1) { 526 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 527 vdev->nr_vectors = nr + 1; 528 ret = vfio_enable_vectors(vdev, true); 529 if (ret) { 530 error_report("vfio: failed to enable vectors, %d", ret); 531 } 532 } else { 533 int argsz; 534 struct vfio_irq_set *irq_set; 535 int32_t *pfd; 536 537 argsz = sizeof(*irq_set) + sizeof(*pfd); 538 539 irq_set = g_malloc0(argsz); 540 irq_set->argsz = argsz; 541 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 542 VFIO_IRQ_SET_ACTION_TRIGGER; 543 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 544 irq_set->start = nr; 545 irq_set->count = 1; 546 pfd = (int32_t *)&irq_set->data; 547 548 if (vector->virq >= 0) { 549 *pfd = event_notifier_get_fd(&vector->kvm_interrupt); 550 } else { 551 *pfd = event_notifier_get_fd(&vector->interrupt); 552 } 553 554 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 555 g_free(irq_set); 556 if (ret) { 557 error_report("vfio: failed to modify vector, %d", ret); 558 } 559 } 560 561 /* Disable PBA emulation when nothing more is pending. */ 562 clear_bit(nr, vdev->msix->pending); 563 if (find_first_bit(vdev->msix->pending, 564 vdev->nr_vectors) == vdev->nr_vectors) { 565 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 566 trace_vfio_msix_pba_disable(vdev->vbasedev.name); 567 } 568 569 return 0; 570 } 571 572 static int vfio_msix_vector_use(PCIDevice *pdev, 573 unsigned int nr, MSIMessage msg) 574 { 575 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt); 576 } 577 578 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr) 579 { 580 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 581 VFIOMSIVector *vector = &vdev->msi_vectors[nr]; 582 583 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr); 584 585 /* 586 * There are still old guests that mask and unmask vectors on every 587 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of 588 * the KVM setup in place, simply switch VFIO to use the non-bypass 589 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X 590 * core will mask the interrupt and set pending bits, allowing it to 591 * be re-asserted on unmask. Nothing to do if already using QEMU mode. 592 */ 593 if (vector->virq >= 0) { 594 int argsz; 595 struct vfio_irq_set *irq_set; 596 int32_t *pfd; 597 598 argsz = sizeof(*irq_set) + sizeof(*pfd); 599 600 irq_set = g_malloc0(argsz); 601 irq_set->argsz = argsz; 602 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 603 VFIO_IRQ_SET_ACTION_TRIGGER; 604 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX; 605 irq_set->start = nr; 606 irq_set->count = 1; 607 pfd = (int32_t *)&irq_set->data; 608 609 *pfd = event_notifier_get_fd(&vector->interrupt); 610 611 ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 612 613 g_free(irq_set); 614 } 615 } 616 617 static void vfio_msix_enable(VFIOPCIDevice *vdev) 618 { 619 vfio_disable_interrupts(vdev); 620 621 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries); 622 623 vdev->interrupt = VFIO_INT_MSIX; 624 625 /* 626 * Some communication channels between VF & PF or PF & fw rely on the 627 * physical state of the device and expect that enabling MSI-X from the 628 * guest enables the same on the host. When our guest is Linux, the 629 * guest driver call to pci_enable_msix() sets the enabling bit in the 630 * MSI-X capability, but leaves the vector table masked. We therefore 631 * can't rely on a vector_use callback (from request_irq() in the guest) 632 * to switch the physical device into MSI-X mode because that may come a 633 * long time after pci_enable_msix(). This code enables vector 0 with 634 * triggering to userspace, then immediately release the vector, leaving 635 * the physical device with no vectors enabled, but MSI-X enabled, just 636 * like the guest view. 637 */ 638 vfio_msix_vector_do_use(&vdev->pdev, 0, NULL, NULL); 639 vfio_msix_vector_release(&vdev->pdev, 0); 640 641 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use, 642 vfio_msix_vector_release, NULL)) { 643 error_report("vfio: msix_set_vector_notifiers failed"); 644 } 645 646 trace_vfio_msix_enable(vdev->vbasedev.name); 647 } 648 649 static void vfio_msi_enable(VFIOPCIDevice *vdev) 650 { 651 int ret, i; 652 653 vfio_disable_interrupts(vdev); 654 655 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev); 656 retry: 657 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors); 658 659 for (i = 0; i < vdev->nr_vectors; i++) { 660 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 661 662 vector->vdev = vdev; 663 vector->virq = -1; 664 vector->use = true; 665 666 if (event_notifier_init(&vector->interrupt, 0)) { 667 error_report("vfio: Error: event_notifier_init failed"); 668 } 669 670 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 671 vfio_msi_interrupt, NULL, vector); 672 673 /* 674 * Attempt to enable route through KVM irqchip, 675 * default to userspace handling if unavailable. 676 */ 677 vfio_add_kvm_msi_virq(vdev, vector, i, false); 678 } 679 680 /* Set interrupt type prior to possible interrupts */ 681 vdev->interrupt = VFIO_INT_MSI; 682 683 ret = vfio_enable_vectors(vdev, false); 684 if (ret) { 685 if (ret < 0) { 686 error_report("vfio: Error: Failed to setup MSI fds: %m"); 687 } else if (ret != vdev->nr_vectors) { 688 error_report("vfio: Error: Failed to enable %d " 689 "MSI vectors, retry with %d", vdev->nr_vectors, ret); 690 } 691 692 for (i = 0; i < vdev->nr_vectors; i++) { 693 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 694 if (vector->virq >= 0) { 695 vfio_remove_kvm_msi_virq(vector); 696 } 697 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 698 NULL, NULL, NULL); 699 event_notifier_cleanup(&vector->interrupt); 700 } 701 702 g_free(vdev->msi_vectors); 703 704 if (ret > 0 && ret != vdev->nr_vectors) { 705 vdev->nr_vectors = ret; 706 goto retry; 707 } 708 vdev->nr_vectors = 0; 709 710 /* 711 * Failing to setup MSI doesn't really fall within any specification. 712 * Let's try leaving interrupts disabled and hope the guest figures 713 * out to fall back to INTx for this device. 714 */ 715 error_report("vfio: Error: Failed to enable MSI"); 716 vdev->interrupt = VFIO_INT_NONE; 717 718 return; 719 } 720 721 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors); 722 } 723 724 static void vfio_msi_disable_common(VFIOPCIDevice *vdev) 725 { 726 Error *err = NULL; 727 int i; 728 729 for (i = 0; i < vdev->nr_vectors; i++) { 730 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 731 if (vdev->msi_vectors[i].use) { 732 if (vector->virq >= 0) { 733 vfio_remove_kvm_msi_virq(vector); 734 } 735 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt), 736 NULL, NULL, NULL); 737 event_notifier_cleanup(&vector->interrupt); 738 } 739 } 740 741 g_free(vdev->msi_vectors); 742 vdev->msi_vectors = NULL; 743 vdev->nr_vectors = 0; 744 vdev->interrupt = VFIO_INT_NONE; 745 746 vfio_intx_enable(vdev, &err); 747 if (err) { 748 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 749 } 750 } 751 752 static void vfio_msix_disable(VFIOPCIDevice *vdev) 753 { 754 int i; 755 756 msix_unset_vector_notifiers(&vdev->pdev); 757 758 /* 759 * MSI-X will only release vectors if MSI-X is still enabled on the 760 * device, check through the rest and release it ourselves if necessary. 761 */ 762 for (i = 0; i < vdev->nr_vectors; i++) { 763 if (vdev->msi_vectors[i].use) { 764 vfio_msix_vector_release(&vdev->pdev, i); 765 msix_vector_unuse(&vdev->pdev, i); 766 } 767 } 768 769 if (vdev->nr_vectors) { 770 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX); 771 } 772 773 vfio_msi_disable_common(vdev); 774 775 memset(vdev->msix->pending, 0, 776 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long)); 777 778 trace_vfio_msix_disable(vdev->vbasedev.name); 779 } 780 781 static void vfio_msi_disable(VFIOPCIDevice *vdev) 782 { 783 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX); 784 vfio_msi_disable_common(vdev); 785 786 trace_vfio_msi_disable(vdev->vbasedev.name); 787 } 788 789 static void vfio_update_msi(VFIOPCIDevice *vdev) 790 { 791 int i; 792 793 for (i = 0; i < vdev->nr_vectors; i++) { 794 VFIOMSIVector *vector = &vdev->msi_vectors[i]; 795 MSIMessage msg; 796 797 if (!vector->use || vector->virq < 0) { 798 continue; 799 } 800 801 msg = msi_get_message(&vdev->pdev, i); 802 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev); 803 } 804 } 805 806 static void vfio_pci_load_rom(VFIOPCIDevice *vdev) 807 { 808 struct vfio_region_info *reg_info; 809 uint64_t size; 810 off_t off = 0; 811 ssize_t bytes; 812 813 if (vfio_get_region_info(&vdev->vbasedev, 814 VFIO_PCI_ROM_REGION_INDEX, ®_info)) { 815 error_report("vfio: Error getting ROM info: %m"); 816 return; 817 } 818 819 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size, 820 (unsigned long)reg_info->offset, 821 (unsigned long)reg_info->flags); 822 823 vdev->rom_size = size = reg_info->size; 824 vdev->rom_offset = reg_info->offset; 825 826 g_free(reg_info); 827 828 if (!vdev->rom_size) { 829 vdev->rom_read_failed = true; 830 error_report("vfio-pci: Cannot read device rom at " 831 "%s", vdev->vbasedev.name); 832 error_printf("Device option ROM contents are probably invalid " 833 "(check dmesg).\nSkip option ROM probe with rombar=0, " 834 "or load from file with romfile=\n"); 835 return; 836 } 837 838 vdev->rom = g_malloc(size); 839 memset(vdev->rom, 0xff, size); 840 841 while (size) { 842 bytes = pread(vdev->vbasedev.fd, vdev->rom + off, 843 size, vdev->rom_offset + off); 844 if (bytes == 0) { 845 break; 846 } else if (bytes > 0) { 847 off += bytes; 848 size -= bytes; 849 } else { 850 if (errno == EINTR || errno == EAGAIN) { 851 continue; 852 } 853 error_report("vfio: Error reading device ROM: %m"); 854 break; 855 } 856 } 857 858 /* 859 * Test the ROM signature against our device, if the vendor is correct 860 * but the device ID doesn't match, store the correct device ID and 861 * recompute the checksum. Intel IGD devices need this and are known 862 * to have bogus checksums so we can't simply adjust the checksum. 863 */ 864 if (pci_get_word(vdev->rom) == 0xaa55 && 865 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size && 866 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) { 867 uint16_t vid, did; 868 869 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4); 870 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6); 871 872 if (vid == vdev->vendor_id && did != vdev->device_id) { 873 int i; 874 uint8_t csum, *data = vdev->rom; 875 876 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6, 877 vdev->device_id); 878 data[6] = 0; 879 880 for (csum = 0, i = 0; i < vdev->rom_size; i++) { 881 csum += data[i]; 882 } 883 884 data[6] = -csum; 885 } 886 } 887 } 888 889 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size) 890 { 891 VFIOPCIDevice *vdev = opaque; 892 union { 893 uint8_t byte; 894 uint16_t word; 895 uint32_t dword; 896 uint64_t qword; 897 } val; 898 uint64_t data = 0; 899 900 /* Load the ROM lazily when the guest tries to read it */ 901 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) { 902 vfio_pci_load_rom(vdev); 903 } 904 905 memcpy(&val, vdev->rom + addr, 906 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0); 907 908 switch (size) { 909 case 1: 910 data = val.byte; 911 break; 912 case 2: 913 data = le16_to_cpu(val.word); 914 break; 915 case 4: 916 data = le32_to_cpu(val.dword); 917 break; 918 default: 919 hw_error("vfio: unsupported read size, %d bytes\n", size); 920 break; 921 } 922 923 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data); 924 925 return data; 926 } 927 928 static void vfio_rom_write(void *opaque, hwaddr addr, 929 uint64_t data, unsigned size) 930 { 931 } 932 933 static const MemoryRegionOps vfio_rom_ops = { 934 .read = vfio_rom_read, 935 .write = vfio_rom_write, 936 .endianness = DEVICE_LITTLE_ENDIAN, 937 }; 938 939 static void vfio_pci_size_rom(VFIOPCIDevice *vdev) 940 { 941 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK); 942 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS; 943 DeviceState *dev = DEVICE(vdev); 944 char *name; 945 int fd = vdev->vbasedev.fd; 946 947 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) { 948 /* Since pci handles romfile, just print a message and return */ 949 if (vfio_blacklist_opt_rom(vdev) && vdev->pdev.romfile) { 950 warn_report("Device at %s is known to cause system instability" 951 " issues during option rom execution", 952 vdev->vbasedev.name); 953 error_printf("Proceeding anyway since user specified romfile\n"); 954 } 955 return; 956 } 957 958 /* 959 * Use the same size ROM BAR as the physical device. The contents 960 * will get filled in later when the guest tries to read it. 961 */ 962 if (pread(fd, &orig, 4, offset) != 4 || 963 pwrite(fd, &size, 4, offset) != 4 || 964 pread(fd, &size, 4, offset) != 4 || 965 pwrite(fd, &orig, 4, offset) != 4) { 966 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name); 967 return; 968 } 969 970 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1; 971 972 if (!size) { 973 return; 974 } 975 976 if (vfio_blacklist_opt_rom(vdev)) { 977 if (dev->opts && qemu_opt_get(dev->opts, "rombar")) { 978 warn_report("Device at %s is known to cause system instability" 979 " issues during option rom execution", 980 vdev->vbasedev.name); 981 error_printf("Proceeding anyway since user specified" 982 " non zero value for rombar\n"); 983 } else { 984 warn_report("Rom loading for device at %s has been disabled" 985 " due to system instability issues", 986 vdev->vbasedev.name); 987 error_printf("Specify rombar=1 or romfile to force\n"); 988 return; 989 } 990 } 991 992 trace_vfio_pci_size_rom(vdev->vbasedev.name, size); 993 994 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name); 995 996 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev), 997 &vfio_rom_ops, vdev, name, size); 998 g_free(name); 999 1000 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT, 1001 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom); 1002 1003 vdev->rom_read_failed = false; 1004 } 1005 1006 void vfio_vga_write(void *opaque, hwaddr addr, 1007 uint64_t data, unsigned size) 1008 { 1009 VFIOVGARegion *region = opaque; 1010 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1011 union { 1012 uint8_t byte; 1013 uint16_t word; 1014 uint32_t dword; 1015 uint64_t qword; 1016 } buf; 1017 off_t offset = vga->fd_offset + region->offset + addr; 1018 1019 switch (size) { 1020 case 1: 1021 buf.byte = data; 1022 break; 1023 case 2: 1024 buf.word = cpu_to_le16(data); 1025 break; 1026 case 4: 1027 buf.dword = cpu_to_le32(data); 1028 break; 1029 default: 1030 hw_error("vfio: unsupported write size, %d bytes", size); 1031 break; 1032 } 1033 1034 if (pwrite(vga->fd, &buf, size, offset) != size) { 1035 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m", 1036 __func__, region->offset + addr, data, size); 1037 } 1038 1039 trace_vfio_vga_write(region->offset + addr, data, size); 1040 } 1041 1042 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size) 1043 { 1044 VFIOVGARegion *region = opaque; 1045 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]); 1046 union { 1047 uint8_t byte; 1048 uint16_t word; 1049 uint32_t dword; 1050 uint64_t qword; 1051 } buf; 1052 uint64_t data = 0; 1053 off_t offset = vga->fd_offset + region->offset + addr; 1054 1055 if (pread(vga->fd, &buf, size, offset) != size) { 1056 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m", 1057 __func__, region->offset + addr, size); 1058 return (uint64_t)-1; 1059 } 1060 1061 switch (size) { 1062 case 1: 1063 data = buf.byte; 1064 break; 1065 case 2: 1066 data = le16_to_cpu(buf.word); 1067 break; 1068 case 4: 1069 data = le32_to_cpu(buf.dword); 1070 break; 1071 default: 1072 hw_error("vfio: unsupported read size, %d bytes", size); 1073 break; 1074 } 1075 1076 trace_vfio_vga_read(region->offset + addr, size, data); 1077 1078 return data; 1079 } 1080 1081 static const MemoryRegionOps vfio_vga_ops = { 1082 .read = vfio_vga_read, 1083 .write = vfio_vga_write, 1084 .endianness = DEVICE_LITTLE_ENDIAN, 1085 }; 1086 1087 /* 1088 * Expand memory region of sub-page(size < PAGE_SIZE) MMIO BAR to page 1089 * size if the BAR is in an exclusive page in host so that we could map 1090 * this BAR to guest. But this sub-page BAR may not occupy an exclusive 1091 * page in guest. So we should set the priority of the expanded memory 1092 * region to zero in case of overlap with BARs which share the same page 1093 * with the sub-page BAR in guest. Besides, we should also recover the 1094 * size of this sub-page BAR when its base address is changed in guest 1095 * and not page aligned any more. 1096 */ 1097 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar) 1098 { 1099 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1100 VFIORegion *region = &vdev->bars[bar].region; 1101 MemoryRegion *mmap_mr, *region_mr, *base_mr; 1102 PCIIORegion *r; 1103 pcibus_t bar_addr; 1104 uint64_t size = region->size; 1105 1106 /* Make sure that the whole region is allowed to be mmapped */ 1107 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap || 1108 region->mmaps[0].size != region->size) { 1109 return; 1110 } 1111 1112 r = &pdev->io_regions[bar]; 1113 bar_addr = r->addr; 1114 base_mr = vdev->bars[bar].mr; 1115 region_mr = region->mem; 1116 mmap_mr = ®ion->mmaps[0].mem; 1117 1118 /* If BAR is mapped and page aligned, update to fill PAGE_SIZE */ 1119 if (bar_addr != PCI_BAR_UNMAPPED && 1120 !(bar_addr & ~qemu_real_host_page_mask)) { 1121 size = qemu_real_host_page_size; 1122 } 1123 1124 memory_region_transaction_begin(); 1125 1126 if (vdev->bars[bar].size < size) { 1127 memory_region_set_size(base_mr, size); 1128 } 1129 memory_region_set_size(region_mr, size); 1130 memory_region_set_size(mmap_mr, size); 1131 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) { 1132 memory_region_del_subregion(r->address_space, base_mr); 1133 memory_region_add_subregion_overlap(r->address_space, 1134 bar_addr, base_mr, 0); 1135 } 1136 1137 memory_region_transaction_commit(); 1138 } 1139 1140 /* 1141 * PCI config space 1142 */ 1143 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len) 1144 { 1145 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1146 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val; 1147 1148 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len); 1149 emu_bits = le32_to_cpu(emu_bits); 1150 1151 if (emu_bits) { 1152 emu_val = pci_default_read_config(pdev, addr, len); 1153 } 1154 1155 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) { 1156 ssize_t ret; 1157 1158 ret = pread(vdev->vbasedev.fd, &phys_val, len, 1159 vdev->config_offset + addr); 1160 if (ret != len) { 1161 error_report("%s(%s, 0x%x, 0x%x) failed: %m", 1162 __func__, vdev->vbasedev.name, addr, len); 1163 return -errno; 1164 } 1165 phys_val = le32_to_cpu(phys_val); 1166 } 1167 1168 val = (emu_val & emu_bits) | (phys_val & ~emu_bits); 1169 1170 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val); 1171 1172 return val; 1173 } 1174 1175 void vfio_pci_write_config(PCIDevice *pdev, 1176 uint32_t addr, uint32_t val, int len) 1177 { 1178 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 1179 uint32_t val_le = cpu_to_le32(val); 1180 1181 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len); 1182 1183 /* Write everything to VFIO, let it filter out what we can't write */ 1184 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr) 1185 != len) { 1186 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m", 1187 __func__, vdev->vbasedev.name, addr, val, len); 1188 } 1189 1190 /* MSI/MSI-X Enabling/Disabling */ 1191 if (pdev->cap_present & QEMU_PCI_CAP_MSI && 1192 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) { 1193 int is_enabled, was_enabled = msi_enabled(pdev); 1194 1195 pci_default_write_config(pdev, addr, val, len); 1196 1197 is_enabled = msi_enabled(pdev); 1198 1199 if (!was_enabled) { 1200 if (is_enabled) { 1201 vfio_msi_enable(vdev); 1202 } 1203 } else { 1204 if (!is_enabled) { 1205 vfio_msi_disable(vdev); 1206 } else { 1207 vfio_update_msi(vdev); 1208 } 1209 } 1210 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX && 1211 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) { 1212 int is_enabled, was_enabled = msix_enabled(pdev); 1213 1214 pci_default_write_config(pdev, addr, val, len); 1215 1216 is_enabled = msix_enabled(pdev); 1217 1218 if (!was_enabled && is_enabled) { 1219 vfio_msix_enable(vdev); 1220 } else if (was_enabled && !is_enabled) { 1221 vfio_msix_disable(vdev); 1222 } 1223 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) || 1224 range_covers_byte(addr, len, PCI_COMMAND)) { 1225 pcibus_t old_addr[PCI_NUM_REGIONS - 1]; 1226 int bar; 1227 1228 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1229 old_addr[bar] = pdev->io_regions[bar].addr; 1230 } 1231 1232 pci_default_write_config(pdev, addr, val, len); 1233 1234 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { 1235 if (old_addr[bar] != pdev->io_regions[bar].addr && 1236 vdev->bars[bar].region.size > 0 && 1237 vdev->bars[bar].region.size < qemu_real_host_page_size) { 1238 vfio_sub_page_bar_update_mapping(pdev, bar); 1239 } 1240 } 1241 } else { 1242 /* Write everything to QEMU to keep emulated bits correct */ 1243 pci_default_write_config(pdev, addr, val, len); 1244 } 1245 } 1246 1247 /* 1248 * Interrupt setup 1249 */ 1250 static void vfio_disable_interrupts(VFIOPCIDevice *vdev) 1251 { 1252 /* 1253 * More complicated than it looks. Disabling MSI/X transitions the 1254 * device to INTx mode (if supported). Therefore we need to first 1255 * disable MSI/X and then cleanup by disabling INTx. 1256 */ 1257 if (vdev->interrupt == VFIO_INT_MSIX) { 1258 vfio_msix_disable(vdev); 1259 } else if (vdev->interrupt == VFIO_INT_MSI) { 1260 vfio_msi_disable(vdev); 1261 } 1262 1263 if (vdev->interrupt == VFIO_INT_INTx) { 1264 vfio_intx_disable(vdev); 1265 } 1266 } 1267 1268 static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1269 { 1270 uint16_t ctrl; 1271 bool msi_64bit, msi_maskbit; 1272 int ret, entries; 1273 Error *err = NULL; 1274 1275 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl), 1276 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) { 1277 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS"); 1278 return -errno; 1279 } 1280 ctrl = le16_to_cpu(ctrl); 1281 1282 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT); 1283 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT); 1284 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1); 1285 1286 trace_vfio_msi_setup(vdev->vbasedev.name, pos); 1287 1288 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err); 1289 if (ret < 0) { 1290 if (ret == -ENOTSUP) { 1291 return 0; 1292 } 1293 error_propagate_prepend(errp, err, "msi_init failed: "); 1294 return ret; 1295 } 1296 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0); 1297 1298 return 0; 1299 } 1300 1301 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev) 1302 { 1303 off_t start, end; 1304 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region; 1305 1306 /* 1307 * If the host driver allows mapping of a MSIX data, we are going to 1308 * do map the entire BAR and emulate MSIX table on top of that. 1309 */ 1310 if (vfio_has_region_cap(&vdev->vbasedev, region->nr, 1311 VFIO_REGION_INFO_CAP_MSIX_MAPPABLE)) { 1312 return; 1313 } 1314 1315 /* 1316 * We expect to find a single mmap covering the whole BAR, anything else 1317 * means it's either unsupported or already setup. 1318 */ 1319 if (region->nr_mmaps != 1 || region->mmaps[0].offset || 1320 region->size != region->mmaps[0].size) { 1321 return; 1322 } 1323 1324 /* MSI-X table start and end aligned to host page size */ 1325 start = vdev->msix->table_offset & qemu_real_host_page_mask; 1326 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset + 1327 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE)); 1328 1329 /* 1330 * Does the MSI-X table cover the beginning of the BAR? The whole BAR? 1331 * NB - Host page size is necessarily a power of two and so is the PCI 1332 * BAR (not counting EA yet), therefore if we have host page aligned 1333 * @start and @end, then any remainder of the BAR before or after those 1334 * must be at least host page sized and therefore mmap'able. 1335 */ 1336 if (!start) { 1337 if (end >= region->size) { 1338 region->nr_mmaps = 0; 1339 g_free(region->mmaps); 1340 region->mmaps = NULL; 1341 trace_vfio_msix_fixup(vdev->vbasedev.name, 1342 vdev->msix->table_bar, 0, 0); 1343 } else { 1344 region->mmaps[0].offset = end; 1345 region->mmaps[0].size = region->size - end; 1346 trace_vfio_msix_fixup(vdev->vbasedev.name, 1347 vdev->msix->table_bar, region->mmaps[0].offset, 1348 region->mmaps[0].offset + region->mmaps[0].size); 1349 } 1350 1351 /* Maybe it's aligned at the end of the BAR */ 1352 } else if (end >= region->size) { 1353 region->mmaps[0].size = start; 1354 trace_vfio_msix_fixup(vdev->vbasedev.name, 1355 vdev->msix->table_bar, region->mmaps[0].offset, 1356 region->mmaps[0].offset + region->mmaps[0].size); 1357 1358 /* Otherwise it must split the BAR */ 1359 } else { 1360 region->nr_mmaps = 2; 1361 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2); 1362 1363 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap)); 1364 1365 region->mmaps[0].size = start; 1366 trace_vfio_msix_fixup(vdev->vbasedev.name, 1367 vdev->msix->table_bar, region->mmaps[0].offset, 1368 region->mmaps[0].offset + region->mmaps[0].size); 1369 1370 region->mmaps[1].offset = end; 1371 region->mmaps[1].size = region->size - end; 1372 trace_vfio_msix_fixup(vdev->vbasedev.name, 1373 vdev->msix->table_bar, region->mmaps[1].offset, 1374 region->mmaps[1].offset + region->mmaps[1].size); 1375 } 1376 } 1377 1378 static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp) 1379 { 1380 int target_bar = -1; 1381 size_t msix_sz; 1382 1383 if (!vdev->msix || vdev->msix_relo == OFF_AUTOPCIBAR_OFF) { 1384 return; 1385 } 1386 1387 /* The actual minimum size of MSI-X structures */ 1388 msix_sz = (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) + 1389 (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8); 1390 /* Round up to host pages, we don't want to share a page */ 1391 msix_sz = REAL_HOST_PAGE_ALIGN(msix_sz); 1392 /* PCI BARs must be a power of 2 */ 1393 msix_sz = pow2ceil(msix_sz); 1394 1395 if (vdev->msix_relo == OFF_AUTOPCIBAR_AUTO) { 1396 /* 1397 * TODO: Lookup table for known devices. 1398 * 1399 * Logically we might use an algorithm here to select the BAR adding 1400 * the least additional MMIO space, but we cannot programatically 1401 * predict the driver dependency on BAR ordering or sizing, therefore 1402 * 'auto' becomes a lookup for combinations reported to work. 1403 */ 1404 if (target_bar < 0) { 1405 error_setg(errp, "No automatic MSI-X relocation available for " 1406 "device %04x:%04x", vdev->vendor_id, vdev->device_id); 1407 return; 1408 } 1409 } else { 1410 target_bar = (int)(vdev->msix_relo - OFF_AUTOPCIBAR_BAR0); 1411 } 1412 1413 /* I/O port BARs cannot host MSI-X structures */ 1414 if (vdev->bars[target_bar].ioport) { 1415 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1416 "I/O port BAR", target_bar); 1417 return; 1418 } 1419 1420 /* Cannot use a BAR in the "shadow" of a 64-bit BAR */ 1421 if (!vdev->bars[target_bar].size && 1422 target_bar > 0 && vdev->bars[target_bar - 1].mem64) { 1423 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1424 "consumed by 64-bit BAR %d", target_bar, target_bar - 1); 1425 return; 1426 } 1427 1428 /* 2GB max size for 32-bit BARs, cannot double if already > 1G */ 1429 if (vdev->bars[target_bar].size > 1 * GiB && 1430 !vdev->bars[target_bar].mem64) { 1431 error_setg(errp, "Invalid MSI-X relocation BAR %d, " 1432 "no space to extend 32-bit BAR", target_bar); 1433 return; 1434 } 1435 1436 /* 1437 * If adding a new BAR, test if we can make it 64bit. We make it 1438 * prefetchable since QEMU MSI-X emulation has no read side effects 1439 * and doing so makes mapping more flexible. 1440 */ 1441 if (!vdev->bars[target_bar].size) { 1442 if (target_bar < (PCI_ROM_SLOT - 1) && 1443 !vdev->bars[target_bar + 1].size) { 1444 vdev->bars[target_bar].mem64 = true; 1445 vdev->bars[target_bar].type = PCI_BASE_ADDRESS_MEM_TYPE_64; 1446 } 1447 vdev->bars[target_bar].type |= PCI_BASE_ADDRESS_MEM_PREFETCH; 1448 vdev->bars[target_bar].size = msix_sz; 1449 vdev->msix->table_offset = 0; 1450 } else { 1451 vdev->bars[target_bar].size = MAX(vdev->bars[target_bar].size * 2, 1452 msix_sz * 2); 1453 /* 1454 * Due to above size calc, MSI-X always starts halfway into the BAR, 1455 * which will always be a separate host page. 1456 */ 1457 vdev->msix->table_offset = vdev->bars[target_bar].size / 2; 1458 } 1459 1460 vdev->msix->table_bar = target_bar; 1461 vdev->msix->pba_bar = target_bar; 1462 /* Requires 8-byte alignment, but PCI_MSIX_ENTRY_SIZE guarantees that */ 1463 vdev->msix->pba_offset = vdev->msix->table_offset + 1464 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE); 1465 1466 trace_vfio_msix_relo(vdev->vbasedev.name, 1467 vdev->msix->table_bar, vdev->msix->table_offset); 1468 } 1469 1470 /* 1471 * We don't have any control over how pci_add_capability() inserts 1472 * capabilities into the chain. In order to setup MSI-X we need a 1473 * MemoryRegion for the BAR. In order to setup the BAR and not 1474 * attempt to mmap the MSI-X table area, which VFIO won't allow, we 1475 * need to first look for where the MSI-X table lives. So we 1476 * unfortunately split MSI-X setup across two functions. 1477 */ 1478 static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp) 1479 { 1480 uint8_t pos; 1481 uint16_t ctrl; 1482 uint32_t table, pba; 1483 int fd = vdev->vbasedev.fd; 1484 VFIOMSIXInfo *msix; 1485 1486 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX); 1487 if (!pos) { 1488 return; 1489 } 1490 1491 if (pread(fd, &ctrl, sizeof(ctrl), 1492 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) { 1493 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS"); 1494 return; 1495 } 1496 1497 if (pread(fd, &table, sizeof(table), 1498 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) { 1499 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE"); 1500 return; 1501 } 1502 1503 if (pread(fd, &pba, sizeof(pba), 1504 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) { 1505 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA"); 1506 return; 1507 } 1508 1509 ctrl = le16_to_cpu(ctrl); 1510 table = le32_to_cpu(table); 1511 pba = le32_to_cpu(pba); 1512 1513 msix = g_malloc0(sizeof(*msix)); 1514 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK; 1515 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK; 1516 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK; 1517 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK; 1518 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; 1519 1520 /* 1521 * Test the size of the pba_offset variable and catch if it extends outside 1522 * of the specified BAR. If it is the case, we need to apply a hardware 1523 * specific quirk if the device is known or we have a broken configuration. 1524 */ 1525 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) { 1526 /* 1527 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5 1528 * adapters. The T5 hardware returns an incorrect value of 0x8000 for 1529 * the VF PBA offset while the BAR itself is only 8k. The correct value 1530 * is 0x1000, so we hard code that here. 1531 */ 1532 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO && 1533 (vdev->device_id & 0xff00) == 0x5800) { 1534 msix->pba_offset = 0x1000; 1535 } else { 1536 error_setg(errp, "hardware reports invalid configuration, " 1537 "MSIX PBA outside of specified BAR"); 1538 g_free(msix); 1539 return; 1540 } 1541 } 1542 1543 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar, 1544 msix->table_offset, msix->entries); 1545 vdev->msix = msix; 1546 1547 vfio_pci_fixup_msix_region(vdev); 1548 1549 vfio_pci_relocate_msix(vdev, errp); 1550 } 1551 1552 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp) 1553 { 1554 int ret; 1555 Error *err = NULL; 1556 1557 vdev->msix->pending = g_malloc0(BITS_TO_LONGS(vdev->msix->entries) * 1558 sizeof(unsigned long)); 1559 ret = msix_init(&vdev->pdev, vdev->msix->entries, 1560 vdev->bars[vdev->msix->table_bar].mr, 1561 vdev->msix->table_bar, vdev->msix->table_offset, 1562 vdev->bars[vdev->msix->pba_bar].mr, 1563 vdev->msix->pba_bar, vdev->msix->pba_offset, pos, 1564 &err); 1565 if (ret < 0) { 1566 if (ret == -ENOTSUP) { 1567 warn_report_err(err); 1568 return 0; 1569 } 1570 1571 error_propagate(errp, err); 1572 return ret; 1573 } 1574 1575 /* 1576 * The PCI spec suggests that devices provide additional alignment for 1577 * MSI-X structures and avoid overlapping non-MSI-X related registers. 1578 * For an assigned device, this hopefully means that emulation of MSI-X 1579 * structures does not affect the performance of the device. If devices 1580 * fail to provide that alignment, a significant performance penalty may 1581 * result, for instance Mellanox MT27500 VFs: 1582 * http://www.spinics.net/lists/kvm/msg125881.html 1583 * 1584 * The PBA is simply not that important for such a serious regression and 1585 * most drivers do not appear to look at it. The solution for this is to 1586 * disable the PBA MemoryRegion unless it's being used. We disable it 1587 * here and only enable it if a masked vector fires through QEMU. As the 1588 * vector-use notifier is called, which occurs on unmask, we test whether 1589 * PBA emulation is needed and again disable if not. 1590 */ 1591 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false); 1592 1593 /* 1594 * The emulated machine may provide a paravirt interface for MSIX setup 1595 * so it is not strictly necessary to emulate MSIX here. This becomes 1596 * helpful when frequently accessed MMIO registers are located in 1597 * subpages adjacent to the MSIX table but the MSIX data containing page 1598 * cannot be mapped because of a host page size bigger than the MSIX table 1599 * alignment. 1600 */ 1601 if (object_property_get_bool(OBJECT(qdev_get_machine()), 1602 "vfio-no-msix-emulation", NULL)) { 1603 memory_region_set_enabled(&vdev->pdev.msix_table_mmio, false); 1604 } 1605 1606 return 0; 1607 } 1608 1609 static void vfio_teardown_msi(VFIOPCIDevice *vdev) 1610 { 1611 msi_uninit(&vdev->pdev); 1612 1613 if (vdev->msix) { 1614 msix_uninit(&vdev->pdev, 1615 vdev->bars[vdev->msix->table_bar].mr, 1616 vdev->bars[vdev->msix->pba_bar].mr); 1617 g_free(vdev->msix->pending); 1618 } 1619 } 1620 1621 /* 1622 * Resource setup 1623 */ 1624 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled) 1625 { 1626 int i; 1627 1628 for (i = 0; i < PCI_ROM_SLOT; i++) { 1629 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled); 1630 } 1631 } 1632 1633 static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr) 1634 { 1635 VFIOBAR *bar = &vdev->bars[nr]; 1636 1637 uint32_t pci_bar; 1638 int ret; 1639 1640 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */ 1641 if (!bar->region.size) { 1642 return; 1643 } 1644 1645 /* Determine what type of BAR this is for registration */ 1646 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar), 1647 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr)); 1648 if (ret != sizeof(pci_bar)) { 1649 error_report("vfio: Failed to read BAR %d (%m)", nr); 1650 return; 1651 } 1652 1653 pci_bar = le32_to_cpu(pci_bar); 1654 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO); 1655 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64); 1656 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK : 1657 ~PCI_BASE_ADDRESS_MEM_MASK); 1658 bar->size = bar->region.size; 1659 } 1660 1661 static void vfio_bars_prepare(VFIOPCIDevice *vdev) 1662 { 1663 int i; 1664 1665 for (i = 0; i < PCI_ROM_SLOT; i++) { 1666 vfio_bar_prepare(vdev, i); 1667 } 1668 } 1669 1670 static void vfio_bar_register(VFIOPCIDevice *vdev, int nr) 1671 { 1672 VFIOBAR *bar = &vdev->bars[nr]; 1673 char *name; 1674 1675 if (!bar->size) { 1676 return; 1677 } 1678 1679 bar->mr = g_new0(MemoryRegion, 1); 1680 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr); 1681 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size); 1682 g_free(name); 1683 1684 if (bar->region.size) { 1685 memory_region_add_subregion(bar->mr, 0, bar->region.mem); 1686 1687 if (vfio_region_mmap(&bar->region)) { 1688 error_report("Failed to mmap %s BAR %d. Performance may be slow", 1689 vdev->vbasedev.name, nr); 1690 } 1691 } 1692 1693 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr); 1694 } 1695 1696 static void vfio_bars_register(VFIOPCIDevice *vdev) 1697 { 1698 int i; 1699 1700 for (i = 0; i < PCI_ROM_SLOT; i++) { 1701 vfio_bar_register(vdev, i); 1702 } 1703 } 1704 1705 static void vfio_bars_exit(VFIOPCIDevice *vdev) 1706 { 1707 int i; 1708 1709 for (i = 0; i < PCI_ROM_SLOT; i++) { 1710 VFIOBAR *bar = &vdev->bars[i]; 1711 1712 vfio_bar_quirk_exit(vdev, i); 1713 vfio_region_exit(&bar->region); 1714 if (bar->region.size) { 1715 memory_region_del_subregion(bar->mr, bar->region.mem); 1716 } 1717 } 1718 1719 if (vdev->vga) { 1720 pci_unregister_vga(&vdev->pdev); 1721 vfio_vga_quirk_exit(vdev); 1722 } 1723 } 1724 1725 static void vfio_bars_finalize(VFIOPCIDevice *vdev) 1726 { 1727 int i; 1728 1729 for (i = 0; i < PCI_ROM_SLOT; i++) { 1730 VFIOBAR *bar = &vdev->bars[i]; 1731 1732 vfio_bar_quirk_finalize(vdev, i); 1733 vfio_region_finalize(&bar->region); 1734 if (bar->size) { 1735 object_unparent(OBJECT(bar->mr)); 1736 g_free(bar->mr); 1737 } 1738 } 1739 1740 if (vdev->vga) { 1741 vfio_vga_quirk_finalize(vdev); 1742 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) { 1743 object_unparent(OBJECT(&vdev->vga->region[i].mem)); 1744 } 1745 g_free(vdev->vga); 1746 } 1747 } 1748 1749 /* 1750 * General setup 1751 */ 1752 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos) 1753 { 1754 uint8_t tmp; 1755 uint16_t next = PCI_CONFIG_SPACE_SIZE; 1756 1757 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp; 1758 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) { 1759 if (tmp > pos && tmp < next) { 1760 next = tmp; 1761 } 1762 } 1763 1764 return next - pos; 1765 } 1766 1767 1768 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos) 1769 { 1770 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE; 1771 1772 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp; 1773 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) { 1774 if (tmp > pos && tmp < next) { 1775 next = tmp; 1776 } 1777 } 1778 1779 return next - pos; 1780 } 1781 1782 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask) 1783 { 1784 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val); 1785 } 1786 1787 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos, 1788 uint16_t val, uint16_t mask) 1789 { 1790 vfio_set_word_bits(vdev->pdev.config + pos, val, mask); 1791 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask); 1792 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask); 1793 } 1794 1795 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask) 1796 { 1797 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val); 1798 } 1799 1800 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos, 1801 uint32_t val, uint32_t mask) 1802 { 1803 vfio_set_long_bits(vdev->pdev.config + pos, val, mask); 1804 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask); 1805 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask); 1806 } 1807 1808 static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size, 1809 Error **errp) 1810 { 1811 uint16_t flags; 1812 uint8_t type; 1813 1814 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS); 1815 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4; 1816 1817 if (type != PCI_EXP_TYPE_ENDPOINT && 1818 type != PCI_EXP_TYPE_LEG_END && 1819 type != PCI_EXP_TYPE_RC_END) { 1820 1821 error_setg(errp, "assignment of PCIe type 0x%x " 1822 "devices is not currently supported", type); 1823 return -EINVAL; 1824 } 1825 1826 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) { 1827 PCIBus *bus = pci_get_bus(&vdev->pdev); 1828 PCIDevice *bridge; 1829 1830 /* 1831 * Traditionally PCI device assignment exposes the PCIe capability 1832 * as-is on non-express buses. The reason being that some drivers 1833 * simply assume that it's there, for example tg3. However when 1834 * we're running on a native PCIe machine type, like Q35, we need 1835 * to hide the PCIe capability. The reason for this is twofold; 1836 * first Windows guests get a Code 10 error when the PCIe capability 1837 * is exposed in this configuration. Therefore express devices won't 1838 * work at all unless they're attached to express buses in the VM. 1839 * Second, a native PCIe machine introduces the possibility of fine 1840 * granularity IOMMUs supporting both translation and isolation. 1841 * Guest code to discover the IOMMU visibility of a device, such as 1842 * IOMMU grouping code on Linux, is very aware of device types and 1843 * valid transitions between bus types. An express device on a non- 1844 * express bus is not a valid combination on bare metal systems. 1845 * 1846 * Drivers that require a PCIe capability to make the device 1847 * functional are simply going to need to have their devices placed 1848 * on a PCIe bus in the VM. 1849 */ 1850 while (!pci_bus_is_root(bus)) { 1851 bridge = pci_bridge_get_device(bus); 1852 bus = pci_get_bus(bridge); 1853 } 1854 1855 if (pci_bus_is_express(bus)) { 1856 return 0; 1857 } 1858 1859 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) { 1860 /* 1861 * On a Root Complex bus Endpoints become Root Complex Integrated 1862 * Endpoints, which changes the type and clears the LNK & LNK2 fields. 1863 */ 1864 if (type == PCI_EXP_TYPE_ENDPOINT) { 1865 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1866 PCI_EXP_TYPE_RC_END << 4, 1867 PCI_EXP_FLAGS_TYPE); 1868 1869 /* Link Capabilities, Status, and Control goes away */ 1870 if (size > PCI_EXP_LNKCTL) { 1871 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0); 1872 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1873 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0); 1874 1875 #ifndef PCI_EXP_LNKCAP2 1876 #define PCI_EXP_LNKCAP2 44 1877 #endif 1878 #ifndef PCI_EXP_LNKSTA2 1879 #define PCI_EXP_LNKSTA2 50 1880 #endif 1881 /* Link 2 Capabilities, Status, and Control goes away */ 1882 if (size > PCI_EXP_LNKCAP2) { 1883 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0); 1884 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0); 1885 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0); 1886 } 1887 } 1888 1889 } else if (type == PCI_EXP_TYPE_LEG_END) { 1890 /* 1891 * Legacy endpoints don't belong on the root complex. Windows 1892 * seems to be happier with devices if we skip the capability. 1893 */ 1894 return 0; 1895 } 1896 1897 } else { 1898 /* 1899 * Convert Root Complex Integrated Endpoints to regular endpoints. 1900 * These devices don't support LNK/LNK2 capabilities, so make them up. 1901 */ 1902 if (type == PCI_EXP_TYPE_RC_END) { 1903 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1904 PCI_EXP_TYPE_ENDPOINT << 4, 1905 PCI_EXP_FLAGS_TYPE); 1906 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 1907 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) | 1908 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT), ~0); 1909 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0); 1910 } 1911 } 1912 1913 /* 1914 * Intel 82599 SR-IOV VFs report an invalid PCIe capability version 0 1915 * (Niantic errate #35) causing Windows to error with a Code 10 for the 1916 * device on Q35. Fixup any such devices to report version 1. If we 1917 * were to remove the capability entirely the guest would lose extended 1918 * config space. 1919 */ 1920 if ((flags & PCI_EXP_FLAGS_VERS) == 0) { 1921 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS, 1922 1, PCI_EXP_FLAGS_VERS); 1923 } 1924 1925 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size, 1926 errp); 1927 if (pos < 0) { 1928 return pos; 1929 } 1930 1931 vdev->pdev.exp.exp_cap = pos; 1932 1933 return pos; 1934 } 1935 1936 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos) 1937 { 1938 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP); 1939 1940 if (cap & PCI_EXP_DEVCAP_FLR) { 1941 trace_vfio_check_pcie_flr(vdev->vbasedev.name); 1942 vdev->has_flr = true; 1943 } 1944 } 1945 1946 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos) 1947 { 1948 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL); 1949 1950 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) { 1951 trace_vfio_check_pm_reset(vdev->vbasedev.name); 1952 vdev->has_pm_reset = true; 1953 } 1954 } 1955 1956 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos) 1957 { 1958 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP); 1959 1960 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) { 1961 trace_vfio_check_af_flr(vdev->vbasedev.name); 1962 vdev->has_flr = true; 1963 } 1964 } 1965 1966 static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp) 1967 { 1968 PCIDevice *pdev = &vdev->pdev; 1969 uint8_t cap_id, next, size; 1970 int ret; 1971 1972 cap_id = pdev->config[pos]; 1973 next = pdev->config[pos + PCI_CAP_LIST_NEXT]; 1974 1975 /* 1976 * If it becomes important to configure capabilities to their actual 1977 * size, use this as the default when it's something we don't recognize. 1978 * Since QEMU doesn't actually handle many of the config accesses, 1979 * exact size doesn't seem worthwhile. 1980 */ 1981 size = vfio_std_cap_max_size(pdev, pos); 1982 1983 /* 1984 * pci_add_capability always inserts the new capability at the head 1985 * of the chain. Therefore to end up with a chain that matches the 1986 * physical device, we insert from the end by making this recursive. 1987 * This is also why we pre-calculate size above as cached config space 1988 * will be changed as we unwind the stack. 1989 */ 1990 if (next) { 1991 ret = vfio_add_std_cap(vdev, next, errp); 1992 if (ret) { 1993 return ret; 1994 } 1995 } else { 1996 /* Begin the rebuild, use QEMU emulated list bits */ 1997 pdev->config[PCI_CAPABILITY_LIST] = 0; 1998 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff; 1999 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2000 2001 ret = vfio_add_virt_caps(vdev, errp); 2002 if (ret) { 2003 return ret; 2004 } 2005 } 2006 2007 /* Scale down size, esp in case virt caps were added above */ 2008 size = MIN(size, vfio_std_cap_max_size(pdev, pos)); 2009 2010 /* Use emulated next pointer to allow dropping caps */ 2011 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff); 2012 2013 switch (cap_id) { 2014 case PCI_CAP_ID_MSI: 2015 ret = vfio_msi_setup(vdev, pos, errp); 2016 break; 2017 case PCI_CAP_ID_EXP: 2018 vfio_check_pcie_flr(vdev, pos); 2019 ret = vfio_setup_pcie_cap(vdev, pos, size, errp); 2020 break; 2021 case PCI_CAP_ID_MSIX: 2022 ret = vfio_msix_setup(vdev, pos, errp); 2023 break; 2024 case PCI_CAP_ID_PM: 2025 vfio_check_pm_reset(vdev, pos); 2026 vdev->pm_cap = pos; 2027 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2028 break; 2029 case PCI_CAP_ID_AF: 2030 vfio_check_af_flr(vdev, pos); 2031 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2032 break; 2033 default: 2034 ret = pci_add_capability(pdev, cap_id, pos, size, errp); 2035 break; 2036 } 2037 2038 if (ret < 0) { 2039 error_prepend(errp, 2040 "failed to add PCI capability 0x%x[0x%x]@0x%x: ", 2041 cap_id, size, pos); 2042 return ret; 2043 } 2044 2045 return 0; 2046 } 2047 2048 static void vfio_add_ext_cap(VFIOPCIDevice *vdev) 2049 { 2050 PCIDevice *pdev = &vdev->pdev; 2051 uint32_t header; 2052 uint16_t cap_id, next, size; 2053 uint8_t cap_ver; 2054 uint8_t *config; 2055 2056 /* Only add extended caps if we have them and the guest can see them */ 2057 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) || 2058 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) { 2059 return; 2060 } 2061 2062 /* 2063 * pcie_add_capability always inserts the new capability at the tail 2064 * of the chain. Therefore to end up with a chain that matches the 2065 * physical device, we cache the config space to avoid overwriting 2066 * the original config space when we parse the extended capabilities. 2067 */ 2068 config = g_memdup(pdev->config, vdev->config_size); 2069 2070 /* 2071 * Extended capabilities are chained with each pointing to the next, so we 2072 * can drop anything other than the head of the chain simply by modifying 2073 * the previous next pointer. Seed the head of the chain here such that 2074 * we can simply skip any capabilities we want to drop below, regardless 2075 * of their position in the chain. If this stub capability still exists 2076 * after we add the capabilities we want to expose, update the capability 2077 * ID to zero. Note that we cannot seed with the capability header being 2078 * zero as this conflicts with definition of an absent capability chain 2079 * and prevents capabilities beyond the head of the list from being added. 2080 * By replacing the dummy capability ID with zero after walking the device 2081 * chain, we also transparently mark extended capabilities as absent if 2082 * no capabilities were added. Note that the PCIe spec defines an absence 2083 * of extended capabilities to be determined by a value of zero for the 2084 * capability ID, version, AND next pointer. A non-zero next pointer 2085 * should be sufficient to indicate additional capabilities are present, 2086 * which will occur if we call pcie_add_capability() below. The entire 2087 * first dword is emulated to support this. 2088 * 2089 * NB. The kernel side does similar masking, so be prepared that our 2090 * view of the device may also contain a capability ID zero in the head 2091 * of the chain. Skip it for the same reason that we cannot seed the 2092 * chain with a zero capability. 2093 */ 2094 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE, 2095 PCI_EXT_CAP(0xFFFF, 0, 0)); 2096 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); 2097 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); 2098 2099 for (next = PCI_CONFIG_SPACE_SIZE; next; 2100 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { 2101 header = pci_get_long(config + next); 2102 cap_id = PCI_EXT_CAP_ID(header); 2103 cap_ver = PCI_EXT_CAP_VER(header); 2104 2105 /* 2106 * If it becomes important to configure extended capabilities to their 2107 * actual size, use this as the default when it's something we don't 2108 * recognize. Since QEMU doesn't actually handle many of the config 2109 * accesses, exact size doesn't seem worthwhile. 2110 */ 2111 size = vfio_ext_cap_max_size(config, next); 2112 2113 /* Use emulated next pointer to allow dropping extended caps */ 2114 pci_long_test_and_set_mask(vdev->emulated_config_bits + next, 2115 PCI_EXT_CAP_NEXT_MASK); 2116 2117 switch (cap_id) { 2118 case 0: /* kernel masked capability */ 2119 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */ 2120 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */ 2121 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next); 2122 break; 2123 default: 2124 pcie_add_capability(pdev, cap_id, cap_ver, next, size); 2125 } 2126 2127 } 2128 2129 /* Cleanup chain head ID if necessary */ 2130 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) { 2131 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0); 2132 } 2133 2134 g_free(config); 2135 return; 2136 } 2137 2138 static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp) 2139 { 2140 PCIDevice *pdev = &vdev->pdev; 2141 int ret; 2142 2143 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) || 2144 !pdev->config[PCI_CAPABILITY_LIST]) { 2145 return 0; /* Nothing to add */ 2146 } 2147 2148 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp); 2149 if (ret) { 2150 return ret; 2151 } 2152 2153 vfio_add_ext_cap(vdev); 2154 return 0; 2155 } 2156 2157 static void vfio_pci_pre_reset(VFIOPCIDevice *vdev) 2158 { 2159 PCIDevice *pdev = &vdev->pdev; 2160 uint16_t cmd; 2161 2162 vfio_disable_interrupts(vdev); 2163 2164 /* Make sure the device is in D0 */ 2165 if (vdev->pm_cap) { 2166 uint16_t pmcsr; 2167 uint8_t state; 2168 2169 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2170 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2171 if (state) { 2172 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 2173 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2); 2174 /* vfio handles the necessary delay here */ 2175 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2); 2176 state = pmcsr & PCI_PM_CTRL_STATE_MASK; 2177 if (state) { 2178 error_report("vfio: Unable to power on device, stuck in D%d", 2179 state); 2180 } 2181 } 2182 } 2183 2184 /* 2185 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master. 2186 * Also put INTx Disable in known state. 2187 */ 2188 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2); 2189 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 2190 PCI_COMMAND_INTX_DISABLE); 2191 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2); 2192 } 2193 2194 static void vfio_pci_post_reset(VFIOPCIDevice *vdev) 2195 { 2196 Error *err = NULL; 2197 int nr; 2198 2199 vfio_intx_enable(vdev, &err); 2200 if (err) { 2201 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 2202 } 2203 2204 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) { 2205 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr); 2206 uint32_t val = 0; 2207 uint32_t len = sizeof(val); 2208 2209 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) { 2210 error_report("%s(%s) reset bar %d failed: %m", __func__, 2211 vdev->vbasedev.name, nr); 2212 } 2213 } 2214 2215 vfio_quirk_reset(vdev); 2216 } 2217 2218 static bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name) 2219 { 2220 char tmp[13]; 2221 2222 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain, 2223 addr->bus, addr->slot, addr->function); 2224 2225 return (strcmp(tmp, name) == 0); 2226 } 2227 2228 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single) 2229 { 2230 VFIOGroup *group; 2231 struct vfio_pci_hot_reset_info *info; 2232 struct vfio_pci_dependent_device *devices; 2233 struct vfio_pci_hot_reset *reset; 2234 int32_t *fds; 2235 int ret, i, count; 2236 bool multi = false; 2237 2238 trace_vfio_pci_hot_reset(vdev->vbasedev.name, single ? "one" : "multi"); 2239 2240 if (!single) { 2241 vfio_pci_pre_reset(vdev); 2242 } 2243 vdev->vbasedev.needs_reset = false; 2244 2245 info = g_malloc0(sizeof(*info)); 2246 info->argsz = sizeof(*info); 2247 2248 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2249 if (ret && errno != ENOSPC) { 2250 ret = -errno; 2251 if (!vdev->has_pm_reset) { 2252 error_report("vfio: Cannot reset device %s, " 2253 "no available reset mechanism.", vdev->vbasedev.name); 2254 } 2255 goto out_single; 2256 } 2257 2258 count = info->count; 2259 info = g_realloc(info, sizeof(*info) + (count * sizeof(*devices))); 2260 info->argsz = sizeof(*info) + (count * sizeof(*devices)); 2261 devices = &info->devices[0]; 2262 2263 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info); 2264 if (ret) { 2265 ret = -errno; 2266 error_report("vfio: hot reset info failed: %m"); 2267 goto out_single; 2268 } 2269 2270 trace_vfio_pci_hot_reset_has_dep_devices(vdev->vbasedev.name); 2271 2272 /* Verify that we have all the groups required */ 2273 for (i = 0; i < info->count; i++) { 2274 PCIHostDeviceAddress host; 2275 VFIOPCIDevice *tmp; 2276 VFIODevice *vbasedev_iter; 2277 2278 host.domain = devices[i].segment; 2279 host.bus = devices[i].bus; 2280 host.slot = PCI_SLOT(devices[i].devfn); 2281 host.function = PCI_FUNC(devices[i].devfn); 2282 2283 trace_vfio_pci_hot_reset_dep_devices(host.domain, 2284 host.bus, host.slot, host.function, devices[i].group_id); 2285 2286 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2287 continue; 2288 } 2289 2290 QLIST_FOREACH(group, &vfio_group_list, next) { 2291 if (group->groupid == devices[i].group_id) { 2292 break; 2293 } 2294 } 2295 2296 if (!group) { 2297 if (!vdev->has_pm_reset) { 2298 error_report("vfio: Cannot reset device %s, " 2299 "depends on group %d which is not owned.", 2300 vdev->vbasedev.name, devices[i].group_id); 2301 } 2302 ret = -EPERM; 2303 goto out; 2304 } 2305 2306 /* Prep dependent devices for reset and clear our marker. */ 2307 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2308 if (!vbasedev_iter->dev->realized || 2309 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2310 continue; 2311 } 2312 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2313 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2314 if (single) { 2315 ret = -EINVAL; 2316 goto out_single; 2317 } 2318 vfio_pci_pre_reset(tmp); 2319 tmp->vbasedev.needs_reset = false; 2320 multi = true; 2321 break; 2322 } 2323 } 2324 } 2325 2326 if (!single && !multi) { 2327 ret = -EINVAL; 2328 goto out_single; 2329 } 2330 2331 /* Determine how many group fds need to be passed */ 2332 count = 0; 2333 QLIST_FOREACH(group, &vfio_group_list, next) { 2334 for (i = 0; i < info->count; i++) { 2335 if (group->groupid == devices[i].group_id) { 2336 count++; 2337 break; 2338 } 2339 } 2340 } 2341 2342 reset = g_malloc0(sizeof(*reset) + (count * sizeof(*fds))); 2343 reset->argsz = sizeof(*reset) + (count * sizeof(*fds)); 2344 fds = &reset->group_fds[0]; 2345 2346 /* Fill in group fds */ 2347 QLIST_FOREACH(group, &vfio_group_list, next) { 2348 for (i = 0; i < info->count; i++) { 2349 if (group->groupid == devices[i].group_id) { 2350 fds[reset->count++] = group->fd; 2351 break; 2352 } 2353 } 2354 } 2355 2356 /* Bus reset! */ 2357 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_PCI_HOT_RESET, reset); 2358 g_free(reset); 2359 2360 trace_vfio_pci_hot_reset_result(vdev->vbasedev.name, 2361 ret ? "%m" : "Success"); 2362 2363 out: 2364 /* Re-enable INTx on affected devices */ 2365 for (i = 0; i < info->count; i++) { 2366 PCIHostDeviceAddress host; 2367 VFIOPCIDevice *tmp; 2368 VFIODevice *vbasedev_iter; 2369 2370 host.domain = devices[i].segment; 2371 host.bus = devices[i].bus; 2372 host.slot = PCI_SLOT(devices[i].devfn); 2373 host.function = PCI_FUNC(devices[i].devfn); 2374 2375 if (vfio_pci_host_match(&host, vdev->vbasedev.name)) { 2376 continue; 2377 } 2378 2379 QLIST_FOREACH(group, &vfio_group_list, next) { 2380 if (group->groupid == devices[i].group_id) { 2381 break; 2382 } 2383 } 2384 2385 if (!group) { 2386 break; 2387 } 2388 2389 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2390 if (!vbasedev_iter->dev->realized || 2391 vbasedev_iter->type != VFIO_DEVICE_TYPE_PCI) { 2392 continue; 2393 } 2394 tmp = container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); 2395 if (vfio_pci_host_match(&host, tmp->vbasedev.name)) { 2396 vfio_pci_post_reset(tmp); 2397 break; 2398 } 2399 } 2400 } 2401 out_single: 2402 if (!single) { 2403 vfio_pci_post_reset(vdev); 2404 } 2405 g_free(info); 2406 2407 return ret; 2408 } 2409 2410 /* 2411 * We want to differentiate hot reset of mulitple in-use devices vs hot reset 2412 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case 2413 * of doing hot resets when there is only a single device per bus. The in-use 2414 * here refers to how many VFIODevices are affected. A hot reset that affects 2415 * multiple devices, but only a single in-use device, means that we can call 2416 * it from our bus ->reset() callback since the extent is effectively a single 2417 * device. This allows us to make use of it in the hotplug path. When there 2418 * are multiple in-use devices, we can only trigger the hot reset during a 2419 * system reset and thus from our reset handler. We separate _one vs _multi 2420 * here so that we don't overlap and do a double reset on the system reset 2421 * path where both our reset handler and ->reset() callback are used. Calling 2422 * _one() will only do a hot reset for the one in-use devices case, calling 2423 * _multi() will do nothing if a _one() would have been sufficient. 2424 */ 2425 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev) 2426 { 2427 return vfio_pci_hot_reset(vdev, true); 2428 } 2429 2430 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev) 2431 { 2432 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2433 return vfio_pci_hot_reset(vdev, false); 2434 } 2435 2436 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev) 2437 { 2438 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev); 2439 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) { 2440 vbasedev->needs_reset = true; 2441 } 2442 } 2443 2444 static VFIODeviceOps vfio_pci_ops = { 2445 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset, 2446 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi, 2447 .vfio_eoi = vfio_intx_eoi, 2448 }; 2449 2450 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) 2451 { 2452 VFIODevice *vbasedev = &vdev->vbasedev; 2453 struct vfio_region_info *reg_info; 2454 int ret; 2455 2456 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info); 2457 if (ret) { 2458 error_setg_errno(errp, -ret, 2459 "failed getting region info for VGA region index %d", 2460 VFIO_PCI_VGA_REGION_INDEX); 2461 return ret; 2462 } 2463 2464 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) || 2465 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) || 2466 reg_info->size < 0xbffff + 1) { 2467 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx", 2468 (unsigned long)reg_info->flags, 2469 (unsigned long)reg_info->size); 2470 g_free(reg_info); 2471 return -EINVAL; 2472 } 2473 2474 vdev->vga = g_new0(VFIOVGA, 1); 2475 2476 vdev->vga->fd_offset = reg_info->offset; 2477 vdev->vga->fd = vdev->vbasedev.fd; 2478 2479 g_free(reg_info); 2480 2481 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE; 2482 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM; 2483 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks); 2484 2485 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2486 OBJECT(vdev), &vfio_vga_ops, 2487 &vdev->vga->region[QEMU_PCI_VGA_MEM], 2488 "vfio-vga-mmio@0xa0000", 2489 QEMU_PCI_VGA_MEM_SIZE); 2490 2491 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE; 2492 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO; 2493 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks); 2494 2495 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2496 OBJECT(vdev), &vfio_vga_ops, 2497 &vdev->vga->region[QEMU_PCI_VGA_IO_LO], 2498 "vfio-vga-io@0x3b0", 2499 QEMU_PCI_VGA_IO_LO_SIZE); 2500 2501 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE; 2502 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI; 2503 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks); 2504 2505 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, 2506 OBJECT(vdev), &vfio_vga_ops, 2507 &vdev->vga->region[QEMU_PCI_VGA_IO_HI], 2508 "vfio-vga-io@0x3c0", 2509 QEMU_PCI_VGA_IO_HI_SIZE); 2510 2511 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem, 2512 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem, 2513 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem); 2514 2515 return 0; 2516 } 2517 2518 static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp) 2519 { 2520 VFIODevice *vbasedev = &vdev->vbasedev; 2521 struct vfio_region_info *reg_info; 2522 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) }; 2523 int i, ret = -1; 2524 2525 /* Sanity check device */ 2526 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) { 2527 error_setg(errp, "this isn't a PCI device"); 2528 return; 2529 } 2530 2531 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) { 2532 error_setg(errp, "unexpected number of io regions %u", 2533 vbasedev->num_regions); 2534 return; 2535 } 2536 2537 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) { 2538 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs); 2539 return; 2540 } 2541 2542 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) { 2543 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i); 2544 2545 ret = vfio_region_setup(OBJECT(vdev), vbasedev, 2546 &vdev->bars[i].region, i, name); 2547 g_free(name); 2548 2549 if (ret) { 2550 error_setg_errno(errp, -ret, "failed to get region %d info", i); 2551 return; 2552 } 2553 2554 QLIST_INIT(&vdev->bars[i].quirks); 2555 } 2556 2557 ret = vfio_get_region_info(vbasedev, 2558 VFIO_PCI_CONFIG_REGION_INDEX, ®_info); 2559 if (ret) { 2560 error_setg_errno(errp, -ret, "failed to get config info"); 2561 return; 2562 } 2563 2564 trace_vfio_populate_device_config(vdev->vbasedev.name, 2565 (unsigned long)reg_info->size, 2566 (unsigned long)reg_info->offset, 2567 (unsigned long)reg_info->flags); 2568 2569 vdev->config_size = reg_info->size; 2570 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) { 2571 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS; 2572 } 2573 vdev->config_offset = reg_info->offset; 2574 2575 g_free(reg_info); 2576 2577 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) { 2578 ret = vfio_populate_vga(vdev, errp); 2579 if (ret) { 2580 error_append_hint(errp, "device does not support " 2581 "requested feature x-vga\n"); 2582 return; 2583 } 2584 } 2585 2586 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX; 2587 2588 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); 2589 if (ret) { 2590 /* This can fail for an old kernel or legacy PCI dev */ 2591 trace_vfio_populate_device_get_irq_info_failure(strerror(errno)); 2592 } else if (irq_info.count == 1) { 2593 vdev->pci_aer = true; 2594 } else { 2595 warn_report(VFIO_MSG_PREFIX 2596 "Could not enable error recovery for the device", 2597 vbasedev->name); 2598 } 2599 } 2600 2601 static void vfio_put_device(VFIOPCIDevice *vdev) 2602 { 2603 g_free(vdev->vbasedev.name); 2604 g_free(vdev->msix); 2605 2606 vfio_put_base_device(&vdev->vbasedev); 2607 } 2608 2609 static void vfio_err_notifier_handler(void *opaque) 2610 { 2611 VFIOPCIDevice *vdev = opaque; 2612 2613 if (!event_notifier_test_and_clear(&vdev->err_notifier)) { 2614 return; 2615 } 2616 2617 /* 2618 * TBD. Retrieve the error details and decide what action 2619 * needs to be taken. One of the actions could be to pass 2620 * the error to the guest and have the guest driver recover 2621 * from the error. This requires that PCIe capabilities be 2622 * exposed to the guest. For now, we just terminate the 2623 * guest to contain the error. 2624 */ 2625 2626 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name); 2627 2628 vm_stop(RUN_STATE_INTERNAL_ERROR); 2629 } 2630 2631 /* 2632 * Registers error notifier for devices supporting error recovery. 2633 * If we encounter a failure in this function, we report an error 2634 * and continue after disabling error recovery support for the 2635 * device. 2636 */ 2637 static void vfio_register_err_notifier(VFIOPCIDevice *vdev) 2638 { 2639 int ret; 2640 int argsz; 2641 struct vfio_irq_set *irq_set; 2642 int32_t *pfd; 2643 2644 if (!vdev->pci_aer) { 2645 return; 2646 } 2647 2648 if (event_notifier_init(&vdev->err_notifier, 0)) { 2649 error_report("vfio: Unable to init event notifier for error detection"); 2650 vdev->pci_aer = false; 2651 return; 2652 } 2653 2654 argsz = sizeof(*irq_set) + sizeof(*pfd); 2655 2656 irq_set = g_malloc0(argsz); 2657 irq_set->argsz = argsz; 2658 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2659 VFIO_IRQ_SET_ACTION_TRIGGER; 2660 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2661 irq_set->start = 0; 2662 irq_set->count = 1; 2663 pfd = (int32_t *)&irq_set->data; 2664 2665 *pfd = event_notifier_get_fd(&vdev->err_notifier); 2666 qemu_set_fd_handler(*pfd, vfio_err_notifier_handler, NULL, vdev); 2667 2668 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2669 if (ret) { 2670 error_report("vfio: Failed to set up error notification"); 2671 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2672 event_notifier_cleanup(&vdev->err_notifier); 2673 vdev->pci_aer = false; 2674 } 2675 g_free(irq_set); 2676 } 2677 2678 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev) 2679 { 2680 int argsz; 2681 struct vfio_irq_set *irq_set; 2682 int32_t *pfd; 2683 int ret; 2684 2685 if (!vdev->pci_aer) { 2686 return; 2687 } 2688 2689 argsz = sizeof(*irq_set) + sizeof(*pfd); 2690 2691 irq_set = g_malloc0(argsz); 2692 irq_set->argsz = argsz; 2693 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2694 VFIO_IRQ_SET_ACTION_TRIGGER; 2695 irq_set->index = VFIO_PCI_ERR_IRQ_INDEX; 2696 irq_set->start = 0; 2697 irq_set->count = 1; 2698 pfd = (int32_t *)&irq_set->data; 2699 *pfd = -1; 2700 2701 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set); 2702 if (ret) { 2703 error_report("vfio: Failed to de-assign error fd: %m"); 2704 } 2705 g_free(irq_set); 2706 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier), 2707 NULL, NULL, vdev); 2708 event_notifier_cleanup(&vdev->err_notifier); 2709 } 2710 2711 static void vfio_req_notifier_handler(void *opaque) 2712 { 2713 VFIOPCIDevice *vdev = opaque; 2714 Error *err = NULL; 2715 2716 if (!event_notifier_test_and_clear(&vdev->req_notifier)) { 2717 return; 2718 } 2719 2720 qdev_unplug(&vdev->pdev.qdev, &err); 2721 if (err) { 2722 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name); 2723 } 2724 } 2725 2726 static void vfio_register_req_notifier(VFIOPCIDevice *vdev) 2727 { 2728 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info), 2729 .index = VFIO_PCI_REQ_IRQ_INDEX }; 2730 int argsz; 2731 struct vfio_irq_set *irq_set; 2732 int32_t *pfd; 2733 2734 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) { 2735 return; 2736 } 2737 2738 if (ioctl(vdev->vbasedev.fd, 2739 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) { 2740 return; 2741 } 2742 2743 if (event_notifier_init(&vdev->req_notifier, 0)) { 2744 error_report("vfio: Unable to init event notifier for device request"); 2745 return; 2746 } 2747 2748 argsz = sizeof(*irq_set) + sizeof(*pfd); 2749 2750 irq_set = g_malloc0(argsz); 2751 irq_set->argsz = argsz; 2752 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2753 VFIO_IRQ_SET_ACTION_TRIGGER; 2754 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2755 irq_set->start = 0; 2756 irq_set->count = 1; 2757 pfd = (int32_t *)&irq_set->data; 2758 2759 *pfd = event_notifier_get_fd(&vdev->req_notifier); 2760 qemu_set_fd_handler(*pfd, vfio_req_notifier_handler, NULL, vdev); 2761 2762 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2763 error_report("vfio: Failed to set up device request notification"); 2764 qemu_set_fd_handler(*pfd, NULL, NULL, vdev); 2765 event_notifier_cleanup(&vdev->req_notifier); 2766 } else { 2767 vdev->req_enabled = true; 2768 } 2769 2770 g_free(irq_set); 2771 } 2772 2773 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev) 2774 { 2775 int argsz; 2776 struct vfio_irq_set *irq_set; 2777 int32_t *pfd; 2778 2779 if (!vdev->req_enabled) { 2780 return; 2781 } 2782 2783 argsz = sizeof(*irq_set) + sizeof(*pfd); 2784 2785 irq_set = g_malloc0(argsz); 2786 irq_set->argsz = argsz; 2787 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | 2788 VFIO_IRQ_SET_ACTION_TRIGGER; 2789 irq_set->index = VFIO_PCI_REQ_IRQ_INDEX; 2790 irq_set->start = 0; 2791 irq_set->count = 1; 2792 pfd = (int32_t *)&irq_set->data; 2793 *pfd = -1; 2794 2795 if (ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set)) { 2796 error_report("vfio: Failed to de-assign device request fd: %m"); 2797 } 2798 g_free(irq_set); 2799 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier), 2800 NULL, NULL, vdev); 2801 event_notifier_cleanup(&vdev->req_notifier); 2802 2803 vdev->req_enabled = false; 2804 } 2805 2806 static void vfio_realize(PCIDevice *pdev, Error **errp) 2807 { 2808 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 2809 VFIODevice *vbasedev_iter; 2810 VFIOGroup *group; 2811 char *tmp, *subsys, group_path[PATH_MAX], *group_name; 2812 Error *err = NULL; 2813 ssize_t len; 2814 struct stat st; 2815 int groupid; 2816 int i, ret; 2817 bool is_mdev; 2818 2819 if (!vdev->vbasedev.sysfsdev) { 2820 if (!(~vdev->host.domain || ~vdev->host.bus || 2821 ~vdev->host.slot || ~vdev->host.function)) { 2822 error_setg(errp, "No provided host device"); 2823 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F " 2824 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n"); 2825 return; 2826 } 2827 vdev->vbasedev.sysfsdev = 2828 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x", 2829 vdev->host.domain, vdev->host.bus, 2830 vdev->host.slot, vdev->host.function); 2831 } 2832 2833 if (stat(vdev->vbasedev.sysfsdev, &st) < 0) { 2834 error_setg_errno(errp, errno, "no such host device"); 2835 error_prepend(errp, VFIO_MSG_PREFIX, vdev->vbasedev.sysfsdev); 2836 return; 2837 } 2838 2839 vdev->vbasedev.name = g_path_get_basename(vdev->vbasedev.sysfsdev); 2840 vdev->vbasedev.ops = &vfio_pci_ops; 2841 vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI; 2842 vdev->vbasedev.dev = &vdev->pdev.qdev; 2843 2844 tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev); 2845 len = readlink(tmp, group_path, sizeof(group_path)); 2846 g_free(tmp); 2847 2848 if (len <= 0 || len >= sizeof(group_path)) { 2849 error_setg_errno(errp, len < 0 ? errno : ENAMETOOLONG, 2850 "no iommu_group found"); 2851 goto error; 2852 } 2853 2854 group_path[len] = 0; 2855 2856 group_name = basename(group_path); 2857 if (sscanf(group_name, "%d", &groupid) != 1) { 2858 error_setg_errno(errp, errno, "failed to read %s", group_path); 2859 goto error; 2860 } 2861 2862 trace_vfio_realize(vdev->vbasedev.name, groupid); 2863 2864 group = vfio_get_group(groupid, pci_device_iommu_address_space(pdev), errp); 2865 if (!group) { 2866 goto error; 2867 } 2868 2869 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { 2870 if (strcmp(vbasedev_iter->name, vdev->vbasedev.name) == 0) { 2871 error_setg(errp, "device is already attached"); 2872 vfio_put_group(group); 2873 goto error; 2874 } 2875 } 2876 2877 /* 2878 * Mediated devices *might* operate compatibly with memory ballooning, but 2879 * we cannot know for certain, it depends on whether the mdev vendor driver 2880 * stays in sync with the active working set of the guest driver. Prevent 2881 * the x-balloon-allowed option unless this is minimally an mdev device. 2882 */ 2883 tmp = g_strdup_printf("%s/subsystem", vdev->vbasedev.sysfsdev); 2884 subsys = realpath(tmp, NULL); 2885 g_free(tmp); 2886 is_mdev = subsys && (strcmp(subsys, "/sys/bus/mdev") == 0); 2887 free(subsys); 2888 2889 trace_vfio_mdev(vdev->vbasedev.name, is_mdev); 2890 2891 if (vdev->vbasedev.balloon_allowed && !is_mdev) { 2892 error_setg(errp, "x-balloon-allowed only potentially compatible " 2893 "with mdev devices"); 2894 vfio_put_group(group); 2895 goto error; 2896 } 2897 2898 ret = vfio_get_device(group, vdev->vbasedev.name, &vdev->vbasedev, errp); 2899 if (ret) { 2900 vfio_put_group(group); 2901 goto error; 2902 } 2903 2904 vfio_populate_device(vdev, &err); 2905 if (err) { 2906 error_propagate(errp, err); 2907 goto error; 2908 } 2909 2910 /* Get a copy of config space */ 2911 ret = pread(vdev->vbasedev.fd, vdev->pdev.config, 2912 MIN(pci_config_size(&vdev->pdev), vdev->config_size), 2913 vdev->config_offset); 2914 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) { 2915 ret = ret < 0 ? -errno : -EFAULT; 2916 error_setg_errno(errp, -ret, "failed to read device config space"); 2917 goto error; 2918 } 2919 2920 /* vfio emulates a lot for us, but some bits need extra love */ 2921 vdev->emulated_config_bits = g_malloc0(vdev->config_size); 2922 2923 /* QEMU can choose to expose the ROM or not */ 2924 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4); 2925 /* QEMU can also add or extend BARs */ 2926 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4); 2927 2928 /* 2929 * The PCI spec reserves vendor ID 0xffff as an invalid value. The 2930 * device ID is managed by the vendor and need only be a 16-bit value. 2931 * Allow any 16-bit value for subsystem so they can be hidden or changed. 2932 */ 2933 if (vdev->vendor_id != PCI_ANY_ID) { 2934 if (vdev->vendor_id >= 0xffff) { 2935 error_setg(errp, "invalid PCI vendor ID provided"); 2936 goto error; 2937 } 2938 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0); 2939 trace_vfio_pci_emulated_vendor_id(vdev->vbasedev.name, vdev->vendor_id); 2940 } else { 2941 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2942 } 2943 2944 if (vdev->device_id != PCI_ANY_ID) { 2945 if (vdev->device_id > 0xffff) { 2946 error_setg(errp, "invalid PCI device ID provided"); 2947 goto error; 2948 } 2949 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0); 2950 trace_vfio_pci_emulated_device_id(vdev->vbasedev.name, vdev->device_id); 2951 } else { 2952 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2953 } 2954 2955 if (vdev->sub_vendor_id != PCI_ANY_ID) { 2956 if (vdev->sub_vendor_id > 0xffff) { 2957 error_setg(errp, "invalid PCI subsystem vendor ID provided"); 2958 goto error; 2959 } 2960 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID, 2961 vdev->sub_vendor_id, ~0); 2962 trace_vfio_pci_emulated_sub_vendor_id(vdev->vbasedev.name, 2963 vdev->sub_vendor_id); 2964 } 2965 2966 if (vdev->sub_device_id != PCI_ANY_ID) { 2967 if (vdev->sub_device_id > 0xffff) { 2968 error_setg(errp, "invalid PCI subsystem device ID provided"); 2969 goto error; 2970 } 2971 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0); 2972 trace_vfio_pci_emulated_sub_device_id(vdev->vbasedev.name, 2973 vdev->sub_device_id); 2974 } 2975 2976 /* QEMU can change multi-function devices to single function, or reverse */ 2977 vdev->emulated_config_bits[PCI_HEADER_TYPE] = 2978 PCI_HEADER_TYPE_MULTI_FUNCTION; 2979 2980 /* Restore or clear multifunction, this is always controlled by QEMU */ 2981 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 2982 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 2983 } else { 2984 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; 2985 } 2986 2987 /* 2988 * Clear host resource mapping info. If we choose not to register a 2989 * BAR, such as might be the case with the option ROM, we can get 2990 * confusing, unwritable, residual addresses from the host here. 2991 */ 2992 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24); 2993 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4); 2994 2995 vfio_pci_size_rom(vdev); 2996 2997 vfio_bars_prepare(vdev); 2998 2999 vfio_msix_early_setup(vdev, &err); 3000 if (err) { 3001 error_propagate(errp, err); 3002 goto error; 3003 } 3004 3005 vfio_bars_register(vdev); 3006 3007 ret = vfio_add_capabilities(vdev, errp); 3008 if (ret) { 3009 goto out_teardown; 3010 } 3011 3012 if (vdev->vga) { 3013 vfio_vga_quirk_setup(vdev); 3014 } 3015 3016 for (i = 0; i < PCI_ROM_SLOT; i++) { 3017 vfio_bar_quirk_setup(vdev, i); 3018 } 3019 3020 if (!vdev->igd_opregion && 3021 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) { 3022 struct vfio_region_info *opregion; 3023 3024 if (vdev->pdev.qdev.hotplugged) { 3025 error_setg(errp, 3026 "cannot support IGD OpRegion feature on hotplugged " 3027 "device"); 3028 goto out_teardown; 3029 } 3030 3031 ret = vfio_get_dev_region_info(&vdev->vbasedev, 3032 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL, 3033 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion); 3034 if (ret) { 3035 error_setg_errno(errp, -ret, 3036 "does not support requested IGD OpRegion feature"); 3037 goto out_teardown; 3038 } 3039 3040 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp); 3041 g_free(opregion); 3042 if (ret) { 3043 goto out_teardown; 3044 } 3045 } 3046 3047 /* QEMU emulates all of MSI & MSIX */ 3048 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) { 3049 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff, 3050 MSIX_CAP_LENGTH); 3051 } 3052 3053 if (pdev->cap_present & QEMU_PCI_CAP_MSI) { 3054 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff, 3055 vdev->msi_cap_size); 3056 } 3057 3058 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) { 3059 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, 3060 vfio_intx_mmap_enable, vdev); 3061 pci_device_set_intx_routing_notifier(&vdev->pdev, vfio_intx_update); 3062 ret = vfio_intx_enable(vdev, errp); 3063 if (ret) { 3064 goto out_teardown; 3065 } 3066 } 3067 3068 if (vdev->display != ON_OFF_AUTO_OFF) { 3069 ret = vfio_display_probe(vdev, errp); 3070 if (ret) { 3071 goto out_teardown; 3072 } 3073 } 3074 if (vdev->enable_ramfb && vdev->dpy == NULL) { 3075 error_setg(errp, "ramfb=on requires display=on"); 3076 goto out_teardown; 3077 } 3078 if (vdev->display_xres || vdev->display_yres) { 3079 if (vdev->dpy == NULL) { 3080 error_setg(errp, "xres and yres properties require display=on"); 3081 goto out_teardown; 3082 } 3083 if (vdev->dpy->edid_regs == NULL) { 3084 error_setg(errp, "xres and yres properties need edid support"); 3085 goto out_teardown; 3086 } 3087 } 3088 3089 if (vdev->vendor_id == PCI_VENDOR_ID_NVIDIA) { 3090 ret = vfio_pci_nvidia_v100_ram_init(vdev, errp); 3091 if (ret && ret != -ENODEV) { 3092 error_report("Failed to setup NVIDIA V100 GPU RAM"); 3093 } 3094 } 3095 3096 if (vdev->vendor_id == PCI_VENDOR_ID_IBM) { 3097 ret = vfio_pci_nvlink2_init(vdev, errp); 3098 if (ret && ret != -ENODEV) { 3099 error_report("Failed to setup NVlink2 bridge"); 3100 } 3101 } 3102 3103 vfio_register_err_notifier(vdev); 3104 vfio_register_req_notifier(vdev); 3105 vfio_setup_resetfn_quirk(vdev); 3106 3107 return; 3108 3109 out_teardown: 3110 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 3111 vfio_teardown_msi(vdev); 3112 vfio_bars_exit(vdev); 3113 error: 3114 error_prepend(errp, VFIO_MSG_PREFIX, vdev->vbasedev.name); 3115 } 3116 3117 static void vfio_instance_finalize(Object *obj) 3118 { 3119 VFIOPCIDevice *vdev = PCI_VFIO(obj); 3120 VFIOGroup *group = vdev->vbasedev.group; 3121 3122 vfio_display_finalize(vdev); 3123 vfio_bars_finalize(vdev); 3124 g_free(vdev->emulated_config_bits); 3125 g_free(vdev->rom); 3126 /* 3127 * XXX Leaking igd_opregion is not an oversight, we can't remove the 3128 * fw_cfg entry therefore leaking this allocation seems like the safest 3129 * option. 3130 * 3131 * g_free(vdev->igd_opregion); 3132 */ 3133 vfio_put_device(vdev); 3134 vfio_put_group(group); 3135 } 3136 3137 static void vfio_exitfn(PCIDevice *pdev) 3138 { 3139 VFIOPCIDevice *vdev = PCI_VFIO(pdev); 3140 3141 vfio_unregister_req_notifier(vdev); 3142 vfio_unregister_err_notifier(vdev); 3143 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL); 3144 vfio_disable_interrupts(vdev); 3145 if (vdev->intx.mmap_timer) { 3146 timer_free(vdev->intx.mmap_timer); 3147 } 3148 vfio_teardown_msi(vdev); 3149 vfio_bars_exit(vdev); 3150 } 3151 3152 static void vfio_pci_reset(DeviceState *dev) 3153 { 3154 VFIOPCIDevice *vdev = PCI_VFIO(dev); 3155 3156 trace_vfio_pci_reset(vdev->vbasedev.name); 3157 3158 vfio_pci_pre_reset(vdev); 3159 3160 if (vdev->display != ON_OFF_AUTO_OFF) { 3161 vfio_display_reset(vdev); 3162 } 3163 3164 if (vdev->resetfn && !vdev->resetfn(vdev)) { 3165 goto post_reset; 3166 } 3167 3168 if (vdev->vbasedev.reset_works && 3169 (vdev->has_flr || !vdev->has_pm_reset) && 3170 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 3171 trace_vfio_pci_reset_flr(vdev->vbasedev.name); 3172 goto post_reset; 3173 } 3174 3175 /* See if we can do our own bus reset */ 3176 if (!vfio_pci_hot_reset_one(vdev)) { 3177 goto post_reset; 3178 } 3179 3180 /* If nothing else works and the device supports PM reset, use it */ 3181 if (vdev->vbasedev.reset_works && vdev->has_pm_reset && 3182 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) { 3183 trace_vfio_pci_reset_pm(vdev->vbasedev.name); 3184 goto post_reset; 3185 } 3186 3187 post_reset: 3188 vfio_pci_post_reset(vdev); 3189 } 3190 3191 static void vfio_instance_init(Object *obj) 3192 { 3193 PCIDevice *pci_dev = PCI_DEVICE(obj); 3194 VFIOPCIDevice *vdev = PCI_VFIO(obj); 3195 3196 device_add_bootindex_property(obj, &vdev->bootindex, 3197 "bootindex", NULL, 3198 &pci_dev->qdev, NULL); 3199 vdev->host.domain = ~0U; 3200 vdev->host.bus = ~0U; 3201 vdev->host.slot = ~0U; 3202 vdev->host.function = ~0U; 3203 3204 vdev->nv_gpudirect_clique = 0xFF; 3205 3206 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 3207 * line, therefore, no need to wait to realize like other devices */ 3208 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 3209 } 3210 3211 static Property vfio_pci_dev_properties[] = { 3212 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host), 3213 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev), 3214 DEFINE_PROP_ON_OFF_AUTO("display", VFIOPCIDevice, 3215 display, ON_OFF_AUTO_OFF), 3216 DEFINE_PROP_UINT32("xres", VFIOPCIDevice, display_xres, 0), 3217 DEFINE_PROP_UINT32("yres", VFIOPCIDevice, display_yres, 0), 3218 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice, 3219 intx.mmap_timeout, 1100), 3220 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features, 3221 VFIO_FEATURE_ENABLE_VGA_BIT, false), 3222 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features, 3223 VFIO_FEATURE_ENABLE_REQ_BIT, true), 3224 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features, 3225 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false), 3226 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false), 3227 DEFINE_PROP_BOOL("x-balloon-allowed", VFIOPCIDevice, 3228 vbasedev.balloon_allowed, false), 3229 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false), 3230 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false), 3231 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false), 3232 DEFINE_PROP_BOOL("x-no-geforce-quirks", VFIOPCIDevice, 3233 no_geforce_quirks, false), 3234 DEFINE_PROP_BOOL("x-no-kvm-ioeventfd", VFIOPCIDevice, no_kvm_ioeventfd, 3235 false), 3236 DEFINE_PROP_BOOL("x-no-vfio-ioeventfd", VFIOPCIDevice, no_vfio_ioeventfd, 3237 false), 3238 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID), 3239 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID), 3240 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice, 3241 sub_vendor_id, PCI_ANY_ID), 3242 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice, 3243 sub_device_id, PCI_ANY_ID), 3244 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0), 3245 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice, 3246 nv_gpudirect_clique, 3247 qdev_prop_nv_gpudirect_clique, uint8_t), 3248 DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_relo, 3249 OFF_AUTOPCIBAR_OFF), 3250 /* 3251 * TODO - support passed fds... is this necessary? 3252 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name), 3253 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name), 3254 */ 3255 DEFINE_PROP_END_OF_LIST(), 3256 }; 3257 3258 static const VMStateDescription vfio_pci_vmstate = { 3259 .name = "vfio-pci", 3260 .unmigratable = 1, 3261 }; 3262 3263 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data) 3264 { 3265 DeviceClass *dc = DEVICE_CLASS(klass); 3266 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass); 3267 3268 dc->reset = vfio_pci_reset; 3269 dc->props = vfio_pci_dev_properties; 3270 dc->vmsd = &vfio_pci_vmstate; 3271 dc->desc = "VFIO-based PCI device assignment"; 3272 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 3273 pdc->realize = vfio_realize; 3274 pdc->exit = vfio_exitfn; 3275 pdc->config_read = vfio_pci_read_config; 3276 pdc->config_write = vfio_pci_write_config; 3277 } 3278 3279 static const TypeInfo vfio_pci_dev_info = { 3280 .name = TYPE_VFIO_PCI, 3281 .parent = TYPE_PCI_DEVICE, 3282 .instance_size = sizeof(VFIOPCIDevice), 3283 .class_init = vfio_pci_dev_class_init, 3284 .instance_init = vfio_instance_init, 3285 .instance_finalize = vfio_instance_finalize, 3286 .interfaces = (InterfaceInfo[]) { 3287 { INTERFACE_PCIE_DEVICE }, 3288 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 3289 { } 3290 }, 3291 }; 3292 3293 static Property vfio_pci_dev_nohotplug_properties[] = { 3294 DEFINE_PROP_BOOL("ramfb", VFIOPCIDevice, enable_ramfb, false), 3295 DEFINE_PROP_END_OF_LIST(), 3296 }; 3297 3298 static void vfio_pci_nohotplug_dev_class_init(ObjectClass *klass, void *data) 3299 { 3300 DeviceClass *dc = DEVICE_CLASS(klass); 3301 3302 dc->props = vfio_pci_dev_nohotplug_properties; 3303 dc->hotpluggable = false; 3304 } 3305 3306 static const TypeInfo vfio_pci_nohotplug_dev_info = { 3307 .name = "vfio-pci-nohotplug", 3308 .parent = "vfio-pci", 3309 .instance_size = sizeof(VFIOPCIDevice), 3310 .class_init = vfio_pci_nohotplug_dev_class_init, 3311 }; 3312 3313 static void register_vfio_pci_dev_type(void) 3314 { 3315 type_register_static(&vfio_pci_dev_info); 3316 type_register_static(&vfio_pci_nohotplug_dev_info); 3317 } 3318 3319 type_init(register_vfio_pci_dev_type) 3320