1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef HW_USB_HCD_XHCI_H 23 #define HW_USB_HCD_XHCI_H 24 25 #define TYPE_XHCI "base-xhci" 26 #define TYPE_NEC_XHCI "nec-usb-xhci" 27 #define TYPE_QEMU_XHCI "qemu-xhci" 28 29 #define XHCI(obj) \ 30 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 31 32 #define MAXPORTS_2 15 33 #define MAXPORTS_3 15 34 35 #define MAXPORTS (MAXPORTS_2 + MAXPORTS_3) 36 #define MAXSLOTS 64 37 #define MAXINTRS 16 38 39 /* Very pessimistic, let's hope it's enough for all cases */ 40 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 41 42 typedef struct XHCIState XHCIState; 43 typedef struct XHCIStreamContext XHCIStreamContext; 44 typedef struct XHCIEPContext XHCIEPContext; 45 46 enum xhci_flags { 47 XHCI_FLAG_SS_FIRST = 1, 48 XHCI_FLAG_FORCE_PCIE_ENDCAP, 49 XHCI_FLAG_ENABLE_STREAMS, 50 }; 51 52 typedef enum TRBType { 53 TRB_RESERVED = 0, 54 TR_NORMAL, 55 TR_SETUP, 56 TR_DATA, 57 TR_STATUS, 58 TR_ISOCH, 59 TR_LINK, 60 TR_EVDATA, 61 TR_NOOP, 62 CR_ENABLE_SLOT, 63 CR_DISABLE_SLOT, 64 CR_ADDRESS_DEVICE, 65 CR_CONFIGURE_ENDPOINT, 66 CR_EVALUATE_CONTEXT, 67 CR_RESET_ENDPOINT, 68 CR_STOP_ENDPOINT, 69 CR_SET_TR_DEQUEUE, 70 CR_RESET_DEVICE, 71 CR_FORCE_EVENT, 72 CR_NEGOTIATE_BW, 73 CR_SET_LATENCY_TOLERANCE, 74 CR_GET_PORT_BANDWIDTH, 75 CR_FORCE_HEADER, 76 CR_NOOP, 77 ER_TRANSFER = 32, 78 ER_COMMAND_COMPLETE, 79 ER_PORT_STATUS_CHANGE, 80 ER_BANDWIDTH_REQUEST, 81 ER_DOORBELL, 82 ER_HOST_CONTROLLER, 83 ER_DEVICE_NOTIFICATION, 84 ER_MFINDEX_WRAP, 85 /* vendor specific bits */ 86 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 87 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 88 } TRBType; 89 90 typedef enum TRBCCode { 91 CC_INVALID = 0, 92 CC_SUCCESS, 93 CC_DATA_BUFFER_ERROR, 94 CC_BABBLE_DETECTED, 95 CC_USB_TRANSACTION_ERROR, 96 CC_TRB_ERROR, 97 CC_STALL_ERROR, 98 CC_RESOURCE_ERROR, 99 CC_BANDWIDTH_ERROR, 100 CC_NO_SLOTS_ERROR, 101 CC_INVALID_STREAM_TYPE_ERROR, 102 CC_SLOT_NOT_ENABLED_ERROR, 103 CC_EP_NOT_ENABLED_ERROR, 104 CC_SHORT_PACKET, 105 CC_RING_UNDERRUN, 106 CC_RING_OVERRUN, 107 CC_VF_ER_FULL, 108 CC_PARAMETER_ERROR, 109 CC_BANDWIDTH_OVERRUN, 110 CC_CONTEXT_STATE_ERROR, 111 CC_NO_PING_RESPONSE_ERROR, 112 CC_EVENT_RING_FULL_ERROR, 113 CC_INCOMPATIBLE_DEVICE_ERROR, 114 CC_MISSED_SERVICE_ERROR, 115 CC_COMMAND_RING_STOPPED, 116 CC_COMMAND_ABORTED, 117 CC_STOPPED, 118 CC_STOPPED_LENGTH_INVALID, 119 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 120 CC_ISOCH_BUFFER_OVERRUN = 31, 121 CC_EVENT_LOST_ERROR, 122 CC_UNDEFINED_ERROR, 123 CC_INVALID_STREAM_ID_ERROR, 124 CC_SECONDARY_BANDWIDTH_ERROR, 125 CC_SPLIT_TRANSACTION_ERROR 126 } TRBCCode; 127 128 typedef struct XHCIRing { 129 dma_addr_t dequeue; 130 bool ccs; 131 } XHCIRing; 132 133 typedef struct XHCIPort { 134 XHCIState *xhci; 135 uint32_t portsc; 136 uint32_t portnr; 137 USBPort *uport; 138 uint32_t speedmask; 139 char name[16]; 140 MemoryRegion mem; 141 } XHCIPort; 142 143 typedef struct XHCISlot { 144 bool enabled; 145 bool addressed; 146 uint16_t intr; 147 dma_addr_t ctx; 148 USBPort *uport; 149 XHCIEPContext *eps[31]; 150 } XHCISlot; 151 152 typedef struct XHCIEvent { 153 TRBType type; 154 TRBCCode ccode; 155 uint64_t ptr; 156 uint32_t length; 157 uint32_t flags; 158 uint8_t slotid; 159 uint8_t epid; 160 } XHCIEvent; 161 162 typedef struct XHCIInterrupter { 163 uint32_t iman; 164 uint32_t imod; 165 uint32_t erstsz; 166 uint32_t erstba_low; 167 uint32_t erstba_high; 168 uint32_t erdp_low; 169 uint32_t erdp_high; 170 171 bool msix_used, er_pcs; 172 173 dma_addr_t er_start; 174 uint32_t er_size; 175 unsigned int er_ep_idx; 176 177 /* kept for live migration compat only */ 178 bool er_full_unused; 179 XHCIEvent ev_buffer[EV_QUEUE]; 180 unsigned int ev_buffer_put; 181 unsigned int ev_buffer_get; 182 183 } XHCIInterrupter; 184 185 struct XHCIState { 186 /*< private >*/ 187 PCIDevice parent_obj; 188 /*< public >*/ 189 190 USBBus bus; 191 MemoryRegion mem; 192 MemoryRegion mem_cap; 193 MemoryRegion mem_oper; 194 MemoryRegion mem_runtime; 195 MemoryRegion mem_doorbell; 196 197 /* properties */ 198 uint32_t numports_2; 199 uint32_t numports_3; 200 uint32_t numintrs; 201 uint32_t numslots; 202 uint32_t flags; 203 uint32_t max_pstreams_mask; 204 OnOffAuto msi; 205 OnOffAuto msix; 206 207 /* Operational Registers */ 208 uint32_t usbcmd; 209 uint32_t usbsts; 210 uint32_t dnctrl; 211 uint32_t crcr_low; 212 uint32_t crcr_high; 213 uint32_t dcbaap_low; 214 uint32_t dcbaap_high; 215 uint32_t config; 216 217 USBPort uports[MAX_CONST(MAXPORTS_2, MAXPORTS_3)]; 218 XHCIPort ports[MAXPORTS]; 219 XHCISlot slots[MAXSLOTS]; 220 uint32_t numports; 221 222 /* Runtime Registers */ 223 int64_t mfindex_start; 224 QEMUTimer *mfwrap_timer; 225 XHCIInterrupter intr[MAXINTRS]; 226 227 XHCIRing cmd_ring; 228 229 bool nec_quirks; 230 }; 231 232 #endif 233