1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef HW_USB_HCD_XHCI_H 23 #define HW_USB_HCD_XHCI_H 24 #include "qom/object.h" 25 26 #include "hw/usb.h" 27 #include "sysemu/dma.h" 28 29 #define TYPE_XHCI "base-xhci" 30 #define TYPE_NEC_XHCI "nec-usb-xhci" 31 #define TYPE_QEMU_XHCI "qemu-xhci" 32 33 OBJECT_DECLARE_SIMPLE_TYPE(XHCIState, XHCI) 34 35 #define MAXPORTS_2 15 36 #define MAXPORTS_3 15 37 38 #define MAXPORTS (MAXPORTS_2 + MAXPORTS_3) 39 #define MAXSLOTS 64 40 #define MAXINTRS 16 41 42 /* Very pessimistic, let's hope it's enough for all cases */ 43 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 44 45 typedef struct XHCIStreamContext XHCIStreamContext; 46 typedef struct XHCIEPContext XHCIEPContext; 47 48 enum xhci_flags { 49 XHCI_FLAG_SS_FIRST = 1, 50 XHCI_FLAG_FORCE_PCIE_ENDCAP, 51 XHCI_FLAG_ENABLE_STREAMS, 52 }; 53 54 typedef enum TRBType { 55 TRB_RESERVED = 0, 56 TR_NORMAL, 57 TR_SETUP, 58 TR_DATA, 59 TR_STATUS, 60 TR_ISOCH, 61 TR_LINK, 62 TR_EVDATA, 63 TR_NOOP, 64 CR_ENABLE_SLOT, 65 CR_DISABLE_SLOT, 66 CR_ADDRESS_DEVICE, 67 CR_CONFIGURE_ENDPOINT, 68 CR_EVALUATE_CONTEXT, 69 CR_RESET_ENDPOINT, 70 CR_STOP_ENDPOINT, 71 CR_SET_TR_DEQUEUE, 72 CR_RESET_DEVICE, 73 CR_FORCE_EVENT, 74 CR_NEGOTIATE_BW, 75 CR_SET_LATENCY_TOLERANCE, 76 CR_GET_PORT_BANDWIDTH, 77 CR_FORCE_HEADER, 78 CR_NOOP, 79 ER_TRANSFER = 32, 80 ER_COMMAND_COMPLETE, 81 ER_PORT_STATUS_CHANGE, 82 ER_BANDWIDTH_REQUEST, 83 ER_DOORBELL, 84 ER_HOST_CONTROLLER, 85 ER_DEVICE_NOTIFICATION, 86 ER_MFINDEX_WRAP, 87 /* vendor specific bits */ 88 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 89 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 90 } TRBType; 91 92 typedef enum TRBCCode { 93 CC_INVALID = 0, 94 CC_SUCCESS, 95 CC_DATA_BUFFER_ERROR, 96 CC_BABBLE_DETECTED, 97 CC_USB_TRANSACTION_ERROR, 98 CC_TRB_ERROR, 99 CC_STALL_ERROR, 100 CC_RESOURCE_ERROR, 101 CC_BANDWIDTH_ERROR, 102 CC_NO_SLOTS_ERROR, 103 CC_INVALID_STREAM_TYPE_ERROR, 104 CC_SLOT_NOT_ENABLED_ERROR, 105 CC_EP_NOT_ENABLED_ERROR, 106 CC_SHORT_PACKET, 107 CC_RING_UNDERRUN, 108 CC_RING_OVERRUN, 109 CC_VF_ER_FULL, 110 CC_PARAMETER_ERROR, 111 CC_BANDWIDTH_OVERRUN, 112 CC_CONTEXT_STATE_ERROR, 113 CC_NO_PING_RESPONSE_ERROR, 114 CC_EVENT_RING_FULL_ERROR, 115 CC_INCOMPATIBLE_DEVICE_ERROR, 116 CC_MISSED_SERVICE_ERROR, 117 CC_COMMAND_RING_STOPPED, 118 CC_COMMAND_ABORTED, 119 CC_STOPPED, 120 CC_STOPPED_LENGTH_INVALID, 121 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 122 CC_ISOCH_BUFFER_OVERRUN = 31, 123 CC_EVENT_LOST_ERROR, 124 CC_UNDEFINED_ERROR, 125 CC_INVALID_STREAM_ID_ERROR, 126 CC_SECONDARY_BANDWIDTH_ERROR, 127 CC_SPLIT_TRANSACTION_ERROR 128 } TRBCCode; 129 130 typedef struct XHCIRing { 131 dma_addr_t dequeue; 132 bool ccs; 133 } XHCIRing; 134 135 typedef struct XHCIPort { 136 XHCIState *xhci; 137 uint32_t portsc; 138 uint32_t portnr; 139 USBPort *uport; 140 uint32_t speedmask; 141 char name[16]; 142 MemoryRegion mem; 143 } XHCIPort; 144 145 typedef struct XHCISlot { 146 bool enabled; 147 bool addressed; 148 uint16_t intr; 149 dma_addr_t ctx; 150 USBPort *uport; 151 XHCIEPContext *eps[31]; 152 } XHCISlot; 153 154 typedef struct XHCIEvent { 155 TRBType type; 156 TRBCCode ccode; 157 uint64_t ptr; 158 uint32_t length; 159 uint32_t flags; 160 uint8_t slotid; 161 uint8_t epid; 162 } XHCIEvent; 163 164 typedef struct XHCIInterrupter { 165 uint32_t iman; 166 uint32_t imod; 167 uint32_t erstsz; 168 uint32_t erstba_low; 169 uint32_t erstba_high; 170 uint32_t erdp_low; 171 uint32_t erdp_high; 172 173 bool msix_used, er_pcs; 174 175 dma_addr_t er_start; 176 uint32_t er_size; 177 unsigned int er_ep_idx; 178 179 /* kept for live migration compat only */ 180 bool er_full_unused; 181 XHCIEvent ev_buffer[EV_QUEUE]; 182 unsigned int ev_buffer_put; 183 unsigned int ev_buffer_get; 184 185 } XHCIInterrupter; 186 187 typedef struct XHCIState { 188 DeviceState parent; 189 190 USBBus bus; 191 MemoryRegion mem; 192 MemoryRegion *dma_mr; 193 AddressSpace *as; 194 MemoryRegion mem_cap; 195 MemoryRegion mem_oper; 196 MemoryRegion mem_runtime; 197 MemoryRegion mem_doorbell; 198 199 /* properties */ 200 uint32_t numports_2; 201 uint32_t numports_3; 202 uint32_t numintrs; 203 uint32_t numslots; 204 uint32_t flags; 205 uint32_t max_pstreams_mask; 206 void (*intr_update)(XHCIState *s, int n, bool enable); 207 void (*intr_raise)(XHCIState *s, int n, bool level); 208 DeviceState *hostOpaque; 209 210 /* Operational Registers */ 211 uint32_t usbcmd; 212 uint32_t usbsts; 213 uint32_t dnctrl; 214 uint32_t crcr_low; 215 uint32_t crcr_high; 216 uint32_t dcbaap_low; 217 uint32_t dcbaap_high; 218 uint32_t config; 219 220 USBPort uports[MAX_CONST(MAXPORTS_2, MAXPORTS_3)]; 221 XHCIPort ports[MAXPORTS]; 222 XHCISlot slots[MAXSLOTS]; 223 uint32_t numports; 224 225 /* Runtime Registers */ 226 int64_t mfindex_start; 227 QEMUTimer *mfwrap_timer; 228 XHCIInterrupter intr[MAXINTRS]; 229 230 XHCIRing cmd_ring; 231 232 bool nec_quirks; 233 } XHCIState; 234 235 extern const VMStateDescription vmstate_xhci; 236 bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit); 237 void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit); 238 #endif 239