1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef HW_USB_HCD_XHCI_H 23 #define HW_USB_HCD_XHCI_H 24 #include "qom/object.h" 25 26 #define TYPE_XHCI "base-xhci" 27 #define TYPE_NEC_XHCI "nec-usb-xhci" 28 #define TYPE_QEMU_XHCI "qemu-xhci" 29 30 OBJECT_DECLARE_SIMPLE_TYPE(XHCIState, XHCI) 31 32 #define MAXPORTS_2 15 33 #define MAXPORTS_3 15 34 35 #define MAXPORTS (MAXPORTS_2 + MAXPORTS_3) 36 #define MAXSLOTS 64 37 #define MAXINTRS 16 38 39 /* Very pessimistic, let's hope it's enough for all cases */ 40 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 41 42 typedef struct XHCIStreamContext XHCIStreamContext; 43 typedef struct XHCIEPContext XHCIEPContext; 44 45 enum xhci_flags { 46 XHCI_FLAG_SS_FIRST = 1, 47 XHCI_FLAG_FORCE_PCIE_ENDCAP, 48 XHCI_FLAG_ENABLE_STREAMS, 49 }; 50 51 typedef enum TRBType { 52 TRB_RESERVED = 0, 53 TR_NORMAL, 54 TR_SETUP, 55 TR_DATA, 56 TR_STATUS, 57 TR_ISOCH, 58 TR_LINK, 59 TR_EVDATA, 60 TR_NOOP, 61 CR_ENABLE_SLOT, 62 CR_DISABLE_SLOT, 63 CR_ADDRESS_DEVICE, 64 CR_CONFIGURE_ENDPOINT, 65 CR_EVALUATE_CONTEXT, 66 CR_RESET_ENDPOINT, 67 CR_STOP_ENDPOINT, 68 CR_SET_TR_DEQUEUE, 69 CR_RESET_DEVICE, 70 CR_FORCE_EVENT, 71 CR_NEGOTIATE_BW, 72 CR_SET_LATENCY_TOLERANCE, 73 CR_GET_PORT_BANDWIDTH, 74 CR_FORCE_HEADER, 75 CR_NOOP, 76 ER_TRANSFER = 32, 77 ER_COMMAND_COMPLETE, 78 ER_PORT_STATUS_CHANGE, 79 ER_BANDWIDTH_REQUEST, 80 ER_DOORBELL, 81 ER_HOST_CONTROLLER, 82 ER_DEVICE_NOTIFICATION, 83 ER_MFINDEX_WRAP, 84 /* vendor specific bits */ 85 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 86 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 87 } TRBType; 88 89 typedef enum TRBCCode { 90 CC_INVALID = 0, 91 CC_SUCCESS, 92 CC_DATA_BUFFER_ERROR, 93 CC_BABBLE_DETECTED, 94 CC_USB_TRANSACTION_ERROR, 95 CC_TRB_ERROR, 96 CC_STALL_ERROR, 97 CC_RESOURCE_ERROR, 98 CC_BANDWIDTH_ERROR, 99 CC_NO_SLOTS_ERROR, 100 CC_INVALID_STREAM_TYPE_ERROR, 101 CC_SLOT_NOT_ENABLED_ERROR, 102 CC_EP_NOT_ENABLED_ERROR, 103 CC_SHORT_PACKET, 104 CC_RING_UNDERRUN, 105 CC_RING_OVERRUN, 106 CC_VF_ER_FULL, 107 CC_PARAMETER_ERROR, 108 CC_BANDWIDTH_OVERRUN, 109 CC_CONTEXT_STATE_ERROR, 110 CC_NO_PING_RESPONSE_ERROR, 111 CC_EVENT_RING_FULL_ERROR, 112 CC_INCOMPATIBLE_DEVICE_ERROR, 113 CC_MISSED_SERVICE_ERROR, 114 CC_COMMAND_RING_STOPPED, 115 CC_COMMAND_ABORTED, 116 CC_STOPPED, 117 CC_STOPPED_LENGTH_INVALID, 118 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 119 CC_ISOCH_BUFFER_OVERRUN = 31, 120 CC_EVENT_LOST_ERROR, 121 CC_UNDEFINED_ERROR, 122 CC_INVALID_STREAM_ID_ERROR, 123 CC_SECONDARY_BANDWIDTH_ERROR, 124 CC_SPLIT_TRANSACTION_ERROR 125 } TRBCCode; 126 127 typedef struct XHCIRing { 128 dma_addr_t dequeue; 129 bool ccs; 130 } XHCIRing; 131 132 typedef struct XHCIPort { 133 XHCIState *xhci; 134 uint32_t portsc; 135 uint32_t portnr; 136 USBPort *uport; 137 uint32_t speedmask; 138 char name[16]; 139 MemoryRegion mem; 140 } XHCIPort; 141 142 typedef struct XHCISlot { 143 bool enabled; 144 bool addressed; 145 uint16_t intr; 146 dma_addr_t ctx; 147 USBPort *uport; 148 XHCIEPContext *eps[31]; 149 } XHCISlot; 150 151 typedef struct XHCIEvent { 152 TRBType type; 153 TRBCCode ccode; 154 uint64_t ptr; 155 uint32_t length; 156 uint32_t flags; 157 uint8_t slotid; 158 uint8_t epid; 159 } XHCIEvent; 160 161 typedef struct XHCIInterrupter { 162 uint32_t iman; 163 uint32_t imod; 164 uint32_t erstsz; 165 uint32_t erstba_low; 166 uint32_t erstba_high; 167 uint32_t erdp_low; 168 uint32_t erdp_high; 169 170 bool msix_used, er_pcs; 171 172 dma_addr_t er_start; 173 uint32_t er_size; 174 unsigned int er_ep_idx; 175 176 /* kept for live migration compat only */ 177 bool er_full_unused; 178 XHCIEvent ev_buffer[EV_QUEUE]; 179 unsigned int ev_buffer_put; 180 unsigned int ev_buffer_get; 181 182 } XHCIInterrupter; 183 184 struct XHCIState { 185 /*< private >*/ 186 PCIDevice parent_obj; 187 /*< public >*/ 188 189 USBBus bus; 190 MemoryRegion mem; 191 MemoryRegion mem_cap; 192 MemoryRegion mem_oper; 193 MemoryRegion mem_runtime; 194 MemoryRegion mem_doorbell; 195 196 /* properties */ 197 uint32_t numports_2; 198 uint32_t numports_3; 199 uint32_t numintrs; 200 uint32_t numslots; 201 uint32_t flags; 202 uint32_t max_pstreams_mask; 203 OnOffAuto msi; 204 OnOffAuto msix; 205 206 /* Operational Registers */ 207 uint32_t usbcmd; 208 uint32_t usbsts; 209 uint32_t dnctrl; 210 uint32_t crcr_low; 211 uint32_t crcr_high; 212 uint32_t dcbaap_low; 213 uint32_t dcbaap_high; 214 uint32_t config; 215 216 USBPort uports[MAX_CONST(MAXPORTS_2, MAXPORTS_3)]; 217 XHCIPort ports[MAXPORTS]; 218 XHCISlot slots[MAXSLOTS]; 219 uint32_t numports; 220 221 /* Runtime Registers */ 222 int64_t mfindex_start; 223 QEMUTimer *mfwrap_timer; 224 XHCIInterrupter intr[MAXINTRS]; 225 226 XHCIRing cmd_ring; 227 228 bool nec_quirks; 229 }; 230 231 #endif 232