1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 8 41 #define MAXPORTS_3 8 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS MAXPORTS 45 #define MAXINTRS MAXPORTS 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 150 typedef enum TRBType { 151 TRB_RESERVED = 0, 152 TR_NORMAL, 153 TR_SETUP, 154 TR_DATA, 155 TR_STATUS, 156 TR_ISOCH, 157 TR_LINK, 158 TR_EVDATA, 159 TR_NOOP, 160 CR_ENABLE_SLOT, 161 CR_DISABLE_SLOT, 162 CR_ADDRESS_DEVICE, 163 CR_CONFIGURE_ENDPOINT, 164 CR_EVALUATE_CONTEXT, 165 CR_RESET_ENDPOINT, 166 CR_STOP_ENDPOINT, 167 CR_SET_TR_DEQUEUE, 168 CR_RESET_DEVICE, 169 CR_FORCE_EVENT, 170 CR_NEGOTIATE_BW, 171 CR_SET_LATENCY_TOLERANCE, 172 CR_GET_PORT_BANDWIDTH, 173 CR_FORCE_HEADER, 174 CR_NOOP, 175 ER_TRANSFER = 32, 176 ER_COMMAND_COMPLETE, 177 ER_PORT_STATUS_CHANGE, 178 ER_BANDWIDTH_REQUEST, 179 ER_DOORBELL, 180 ER_HOST_CONTROLLER, 181 ER_DEVICE_NOTIFICATION, 182 ER_MFINDEX_WRAP, 183 /* vendor specific bits */ 184 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 185 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 186 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 187 } TRBType; 188 189 #define CR_LINK TR_LINK 190 191 typedef enum TRBCCode { 192 CC_INVALID = 0, 193 CC_SUCCESS, 194 CC_DATA_BUFFER_ERROR, 195 CC_BABBLE_DETECTED, 196 CC_USB_TRANSACTION_ERROR, 197 CC_TRB_ERROR, 198 CC_STALL_ERROR, 199 CC_RESOURCE_ERROR, 200 CC_BANDWIDTH_ERROR, 201 CC_NO_SLOTS_ERROR, 202 CC_INVALID_STREAM_TYPE_ERROR, 203 CC_SLOT_NOT_ENABLED_ERROR, 204 CC_EP_NOT_ENABLED_ERROR, 205 CC_SHORT_PACKET, 206 CC_RING_UNDERRUN, 207 CC_RING_OVERRUN, 208 CC_VF_ER_FULL, 209 CC_PARAMETER_ERROR, 210 CC_BANDWIDTH_OVERRUN, 211 CC_CONTEXT_STATE_ERROR, 212 CC_NO_PING_RESPONSE_ERROR, 213 CC_EVENT_RING_FULL_ERROR, 214 CC_INCOMPATIBLE_DEVICE_ERROR, 215 CC_MISSED_SERVICE_ERROR, 216 CC_COMMAND_RING_STOPPED, 217 CC_COMMAND_ABORTED, 218 CC_STOPPED, 219 CC_STOPPED_LENGTH_INVALID, 220 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 221 CC_ISOCH_BUFFER_OVERRUN = 31, 222 CC_EVENT_LOST_ERROR, 223 CC_UNDEFINED_ERROR, 224 CC_INVALID_STREAM_ID_ERROR, 225 CC_SECONDARY_BANDWIDTH_ERROR, 226 CC_SPLIT_TRANSACTION_ERROR 227 } TRBCCode; 228 229 #define TRB_C (1<<0) 230 #define TRB_TYPE_SHIFT 10 231 #define TRB_TYPE_MASK 0x3f 232 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 233 234 #define TRB_EV_ED (1<<2) 235 236 #define TRB_TR_ENT (1<<1) 237 #define TRB_TR_ISP (1<<2) 238 #define TRB_TR_NS (1<<3) 239 #define TRB_TR_CH (1<<4) 240 #define TRB_TR_IOC (1<<5) 241 #define TRB_TR_IDT (1<<6) 242 #define TRB_TR_TBC_SHIFT 7 243 #define TRB_TR_TBC_MASK 0x3 244 #define TRB_TR_BEI (1<<9) 245 #define TRB_TR_TLBPC_SHIFT 16 246 #define TRB_TR_TLBPC_MASK 0xf 247 #define TRB_TR_FRAMEID_SHIFT 20 248 #define TRB_TR_FRAMEID_MASK 0x7ff 249 #define TRB_TR_SIA (1<<31) 250 251 #define TRB_TR_DIR (1<<16) 252 253 #define TRB_CR_SLOTID_SHIFT 24 254 #define TRB_CR_SLOTID_MASK 0xff 255 #define TRB_CR_EPID_SHIFT 16 256 #define TRB_CR_EPID_MASK 0x1f 257 258 #define TRB_CR_BSR (1<<9) 259 #define TRB_CR_DC (1<<9) 260 261 #define TRB_LK_TC (1<<1) 262 263 #define TRB_INTR_SHIFT 22 264 #define TRB_INTR_MASK 0x3ff 265 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef enum EPType { 289 ET_INVALID = 0, 290 ET_ISO_OUT, 291 ET_BULK_OUT, 292 ET_INTR_OUT, 293 ET_CONTROL, 294 ET_ISO_IN, 295 ET_BULK_IN, 296 ET_INTR_IN, 297 } EPType; 298 299 typedef struct XHCIRing { 300 dma_addr_t base; 301 dma_addr_t dequeue; 302 bool ccs; 303 } XHCIRing; 304 305 typedef struct XHCIPort { 306 uint32_t portsc; 307 uint32_t portnr; 308 USBPort *uport; 309 uint32_t speedmask; 310 } XHCIPort; 311 312 struct XHCIState; 313 typedef struct XHCIState XHCIState; 314 315 typedef struct XHCITransfer { 316 XHCIState *xhci; 317 USBPacket packet; 318 QEMUSGList sgl; 319 bool running_async; 320 bool running_retry; 321 bool cancelled; 322 bool complete; 323 unsigned int iso_pkts; 324 unsigned int slotid; 325 unsigned int epid; 326 bool in_xfer; 327 bool iso_xfer; 328 329 unsigned int trb_count; 330 unsigned int trb_alloced; 331 XHCITRB *trbs; 332 333 TRBCCode status; 334 335 unsigned int pkts; 336 unsigned int pktsize; 337 unsigned int cur_pkt; 338 339 uint64_t mfindex_kick; 340 } XHCITransfer; 341 342 typedef struct XHCIEPContext { 343 XHCIState *xhci; 344 unsigned int slotid; 345 unsigned int epid; 346 347 XHCIRing ring; 348 unsigned int next_xfer; 349 unsigned int comp_xfer; 350 XHCITransfer transfers[TD_QUEUE]; 351 XHCITransfer *retry; 352 EPType type; 353 dma_addr_t pctx; 354 unsigned int max_psize; 355 uint32_t state; 356 357 /* iso xfer scheduling */ 358 unsigned int interval; 359 int64_t mfindex_last; 360 QEMUTimer *kick_timer; 361 } XHCIEPContext; 362 363 typedef struct XHCISlot { 364 bool enabled; 365 dma_addr_t ctx; 366 unsigned int port; 367 unsigned int devaddr; 368 XHCIEPContext * eps[31]; 369 } XHCISlot; 370 371 typedef struct XHCIEvent { 372 TRBType type; 373 TRBCCode ccode; 374 uint64_t ptr; 375 uint32_t length; 376 uint32_t flags; 377 uint8_t slotid; 378 uint8_t epid; 379 } XHCIEvent; 380 381 typedef struct XHCIInterrupter { 382 uint32_t iman; 383 uint32_t imod; 384 uint32_t erstsz; 385 uint32_t erstba_low; 386 uint32_t erstba_high; 387 uint32_t erdp_low; 388 uint32_t erdp_high; 389 390 bool msix_used, er_pcs, er_full; 391 392 dma_addr_t er_start; 393 uint32_t er_size; 394 unsigned int er_ep_idx; 395 396 XHCIEvent ev_buffer[EV_QUEUE]; 397 unsigned int ev_buffer_put; 398 unsigned int ev_buffer_get; 399 400 } XHCIInterrupter; 401 402 struct XHCIState { 403 PCIDevice pci_dev; 404 USBBus bus; 405 qemu_irq irq; 406 MemoryRegion mem; 407 const char *name; 408 unsigned int devaddr; 409 410 /* properties */ 411 uint32_t numports_2; 412 uint32_t numports_3; 413 uint32_t flags; 414 415 /* Operational Registers */ 416 uint32_t usbcmd; 417 uint32_t usbsts; 418 uint32_t dnctrl; 419 uint32_t crcr_low; 420 uint32_t crcr_high; 421 uint32_t dcbaap_low; 422 uint32_t dcbaap_high; 423 uint32_t config; 424 425 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 426 XHCIPort ports[MAXPORTS]; 427 XHCISlot slots[MAXSLOTS]; 428 uint32_t numports; 429 430 /* Runtime Registers */ 431 int64_t mfindex_start; 432 QEMUTimer *mfwrap_timer; 433 XHCIInterrupter intr[MAXINTRS]; 434 435 XHCIRing cmd_ring; 436 }; 437 438 typedef struct XHCIEvRingSeg { 439 uint32_t addr_low; 440 uint32_t addr_high; 441 uint32_t size; 442 uint32_t rsvd; 443 } XHCIEvRingSeg; 444 445 enum xhci_flags { 446 XHCI_FLAG_USE_MSI = 1, 447 XHCI_FLAG_USE_MSI_X, 448 }; 449 450 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 451 unsigned int epid); 452 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 453 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 454 455 static const char *TRBType_names[] = { 456 [TRB_RESERVED] = "TRB_RESERVED", 457 [TR_NORMAL] = "TR_NORMAL", 458 [TR_SETUP] = "TR_SETUP", 459 [TR_DATA] = "TR_DATA", 460 [TR_STATUS] = "TR_STATUS", 461 [TR_ISOCH] = "TR_ISOCH", 462 [TR_LINK] = "TR_LINK", 463 [TR_EVDATA] = "TR_EVDATA", 464 [TR_NOOP] = "TR_NOOP", 465 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 466 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 467 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 468 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 469 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 470 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 471 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 472 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 473 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 474 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 475 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 476 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 477 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 478 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 479 [CR_NOOP] = "CR_NOOP", 480 [ER_TRANSFER] = "ER_TRANSFER", 481 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 482 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 483 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 484 [ER_DOORBELL] = "ER_DOORBELL", 485 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 486 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 487 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 488 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 489 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 490 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 491 }; 492 493 static const char *TRBCCode_names[] = { 494 [CC_INVALID] = "CC_INVALID", 495 [CC_SUCCESS] = "CC_SUCCESS", 496 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 497 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 498 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 499 [CC_TRB_ERROR] = "CC_TRB_ERROR", 500 [CC_STALL_ERROR] = "CC_STALL_ERROR", 501 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 502 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 503 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 504 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 505 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 506 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 507 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 508 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 509 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 510 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 511 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 512 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 513 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 514 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 515 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 516 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 517 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 518 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 519 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 520 [CC_STOPPED] = "CC_STOPPED", 521 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 522 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 523 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 524 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 525 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 526 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 527 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 528 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 529 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 530 }; 531 532 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 533 { 534 if (index >= llen || list[index] == NULL) { 535 return "???"; 536 } 537 return list[index]; 538 } 539 540 static const char *trb_name(XHCITRB *trb) 541 { 542 return lookup_name(TRB_TYPE(*trb), TRBType_names, 543 ARRAY_SIZE(TRBType_names)); 544 } 545 546 static const char *event_name(XHCIEvent *event) 547 { 548 return lookup_name(event->ccode, TRBCCode_names, 549 ARRAY_SIZE(TRBCCode_names)); 550 } 551 552 static uint64_t xhci_mfindex_get(XHCIState *xhci) 553 { 554 int64_t now = qemu_get_clock_ns(vm_clock); 555 return (now - xhci->mfindex_start) / 125000; 556 } 557 558 static void xhci_mfwrap_update(XHCIState *xhci) 559 { 560 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 561 uint32_t mfindex, left; 562 int64_t now; 563 564 if ((xhci->usbcmd & bits) == bits) { 565 now = qemu_get_clock_ns(vm_clock); 566 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 567 left = 0x4000 - mfindex; 568 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 569 } else { 570 qemu_del_timer(xhci->mfwrap_timer); 571 } 572 } 573 574 static void xhci_mfwrap_timer(void *opaque) 575 { 576 XHCIState *xhci = opaque; 577 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 578 579 xhci_event(xhci, &wrap, 0); 580 xhci_mfwrap_update(xhci); 581 } 582 583 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 584 { 585 if (sizeof(dma_addr_t) == 4) { 586 return low; 587 } else { 588 return low | (((dma_addr_t)high << 16) << 16); 589 } 590 } 591 592 static inline dma_addr_t xhci_mask64(uint64_t addr) 593 { 594 if (sizeof(dma_addr_t) == 4) { 595 return addr & 0xffffffff; 596 } else { 597 return addr; 598 } 599 } 600 601 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 602 { 603 int index; 604 605 if (!uport->dev) { 606 return NULL; 607 } 608 switch (uport->dev->speed) { 609 case USB_SPEED_LOW: 610 case USB_SPEED_FULL: 611 case USB_SPEED_HIGH: 612 index = uport->index; 613 break; 614 case USB_SPEED_SUPER: 615 index = uport->index + xhci->numports_2; 616 break; 617 default: 618 return NULL; 619 } 620 return &xhci->ports[index]; 621 } 622 623 static void xhci_intx_update(XHCIState *xhci) 624 { 625 int level = 0; 626 627 if (msix_enabled(&xhci->pci_dev) || 628 msi_enabled(&xhci->pci_dev)) { 629 return; 630 } 631 632 if (xhci->intr[0].iman & IMAN_IP && 633 xhci->intr[0].iman & IMAN_IE && 634 xhci->usbcmd & USBCMD_INTE) { 635 level = 1; 636 } 637 638 trace_usb_xhci_irq_intx(level); 639 qemu_set_irq(xhci->irq, level); 640 } 641 642 static void xhci_msix_update(XHCIState *xhci, int v) 643 { 644 bool enabled; 645 646 if (!msix_enabled(&xhci->pci_dev)) { 647 return; 648 } 649 650 enabled = xhci->intr[v].iman & IMAN_IE; 651 if (enabled == xhci->intr[v].msix_used) { 652 return; 653 } 654 655 if (enabled) { 656 trace_usb_xhci_irq_msix_use(v); 657 msix_vector_use(&xhci->pci_dev, v); 658 xhci->intr[v].msix_used = true; 659 } else { 660 trace_usb_xhci_irq_msix_unuse(v); 661 msix_vector_unuse(&xhci->pci_dev, v); 662 xhci->intr[v].msix_used = false; 663 } 664 } 665 666 static void xhci_intr_raise(XHCIState *xhci, int v) 667 { 668 xhci->intr[v].erdp_low |= ERDP_EHB; 669 xhci->intr[v].iman |= IMAN_IP; 670 xhci->usbsts |= USBSTS_EINT; 671 672 if (!(xhci->intr[v].iman & IMAN_IE)) { 673 return; 674 } 675 676 if (!(xhci->usbcmd & USBCMD_INTE)) { 677 return; 678 } 679 680 if (msix_enabled(&xhci->pci_dev)) { 681 trace_usb_xhci_irq_msix(v); 682 msix_notify(&xhci->pci_dev, v); 683 return; 684 } 685 686 if (msi_enabled(&xhci->pci_dev)) { 687 trace_usb_xhci_irq_msi(v); 688 msi_notify(&xhci->pci_dev, v); 689 return; 690 } 691 692 if (v == 0) { 693 trace_usb_xhci_irq_intx(1); 694 qemu_set_irq(xhci->irq, 1); 695 } 696 } 697 698 static inline int xhci_running(XHCIState *xhci) 699 { 700 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 701 } 702 703 static void xhci_die(XHCIState *xhci) 704 { 705 xhci->usbsts |= USBSTS_HCE; 706 fprintf(stderr, "xhci: asserted controller error\n"); 707 } 708 709 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 710 { 711 XHCIInterrupter *intr = &xhci->intr[v]; 712 XHCITRB ev_trb; 713 dma_addr_t addr; 714 715 ev_trb.parameter = cpu_to_le64(event->ptr); 716 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 717 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 718 event->flags | (event->type << TRB_TYPE_SHIFT); 719 if (intr->er_pcs) { 720 ev_trb.control |= TRB_C; 721 } 722 ev_trb.control = cpu_to_le32(ev_trb.control); 723 724 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 725 event_name(event), ev_trb.parameter, 726 ev_trb.status, ev_trb.control); 727 728 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 729 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 730 731 intr->er_ep_idx++; 732 if (intr->er_ep_idx >= intr->er_size) { 733 intr->er_ep_idx = 0; 734 intr->er_pcs = !intr->er_pcs; 735 } 736 } 737 738 static void xhci_events_update(XHCIState *xhci, int v) 739 { 740 XHCIInterrupter *intr = &xhci->intr[v]; 741 dma_addr_t erdp; 742 unsigned int dp_idx; 743 bool do_irq = 0; 744 745 if (xhci->usbsts & USBSTS_HCH) { 746 return; 747 } 748 749 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 750 if (erdp < intr->er_start || 751 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 752 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 753 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 754 v, intr->er_start, intr->er_size); 755 xhci_die(xhci); 756 return; 757 } 758 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 759 assert(dp_idx < intr->er_size); 760 761 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 762 * deadlocks when the ER is full. Hack it by holding off events until 763 * the driver decides to free at least half of the ring */ 764 if (intr->er_full) { 765 int er_free = dp_idx - intr->er_ep_idx; 766 if (er_free <= 0) { 767 er_free += intr->er_size; 768 } 769 if (er_free < (intr->er_size/2)) { 770 DPRINTF("xhci_events_update(): event ring still " 771 "more than half full (hack)\n"); 772 return; 773 } 774 } 775 776 while (intr->ev_buffer_put != intr->ev_buffer_get) { 777 assert(intr->er_full); 778 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 779 DPRINTF("xhci_events_update(): event ring full again\n"); 780 #ifndef ER_FULL_HACK 781 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 782 xhci_write_event(xhci, &full, v); 783 #endif 784 do_irq = 1; 785 break; 786 } 787 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 788 xhci_write_event(xhci, event, v); 789 intr->ev_buffer_get++; 790 do_irq = 1; 791 if (intr->ev_buffer_get == EV_QUEUE) { 792 intr->ev_buffer_get = 0; 793 } 794 } 795 796 if (do_irq) { 797 xhci_intr_raise(xhci, v); 798 } 799 800 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 801 DPRINTF("xhci_events_update(): event ring no longer full\n"); 802 intr->er_full = 0; 803 } 804 return; 805 } 806 807 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 808 { 809 XHCIInterrupter *intr; 810 dma_addr_t erdp; 811 unsigned int dp_idx; 812 813 if (v >= MAXINTRS) { 814 DPRINTF("intr nr out of range (%d >= %d)\n", v, MAXINTRS); 815 return; 816 } 817 intr = &xhci->intr[v]; 818 819 if (intr->er_full) { 820 DPRINTF("xhci_event(): ER full, queueing\n"); 821 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 822 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 823 return; 824 } 825 intr->ev_buffer[intr->ev_buffer_put++] = *event; 826 if (intr->ev_buffer_put == EV_QUEUE) { 827 intr->ev_buffer_put = 0; 828 } 829 return; 830 } 831 832 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 833 if (erdp < intr->er_start || 834 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 835 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 836 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 837 v, intr->er_start, intr->er_size); 838 xhci_die(xhci); 839 return; 840 } 841 842 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 843 assert(dp_idx < intr->er_size); 844 845 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 846 DPRINTF("xhci_event(): ER full, queueing\n"); 847 #ifndef ER_FULL_HACK 848 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 849 xhci_write_event(xhci, &full); 850 #endif 851 intr->er_full = 1; 852 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 853 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 854 return; 855 } 856 intr->ev_buffer[intr->ev_buffer_put++] = *event; 857 if (intr->ev_buffer_put == EV_QUEUE) { 858 intr->ev_buffer_put = 0; 859 } 860 } else { 861 xhci_write_event(xhci, event, v); 862 } 863 864 xhci_intr_raise(xhci, v); 865 } 866 867 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 868 dma_addr_t base) 869 { 870 ring->base = base; 871 ring->dequeue = base; 872 ring->ccs = 1; 873 } 874 875 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 876 dma_addr_t *addr) 877 { 878 while (1) { 879 TRBType type; 880 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 881 trb->addr = ring->dequeue; 882 trb->ccs = ring->ccs; 883 le64_to_cpus(&trb->parameter); 884 le32_to_cpus(&trb->status); 885 le32_to_cpus(&trb->control); 886 887 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 888 trb->parameter, trb->status, trb->control); 889 890 if ((trb->control & TRB_C) != ring->ccs) { 891 return 0; 892 } 893 894 type = TRB_TYPE(*trb); 895 896 if (type != TR_LINK) { 897 if (addr) { 898 *addr = ring->dequeue; 899 } 900 ring->dequeue += TRB_SIZE; 901 return type; 902 } else { 903 ring->dequeue = xhci_mask64(trb->parameter); 904 if (trb->control & TRB_LK_TC) { 905 ring->ccs = !ring->ccs; 906 } 907 } 908 } 909 } 910 911 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 912 { 913 XHCITRB trb; 914 int length = 0; 915 dma_addr_t dequeue = ring->dequeue; 916 bool ccs = ring->ccs; 917 /* hack to bundle together the two/three TDs that make a setup transfer */ 918 bool control_td_set = 0; 919 920 while (1) { 921 TRBType type; 922 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 923 le64_to_cpus(&trb.parameter); 924 le32_to_cpus(&trb.status); 925 le32_to_cpus(&trb.control); 926 927 if ((trb.control & TRB_C) != ccs) { 928 return -length; 929 } 930 931 type = TRB_TYPE(trb); 932 933 if (type == TR_LINK) { 934 dequeue = xhci_mask64(trb.parameter); 935 if (trb.control & TRB_LK_TC) { 936 ccs = !ccs; 937 } 938 continue; 939 } 940 941 length += 1; 942 dequeue += TRB_SIZE; 943 944 if (type == TR_SETUP) { 945 control_td_set = 1; 946 } else if (type == TR_STATUS) { 947 control_td_set = 0; 948 } 949 950 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 951 return length; 952 } 953 } 954 } 955 956 static void xhci_er_reset(XHCIState *xhci, int v) 957 { 958 XHCIInterrupter *intr = &xhci->intr[v]; 959 XHCIEvRingSeg seg; 960 961 /* cache the (sole) event ring segment location */ 962 if (intr->erstsz != 1) { 963 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 964 xhci_die(xhci); 965 return; 966 } 967 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 968 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 969 le32_to_cpus(&seg.addr_low); 970 le32_to_cpus(&seg.addr_high); 971 le32_to_cpus(&seg.size); 972 if (seg.size < 16 || seg.size > 4096) { 973 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 974 xhci_die(xhci); 975 return; 976 } 977 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 978 intr->er_size = seg.size; 979 980 intr->er_ep_idx = 0; 981 intr->er_pcs = 1; 982 intr->er_full = 0; 983 984 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 985 v, intr->er_start, intr->er_size); 986 } 987 988 static void xhci_run(XHCIState *xhci) 989 { 990 trace_usb_xhci_run(); 991 xhci->usbsts &= ~USBSTS_HCH; 992 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 993 } 994 995 static void xhci_stop(XHCIState *xhci) 996 { 997 trace_usb_xhci_stop(); 998 xhci->usbsts |= USBSTS_HCH; 999 xhci->crcr_low &= ~CRCR_CRR; 1000 } 1001 1002 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1003 uint32_t state) 1004 { 1005 uint32_t ctx[5]; 1006 if (epctx->state == state) { 1007 return; 1008 } 1009 1010 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1011 ctx[0] &= ~EP_STATE_MASK; 1012 ctx[0] |= state; 1013 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1014 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1015 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1016 epctx->pctx, state, ctx[3], ctx[2]); 1017 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1018 epctx->state = state; 1019 } 1020 1021 static void xhci_ep_kick_timer(void *opaque) 1022 { 1023 XHCIEPContext *epctx = opaque; 1024 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1025 } 1026 1027 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1028 unsigned int epid, dma_addr_t pctx, 1029 uint32_t *ctx) 1030 { 1031 XHCISlot *slot; 1032 XHCIEPContext *epctx; 1033 dma_addr_t dequeue; 1034 int i; 1035 1036 trace_usb_xhci_ep_enable(slotid, epid); 1037 assert(slotid >= 1 && slotid <= MAXSLOTS); 1038 assert(epid >= 1 && epid <= 31); 1039 1040 slot = &xhci->slots[slotid-1]; 1041 if (slot->eps[epid-1]) { 1042 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1043 return CC_TRB_ERROR; 1044 } 1045 1046 epctx = g_malloc(sizeof(XHCIEPContext)); 1047 memset(epctx, 0, sizeof(XHCIEPContext)); 1048 epctx->xhci = xhci; 1049 epctx->slotid = slotid; 1050 epctx->epid = epid; 1051 1052 slot->eps[epid-1] = epctx; 1053 1054 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1055 xhci_ring_init(xhci, &epctx->ring, dequeue); 1056 epctx->ring.ccs = ctx[2] & 1; 1057 1058 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1059 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1060 epctx->pctx = pctx; 1061 epctx->max_psize = ctx[1]>>16; 1062 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1063 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1064 epid/2, epid%2, epctx->max_psize); 1065 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1066 usb_packet_init(&epctx->transfers[i].packet); 1067 } 1068 1069 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1070 epctx->mfindex_last = 0; 1071 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1072 1073 epctx->state = EP_RUNNING; 1074 ctx[0] &= ~EP_STATE_MASK; 1075 ctx[0] |= EP_RUNNING; 1076 1077 return CC_SUCCESS; 1078 } 1079 1080 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1081 unsigned int epid) 1082 { 1083 XHCISlot *slot; 1084 XHCIEPContext *epctx; 1085 int i, xferi, killed = 0; 1086 assert(slotid >= 1 && slotid <= MAXSLOTS); 1087 assert(epid >= 1 && epid <= 31); 1088 1089 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1090 1091 slot = &xhci->slots[slotid-1]; 1092 1093 if (!slot->eps[epid-1]) { 1094 return 0; 1095 } 1096 1097 epctx = slot->eps[epid-1]; 1098 1099 xferi = epctx->next_xfer; 1100 for (i = 0; i < TD_QUEUE; i++) { 1101 XHCITransfer *t = &epctx->transfers[xferi]; 1102 if (t->running_async) { 1103 usb_cancel_packet(&t->packet); 1104 t->running_async = 0; 1105 t->cancelled = 1; 1106 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i); 1107 killed++; 1108 } 1109 if (t->running_retry) { 1110 t->running_retry = 0; 1111 epctx->retry = NULL; 1112 qemu_del_timer(epctx->kick_timer); 1113 } 1114 if (t->trbs) { 1115 g_free(t->trbs); 1116 } 1117 1118 t->trbs = NULL; 1119 t->trb_count = t->trb_alloced = 0; 1120 xferi = (xferi + 1) % TD_QUEUE; 1121 } 1122 return killed; 1123 } 1124 1125 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1126 unsigned int epid) 1127 { 1128 XHCISlot *slot; 1129 XHCIEPContext *epctx; 1130 1131 trace_usb_xhci_ep_disable(slotid, epid); 1132 assert(slotid >= 1 && slotid <= MAXSLOTS); 1133 assert(epid >= 1 && epid <= 31); 1134 1135 slot = &xhci->slots[slotid-1]; 1136 1137 if (!slot->eps[epid-1]) { 1138 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1139 return CC_SUCCESS; 1140 } 1141 1142 xhci_ep_nuke_xfers(xhci, slotid, epid); 1143 1144 epctx = slot->eps[epid-1]; 1145 1146 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1147 1148 qemu_free_timer(epctx->kick_timer); 1149 g_free(epctx); 1150 slot->eps[epid-1] = NULL; 1151 1152 return CC_SUCCESS; 1153 } 1154 1155 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1156 unsigned int epid) 1157 { 1158 XHCISlot *slot; 1159 XHCIEPContext *epctx; 1160 1161 trace_usb_xhci_ep_stop(slotid, epid); 1162 assert(slotid >= 1 && slotid <= MAXSLOTS); 1163 1164 if (epid < 1 || epid > 31) { 1165 fprintf(stderr, "xhci: bad ep %d\n", epid); 1166 return CC_TRB_ERROR; 1167 } 1168 1169 slot = &xhci->slots[slotid-1]; 1170 1171 if (!slot->eps[epid-1]) { 1172 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1173 return CC_EP_NOT_ENABLED_ERROR; 1174 } 1175 1176 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1177 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1178 "data might be lost\n"); 1179 } 1180 1181 epctx = slot->eps[epid-1]; 1182 1183 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1184 1185 return CC_SUCCESS; 1186 } 1187 1188 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1189 unsigned int epid) 1190 { 1191 XHCISlot *slot; 1192 XHCIEPContext *epctx; 1193 USBDevice *dev; 1194 1195 trace_usb_xhci_ep_reset(slotid, epid); 1196 assert(slotid >= 1 && slotid <= MAXSLOTS); 1197 1198 if (epid < 1 || epid > 31) { 1199 fprintf(stderr, "xhci: bad ep %d\n", epid); 1200 return CC_TRB_ERROR; 1201 } 1202 1203 slot = &xhci->slots[slotid-1]; 1204 1205 if (!slot->eps[epid-1]) { 1206 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1207 return CC_EP_NOT_ENABLED_ERROR; 1208 } 1209 1210 epctx = slot->eps[epid-1]; 1211 1212 if (epctx->state != EP_HALTED) { 1213 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1214 epid, epctx->state); 1215 return CC_CONTEXT_STATE_ERROR; 1216 } 1217 1218 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1219 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1220 "data might be lost\n"); 1221 } 1222 1223 uint8_t ep = epid>>1; 1224 1225 if (epid & 1) { 1226 ep |= 0x80; 1227 } 1228 1229 dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev; 1230 if (!dev) { 1231 return CC_USB_TRANSACTION_ERROR; 1232 } 1233 1234 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1235 1236 return CC_SUCCESS; 1237 } 1238 1239 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1240 unsigned int epid, uint64_t pdequeue) 1241 { 1242 XHCISlot *slot; 1243 XHCIEPContext *epctx; 1244 dma_addr_t dequeue; 1245 1246 assert(slotid >= 1 && slotid <= MAXSLOTS); 1247 1248 if (epid < 1 || epid > 31) { 1249 fprintf(stderr, "xhci: bad ep %d\n", epid); 1250 return CC_TRB_ERROR; 1251 } 1252 1253 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1254 dequeue = xhci_mask64(pdequeue); 1255 1256 slot = &xhci->slots[slotid-1]; 1257 1258 if (!slot->eps[epid-1]) { 1259 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1260 return CC_EP_NOT_ENABLED_ERROR; 1261 } 1262 1263 epctx = slot->eps[epid-1]; 1264 1265 1266 if (epctx->state != EP_STOPPED) { 1267 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1268 return CC_CONTEXT_STATE_ERROR; 1269 } 1270 1271 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1272 epctx->ring.ccs = dequeue & 1; 1273 1274 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1275 1276 return CC_SUCCESS; 1277 } 1278 1279 static int xhci_xfer_map(XHCITransfer *xfer) 1280 { 1281 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN); 1282 XHCIState *xhci = xfer->xhci; 1283 int i; 1284 1285 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1286 for (i = 0; i < xfer->trb_count; i++) { 1287 XHCITRB *trb = &xfer->trbs[i]; 1288 dma_addr_t addr; 1289 unsigned int chunk = 0; 1290 1291 switch (TRB_TYPE(*trb)) { 1292 case TR_DATA: 1293 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1294 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1295 goto err; 1296 } 1297 /* fallthrough */ 1298 case TR_NORMAL: 1299 case TR_ISOCH: 1300 addr = xhci_mask64(trb->parameter); 1301 chunk = trb->status & 0x1ffff; 1302 if (trb->control & TRB_TR_IDT) { 1303 if (chunk > 8 || in_xfer) { 1304 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1305 goto err; 1306 } 1307 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1308 } else { 1309 qemu_sglist_add(&xfer->sgl, addr, chunk); 1310 } 1311 break; 1312 } 1313 } 1314 1315 usb_packet_map(&xfer->packet, &xfer->sgl); 1316 return 0; 1317 1318 err: 1319 qemu_sglist_destroy(&xfer->sgl); 1320 xhci_die(xhci); 1321 return -1; 1322 } 1323 1324 static void xhci_xfer_unmap(XHCITransfer *xfer) 1325 { 1326 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1327 qemu_sglist_destroy(&xfer->sgl); 1328 } 1329 1330 static void xhci_xfer_report(XHCITransfer *xfer) 1331 { 1332 uint32_t edtla = 0; 1333 unsigned int left; 1334 bool reported = 0; 1335 bool shortpkt = 0; 1336 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1337 XHCIState *xhci = xfer->xhci; 1338 int i; 1339 1340 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1341 1342 for (i = 0; i < xfer->trb_count; i++) { 1343 XHCITRB *trb = &xfer->trbs[i]; 1344 unsigned int chunk = 0; 1345 1346 switch (TRB_TYPE(*trb)) { 1347 case TR_DATA: 1348 case TR_NORMAL: 1349 case TR_ISOCH: 1350 chunk = trb->status & 0x1ffff; 1351 if (chunk > left) { 1352 chunk = left; 1353 if (xfer->status == CC_SUCCESS) { 1354 shortpkt = 1; 1355 } 1356 } 1357 left -= chunk; 1358 edtla += chunk; 1359 break; 1360 case TR_STATUS: 1361 reported = 0; 1362 shortpkt = 0; 1363 break; 1364 } 1365 1366 if (!reported && ((trb->control & TRB_TR_IOC) || 1367 (shortpkt && (trb->control & TRB_TR_ISP)) || 1368 (xfer->status != CC_SUCCESS))) { 1369 event.slotid = xfer->slotid; 1370 event.epid = xfer->epid; 1371 event.length = (trb->status & 0x1ffff) - chunk; 1372 event.flags = 0; 1373 event.ptr = trb->addr; 1374 if (xfer->status == CC_SUCCESS) { 1375 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1376 } else { 1377 event.ccode = xfer->status; 1378 } 1379 if (TRB_TYPE(*trb) == TR_EVDATA) { 1380 event.ptr = trb->parameter; 1381 event.flags |= TRB_EV_ED; 1382 event.length = edtla & 0xffffff; 1383 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1384 edtla = 0; 1385 } 1386 xhci_event(xhci, &event, TRB_INTR(*trb)); 1387 reported = 1; 1388 if (xfer->status != CC_SUCCESS) { 1389 return; 1390 } 1391 } 1392 } 1393 } 1394 1395 static void xhci_stall_ep(XHCITransfer *xfer) 1396 { 1397 XHCIState *xhci = xfer->xhci; 1398 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1399 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1400 1401 epctx->ring.dequeue = xfer->trbs[0].addr; 1402 epctx->ring.ccs = xfer->trbs[0].ccs; 1403 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1404 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1405 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1406 } 1407 1408 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1409 XHCIEPContext *epctx); 1410 1411 static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr) 1412 { 1413 if (!(port->portsc & PORTSC_PED)) { 1414 return NULL; 1415 } 1416 return usb_find_device(port->uport, addr); 1417 } 1418 1419 static int xhci_setup_packet(XHCITransfer *xfer) 1420 { 1421 XHCIState *xhci = xfer->xhci; 1422 XHCIPort *port; 1423 USBDevice *dev; 1424 USBEndpoint *ep; 1425 int dir; 1426 1427 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1428 1429 if (xfer->packet.ep) { 1430 ep = xfer->packet.ep; 1431 dev = ep->dev; 1432 } else { 1433 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1]; 1434 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr); 1435 if (!dev) { 1436 fprintf(stderr, "xhci: slot %d port %d has no device\n", 1437 xfer->slotid, xhci->slots[xfer->slotid-1].port); 1438 return -1; 1439 } 1440 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1441 } 1442 1443 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr); 1444 xhci_xfer_map(xfer); 1445 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1446 xfer->packet.pid, dev->addr, ep->nr); 1447 return 0; 1448 } 1449 1450 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1451 { 1452 if (ret == USB_RET_ASYNC) { 1453 trace_usb_xhci_xfer_async(xfer); 1454 xfer->running_async = 1; 1455 xfer->running_retry = 0; 1456 xfer->complete = 0; 1457 xfer->cancelled = 0; 1458 return 0; 1459 } else if (ret == USB_RET_NAK) { 1460 trace_usb_xhci_xfer_nak(xfer); 1461 xfer->running_async = 0; 1462 xfer->running_retry = 1; 1463 xfer->complete = 0; 1464 xfer->cancelled = 0; 1465 return 0; 1466 } else { 1467 xfer->running_async = 0; 1468 xfer->running_retry = 0; 1469 xfer->complete = 1; 1470 xhci_xfer_unmap(xfer); 1471 } 1472 1473 if (ret >= 0) { 1474 trace_usb_xhci_xfer_success(xfer, ret); 1475 xfer->status = CC_SUCCESS; 1476 xhci_xfer_report(xfer); 1477 return 0; 1478 } 1479 1480 /* error */ 1481 trace_usb_xhci_xfer_error(xfer, ret); 1482 switch (ret) { 1483 case USB_RET_NODEV: 1484 xfer->status = CC_USB_TRANSACTION_ERROR; 1485 xhci_xfer_report(xfer); 1486 xhci_stall_ep(xfer); 1487 break; 1488 case USB_RET_STALL: 1489 xfer->status = CC_STALL_ERROR; 1490 xhci_xfer_report(xfer); 1491 xhci_stall_ep(xfer); 1492 break; 1493 default: 1494 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1495 FIXME(); 1496 } 1497 return 0; 1498 } 1499 1500 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1501 { 1502 XHCITRB *trb_setup, *trb_status; 1503 uint8_t bmRequestType; 1504 int ret; 1505 1506 trb_setup = &xfer->trbs[0]; 1507 trb_status = &xfer->trbs[xfer->trb_count-1]; 1508 1509 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1510 1511 /* at most one Event Data TRB allowed after STATUS */ 1512 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1513 trb_status--; 1514 } 1515 1516 /* do some sanity checks */ 1517 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1518 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1519 TRB_TYPE(*trb_setup)); 1520 return -1; 1521 } 1522 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1523 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1524 TRB_TYPE(*trb_status)); 1525 return -1; 1526 } 1527 if (!(trb_setup->control & TRB_TR_IDT)) { 1528 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1529 return -1; 1530 } 1531 if ((trb_setup->status & 0x1ffff) != 8) { 1532 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1533 (trb_setup->status & 0x1ffff)); 1534 return -1; 1535 } 1536 1537 bmRequestType = trb_setup->parameter; 1538 1539 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1540 xfer->iso_xfer = false; 1541 1542 if (xhci_setup_packet(xfer) < 0) { 1543 return -1; 1544 } 1545 xfer->packet.parameter = trb_setup->parameter; 1546 1547 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1548 1549 xhci_complete_packet(xfer, ret); 1550 if (!xfer->running_async && !xfer->running_retry) { 1551 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1552 } 1553 return 0; 1554 } 1555 1556 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1557 XHCIEPContext *epctx, uint64_t mfindex) 1558 { 1559 if (xfer->trbs[0].control & TRB_TR_SIA) { 1560 uint64_t asap = ((mfindex + epctx->interval - 1) & 1561 ~(epctx->interval-1)); 1562 if (asap >= epctx->mfindex_last && 1563 asap <= epctx->mfindex_last + epctx->interval * 4) { 1564 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1565 } else { 1566 xfer->mfindex_kick = asap; 1567 } 1568 } else { 1569 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1570 & TRB_TR_FRAMEID_MASK; 1571 xfer->mfindex_kick |= mfindex & ~0x3fff; 1572 if (xfer->mfindex_kick < mfindex) { 1573 xfer->mfindex_kick += 0x4000; 1574 } 1575 } 1576 } 1577 1578 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1579 XHCIEPContext *epctx, uint64_t mfindex) 1580 { 1581 if (xfer->mfindex_kick > mfindex) { 1582 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1583 (xfer->mfindex_kick - mfindex) * 125000); 1584 xfer->running_retry = 1; 1585 } else { 1586 epctx->mfindex_last = xfer->mfindex_kick; 1587 qemu_del_timer(epctx->kick_timer); 1588 xfer->running_retry = 0; 1589 } 1590 } 1591 1592 1593 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1594 { 1595 uint64_t mfindex; 1596 int ret; 1597 1598 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1599 1600 xfer->in_xfer = epctx->type>>2; 1601 1602 switch(epctx->type) { 1603 case ET_INTR_OUT: 1604 case ET_INTR_IN: 1605 case ET_BULK_OUT: 1606 case ET_BULK_IN: 1607 xfer->pkts = 0; 1608 xfer->iso_xfer = false; 1609 break; 1610 case ET_ISO_OUT: 1611 case ET_ISO_IN: 1612 xfer->pkts = 1; 1613 xfer->iso_xfer = true; 1614 mfindex = xhci_mfindex_get(xhci); 1615 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1616 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1617 if (xfer->running_retry) { 1618 return -1; 1619 } 1620 break; 1621 default: 1622 fprintf(stderr, "xhci: unknown or unhandled EP " 1623 "(type %d, in %d, ep %02x)\n", 1624 epctx->type, xfer->in_xfer, xfer->epid); 1625 return -1; 1626 } 1627 1628 if (xhci_setup_packet(xfer) < 0) { 1629 return -1; 1630 } 1631 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1632 1633 xhci_complete_packet(xfer, ret); 1634 if (!xfer->running_async && !xfer->running_retry) { 1635 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1636 } 1637 return 0; 1638 } 1639 1640 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1641 { 1642 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1643 return xhci_submit(xhci, xfer, epctx); 1644 } 1645 1646 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1647 { 1648 XHCIEPContext *epctx; 1649 uint64_t mfindex; 1650 int length; 1651 int i; 1652 1653 trace_usb_xhci_ep_kick(slotid, epid); 1654 assert(slotid >= 1 && slotid <= MAXSLOTS); 1655 assert(epid >= 1 && epid <= 31); 1656 1657 if (!xhci->slots[slotid-1].enabled) { 1658 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1659 return; 1660 } 1661 epctx = xhci->slots[slotid-1].eps[epid-1]; 1662 if (!epctx) { 1663 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1664 epid, slotid); 1665 return; 1666 } 1667 1668 if (epctx->retry) { 1669 XHCITransfer *xfer = epctx->retry; 1670 int result; 1671 1672 trace_usb_xhci_xfer_retry(xfer); 1673 assert(xfer->running_retry); 1674 if (xfer->iso_xfer) { 1675 /* retry delayed iso transfer */ 1676 mfindex = xhci_mfindex_get(xhci); 1677 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1678 if (xfer->running_retry) { 1679 return; 1680 } 1681 if (xhci_setup_packet(xfer) < 0) { 1682 return; 1683 } 1684 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1685 assert(result != USB_RET_NAK); 1686 xhci_complete_packet(xfer, result); 1687 } else { 1688 /* retry nak'ed transfer */ 1689 if (xhci_setup_packet(xfer) < 0) { 1690 return; 1691 } 1692 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1693 if (result == USB_RET_NAK) { 1694 return; 1695 } 1696 xhci_complete_packet(xfer, result); 1697 } 1698 assert(!xfer->running_retry); 1699 epctx->retry = NULL; 1700 } 1701 1702 if (epctx->state == EP_HALTED) { 1703 DPRINTF("xhci: ep halted, not running schedule\n"); 1704 return; 1705 } 1706 1707 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1708 1709 while (1) { 1710 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1711 if (xfer->running_async || xfer->running_retry) { 1712 break; 1713 } 1714 length = xhci_ring_chain_length(xhci, &epctx->ring); 1715 if (length < 0) { 1716 break; 1717 } else if (length == 0) { 1718 break; 1719 } 1720 if (xfer->trbs && xfer->trb_alloced < length) { 1721 xfer->trb_count = 0; 1722 xfer->trb_alloced = 0; 1723 g_free(xfer->trbs); 1724 xfer->trbs = NULL; 1725 } 1726 if (!xfer->trbs) { 1727 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1728 xfer->trb_alloced = length; 1729 } 1730 xfer->trb_count = length; 1731 1732 for (i = 0; i < length; i++) { 1733 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1734 } 1735 xfer->xhci = xhci; 1736 xfer->epid = epid; 1737 xfer->slotid = slotid; 1738 1739 if (epid == 1) { 1740 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1741 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1742 } else { 1743 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1744 } 1745 } else { 1746 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1747 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1748 } else { 1749 if (!xfer->iso_xfer) { 1750 fprintf(stderr, "xhci: error firing data transfer\n"); 1751 } 1752 } 1753 } 1754 1755 if (epctx->state == EP_HALTED) { 1756 break; 1757 } 1758 if (xfer->running_retry) { 1759 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1760 epctx->retry = xfer; 1761 break; 1762 } 1763 } 1764 } 1765 1766 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1767 { 1768 trace_usb_xhci_slot_enable(slotid); 1769 assert(slotid >= 1 && slotid <= MAXSLOTS); 1770 xhci->slots[slotid-1].enabled = 1; 1771 xhci->slots[slotid-1].port = 0; 1772 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1773 1774 return CC_SUCCESS; 1775 } 1776 1777 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1778 { 1779 int i; 1780 1781 trace_usb_xhci_slot_disable(slotid); 1782 assert(slotid >= 1 && slotid <= MAXSLOTS); 1783 1784 for (i = 1; i <= 31; i++) { 1785 if (xhci->slots[slotid-1].eps[i-1]) { 1786 xhci_disable_ep(xhci, slotid, i); 1787 } 1788 } 1789 1790 xhci->slots[slotid-1].enabled = 0; 1791 return CC_SUCCESS; 1792 } 1793 1794 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1795 uint64_t pictx, bool bsr) 1796 { 1797 XHCISlot *slot; 1798 USBDevice *dev; 1799 dma_addr_t ictx, octx, dcbaap; 1800 uint64_t poctx; 1801 uint32_t ictl_ctx[2]; 1802 uint32_t slot_ctx[4]; 1803 uint32_t ep0_ctx[5]; 1804 unsigned int port; 1805 int i; 1806 TRBCCode res; 1807 1808 trace_usb_xhci_slot_address(slotid); 1809 assert(slotid >= 1 && slotid <= MAXSLOTS); 1810 1811 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1812 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1813 ictx = xhci_mask64(pictx); 1814 octx = xhci_mask64(le64_to_cpu(poctx)); 1815 1816 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1817 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1818 1819 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1820 1821 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1822 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1823 ictl_ctx[0], ictl_ctx[1]); 1824 return CC_TRB_ERROR; 1825 } 1826 1827 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1828 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1829 1830 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1831 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1832 1833 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1834 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1835 1836 port = (slot_ctx[1]>>16) & 0xFF; 1837 dev = xhci->ports[port-1].uport->dev; 1838 1839 if (port < 1 || port > xhci->numports) { 1840 fprintf(stderr, "xhci: bad port %d\n", port); 1841 return CC_TRB_ERROR; 1842 } else if (!dev) { 1843 fprintf(stderr, "xhci: port %d not connected\n", port); 1844 return CC_USB_TRANSACTION_ERROR; 1845 } 1846 1847 for (i = 0; i < MAXSLOTS; i++) { 1848 if (xhci->slots[i].port == port) { 1849 fprintf(stderr, "xhci: port %d already assigned to slot %d\n", 1850 port, i+1); 1851 return CC_TRB_ERROR; 1852 } 1853 } 1854 1855 slot = &xhci->slots[slotid-1]; 1856 slot->port = port; 1857 slot->ctx = octx; 1858 1859 if (bsr) { 1860 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1861 } else { 1862 slot->devaddr = xhci->devaddr++; 1863 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1864 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1865 usb_device_handle_control(dev, NULL, 1866 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1867 slot->devaddr, 0, 0, NULL); 1868 } 1869 1870 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1871 1872 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1873 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1874 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1875 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1876 1877 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1878 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1879 1880 return res; 1881 } 1882 1883 1884 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1885 uint64_t pictx, bool dc) 1886 { 1887 dma_addr_t ictx, octx; 1888 uint32_t ictl_ctx[2]; 1889 uint32_t slot_ctx[4]; 1890 uint32_t islot_ctx[4]; 1891 uint32_t ep_ctx[5]; 1892 int i; 1893 TRBCCode res; 1894 1895 trace_usb_xhci_slot_configure(slotid); 1896 assert(slotid >= 1 && slotid <= MAXSLOTS); 1897 1898 ictx = xhci_mask64(pictx); 1899 octx = xhci->slots[slotid-1].ctx; 1900 1901 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1902 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1903 1904 if (dc) { 1905 for (i = 2; i <= 31; i++) { 1906 if (xhci->slots[slotid-1].eps[i-1]) { 1907 xhci_disable_ep(xhci, slotid, i); 1908 } 1909 } 1910 1911 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1912 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1913 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1914 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1915 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1916 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1917 1918 return CC_SUCCESS; 1919 } 1920 1921 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1922 1923 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1924 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1925 ictl_ctx[0], ictl_ctx[1]); 1926 return CC_TRB_ERROR; 1927 } 1928 1929 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1930 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1931 1932 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1933 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1934 return CC_CONTEXT_STATE_ERROR; 1935 } 1936 1937 for (i = 2; i <= 31; i++) { 1938 if (ictl_ctx[0] & (1<<i)) { 1939 xhci_disable_ep(xhci, slotid, i); 1940 } 1941 if (ictl_ctx[1] & (1<<i)) { 1942 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1943 sizeof(ep_ctx)); 1944 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1945 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1946 ep_ctx[3], ep_ctx[4]); 1947 xhci_disable_ep(xhci, slotid, i); 1948 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1949 if (res != CC_SUCCESS) { 1950 return res; 1951 } 1952 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 1953 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1954 ep_ctx[3], ep_ctx[4]); 1955 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 1956 } 1957 } 1958 1959 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1960 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 1961 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 1962 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 1963 SLOT_CONTEXT_ENTRIES_SHIFT); 1964 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1965 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1966 1967 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1968 1969 return CC_SUCCESS; 1970 } 1971 1972 1973 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 1974 uint64_t pictx) 1975 { 1976 dma_addr_t ictx, octx; 1977 uint32_t ictl_ctx[2]; 1978 uint32_t iep0_ctx[5]; 1979 uint32_t ep0_ctx[5]; 1980 uint32_t islot_ctx[4]; 1981 uint32_t slot_ctx[4]; 1982 1983 trace_usb_xhci_slot_evaluate(slotid); 1984 assert(slotid >= 1 && slotid <= MAXSLOTS); 1985 1986 ictx = xhci_mask64(pictx); 1987 octx = xhci->slots[slotid-1].ctx; 1988 1989 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1990 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1991 1992 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1993 1994 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 1995 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1996 ictl_ctx[0], ictl_ctx[1]); 1997 return CC_TRB_ERROR; 1998 } 1999 2000 if (ictl_ctx[1] & 0x1) { 2001 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2002 2003 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2004 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2005 2006 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2007 2008 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2009 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2010 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2011 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2012 2013 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2014 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2015 2016 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2017 } 2018 2019 if (ictl_ctx[1] & 0x2) { 2020 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2021 2022 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2023 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2024 iep0_ctx[3], iep0_ctx[4]); 2025 2026 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2027 2028 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2029 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2030 2031 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2032 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2033 2034 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2035 } 2036 2037 return CC_SUCCESS; 2038 } 2039 2040 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2041 { 2042 uint32_t slot_ctx[4]; 2043 dma_addr_t octx; 2044 int i; 2045 2046 trace_usb_xhci_slot_reset(slotid); 2047 assert(slotid >= 1 && slotid <= MAXSLOTS); 2048 2049 octx = xhci->slots[slotid-1].ctx; 2050 2051 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2052 2053 for (i = 2; i <= 31; i++) { 2054 if (xhci->slots[slotid-1].eps[i-1]) { 2055 xhci_disable_ep(xhci, slotid, i); 2056 } 2057 } 2058 2059 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2060 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2061 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2062 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2063 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2064 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2065 2066 return CC_SUCCESS; 2067 } 2068 2069 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2070 { 2071 unsigned int slotid; 2072 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2073 if (slotid < 1 || slotid > MAXSLOTS) { 2074 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2075 event->ccode = CC_TRB_ERROR; 2076 return 0; 2077 } else if (!xhci->slots[slotid-1].enabled) { 2078 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2079 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2080 return 0; 2081 } 2082 return slotid; 2083 } 2084 2085 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2086 { 2087 dma_addr_t ctx; 2088 uint8_t bw_ctx[xhci->numports+1]; 2089 2090 DPRINTF("xhci_get_port_bandwidth()\n"); 2091 2092 ctx = xhci_mask64(pctx); 2093 2094 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2095 2096 /* TODO: actually implement real values here */ 2097 bw_ctx[0] = 0; 2098 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2099 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2100 2101 return CC_SUCCESS; 2102 } 2103 2104 static uint32_t rotl(uint32_t v, unsigned count) 2105 { 2106 count &= 31; 2107 return (v << count) | (v >> (32 - count)); 2108 } 2109 2110 2111 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2112 { 2113 uint32_t val; 2114 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2115 val += rotl(lo + 0x49434878, hi & 0x1F); 2116 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2117 return ~val; 2118 } 2119 2120 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2121 { 2122 uint32_t buf[8]; 2123 uint32_t obuf[8]; 2124 dma_addr_t paddr = xhci_mask64(addr); 2125 2126 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2127 2128 memcpy(obuf, buf, sizeof(obuf)); 2129 2130 if ((buf[0] & 0xff) == 2) { 2131 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2132 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2133 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2134 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2135 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2136 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2137 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2138 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2139 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2140 } 2141 2142 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2143 } 2144 2145 static void xhci_process_commands(XHCIState *xhci) 2146 { 2147 XHCITRB trb; 2148 TRBType type; 2149 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2150 dma_addr_t addr; 2151 unsigned int i, slotid = 0; 2152 2153 DPRINTF("xhci_process_commands()\n"); 2154 if (!xhci_running(xhci)) { 2155 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2156 return; 2157 } 2158 2159 xhci->crcr_low |= CRCR_CRR; 2160 2161 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2162 event.ptr = addr; 2163 switch (type) { 2164 case CR_ENABLE_SLOT: 2165 for (i = 0; i < MAXSLOTS; i++) { 2166 if (!xhci->slots[i].enabled) { 2167 break; 2168 } 2169 } 2170 if (i >= MAXSLOTS) { 2171 fprintf(stderr, "xhci: no device slots available\n"); 2172 event.ccode = CC_NO_SLOTS_ERROR; 2173 } else { 2174 slotid = i+1; 2175 event.ccode = xhci_enable_slot(xhci, slotid); 2176 } 2177 break; 2178 case CR_DISABLE_SLOT: 2179 slotid = xhci_get_slot(xhci, &event, &trb); 2180 if (slotid) { 2181 event.ccode = xhci_disable_slot(xhci, slotid); 2182 } 2183 break; 2184 case CR_ADDRESS_DEVICE: 2185 slotid = xhci_get_slot(xhci, &event, &trb); 2186 if (slotid) { 2187 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2188 trb.control & TRB_CR_BSR); 2189 } 2190 break; 2191 case CR_CONFIGURE_ENDPOINT: 2192 slotid = xhci_get_slot(xhci, &event, &trb); 2193 if (slotid) { 2194 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2195 trb.control & TRB_CR_DC); 2196 } 2197 break; 2198 case CR_EVALUATE_CONTEXT: 2199 slotid = xhci_get_slot(xhci, &event, &trb); 2200 if (slotid) { 2201 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2202 } 2203 break; 2204 case CR_STOP_ENDPOINT: 2205 slotid = xhci_get_slot(xhci, &event, &trb); 2206 if (slotid) { 2207 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2208 & TRB_CR_EPID_MASK; 2209 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2210 } 2211 break; 2212 case CR_RESET_ENDPOINT: 2213 slotid = xhci_get_slot(xhci, &event, &trb); 2214 if (slotid) { 2215 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2216 & TRB_CR_EPID_MASK; 2217 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2218 } 2219 break; 2220 case CR_SET_TR_DEQUEUE: 2221 slotid = xhci_get_slot(xhci, &event, &trb); 2222 if (slotid) { 2223 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2224 & TRB_CR_EPID_MASK; 2225 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2226 trb.parameter); 2227 } 2228 break; 2229 case CR_RESET_DEVICE: 2230 slotid = xhci_get_slot(xhci, &event, &trb); 2231 if (slotid) { 2232 event.ccode = xhci_reset_slot(xhci, slotid); 2233 } 2234 break; 2235 case CR_GET_PORT_BANDWIDTH: 2236 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2237 break; 2238 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2239 xhci_via_challenge(xhci, trb.parameter); 2240 break; 2241 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2242 event.type = 48; /* NEC reply */ 2243 event.length = 0x3025; 2244 break; 2245 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2246 { 2247 uint32_t chi = trb.parameter >> 32; 2248 uint32_t clo = trb.parameter; 2249 uint32_t val = xhci_nec_challenge(chi, clo); 2250 event.length = val & 0xFFFF; 2251 event.epid = val >> 16; 2252 slotid = val >> 24; 2253 event.type = 48; /* NEC reply */ 2254 } 2255 break; 2256 default: 2257 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2258 event.ccode = CC_TRB_ERROR; 2259 break; 2260 } 2261 event.slotid = slotid; 2262 xhci_event(xhci, &event, 0); 2263 } 2264 } 2265 2266 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2267 { 2268 port->portsc = PORTSC_PP; 2269 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2270 (1 << port->uport->dev->speed) & port->speedmask) { 2271 port->portsc |= PORTSC_CCS; 2272 switch (port->uport->dev->speed) { 2273 case USB_SPEED_LOW: 2274 port->portsc |= PORTSC_SPEED_LOW; 2275 break; 2276 case USB_SPEED_FULL: 2277 port->portsc |= PORTSC_SPEED_FULL; 2278 break; 2279 case USB_SPEED_HIGH: 2280 port->portsc |= PORTSC_SPEED_HIGH; 2281 break; 2282 case USB_SPEED_SUPER: 2283 port->portsc |= PORTSC_SPEED_SUPER; 2284 break; 2285 } 2286 } 2287 2288 if (xhci_running(xhci)) { 2289 port->portsc |= PORTSC_CSC; 2290 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2291 port->portnr << 24}; 2292 xhci_event(xhci, &ev, 0); 2293 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2294 } 2295 } 2296 2297 static void xhci_reset(DeviceState *dev) 2298 { 2299 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2300 int i; 2301 2302 trace_usb_xhci_reset(); 2303 if (!(xhci->usbsts & USBSTS_HCH)) { 2304 fprintf(stderr, "xhci: reset while running!\n"); 2305 } 2306 2307 xhci->usbcmd = 0; 2308 xhci->usbsts = USBSTS_HCH; 2309 xhci->dnctrl = 0; 2310 xhci->crcr_low = 0; 2311 xhci->crcr_high = 0; 2312 xhci->dcbaap_low = 0; 2313 xhci->dcbaap_high = 0; 2314 xhci->config = 0; 2315 xhci->devaddr = 2; 2316 2317 for (i = 0; i < MAXSLOTS; i++) { 2318 xhci_disable_slot(xhci, i+1); 2319 } 2320 2321 for (i = 0; i < xhci->numports; i++) { 2322 xhci_update_port(xhci, xhci->ports + i, 0); 2323 } 2324 2325 for (i = 0; i < MAXINTRS; i++) { 2326 xhci->intr[i].iman = 0; 2327 xhci->intr[i].imod = 0; 2328 xhci->intr[i].erstsz = 0; 2329 xhci->intr[i].erstba_low = 0; 2330 xhci->intr[i].erstba_high = 0; 2331 xhci->intr[i].erdp_low = 0; 2332 xhci->intr[i].erdp_high = 0; 2333 xhci->intr[i].msix_used = 0; 2334 2335 xhci->intr[i].er_ep_idx = 0; 2336 xhci->intr[i].er_pcs = 1; 2337 xhci->intr[i].er_full = 0; 2338 xhci->intr[i].ev_buffer_put = 0; 2339 xhci->intr[i].ev_buffer_get = 0; 2340 } 2341 2342 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2343 xhci_mfwrap_update(xhci); 2344 } 2345 2346 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg) 2347 { 2348 uint32_t ret; 2349 2350 switch (reg) { 2351 case 0x00: /* HCIVERSION, CAPLENGTH */ 2352 ret = 0x01000000 | LEN_CAP; 2353 break; 2354 case 0x04: /* HCSPARAMS 1 */ 2355 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2356 | (MAXINTRS<<8) | MAXSLOTS; 2357 break; 2358 case 0x08: /* HCSPARAMS 2 */ 2359 ret = 0x0000000f; 2360 break; 2361 case 0x0c: /* HCSPARAMS 3 */ 2362 ret = 0x00000000; 2363 break; 2364 case 0x10: /* HCCPARAMS */ 2365 if (sizeof(dma_addr_t) == 4) { 2366 ret = 0x00081000; 2367 } else { 2368 ret = 0x00081001; 2369 } 2370 break; 2371 case 0x14: /* DBOFF */ 2372 ret = OFF_DOORBELL; 2373 break; 2374 case 0x18: /* RTSOFF */ 2375 ret = OFF_RUNTIME; 2376 break; 2377 2378 /* extended capabilities */ 2379 case 0x20: /* Supported Protocol:00 */ 2380 ret = 0x02000402; /* USB 2.0 */ 2381 break; 2382 case 0x24: /* Supported Protocol:04 */ 2383 ret = 0x20425455; /* "USB " */ 2384 break; 2385 case 0x28: /* Supported Protocol:08 */ 2386 ret = 0x00000001 | (xhci->numports_2<<8); 2387 break; 2388 case 0x2c: /* Supported Protocol:0c */ 2389 ret = 0x00000000; /* reserved */ 2390 break; 2391 case 0x30: /* Supported Protocol:00 */ 2392 ret = 0x03000002; /* USB 3.0 */ 2393 break; 2394 case 0x34: /* Supported Protocol:04 */ 2395 ret = 0x20425455; /* "USB " */ 2396 break; 2397 case 0x38: /* Supported Protocol:08 */ 2398 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2399 break; 2400 case 0x3c: /* Supported Protocol:0c */ 2401 ret = 0x00000000; /* reserved */ 2402 break; 2403 default: 2404 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg); 2405 ret = 0; 2406 } 2407 2408 trace_usb_xhci_cap_read(reg, ret); 2409 return ret; 2410 } 2411 2412 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg) 2413 { 2414 uint32_t port = reg >> 4; 2415 uint32_t ret; 2416 2417 if (port >= xhci->numports) { 2418 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2419 ret = 0; 2420 goto out; 2421 } 2422 2423 switch (reg & 0xf) { 2424 case 0x00: /* PORTSC */ 2425 ret = xhci->ports[port].portsc; 2426 break; 2427 case 0x04: /* PORTPMSC */ 2428 case 0x08: /* PORTLI */ 2429 ret = 0; 2430 break; 2431 case 0x0c: /* reserved */ 2432 default: 2433 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2434 port, reg); 2435 ret = 0; 2436 } 2437 2438 out: 2439 trace_usb_xhci_port_read(port, reg & 0x0f, ret); 2440 return ret; 2441 } 2442 2443 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2444 { 2445 uint32_t port = reg >> 4; 2446 uint32_t portsc; 2447 2448 trace_usb_xhci_port_write(port, reg & 0x0f, val); 2449 2450 if (port >= xhci->numports) { 2451 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2452 return; 2453 } 2454 2455 switch (reg & 0xf) { 2456 case 0x00: /* PORTSC */ 2457 portsc = xhci->ports[port].portsc; 2458 /* write-1-to-clear bits*/ 2459 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2460 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2461 if (val & PORTSC_LWS) { 2462 /* overwrite PLS only when LWS=1 */ 2463 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2464 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2465 } 2466 /* read/write bits */ 2467 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2468 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2469 /* write-1-to-start bits */ 2470 if (val & PORTSC_PR) { 2471 DPRINTF("xhci: port %d reset\n", port); 2472 usb_device_reset(xhci->ports[port].uport->dev); 2473 portsc |= PORTSC_PRC | PORTSC_PED; 2474 } 2475 xhci->ports[port].portsc = portsc; 2476 break; 2477 case 0x04: /* PORTPMSC */ 2478 case 0x08: /* PORTLI */ 2479 default: 2480 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2481 port, reg); 2482 } 2483 } 2484 2485 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg) 2486 { 2487 uint32_t ret; 2488 2489 if (reg >= 0x400) { 2490 return xhci_port_read(xhci, reg - 0x400); 2491 } 2492 2493 switch (reg) { 2494 case 0x00: /* USBCMD */ 2495 ret = xhci->usbcmd; 2496 break; 2497 case 0x04: /* USBSTS */ 2498 ret = xhci->usbsts; 2499 break; 2500 case 0x08: /* PAGESIZE */ 2501 ret = 1; /* 4KiB */ 2502 break; 2503 case 0x14: /* DNCTRL */ 2504 ret = xhci->dnctrl; 2505 break; 2506 case 0x18: /* CRCR low */ 2507 ret = xhci->crcr_low & ~0xe; 2508 break; 2509 case 0x1c: /* CRCR high */ 2510 ret = xhci->crcr_high; 2511 break; 2512 case 0x30: /* DCBAAP low */ 2513 ret = xhci->dcbaap_low; 2514 break; 2515 case 0x34: /* DCBAAP high */ 2516 ret = xhci->dcbaap_high; 2517 break; 2518 case 0x38: /* CONFIG */ 2519 ret = xhci->config; 2520 break; 2521 default: 2522 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg); 2523 ret = 0; 2524 } 2525 2526 trace_usb_xhci_oper_read(reg, ret); 2527 return ret; 2528 } 2529 2530 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2531 { 2532 if (reg >= 0x400) { 2533 xhci_port_write(xhci, reg - 0x400, val); 2534 return; 2535 } 2536 2537 trace_usb_xhci_oper_write(reg, val); 2538 2539 switch (reg) { 2540 case 0x00: /* USBCMD */ 2541 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2542 xhci_run(xhci); 2543 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2544 xhci_stop(xhci); 2545 } 2546 xhci->usbcmd = val & 0xc0f; 2547 xhci_mfwrap_update(xhci); 2548 if (val & USBCMD_HCRST) { 2549 xhci_reset(&xhci->pci_dev.qdev); 2550 } 2551 xhci_intx_update(xhci); 2552 break; 2553 2554 case 0x04: /* USBSTS */ 2555 /* these bits are write-1-to-clear */ 2556 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2557 xhci_intx_update(xhci); 2558 break; 2559 2560 case 0x14: /* DNCTRL */ 2561 xhci->dnctrl = val & 0xffff; 2562 break; 2563 case 0x18: /* CRCR low */ 2564 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2565 break; 2566 case 0x1c: /* CRCR high */ 2567 xhci->crcr_high = val; 2568 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2569 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2570 xhci->crcr_low &= ~CRCR_CRR; 2571 xhci_event(xhci, &event, 0); 2572 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2573 } else { 2574 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2575 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2576 } 2577 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2578 break; 2579 case 0x30: /* DCBAAP low */ 2580 xhci->dcbaap_low = val & 0xffffffc0; 2581 break; 2582 case 0x34: /* DCBAAP high */ 2583 xhci->dcbaap_high = val; 2584 break; 2585 case 0x38: /* CONFIG */ 2586 xhci->config = val & 0xff; 2587 break; 2588 default: 2589 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg); 2590 } 2591 } 2592 2593 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg) 2594 { 2595 uint32_t ret = 0; 2596 2597 if (reg < 0x20) { 2598 switch (reg) { 2599 case 0x00: /* MFINDEX */ 2600 ret = xhci_mfindex_get(xhci) & 0x3fff; 2601 break; 2602 default: 2603 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg); 2604 break; 2605 } 2606 } else { 2607 int v = (reg - 0x20) / 0x20; 2608 XHCIInterrupter *intr = &xhci->intr[v]; 2609 switch (reg & 0x1f) { 2610 case 0x00: /* IMAN */ 2611 ret = intr->iman; 2612 break; 2613 case 0x04: /* IMOD */ 2614 ret = intr->imod; 2615 break; 2616 case 0x08: /* ERSTSZ */ 2617 ret = intr->erstsz; 2618 break; 2619 case 0x10: /* ERSTBA low */ 2620 ret = intr->erstba_low; 2621 break; 2622 case 0x14: /* ERSTBA high */ 2623 ret = intr->erstba_high; 2624 break; 2625 case 0x18: /* ERDP low */ 2626 ret = intr->erdp_low; 2627 break; 2628 case 0x1c: /* ERDP high */ 2629 ret = intr->erdp_high; 2630 break; 2631 } 2632 } 2633 2634 trace_usb_xhci_runtime_read(reg, ret); 2635 return ret; 2636 } 2637 2638 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2639 { 2640 int v = (reg - 0x20) / 0x20; 2641 XHCIInterrupter *intr = &xhci->intr[v]; 2642 trace_usb_xhci_runtime_write(reg, val); 2643 2644 if (reg < 0x20) { 2645 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg); 2646 return; 2647 } 2648 2649 switch (reg & 0x1f) { 2650 case 0x00: /* IMAN */ 2651 if (val & IMAN_IP) { 2652 intr->iman &= ~IMAN_IP; 2653 } 2654 intr->iman &= ~IMAN_IE; 2655 intr->iman |= val & IMAN_IE; 2656 if (v == 0) { 2657 xhci_intx_update(xhci); 2658 } 2659 xhci_msix_update(xhci, v); 2660 break; 2661 case 0x04: /* IMOD */ 2662 intr->imod = val; 2663 break; 2664 case 0x08: /* ERSTSZ */ 2665 intr->erstsz = val & 0xffff; 2666 break; 2667 case 0x10: /* ERSTBA low */ 2668 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2669 intr->erstba_low = val & 0xffffffc0; */ 2670 intr->erstba_low = val & 0xfffffff0; 2671 break; 2672 case 0x14: /* ERSTBA high */ 2673 intr->erstba_high = val; 2674 xhci_er_reset(xhci, v); 2675 break; 2676 case 0x18: /* ERDP low */ 2677 if (val & ERDP_EHB) { 2678 intr->erdp_low &= ~ERDP_EHB; 2679 } 2680 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2681 break; 2682 case 0x1c: /* ERDP high */ 2683 intr->erdp_high = val; 2684 xhci_events_update(xhci, v); 2685 break; 2686 default: 2687 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg); 2688 } 2689 } 2690 2691 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg) 2692 { 2693 /* doorbells always read as 0 */ 2694 trace_usb_xhci_doorbell_read(reg, 0); 2695 return 0; 2696 } 2697 2698 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2699 { 2700 trace_usb_xhci_doorbell_write(reg, val); 2701 2702 if (!xhci_running(xhci)) { 2703 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2704 return; 2705 } 2706 2707 reg >>= 2; 2708 2709 if (reg == 0) { 2710 if (val == 0) { 2711 xhci_process_commands(xhci); 2712 } else { 2713 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val); 2714 } 2715 } else { 2716 if (reg > MAXSLOTS) { 2717 fprintf(stderr, "xhci: bad doorbell %d\n", reg); 2718 } else if (val > 31) { 2719 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val); 2720 } else { 2721 xhci_kick_ep(xhci, reg, val); 2722 } 2723 } 2724 } 2725 2726 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr, 2727 unsigned size) 2728 { 2729 XHCIState *xhci = ptr; 2730 2731 /* Only aligned reads are allowed on xHCI */ 2732 if (addr & 3) { 2733 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n"); 2734 return 0; 2735 } 2736 2737 if (addr < LEN_CAP) { 2738 return xhci_cap_read(xhci, addr); 2739 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { 2740 return xhci_oper_read(xhci, addr - OFF_OPER); 2741 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { 2742 return xhci_runtime_read(xhci, addr - OFF_RUNTIME); 2743 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { 2744 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL); 2745 } else { 2746 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr); 2747 return 0; 2748 } 2749 } 2750 2751 static void xhci_mem_write(void *ptr, target_phys_addr_t addr, 2752 uint64_t val, unsigned size) 2753 { 2754 XHCIState *xhci = ptr; 2755 2756 /* Only aligned writes are allowed on xHCI */ 2757 if (addr & 3) { 2758 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n"); 2759 return; 2760 } 2761 2762 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { 2763 xhci_oper_write(xhci, addr - OFF_OPER, val); 2764 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { 2765 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val); 2766 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { 2767 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val); 2768 } else { 2769 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr); 2770 } 2771 } 2772 2773 static const MemoryRegionOps xhci_mem_ops = { 2774 .read = xhci_mem_read, 2775 .write = xhci_mem_write, 2776 .valid.min_access_size = 4, 2777 .valid.max_access_size = 4, 2778 .endianness = DEVICE_LITTLE_ENDIAN, 2779 }; 2780 2781 static void xhci_attach(USBPort *usbport) 2782 { 2783 XHCIState *xhci = usbport->opaque; 2784 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2785 2786 xhci_update_port(xhci, port, 0); 2787 } 2788 2789 static void xhci_detach(USBPort *usbport) 2790 { 2791 XHCIState *xhci = usbport->opaque; 2792 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2793 2794 xhci_update_port(xhci, port, 1); 2795 } 2796 2797 static void xhci_wakeup(USBPort *usbport) 2798 { 2799 XHCIState *xhci = usbport->opaque; 2800 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2801 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2802 port->portnr << 24}; 2803 uint32_t pls; 2804 2805 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2806 if (pls != 3) { 2807 return; 2808 } 2809 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2810 if (port->portsc & PORTSC_PLC) { 2811 return; 2812 } 2813 port->portsc |= PORTSC_PLC; 2814 xhci_event(xhci, &ev, 0); 2815 } 2816 2817 static void xhci_complete(USBPort *port, USBPacket *packet) 2818 { 2819 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2820 2821 xhci_complete_packet(xfer, packet->result); 2822 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2823 } 2824 2825 static void xhci_child_detach(USBPort *port, USBDevice *child) 2826 { 2827 FIXME(); 2828 } 2829 2830 static USBPortOps xhci_port_ops = { 2831 .attach = xhci_attach, 2832 .detach = xhci_detach, 2833 .wakeup = xhci_wakeup, 2834 .complete = xhci_complete, 2835 .child_detach = xhci_child_detach, 2836 }; 2837 2838 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2839 { 2840 XHCISlot *slot; 2841 int slotid; 2842 2843 for (slotid = 1; slotid <= MAXSLOTS; slotid++) { 2844 slot = &xhci->slots[slotid-1]; 2845 if (slot->devaddr == dev->addr) { 2846 return slotid; 2847 } 2848 } 2849 return 0; 2850 } 2851 2852 static int xhci_find_epid(USBEndpoint *ep) 2853 { 2854 if (ep->nr == 0) { 2855 return 1; 2856 } 2857 if (ep->pid == USB_TOKEN_IN) { 2858 return ep->nr * 2 + 1; 2859 } else { 2860 return ep->nr * 2; 2861 } 2862 } 2863 2864 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2865 { 2866 XHCIState *xhci = container_of(bus, XHCIState, bus); 2867 int slotid; 2868 2869 DPRINTF("%s\n", __func__); 2870 slotid = xhci_find_slotid(xhci, ep->dev); 2871 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2872 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2873 return; 2874 } 2875 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2876 } 2877 2878 static USBBusOps xhci_bus_ops = { 2879 .wakeup_endpoint = xhci_wakeup_endpoint, 2880 }; 2881 2882 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2883 { 2884 XHCIPort *port; 2885 int i, usbports, speedmask; 2886 2887 xhci->usbsts = USBSTS_HCH; 2888 2889 if (xhci->numports_2 > MAXPORTS_2) { 2890 xhci->numports_2 = MAXPORTS_2; 2891 } 2892 if (xhci->numports_3 > MAXPORTS_3) { 2893 xhci->numports_3 = MAXPORTS_3; 2894 } 2895 usbports = MAX(xhci->numports_2, xhci->numports_3); 2896 xhci->numports = xhci->numports_2 + xhci->numports_3; 2897 2898 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2899 2900 for (i = 0; i < usbports; i++) { 2901 speedmask = 0; 2902 if (i < xhci->numports_2) { 2903 port = &xhci->ports[i]; 2904 port->portnr = i + 1; 2905 port->uport = &xhci->uports[i]; 2906 port->speedmask = 2907 USB_SPEED_MASK_LOW | 2908 USB_SPEED_MASK_FULL | 2909 USB_SPEED_MASK_HIGH; 2910 speedmask |= port->speedmask; 2911 } 2912 if (i < xhci->numports_3) { 2913 port = &xhci->ports[i + xhci->numports_2]; 2914 port->portnr = i + 1 + xhci->numports_2; 2915 port->uport = &xhci->uports[i]; 2916 port->speedmask = USB_SPEED_MASK_SUPER; 2917 speedmask |= port->speedmask; 2918 } 2919 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2920 &xhci_port_ops, speedmask); 2921 } 2922 } 2923 2924 static int usb_xhci_initfn(struct PCIDevice *dev) 2925 { 2926 int ret; 2927 2928 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2929 2930 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2931 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2932 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2933 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2934 2935 usb_xhci_init(xhci, &dev->qdev); 2936 2937 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2938 2939 xhci->irq = xhci->pci_dev.irq[0]; 2940 2941 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci, 2942 "xhci", LEN_REGS); 2943 pci_register_bar(&xhci->pci_dev, 0, 2944 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 2945 &xhci->mem); 2946 2947 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 2948 assert(ret >= 0); 2949 2950 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 2951 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); 2952 } 2953 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 2954 msix_init(&xhci->pci_dev, MAXINTRS, 2955 &xhci->mem, 0, OFF_MSIX_TABLE, 2956 &xhci->mem, 0, OFF_MSIX_PBA, 2957 0x90); 2958 } 2959 2960 return 0; 2961 } 2962 2963 static const VMStateDescription vmstate_xhci = { 2964 .name = "xhci", 2965 .unmigratable = 1, 2966 }; 2967 2968 static Property xhci_properties[] = { 2969 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 2970 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 2971 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 2972 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 2973 DEFINE_PROP_END_OF_LIST(), 2974 }; 2975 2976 static void xhci_class_init(ObjectClass *klass, void *data) 2977 { 2978 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2979 DeviceClass *dc = DEVICE_CLASS(klass); 2980 2981 dc->vmsd = &vmstate_xhci; 2982 dc->props = xhci_properties; 2983 dc->reset = xhci_reset; 2984 k->init = usb_xhci_initfn; 2985 k->vendor_id = PCI_VENDOR_ID_NEC; 2986 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 2987 k->class_id = PCI_CLASS_SERIAL_USB; 2988 k->revision = 0x03; 2989 k->is_express = 1; 2990 } 2991 2992 static TypeInfo xhci_info = { 2993 .name = "nec-usb-xhci", 2994 .parent = TYPE_PCI_DEVICE, 2995 .instance_size = sizeof(XHCIState), 2996 .class_init = xhci_class_init, 2997 }; 2998 2999 static void xhci_register_types(void) 3000 { 3001 type_register_static(&xhci_info); 3002 } 3003 3004 type_init(xhci_register_types) 3005