1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "qemu/queue.h" 25 #include "hw/usb.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/msix.h" 29 #include "trace.h" 30 #include "qapi/error.h" 31 32 //#define DEBUG_XHCI 33 //#define DEBUG_DATA 34 35 #ifdef DEBUG_XHCI 36 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 37 #else 38 #define DPRINTF(...) do {} while (0) 39 #endif 40 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 41 __func__, __LINE__, _msg); abort(); } while (0) 42 43 #define MAXPORTS_2 15 44 #define MAXPORTS_3 15 45 46 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 47 #define MAXSLOTS 64 48 #define MAXINTRS 16 49 50 /* Very pessimistic, let's hope it's enough for all cases */ 51 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 52 /* Do not deliver ER Full events. NEC's driver does some things not bound 53 * to the specs when it gets them */ 54 #define ER_FULL_HACK 55 56 #define TRB_LINK_LIMIT 4 57 58 #define LEN_CAP 0x40 59 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 60 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 61 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 62 63 #define OFF_OPER LEN_CAP 64 #define OFF_RUNTIME 0x1000 65 #define OFF_DOORBELL 0x2000 66 #define OFF_MSIX_TABLE 0x3000 67 #define OFF_MSIX_PBA 0x3800 68 /* must be power of 2 */ 69 #define LEN_REGS 0x4000 70 71 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 72 #error Increase OFF_RUNTIME 73 #endif 74 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 75 #error Increase OFF_DOORBELL 76 #endif 77 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 78 # error Increase LEN_REGS 79 #endif 80 81 /* bit definitions */ 82 #define USBCMD_RS (1<<0) 83 #define USBCMD_HCRST (1<<1) 84 #define USBCMD_INTE (1<<2) 85 #define USBCMD_HSEE (1<<3) 86 #define USBCMD_LHCRST (1<<7) 87 #define USBCMD_CSS (1<<8) 88 #define USBCMD_CRS (1<<9) 89 #define USBCMD_EWE (1<<10) 90 #define USBCMD_EU3S (1<<11) 91 92 #define USBSTS_HCH (1<<0) 93 #define USBSTS_HSE (1<<2) 94 #define USBSTS_EINT (1<<3) 95 #define USBSTS_PCD (1<<4) 96 #define USBSTS_SSS (1<<8) 97 #define USBSTS_RSS (1<<9) 98 #define USBSTS_SRE (1<<10) 99 #define USBSTS_CNR (1<<11) 100 #define USBSTS_HCE (1<<12) 101 102 103 #define PORTSC_CCS (1<<0) 104 #define PORTSC_PED (1<<1) 105 #define PORTSC_OCA (1<<3) 106 #define PORTSC_PR (1<<4) 107 #define PORTSC_PLS_SHIFT 5 108 #define PORTSC_PLS_MASK 0xf 109 #define PORTSC_PP (1<<9) 110 #define PORTSC_SPEED_SHIFT 10 111 #define PORTSC_SPEED_MASK 0xf 112 #define PORTSC_SPEED_FULL (1<<10) 113 #define PORTSC_SPEED_LOW (2<<10) 114 #define PORTSC_SPEED_HIGH (3<<10) 115 #define PORTSC_SPEED_SUPER (4<<10) 116 #define PORTSC_PIC_SHIFT 14 117 #define PORTSC_PIC_MASK 0x3 118 #define PORTSC_LWS (1<<16) 119 #define PORTSC_CSC (1<<17) 120 #define PORTSC_PEC (1<<18) 121 #define PORTSC_WRC (1<<19) 122 #define PORTSC_OCC (1<<20) 123 #define PORTSC_PRC (1<<21) 124 #define PORTSC_PLC (1<<22) 125 #define PORTSC_CEC (1<<23) 126 #define PORTSC_CAS (1<<24) 127 #define PORTSC_WCE (1<<25) 128 #define PORTSC_WDE (1<<26) 129 #define PORTSC_WOE (1<<27) 130 #define PORTSC_DR (1<<30) 131 #define PORTSC_WPR (1<<31) 132 133 #define CRCR_RCS (1<<0) 134 #define CRCR_CS (1<<1) 135 #define CRCR_CA (1<<2) 136 #define CRCR_CRR (1<<3) 137 138 #define IMAN_IP (1<<0) 139 #define IMAN_IE (1<<1) 140 141 #define ERDP_EHB (1<<3) 142 143 #define TRB_SIZE 16 144 typedef struct XHCITRB { 145 uint64_t parameter; 146 uint32_t status; 147 uint32_t control; 148 dma_addr_t addr; 149 bool ccs; 150 } XHCITRB; 151 152 enum { 153 PLS_U0 = 0, 154 PLS_U1 = 1, 155 PLS_U2 = 2, 156 PLS_U3 = 3, 157 PLS_DISABLED = 4, 158 PLS_RX_DETECT = 5, 159 PLS_INACTIVE = 6, 160 PLS_POLLING = 7, 161 PLS_RECOVERY = 8, 162 PLS_HOT_RESET = 9, 163 PLS_COMPILANCE_MODE = 10, 164 PLS_TEST_MODE = 11, 165 PLS_RESUME = 15, 166 }; 167 168 typedef enum TRBType { 169 TRB_RESERVED = 0, 170 TR_NORMAL, 171 TR_SETUP, 172 TR_DATA, 173 TR_STATUS, 174 TR_ISOCH, 175 TR_LINK, 176 TR_EVDATA, 177 TR_NOOP, 178 CR_ENABLE_SLOT, 179 CR_DISABLE_SLOT, 180 CR_ADDRESS_DEVICE, 181 CR_CONFIGURE_ENDPOINT, 182 CR_EVALUATE_CONTEXT, 183 CR_RESET_ENDPOINT, 184 CR_STOP_ENDPOINT, 185 CR_SET_TR_DEQUEUE, 186 CR_RESET_DEVICE, 187 CR_FORCE_EVENT, 188 CR_NEGOTIATE_BW, 189 CR_SET_LATENCY_TOLERANCE, 190 CR_GET_PORT_BANDWIDTH, 191 CR_FORCE_HEADER, 192 CR_NOOP, 193 ER_TRANSFER = 32, 194 ER_COMMAND_COMPLETE, 195 ER_PORT_STATUS_CHANGE, 196 ER_BANDWIDTH_REQUEST, 197 ER_DOORBELL, 198 ER_HOST_CONTROLLER, 199 ER_DEVICE_NOTIFICATION, 200 ER_MFINDEX_WRAP, 201 /* vendor specific bits */ 202 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 203 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 204 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 205 } TRBType; 206 207 #define CR_LINK TR_LINK 208 209 typedef enum TRBCCode { 210 CC_INVALID = 0, 211 CC_SUCCESS, 212 CC_DATA_BUFFER_ERROR, 213 CC_BABBLE_DETECTED, 214 CC_USB_TRANSACTION_ERROR, 215 CC_TRB_ERROR, 216 CC_STALL_ERROR, 217 CC_RESOURCE_ERROR, 218 CC_BANDWIDTH_ERROR, 219 CC_NO_SLOTS_ERROR, 220 CC_INVALID_STREAM_TYPE_ERROR, 221 CC_SLOT_NOT_ENABLED_ERROR, 222 CC_EP_NOT_ENABLED_ERROR, 223 CC_SHORT_PACKET, 224 CC_RING_UNDERRUN, 225 CC_RING_OVERRUN, 226 CC_VF_ER_FULL, 227 CC_PARAMETER_ERROR, 228 CC_BANDWIDTH_OVERRUN, 229 CC_CONTEXT_STATE_ERROR, 230 CC_NO_PING_RESPONSE_ERROR, 231 CC_EVENT_RING_FULL_ERROR, 232 CC_INCOMPATIBLE_DEVICE_ERROR, 233 CC_MISSED_SERVICE_ERROR, 234 CC_COMMAND_RING_STOPPED, 235 CC_COMMAND_ABORTED, 236 CC_STOPPED, 237 CC_STOPPED_LENGTH_INVALID, 238 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 239 CC_ISOCH_BUFFER_OVERRUN = 31, 240 CC_EVENT_LOST_ERROR, 241 CC_UNDEFINED_ERROR, 242 CC_INVALID_STREAM_ID_ERROR, 243 CC_SECONDARY_BANDWIDTH_ERROR, 244 CC_SPLIT_TRANSACTION_ERROR 245 } TRBCCode; 246 247 #define TRB_C (1<<0) 248 #define TRB_TYPE_SHIFT 10 249 #define TRB_TYPE_MASK 0x3f 250 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 251 252 #define TRB_EV_ED (1<<2) 253 254 #define TRB_TR_ENT (1<<1) 255 #define TRB_TR_ISP (1<<2) 256 #define TRB_TR_NS (1<<3) 257 #define TRB_TR_CH (1<<4) 258 #define TRB_TR_IOC (1<<5) 259 #define TRB_TR_IDT (1<<6) 260 #define TRB_TR_TBC_SHIFT 7 261 #define TRB_TR_TBC_MASK 0x3 262 #define TRB_TR_BEI (1<<9) 263 #define TRB_TR_TLBPC_SHIFT 16 264 #define TRB_TR_TLBPC_MASK 0xf 265 #define TRB_TR_FRAMEID_SHIFT 20 266 #define TRB_TR_FRAMEID_MASK 0x7ff 267 #define TRB_TR_SIA (1<<31) 268 269 #define TRB_TR_DIR (1<<16) 270 271 #define TRB_CR_SLOTID_SHIFT 24 272 #define TRB_CR_SLOTID_MASK 0xff 273 #define TRB_CR_EPID_SHIFT 16 274 #define TRB_CR_EPID_MASK 0x1f 275 276 #define TRB_CR_BSR (1<<9) 277 #define TRB_CR_DC (1<<9) 278 279 #define TRB_LK_TC (1<<1) 280 281 #define TRB_INTR_SHIFT 22 282 #define TRB_INTR_MASK 0x3ff 283 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 284 285 #define EP_TYPE_MASK 0x7 286 #define EP_TYPE_SHIFT 3 287 288 #define EP_STATE_MASK 0x7 289 #define EP_DISABLED (0<<0) 290 #define EP_RUNNING (1<<0) 291 #define EP_HALTED (2<<0) 292 #define EP_STOPPED (3<<0) 293 #define EP_ERROR (4<<0) 294 295 #define SLOT_STATE_MASK 0x1f 296 #define SLOT_STATE_SHIFT 27 297 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 298 #define SLOT_ENABLED 0 299 #define SLOT_DEFAULT 1 300 #define SLOT_ADDRESSED 2 301 #define SLOT_CONFIGURED 3 302 303 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 304 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 305 306 typedef struct XHCIState XHCIState; 307 typedef struct XHCIStreamContext XHCIStreamContext; 308 typedef struct XHCIEPContext XHCIEPContext; 309 310 #define get_field(data, field) \ 311 (((data) >> field##_SHIFT) & field##_MASK) 312 313 #define set_field(data, newval, field) do { \ 314 uint32_t val = *data; \ 315 val &= ~(field##_MASK << field##_SHIFT); \ 316 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 317 *data = val; \ 318 } while (0) 319 320 typedef enum EPType { 321 ET_INVALID = 0, 322 ET_ISO_OUT, 323 ET_BULK_OUT, 324 ET_INTR_OUT, 325 ET_CONTROL, 326 ET_ISO_IN, 327 ET_BULK_IN, 328 ET_INTR_IN, 329 } EPType; 330 331 typedef struct XHCIRing { 332 dma_addr_t dequeue; 333 bool ccs; 334 } XHCIRing; 335 336 typedef struct XHCIPort { 337 XHCIState *xhci; 338 uint32_t portsc; 339 uint32_t portnr; 340 USBPort *uport; 341 uint32_t speedmask; 342 char name[16]; 343 MemoryRegion mem; 344 } XHCIPort; 345 346 typedef struct XHCITransfer { 347 XHCIEPContext *epctx; 348 USBPacket packet; 349 QEMUSGList sgl; 350 bool running_async; 351 bool running_retry; 352 bool complete; 353 bool int_req; 354 unsigned int iso_pkts; 355 unsigned int streamid; 356 bool in_xfer; 357 bool iso_xfer; 358 bool timed_xfer; 359 360 unsigned int trb_count; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 371 QTAILQ_ENTRY(XHCITransfer) next; 372 } XHCITransfer; 373 374 struct XHCIStreamContext { 375 dma_addr_t pctx; 376 unsigned int sct; 377 XHCIRing ring; 378 }; 379 380 struct XHCIEPContext { 381 XHCIState *xhci; 382 unsigned int slotid; 383 unsigned int epid; 384 385 XHCIRing ring; 386 uint32_t xfer_count; 387 QTAILQ_HEAD(, XHCITransfer) transfers; 388 XHCITransfer *retry; 389 EPType type; 390 dma_addr_t pctx; 391 unsigned int max_psize; 392 uint32_t state; 393 394 /* streams */ 395 unsigned int max_pstreams; 396 bool lsa; 397 unsigned int nr_pstreams; 398 XHCIStreamContext *pstreams; 399 400 /* iso xfer scheduling */ 401 unsigned int interval; 402 int64_t mfindex_last; 403 QEMUTimer *kick_timer; 404 }; 405 406 typedef struct XHCISlot { 407 bool enabled; 408 bool addressed; 409 dma_addr_t ctx; 410 USBPort *uport; 411 XHCIEPContext * eps[31]; 412 } XHCISlot; 413 414 typedef struct XHCIEvent { 415 TRBType type; 416 TRBCCode ccode; 417 uint64_t ptr; 418 uint32_t length; 419 uint32_t flags; 420 uint8_t slotid; 421 uint8_t epid; 422 } XHCIEvent; 423 424 typedef struct XHCIInterrupter { 425 uint32_t iman; 426 uint32_t imod; 427 uint32_t erstsz; 428 uint32_t erstba_low; 429 uint32_t erstba_high; 430 uint32_t erdp_low; 431 uint32_t erdp_high; 432 433 bool msix_used, er_pcs, er_full; 434 435 dma_addr_t er_start; 436 uint32_t er_size; 437 unsigned int er_ep_idx; 438 439 XHCIEvent ev_buffer[EV_QUEUE]; 440 unsigned int ev_buffer_put; 441 unsigned int ev_buffer_get; 442 443 } XHCIInterrupter; 444 445 struct XHCIState { 446 /*< private >*/ 447 PCIDevice parent_obj; 448 /*< public >*/ 449 450 USBBus bus; 451 MemoryRegion mem; 452 MemoryRegion mem_cap; 453 MemoryRegion mem_oper; 454 MemoryRegion mem_runtime; 455 MemoryRegion mem_doorbell; 456 457 /* properties */ 458 uint32_t numports_2; 459 uint32_t numports_3; 460 uint32_t numintrs; 461 uint32_t numslots; 462 uint32_t flags; 463 uint32_t max_pstreams_mask; 464 OnOffAuto msi; 465 OnOffAuto msix; 466 467 /* Operational Registers */ 468 uint32_t usbcmd; 469 uint32_t usbsts; 470 uint32_t dnctrl; 471 uint32_t crcr_low; 472 uint32_t crcr_high; 473 uint32_t dcbaap_low; 474 uint32_t dcbaap_high; 475 uint32_t config; 476 477 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 478 XHCIPort ports[MAXPORTS]; 479 XHCISlot slots[MAXSLOTS]; 480 uint32_t numports; 481 482 /* Runtime Registers */ 483 int64_t mfindex_start; 484 QEMUTimer *mfwrap_timer; 485 XHCIInterrupter intr[MAXINTRS]; 486 487 XHCIRing cmd_ring; 488 }; 489 490 #define TYPE_XHCI "nec-usb-xhci" 491 492 #define XHCI(obj) \ 493 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 494 495 typedef struct XHCIEvRingSeg { 496 uint32_t addr_low; 497 uint32_t addr_high; 498 uint32_t size; 499 uint32_t rsvd; 500 } XHCIEvRingSeg; 501 502 enum xhci_flags { 503 XHCI_FLAG_SS_FIRST = 1, 504 XHCI_FLAG_FORCE_PCIE_ENDCAP, 505 XHCI_FLAG_ENABLE_STREAMS, 506 }; 507 508 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 509 unsigned int epid, unsigned int streamid); 510 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid); 511 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 512 unsigned int epid); 513 static void xhci_xfer_report(XHCITransfer *xfer); 514 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 515 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 516 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx); 517 518 static const char *TRBType_names[] = { 519 [TRB_RESERVED] = "TRB_RESERVED", 520 [TR_NORMAL] = "TR_NORMAL", 521 [TR_SETUP] = "TR_SETUP", 522 [TR_DATA] = "TR_DATA", 523 [TR_STATUS] = "TR_STATUS", 524 [TR_ISOCH] = "TR_ISOCH", 525 [TR_LINK] = "TR_LINK", 526 [TR_EVDATA] = "TR_EVDATA", 527 [TR_NOOP] = "TR_NOOP", 528 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 529 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 530 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 531 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 532 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 533 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 534 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 535 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 536 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 537 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 538 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 539 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 540 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 541 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 542 [CR_NOOP] = "CR_NOOP", 543 [ER_TRANSFER] = "ER_TRANSFER", 544 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 545 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 546 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 547 [ER_DOORBELL] = "ER_DOORBELL", 548 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 549 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 550 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 551 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 552 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 553 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 554 }; 555 556 static const char *TRBCCode_names[] = { 557 [CC_INVALID] = "CC_INVALID", 558 [CC_SUCCESS] = "CC_SUCCESS", 559 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 560 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 561 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 562 [CC_TRB_ERROR] = "CC_TRB_ERROR", 563 [CC_STALL_ERROR] = "CC_STALL_ERROR", 564 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 565 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 566 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 567 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 568 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 569 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 570 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 571 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 572 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 573 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 574 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 575 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 576 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 577 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 578 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 579 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 580 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 581 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 582 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 583 [CC_STOPPED] = "CC_STOPPED", 584 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 585 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 586 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 587 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 588 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 589 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 590 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 591 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 592 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 593 }; 594 595 static const char *ep_state_names[] = { 596 [EP_DISABLED] = "disabled", 597 [EP_RUNNING] = "running", 598 [EP_HALTED] = "halted", 599 [EP_STOPPED] = "stopped", 600 [EP_ERROR] = "error", 601 }; 602 603 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 604 { 605 if (index >= llen || list[index] == NULL) { 606 return "???"; 607 } 608 return list[index]; 609 } 610 611 static const char *trb_name(XHCITRB *trb) 612 { 613 return lookup_name(TRB_TYPE(*trb), TRBType_names, 614 ARRAY_SIZE(TRBType_names)); 615 } 616 617 static const char *event_name(XHCIEvent *event) 618 { 619 return lookup_name(event->ccode, TRBCCode_names, 620 ARRAY_SIZE(TRBCCode_names)); 621 } 622 623 static const char *ep_state_name(uint32_t state) 624 { 625 return lookup_name(state, ep_state_names, 626 ARRAY_SIZE(ep_state_names)); 627 } 628 629 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 630 { 631 return xhci->flags & (1 << bit); 632 } 633 634 static uint64_t xhci_mfindex_get(XHCIState *xhci) 635 { 636 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 637 return (now - xhci->mfindex_start) / 125000; 638 } 639 640 static void xhci_mfwrap_update(XHCIState *xhci) 641 { 642 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 643 uint32_t mfindex, left; 644 int64_t now; 645 646 if ((xhci->usbcmd & bits) == bits) { 647 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 648 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 649 left = 0x4000 - mfindex; 650 timer_mod(xhci->mfwrap_timer, now + left * 125000); 651 } else { 652 timer_del(xhci->mfwrap_timer); 653 } 654 } 655 656 static void xhci_mfwrap_timer(void *opaque) 657 { 658 XHCIState *xhci = opaque; 659 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 660 661 xhci_event(xhci, &wrap, 0); 662 xhci_mfwrap_update(xhci); 663 } 664 665 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 666 { 667 if (sizeof(dma_addr_t) == 4) { 668 return low; 669 } else { 670 return low | (((dma_addr_t)high << 16) << 16); 671 } 672 } 673 674 static inline dma_addr_t xhci_mask64(uint64_t addr) 675 { 676 if (sizeof(dma_addr_t) == 4) { 677 return addr & 0xffffffff; 678 } else { 679 return addr; 680 } 681 } 682 683 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 684 uint32_t *buf, size_t len) 685 { 686 int i; 687 688 assert((len % sizeof(uint32_t)) == 0); 689 690 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 691 692 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 693 buf[i] = le32_to_cpu(buf[i]); 694 } 695 } 696 697 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 698 uint32_t *buf, size_t len) 699 { 700 int i; 701 uint32_t tmp[5]; 702 uint32_t n = len / sizeof(uint32_t); 703 704 assert((len % sizeof(uint32_t)) == 0); 705 assert(n <= ARRAY_SIZE(tmp)); 706 707 for (i = 0; i < n; i++) { 708 tmp[i] = cpu_to_le32(buf[i]); 709 } 710 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 711 } 712 713 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 714 { 715 int index; 716 717 if (!uport->dev) { 718 return NULL; 719 } 720 switch (uport->dev->speed) { 721 case USB_SPEED_LOW: 722 case USB_SPEED_FULL: 723 case USB_SPEED_HIGH: 724 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 725 index = uport->index + xhci->numports_3; 726 } else { 727 index = uport->index; 728 } 729 break; 730 case USB_SPEED_SUPER: 731 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 732 index = uport->index; 733 } else { 734 index = uport->index + xhci->numports_2; 735 } 736 break; 737 default: 738 return NULL; 739 } 740 return &xhci->ports[index]; 741 } 742 743 static void xhci_intx_update(XHCIState *xhci) 744 { 745 PCIDevice *pci_dev = PCI_DEVICE(xhci); 746 int level = 0; 747 748 if (msix_enabled(pci_dev) || 749 msi_enabled(pci_dev)) { 750 return; 751 } 752 753 if (xhci->intr[0].iman & IMAN_IP && 754 xhci->intr[0].iman & IMAN_IE && 755 xhci->usbcmd & USBCMD_INTE) { 756 level = 1; 757 } 758 759 trace_usb_xhci_irq_intx(level); 760 pci_set_irq(pci_dev, level); 761 } 762 763 static void xhci_msix_update(XHCIState *xhci, int v) 764 { 765 PCIDevice *pci_dev = PCI_DEVICE(xhci); 766 bool enabled; 767 768 if (!msix_enabled(pci_dev)) { 769 return; 770 } 771 772 enabled = xhci->intr[v].iman & IMAN_IE; 773 if (enabled == xhci->intr[v].msix_used) { 774 return; 775 } 776 777 if (enabled) { 778 trace_usb_xhci_irq_msix_use(v); 779 msix_vector_use(pci_dev, v); 780 xhci->intr[v].msix_used = true; 781 } else { 782 trace_usb_xhci_irq_msix_unuse(v); 783 msix_vector_unuse(pci_dev, v); 784 xhci->intr[v].msix_used = false; 785 } 786 } 787 788 static void xhci_intr_raise(XHCIState *xhci, int v) 789 { 790 PCIDevice *pci_dev = PCI_DEVICE(xhci); 791 792 xhci->intr[v].erdp_low |= ERDP_EHB; 793 xhci->intr[v].iman |= IMAN_IP; 794 xhci->usbsts |= USBSTS_EINT; 795 796 if (!(xhci->intr[v].iman & IMAN_IE)) { 797 return; 798 } 799 800 if (!(xhci->usbcmd & USBCMD_INTE)) { 801 return; 802 } 803 804 if (msix_enabled(pci_dev)) { 805 trace_usb_xhci_irq_msix(v); 806 msix_notify(pci_dev, v); 807 return; 808 } 809 810 if (msi_enabled(pci_dev)) { 811 trace_usb_xhci_irq_msi(v); 812 msi_notify(pci_dev, v); 813 return; 814 } 815 816 if (v == 0) { 817 trace_usb_xhci_irq_intx(1); 818 pci_irq_assert(pci_dev); 819 } 820 } 821 822 static inline int xhci_running(XHCIState *xhci) 823 { 824 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 825 } 826 827 static void xhci_die(XHCIState *xhci) 828 { 829 xhci->usbsts |= USBSTS_HCE; 830 DPRINTF("xhci: asserted controller error\n"); 831 } 832 833 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 834 { 835 PCIDevice *pci_dev = PCI_DEVICE(xhci); 836 XHCIInterrupter *intr = &xhci->intr[v]; 837 XHCITRB ev_trb; 838 dma_addr_t addr; 839 840 ev_trb.parameter = cpu_to_le64(event->ptr); 841 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 842 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 843 event->flags | (event->type << TRB_TYPE_SHIFT); 844 if (intr->er_pcs) { 845 ev_trb.control |= TRB_C; 846 } 847 ev_trb.control = cpu_to_le32(ev_trb.control); 848 849 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 850 event_name(event), ev_trb.parameter, 851 ev_trb.status, ev_trb.control); 852 853 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 854 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 855 856 intr->er_ep_idx++; 857 if (intr->er_ep_idx >= intr->er_size) { 858 intr->er_ep_idx = 0; 859 intr->er_pcs = !intr->er_pcs; 860 } 861 } 862 863 static void xhci_events_update(XHCIState *xhci, int v) 864 { 865 XHCIInterrupter *intr = &xhci->intr[v]; 866 dma_addr_t erdp; 867 unsigned int dp_idx; 868 bool do_irq = 0; 869 870 if (xhci->usbsts & USBSTS_HCH) { 871 return; 872 } 873 874 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 875 if (erdp < intr->er_start || 876 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 877 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 878 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 879 v, intr->er_start, intr->er_size); 880 xhci_die(xhci); 881 return; 882 } 883 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 884 assert(dp_idx < intr->er_size); 885 886 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 887 * deadlocks when the ER is full. Hack it by holding off events until 888 * the driver decides to free at least half of the ring */ 889 if (intr->er_full) { 890 int er_free = dp_idx - intr->er_ep_idx; 891 if (er_free <= 0) { 892 er_free += intr->er_size; 893 } 894 if (er_free < (intr->er_size/2)) { 895 DPRINTF("xhci_events_update(): event ring still " 896 "more than half full (hack)\n"); 897 return; 898 } 899 } 900 901 while (intr->ev_buffer_put != intr->ev_buffer_get) { 902 assert(intr->er_full); 903 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 904 DPRINTF("xhci_events_update(): event ring full again\n"); 905 #ifndef ER_FULL_HACK 906 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 907 xhci_write_event(xhci, &full, v); 908 #endif 909 do_irq = 1; 910 break; 911 } 912 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 913 xhci_write_event(xhci, event, v); 914 intr->ev_buffer_get++; 915 do_irq = 1; 916 if (intr->ev_buffer_get == EV_QUEUE) { 917 intr->ev_buffer_get = 0; 918 } 919 } 920 921 if (do_irq) { 922 xhci_intr_raise(xhci, v); 923 } 924 925 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 926 DPRINTF("xhci_events_update(): event ring no longer full\n"); 927 intr->er_full = 0; 928 } 929 } 930 931 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 932 { 933 XHCIInterrupter *intr; 934 dma_addr_t erdp; 935 unsigned int dp_idx; 936 937 if (v >= xhci->numintrs) { 938 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 939 return; 940 } 941 intr = &xhci->intr[v]; 942 943 if (intr->er_full) { 944 DPRINTF("xhci_event(): ER full, queueing\n"); 945 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 946 DPRINTF("xhci: event queue full, dropping event!\n"); 947 return; 948 } 949 intr->ev_buffer[intr->ev_buffer_put++] = *event; 950 if (intr->ev_buffer_put == EV_QUEUE) { 951 intr->ev_buffer_put = 0; 952 } 953 return; 954 } 955 956 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 957 if (erdp < intr->er_start || 958 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 959 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 960 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 961 v, intr->er_start, intr->er_size); 962 xhci_die(xhci); 963 return; 964 } 965 966 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 967 assert(dp_idx < intr->er_size); 968 969 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 970 DPRINTF("xhci_event(): ER full, queueing\n"); 971 #ifndef ER_FULL_HACK 972 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 973 xhci_write_event(xhci, &full); 974 #endif 975 intr->er_full = 1; 976 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 977 DPRINTF("xhci: event queue full, dropping event!\n"); 978 return; 979 } 980 intr->ev_buffer[intr->ev_buffer_put++] = *event; 981 if (intr->ev_buffer_put == EV_QUEUE) { 982 intr->ev_buffer_put = 0; 983 } 984 } else { 985 xhci_write_event(xhci, event, v); 986 } 987 988 xhci_intr_raise(xhci, v); 989 } 990 991 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 992 dma_addr_t base) 993 { 994 ring->dequeue = base; 995 ring->ccs = 1; 996 } 997 998 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 999 dma_addr_t *addr) 1000 { 1001 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1002 uint32_t link_cnt = 0; 1003 1004 while (1) { 1005 TRBType type; 1006 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 1007 trb->addr = ring->dequeue; 1008 trb->ccs = ring->ccs; 1009 le64_to_cpus(&trb->parameter); 1010 le32_to_cpus(&trb->status); 1011 le32_to_cpus(&trb->control); 1012 1013 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 1014 trb->parameter, trb->status, trb->control); 1015 1016 if ((trb->control & TRB_C) != ring->ccs) { 1017 return 0; 1018 } 1019 1020 type = TRB_TYPE(*trb); 1021 1022 if (type != TR_LINK) { 1023 if (addr) { 1024 *addr = ring->dequeue; 1025 } 1026 ring->dequeue += TRB_SIZE; 1027 return type; 1028 } else { 1029 if (++link_cnt > TRB_LINK_LIMIT) { 1030 return 0; 1031 } 1032 ring->dequeue = xhci_mask64(trb->parameter); 1033 if (trb->control & TRB_LK_TC) { 1034 ring->ccs = !ring->ccs; 1035 } 1036 } 1037 } 1038 } 1039 1040 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1041 { 1042 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1043 XHCITRB trb; 1044 int length = 0; 1045 dma_addr_t dequeue = ring->dequeue; 1046 bool ccs = ring->ccs; 1047 /* hack to bundle together the two/three TDs that make a setup transfer */ 1048 bool control_td_set = 0; 1049 uint32_t link_cnt = 0; 1050 1051 while (1) { 1052 TRBType type; 1053 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1054 le64_to_cpus(&trb.parameter); 1055 le32_to_cpus(&trb.status); 1056 le32_to_cpus(&trb.control); 1057 1058 if ((trb.control & TRB_C) != ccs) { 1059 return -length; 1060 } 1061 1062 type = TRB_TYPE(trb); 1063 1064 if (type == TR_LINK) { 1065 if (++link_cnt > TRB_LINK_LIMIT) { 1066 return -length; 1067 } 1068 dequeue = xhci_mask64(trb.parameter); 1069 if (trb.control & TRB_LK_TC) { 1070 ccs = !ccs; 1071 } 1072 continue; 1073 } 1074 1075 length += 1; 1076 dequeue += TRB_SIZE; 1077 1078 if (type == TR_SETUP) { 1079 control_td_set = 1; 1080 } else if (type == TR_STATUS) { 1081 control_td_set = 0; 1082 } 1083 1084 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1085 return length; 1086 } 1087 } 1088 } 1089 1090 static void xhci_er_reset(XHCIState *xhci, int v) 1091 { 1092 XHCIInterrupter *intr = &xhci->intr[v]; 1093 XHCIEvRingSeg seg; 1094 1095 if (intr->erstsz == 0) { 1096 /* disabled */ 1097 intr->er_start = 0; 1098 intr->er_size = 0; 1099 return; 1100 } 1101 /* cache the (sole) event ring segment location */ 1102 if (intr->erstsz != 1) { 1103 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1104 xhci_die(xhci); 1105 return; 1106 } 1107 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1108 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1109 le32_to_cpus(&seg.addr_low); 1110 le32_to_cpus(&seg.addr_high); 1111 le32_to_cpus(&seg.size); 1112 if (seg.size < 16 || seg.size > 4096) { 1113 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 1114 xhci_die(xhci); 1115 return; 1116 } 1117 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1118 intr->er_size = seg.size; 1119 1120 intr->er_ep_idx = 0; 1121 intr->er_pcs = 1; 1122 intr->er_full = 0; 1123 1124 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1125 v, intr->er_start, intr->er_size); 1126 } 1127 1128 static void xhci_run(XHCIState *xhci) 1129 { 1130 trace_usb_xhci_run(); 1131 xhci->usbsts &= ~USBSTS_HCH; 1132 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1133 } 1134 1135 static void xhci_stop(XHCIState *xhci) 1136 { 1137 trace_usb_xhci_stop(); 1138 xhci->usbsts |= USBSTS_HCH; 1139 xhci->crcr_low &= ~CRCR_CRR; 1140 } 1141 1142 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1143 dma_addr_t base) 1144 { 1145 XHCIStreamContext *stctx; 1146 unsigned int i; 1147 1148 stctx = g_new0(XHCIStreamContext, count); 1149 for (i = 0; i < count; i++) { 1150 stctx[i].pctx = base + i * 16; 1151 stctx[i].sct = -1; 1152 } 1153 return stctx; 1154 } 1155 1156 static void xhci_reset_streams(XHCIEPContext *epctx) 1157 { 1158 unsigned int i; 1159 1160 for (i = 0; i < epctx->nr_pstreams; i++) { 1161 epctx->pstreams[i].sct = -1; 1162 } 1163 } 1164 1165 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1166 { 1167 assert(epctx->pstreams == NULL); 1168 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1169 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1170 } 1171 1172 static void xhci_free_streams(XHCIEPContext *epctx) 1173 { 1174 assert(epctx->pstreams != NULL); 1175 1176 g_free(epctx->pstreams); 1177 epctx->pstreams = NULL; 1178 epctx->nr_pstreams = 0; 1179 } 1180 1181 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 1182 unsigned int slotid, 1183 uint32_t epmask, 1184 XHCIEPContext **epctxs, 1185 USBEndpoint **eps) 1186 { 1187 XHCISlot *slot; 1188 XHCIEPContext *epctx; 1189 USBEndpoint *ep; 1190 int i, j; 1191 1192 assert(slotid >= 1 && slotid <= xhci->numslots); 1193 1194 slot = &xhci->slots[slotid - 1]; 1195 1196 for (i = 2, j = 0; i <= 31; i++) { 1197 if (!(epmask & (1u << i))) { 1198 continue; 1199 } 1200 1201 epctx = slot->eps[i - 1]; 1202 ep = xhci_epid_to_usbep(epctx); 1203 if (!epctx || !epctx->nr_pstreams || !ep) { 1204 continue; 1205 } 1206 1207 if (epctxs) { 1208 epctxs[j] = epctx; 1209 } 1210 eps[j++] = ep; 1211 } 1212 return j; 1213 } 1214 1215 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 1216 uint32_t epmask) 1217 { 1218 USBEndpoint *eps[30]; 1219 int nr_eps; 1220 1221 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 1222 if (nr_eps) { 1223 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 1224 } 1225 } 1226 1227 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 1228 uint32_t epmask) 1229 { 1230 XHCIEPContext *epctxs[30]; 1231 USBEndpoint *eps[30]; 1232 int i, r, nr_eps, req_nr_streams, dev_max_streams; 1233 1234 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 1235 eps); 1236 if (nr_eps == 0) { 1237 return CC_SUCCESS; 1238 } 1239 1240 req_nr_streams = epctxs[0]->nr_pstreams; 1241 dev_max_streams = eps[0]->max_streams; 1242 1243 for (i = 1; i < nr_eps; i++) { 1244 /* 1245 * HdG: I don't expect these to ever trigger, but if they do we need 1246 * to come up with another solution, ie group identical endpoints 1247 * together and make an usb_device_alloc_streams call per group. 1248 */ 1249 if (epctxs[i]->nr_pstreams != req_nr_streams) { 1250 FIXME("guest streams config not identical for all eps"); 1251 return CC_RESOURCE_ERROR; 1252 } 1253 if (eps[i]->max_streams != dev_max_streams) { 1254 FIXME("device streams config not identical for all eps"); 1255 return CC_RESOURCE_ERROR; 1256 } 1257 } 1258 1259 /* 1260 * max-streams in both the device descriptor and in the controller is a 1261 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 1262 * streams the guest will ask for 5 rounded up to the next power of 2 which 1263 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 1264 * 1265 * For redirected devices however this is an issue, as there we must ask 1266 * the real xhci controller to alloc streams, and the host driver for the 1267 * real xhci controller will likely disallow allocating more streams then 1268 * the device can handle. 1269 * 1270 * So we limit the requested nr_streams to the maximum number the device 1271 * can handle. 1272 */ 1273 if (req_nr_streams > dev_max_streams) { 1274 req_nr_streams = dev_max_streams; 1275 } 1276 1277 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 1278 if (r != 0) { 1279 DPRINTF("xhci: alloc streams failed\n"); 1280 return CC_RESOURCE_ERROR; 1281 } 1282 1283 return CC_SUCCESS; 1284 } 1285 1286 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1287 unsigned int streamid, 1288 uint32_t *cc_error) 1289 { 1290 XHCIStreamContext *sctx; 1291 dma_addr_t base; 1292 uint32_t ctx[2], sct; 1293 1294 assert(streamid != 0); 1295 if (epctx->lsa) { 1296 if (streamid >= epctx->nr_pstreams) { 1297 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1298 return NULL; 1299 } 1300 sctx = epctx->pstreams + streamid; 1301 } else { 1302 FIXME("secondary streams not implemented yet"); 1303 } 1304 1305 if (sctx->sct == -1) { 1306 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1307 sct = (ctx[0] >> 1) & 0x07; 1308 if (epctx->lsa && sct != 1) { 1309 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1310 return NULL; 1311 } 1312 sctx->sct = sct; 1313 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1314 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1315 } 1316 return sctx; 1317 } 1318 1319 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1320 XHCIStreamContext *sctx, uint32_t state) 1321 { 1322 XHCIRing *ring = NULL; 1323 uint32_t ctx[5]; 1324 uint32_t ctx2[2]; 1325 1326 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1327 ctx[0] &= ~EP_STATE_MASK; 1328 ctx[0] |= state; 1329 1330 /* update ring dequeue ptr */ 1331 if (epctx->nr_pstreams) { 1332 if (sctx != NULL) { 1333 ring = &sctx->ring; 1334 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1335 ctx2[0] &= 0xe; 1336 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1337 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1338 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1339 } 1340 } else { 1341 ring = &epctx->ring; 1342 } 1343 if (ring) { 1344 ctx[2] = ring->dequeue | ring->ccs; 1345 ctx[3] = (ring->dequeue >> 16) >> 16; 1346 1347 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1348 epctx->pctx, state, ctx[3], ctx[2]); 1349 } 1350 1351 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1352 if (epctx->state != state) { 1353 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1354 ep_state_name(epctx->state), 1355 ep_state_name(state)); 1356 } 1357 epctx->state = state; 1358 } 1359 1360 static void xhci_ep_kick_timer(void *opaque) 1361 { 1362 XHCIEPContext *epctx = opaque; 1363 xhci_kick_epctx(epctx, 0); 1364 } 1365 1366 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1367 unsigned int slotid, 1368 unsigned int epid) 1369 { 1370 XHCIEPContext *epctx; 1371 1372 epctx = g_new0(XHCIEPContext, 1); 1373 epctx->xhci = xhci; 1374 epctx->slotid = slotid; 1375 epctx->epid = epid; 1376 1377 QTAILQ_INIT(&epctx->transfers); 1378 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1379 1380 return epctx; 1381 } 1382 1383 static void xhci_init_epctx(XHCIEPContext *epctx, 1384 dma_addr_t pctx, uint32_t *ctx) 1385 { 1386 dma_addr_t dequeue; 1387 1388 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1389 1390 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1391 epctx->pctx = pctx; 1392 epctx->max_psize = ctx[1]>>16; 1393 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1394 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1395 epctx->lsa = (ctx[0] >> 15) & 1; 1396 if (epctx->max_pstreams) { 1397 xhci_alloc_streams(epctx, dequeue); 1398 } else { 1399 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1400 epctx->ring.ccs = ctx[2] & 1; 1401 } 1402 1403 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1404 } 1405 1406 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1407 unsigned int epid, dma_addr_t pctx, 1408 uint32_t *ctx) 1409 { 1410 XHCISlot *slot; 1411 XHCIEPContext *epctx; 1412 1413 trace_usb_xhci_ep_enable(slotid, epid); 1414 assert(slotid >= 1 && slotid <= xhci->numslots); 1415 assert(epid >= 1 && epid <= 31); 1416 1417 slot = &xhci->slots[slotid-1]; 1418 if (slot->eps[epid-1]) { 1419 xhci_disable_ep(xhci, slotid, epid); 1420 } 1421 1422 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1423 slot->eps[epid-1] = epctx; 1424 xhci_init_epctx(epctx, pctx, ctx); 1425 1426 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1427 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1428 1429 epctx->mfindex_last = 0; 1430 1431 epctx->state = EP_RUNNING; 1432 ctx[0] &= ~EP_STATE_MASK; 1433 ctx[0] |= EP_RUNNING; 1434 1435 return CC_SUCCESS; 1436 } 1437 1438 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx, 1439 uint32_t length) 1440 { 1441 uint32_t limit = epctx->nr_pstreams + 16; 1442 XHCITransfer *xfer; 1443 1444 if (epctx->xfer_count >= limit) { 1445 return NULL; 1446 } 1447 1448 xfer = g_new0(XHCITransfer, 1); 1449 xfer->epctx = epctx; 1450 xfer->trbs = g_new(XHCITRB, length); 1451 xfer->trb_count = length; 1452 usb_packet_init(&xfer->packet); 1453 1454 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next); 1455 epctx->xfer_count++; 1456 1457 return xfer; 1458 } 1459 1460 static void xhci_ep_free_xfer(XHCITransfer *xfer) 1461 { 1462 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next); 1463 xfer->epctx->xfer_count--; 1464 1465 usb_packet_cleanup(&xfer->packet); 1466 g_free(xfer->trbs); 1467 g_free(xfer); 1468 } 1469 1470 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1471 { 1472 int killed = 0; 1473 1474 if (report && (t->running_async || t->running_retry)) { 1475 t->status = report; 1476 xhci_xfer_report(t); 1477 } 1478 1479 if (t->running_async) { 1480 usb_cancel_packet(&t->packet); 1481 t->running_async = 0; 1482 killed = 1; 1483 } 1484 if (t->running_retry) { 1485 if (t->epctx) { 1486 t->epctx->retry = NULL; 1487 timer_del(t->epctx->kick_timer); 1488 } 1489 t->running_retry = 0; 1490 killed = 1; 1491 } 1492 g_free(t->trbs); 1493 1494 t->trbs = NULL; 1495 t->trb_count = 0; 1496 1497 return killed; 1498 } 1499 1500 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1501 unsigned int epid, TRBCCode report) 1502 { 1503 XHCISlot *slot; 1504 XHCIEPContext *epctx; 1505 XHCITransfer *xfer; 1506 int killed = 0; 1507 USBEndpoint *ep = NULL; 1508 assert(slotid >= 1 && slotid <= xhci->numslots); 1509 assert(epid >= 1 && epid <= 31); 1510 1511 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1512 1513 slot = &xhci->slots[slotid-1]; 1514 1515 if (!slot->eps[epid-1]) { 1516 return 0; 1517 } 1518 1519 epctx = slot->eps[epid-1]; 1520 1521 for (;;) { 1522 xfer = QTAILQ_FIRST(&epctx->transfers); 1523 if (xfer == NULL) { 1524 break; 1525 } 1526 killed += xhci_ep_nuke_one_xfer(xfer, report); 1527 if (killed) { 1528 report = 0; /* Only report once */ 1529 } 1530 xhci_ep_free_xfer(xfer); 1531 } 1532 1533 ep = xhci_epid_to_usbep(epctx); 1534 if (ep) { 1535 usb_device_ep_stopped(ep->dev, ep); 1536 } 1537 return killed; 1538 } 1539 1540 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1541 unsigned int epid) 1542 { 1543 XHCISlot *slot; 1544 XHCIEPContext *epctx; 1545 1546 trace_usb_xhci_ep_disable(slotid, epid); 1547 assert(slotid >= 1 && slotid <= xhci->numslots); 1548 assert(epid >= 1 && epid <= 31); 1549 1550 slot = &xhci->slots[slotid-1]; 1551 1552 if (!slot->eps[epid-1]) { 1553 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1554 return CC_SUCCESS; 1555 } 1556 1557 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1558 1559 epctx = slot->eps[epid-1]; 1560 1561 if (epctx->nr_pstreams) { 1562 xhci_free_streams(epctx); 1563 } 1564 1565 /* only touch guest RAM if we're not resetting the HC */ 1566 if (xhci->dcbaap_low || xhci->dcbaap_high) { 1567 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1568 } 1569 1570 timer_free(epctx->kick_timer); 1571 g_free(epctx); 1572 slot->eps[epid-1] = NULL; 1573 1574 return CC_SUCCESS; 1575 } 1576 1577 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1578 unsigned int epid) 1579 { 1580 XHCISlot *slot; 1581 XHCIEPContext *epctx; 1582 1583 trace_usb_xhci_ep_stop(slotid, epid); 1584 assert(slotid >= 1 && slotid <= xhci->numslots); 1585 1586 if (epid < 1 || epid > 31) { 1587 DPRINTF("xhci: bad ep %d\n", epid); 1588 return CC_TRB_ERROR; 1589 } 1590 1591 slot = &xhci->slots[slotid-1]; 1592 1593 if (!slot->eps[epid-1]) { 1594 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1595 return CC_EP_NOT_ENABLED_ERROR; 1596 } 1597 1598 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1599 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1600 "data might be lost\n"); 1601 } 1602 1603 epctx = slot->eps[epid-1]; 1604 1605 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1606 1607 if (epctx->nr_pstreams) { 1608 xhci_reset_streams(epctx); 1609 } 1610 1611 return CC_SUCCESS; 1612 } 1613 1614 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1615 unsigned int epid) 1616 { 1617 XHCISlot *slot; 1618 XHCIEPContext *epctx; 1619 1620 trace_usb_xhci_ep_reset(slotid, epid); 1621 assert(slotid >= 1 && slotid <= xhci->numslots); 1622 1623 if (epid < 1 || epid > 31) { 1624 DPRINTF("xhci: bad ep %d\n", epid); 1625 return CC_TRB_ERROR; 1626 } 1627 1628 slot = &xhci->slots[slotid-1]; 1629 1630 if (!slot->eps[epid-1]) { 1631 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1632 return CC_EP_NOT_ENABLED_ERROR; 1633 } 1634 1635 epctx = slot->eps[epid-1]; 1636 1637 if (epctx->state != EP_HALTED) { 1638 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1639 epid, epctx->state); 1640 return CC_CONTEXT_STATE_ERROR; 1641 } 1642 1643 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1644 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1645 "data might be lost\n"); 1646 } 1647 1648 if (!xhci->slots[slotid-1].uport || 1649 !xhci->slots[slotid-1].uport->dev || 1650 !xhci->slots[slotid-1].uport->dev->attached) { 1651 return CC_USB_TRANSACTION_ERROR; 1652 } 1653 1654 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1655 1656 if (epctx->nr_pstreams) { 1657 xhci_reset_streams(epctx); 1658 } 1659 1660 return CC_SUCCESS; 1661 } 1662 1663 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1664 unsigned int epid, unsigned int streamid, 1665 uint64_t pdequeue) 1666 { 1667 XHCISlot *slot; 1668 XHCIEPContext *epctx; 1669 XHCIStreamContext *sctx; 1670 dma_addr_t dequeue; 1671 1672 assert(slotid >= 1 && slotid <= xhci->numslots); 1673 1674 if (epid < 1 || epid > 31) { 1675 DPRINTF("xhci: bad ep %d\n", epid); 1676 return CC_TRB_ERROR; 1677 } 1678 1679 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1680 dequeue = xhci_mask64(pdequeue); 1681 1682 slot = &xhci->slots[slotid-1]; 1683 1684 if (!slot->eps[epid-1]) { 1685 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1686 return CC_EP_NOT_ENABLED_ERROR; 1687 } 1688 1689 epctx = slot->eps[epid-1]; 1690 1691 if (epctx->state != EP_STOPPED) { 1692 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1693 return CC_CONTEXT_STATE_ERROR; 1694 } 1695 1696 if (epctx->nr_pstreams) { 1697 uint32_t err; 1698 sctx = xhci_find_stream(epctx, streamid, &err); 1699 if (sctx == NULL) { 1700 return err; 1701 } 1702 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1703 sctx->ring.ccs = dequeue & 1; 1704 } else { 1705 sctx = NULL; 1706 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1707 epctx->ring.ccs = dequeue & 1; 1708 } 1709 1710 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1711 1712 return CC_SUCCESS; 1713 } 1714 1715 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1716 { 1717 XHCIState *xhci = xfer->epctx->xhci; 1718 int i; 1719 1720 xfer->int_req = false; 1721 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1722 for (i = 0; i < xfer->trb_count; i++) { 1723 XHCITRB *trb = &xfer->trbs[i]; 1724 dma_addr_t addr; 1725 unsigned int chunk = 0; 1726 1727 if (trb->control & TRB_TR_IOC) { 1728 xfer->int_req = true; 1729 } 1730 1731 switch (TRB_TYPE(*trb)) { 1732 case TR_DATA: 1733 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1734 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1735 goto err; 1736 } 1737 /* fallthrough */ 1738 case TR_NORMAL: 1739 case TR_ISOCH: 1740 addr = xhci_mask64(trb->parameter); 1741 chunk = trb->status & 0x1ffff; 1742 if (trb->control & TRB_TR_IDT) { 1743 if (chunk > 8 || in_xfer) { 1744 DPRINTF("xhci: invalid immediate data TRB\n"); 1745 goto err; 1746 } 1747 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1748 } else { 1749 qemu_sglist_add(&xfer->sgl, addr, chunk); 1750 } 1751 break; 1752 } 1753 } 1754 1755 return 0; 1756 1757 err: 1758 qemu_sglist_destroy(&xfer->sgl); 1759 xhci_die(xhci); 1760 return -1; 1761 } 1762 1763 static void xhci_xfer_unmap(XHCITransfer *xfer) 1764 { 1765 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1766 qemu_sglist_destroy(&xfer->sgl); 1767 } 1768 1769 static void xhci_xfer_report(XHCITransfer *xfer) 1770 { 1771 uint32_t edtla = 0; 1772 unsigned int left; 1773 bool reported = 0; 1774 bool shortpkt = 0; 1775 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1776 XHCIState *xhci = xfer->epctx->xhci; 1777 int i; 1778 1779 left = xfer->packet.actual_length; 1780 1781 for (i = 0; i < xfer->trb_count; i++) { 1782 XHCITRB *trb = &xfer->trbs[i]; 1783 unsigned int chunk = 0; 1784 1785 switch (TRB_TYPE(*trb)) { 1786 case TR_SETUP: 1787 chunk = trb->status & 0x1ffff; 1788 if (chunk > 8) { 1789 chunk = 8; 1790 } 1791 break; 1792 case TR_DATA: 1793 case TR_NORMAL: 1794 case TR_ISOCH: 1795 chunk = trb->status & 0x1ffff; 1796 if (chunk > left) { 1797 chunk = left; 1798 if (xfer->status == CC_SUCCESS) { 1799 shortpkt = 1; 1800 } 1801 } 1802 left -= chunk; 1803 edtla += chunk; 1804 break; 1805 case TR_STATUS: 1806 reported = 0; 1807 shortpkt = 0; 1808 break; 1809 } 1810 1811 if (!reported && ((trb->control & TRB_TR_IOC) || 1812 (shortpkt && (trb->control & TRB_TR_ISP)) || 1813 (xfer->status != CC_SUCCESS && left == 0))) { 1814 event.slotid = xfer->epctx->slotid; 1815 event.epid = xfer->epctx->epid; 1816 event.length = (trb->status & 0x1ffff) - chunk; 1817 event.flags = 0; 1818 event.ptr = trb->addr; 1819 if (xfer->status == CC_SUCCESS) { 1820 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1821 } else { 1822 event.ccode = xfer->status; 1823 } 1824 if (TRB_TYPE(*trb) == TR_EVDATA) { 1825 event.ptr = trb->parameter; 1826 event.flags |= TRB_EV_ED; 1827 event.length = edtla & 0xffffff; 1828 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1829 edtla = 0; 1830 } 1831 xhci_event(xhci, &event, TRB_INTR(*trb)); 1832 reported = 1; 1833 if (xfer->status != CC_SUCCESS) { 1834 return; 1835 } 1836 } 1837 1838 switch (TRB_TYPE(*trb)) { 1839 case TR_SETUP: 1840 reported = 0; 1841 shortpkt = 0; 1842 break; 1843 } 1844 1845 } 1846 } 1847 1848 static void xhci_stall_ep(XHCITransfer *xfer) 1849 { 1850 XHCIEPContext *epctx = xfer->epctx; 1851 XHCIState *xhci = epctx->xhci; 1852 uint32_t err; 1853 XHCIStreamContext *sctx; 1854 1855 if (epctx->nr_pstreams) { 1856 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1857 if (sctx == NULL) { 1858 return; 1859 } 1860 sctx->ring.dequeue = xfer->trbs[0].addr; 1861 sctx->ring.ccs = xfer->trbs[0].ccs; 1862 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1863 } else { 1864 epctx->ring.dequeue = xfer->trbs[0].addr; 1865 epctx->ring.ccs = xfer->trbs[0].ccs; 1866 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1867 } 1868 } 1869 1870 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1871 XHCIEPContext *epctx); 1872 1873 static int xhci_setup_packet(XHCITransfer *xfer) 1874 { 1875 USBEndpoint *ep; 1876 int dir; 1877 1878 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1879 1880 if (xfer->packet.ep) { 1881 ep = xfer->packet.ep; 1882 } else { 1883 ep = xhci_epid_to_usbep(xfer->epctx); 1884 if (!ep) { 1885 DPRINTF("xhci: slot %d has no device\n", 1886 xfer->slotid); 1887 return -1; 1888 } 1889 } 1890 1891 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1892 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1893 xfer->trbs[0].addr, false, xfer->int_req); 1894 usb_packet_map(&xfer->packet, &xfer->sgl); 1895 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1896 xfer->packet.pid, ep->dev->addr, ep->nr); 1897 return 0; 1898 } 1899 1900 static int xhci_complete_packet(XHCITransfer *xfer) 1901 { 1902 if (xfer->packet.status == USB_RET_ASYNC) { 1903 trace_usb_xhci_xfer_async(xfer); 1904 xfer->running_async = 1; 1905 xfer->running_retry = 0; 1906 xfer->complete = 0; 1907 return 0; 1908 } else if (xfer->packet.status == USB_RET_NAK) { 1909 trace_usb_xhci_xfer_nak(xfer); 1910 xfer->running_async = 0; 1911 xfer->running_retry = 1; 1912 xfer->complete = 0; 1913 return 0; 1914 } else { 1915 xfer->running_async = 0; 1916 xfer->running_retry = 0; 1917 xfer->complete = 1; 1918 xhci_xfer_unmap(xfer); 1919 } 1920 1921 if (xfer->packet.status == USB_RET_SUCCESS) { 1922 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1923 xfer->status = CC_SUCCESS; 1924 xhci_xfer_report(xfer); 1925 return 0; 1926 } 1927 1928 /* error */ 1929 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1930 switch (xfer->packet.status) { 1931 case USB_RET_NODEV: 1932 case USB_RET_IOERROR: 1933 xfer->status = CC_USB_TRANSACTION_ERROR; 1934 xhci_xfer_report(xfer); 1935 xhci_stall_ep(xfer); 1936 break; 1937 case USB_RET_STALL: 1938 xfer->status = CC_STALL_ERROR; 1939 xhci_xfer_report(xfer); 1940 xhci_stall_ep(xfer); 1941 break; 1942 case USB_RET_BABBLE: 1943 xfer->status = CC_BABBLE_DETECTED; 1944 xhci_xfer_report(xfer); 1945 xhci_stall_ep(xfer); 1946 break; 1947 default: 1948 DPRINTF("%s: FIXME: status = %d\n", __func__, 1949 xfer->packet.status); 1950 FIXME("unhandled USB_RET_*"); 1951 } 1952 return 0; 1953 } 1954 1955 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1956 { 1957 XHCITRB *trb_setup, *trb_status; 1958 uint8_t bmRequestType; 1959 1960 trb_setup = &xfer->trbs[0]; 1961 trb_status = &xfer->trbs[xfer->trb_count-1]; 1962 1963 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 1964 xfer->epctx->epid, xfer->streamid); 1965 1966 /* at most one Event Data TRB allowed after STATUS */ 1967 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1968 trb_status--; 1969 } 1970 1971 /* do some sanity checks */ 1972 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1973 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1974 TRB_TYPE(*trb_setup)); 1975 return -1; 1976 } 1977 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1978 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1979 TRB_TYPE(*trb_status)); 1980 return -1; 1981 } 1982 if (!(trb_setup->control & TRB_TR_IDT)) { 1983 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1984 return -1; 1985 } 1986 if ((trb_setup->status & 0x1ffff) != 8) { 1987 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1988 (trb_setup->status & 0x1ffff)); 1989 return -1; 1990 } 1991 1992 bmRequestType = trb_setup->parameter; 1993 1994 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1995 xfer->iso_xfer = false; 1996 xfer->timed_xfer = false; 1997 1998 if (xhci_setup_packet(xfer) < 0) { 1999 return -1; 2000 } 2001 xfer->packet.parameter = trb_setup->parameter; 2002 2003 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2004 2005 xhci_complete_packet(xfer); 2006 if (!xfer->running_async && !xfer->running_retry) { 2007 xhci_kick_epctx(xfer->epctx, 0); 2008 } 2009 return 0; 2010 } 2011 2012 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 2013 XHCIEPContext *epctx, uint64_t mfindex) 2014 { 2015 uint64_t asap = ((mfindex + epctx->interval - 1) & 2016 ~(epctx->interval-1)); 2017 uint64_t kick = epctx->mfindex_last + epctx->interval; 2018 2019 assert(epctx->interval != 0); 2020 xfer->mfindex_kick = MAX(asap, kick); 2021 } 2022 2023 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 2024 XHCIEPContext *epctx, uint64_t mfindex) 2025 { 2026 if (xfer->trbs[0].control & TRB_TR_SIA) { 2027 uint64_t asap = ((mfindex + epctx->interval - 1) & 2028 ~(epctx->interval-1)); 2029 if (asap >= epctx->mfindex_last && 2030 asap <= epctx->mfindex_last + epctx->interval * 4) { 2031 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 2032 } else { 2033 xfer->mfindex_kick = asap; 2034 } 2035 } else { 2036 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 2037 & TRB_TR_FRAMEID_MASK) << 3; 2038 xfer->mfindex_kick |= mfindex & ~0x3fff; 2039 if (xfer->mfindex_kick + 0x100 < mfindex) { 2040 xfer->mfindex_kick += 0x4000; 2041 } 2042 } 2043 } 2044 2045 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 2046 XHCIEPContext *epctx, uint64_t mfindex) 2047 { 2048 if (xfer->mfindex_kick > mfindex) { 2049 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2050 (xfer->mfindex_kick - mfindex) * 125000); 2051 xfer->running_retry = 1; 2052 } else { 2053 epctx->mfindex_last = xfer->mfindex_kick; 2054 timer_del(epctx->kick_timer); 2055 xfer->running_retry = 0; 2056 } 2057 } 2058 2059 2060 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2061 { 2062 uint64_t mfindex; 2063 2064 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 2065 2066 xfer->in_xfer = epctx->type>>2; 2067 2068 switch(epctx->type) { 2069 case ET_INTR_OUT: 2070 case ET_INTR_IN: 2071 xfer->pkts = 0; 2072 xfer->iso_xfer = false; 2073 xfer->timed_xfer = true; 2074 mfindex = xhci_mfindex_get(xhci); 2075 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 2076 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2077 if (xfer->running_retry) { 2078 return -1; 2079 } 2080 break; 2081 case ET_BULK_OUT: 2082 case ET_BULK_IN: 2083 xfer->pkts = 0; 2084 xfer->iso_xfer = false; 2085 xfer->timed_xfer = false; 2086 break; 2087 case ET_ISO_OUT: 2088 case ET_ISO_IN: 2089 xfer->pkts = 1; 2090 xfer->iso_xfer = true; 2091 xfer->timed_xfer = true; 2092 mfindex = xhci_mfindex_get(xhci); 2093 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 2094 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2095 if (xfer->running_retry) { 2096 return -1; 2097 } 2098 break; 2099 default: 2100 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 2101 return -1; 2102 } 2103 2104 if (xhci_setup_packet(xfer) < 0) { 2105 return -1; 2106 } 2107 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2108 2109 xhci_complete_packet(xfer); 2110 if (!xfer->running_async && !xfer->running_retry) { 2111 xhci_kick_epctx(xfer->epctx, xfer->streamid); 2112 } 2113 return 0; 2114 } 2115 2116 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2117 { 2118 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 2119 xfer->epctx->epid, xfer->streamid); 2120 return xhci_submit(xhci, xfer, epctx); 2121 } 2122 2123 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 2124 unsigned int epid, unsigned int streamid) 2125 { 2126 XHCIEPContext *epctx; 2127 2128 assert(slotid >= 1 && slotid <= xhci->numslots); 2129 assert(epid >= 1 && epid <= 31); 2130 2131 if (!xhci->slots[slotid-1].enabled) { 2132 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 2133 return; 2134 } 2135 epctx = xhci->slots[slotid-1].eps[epid-1]; 2136 if (!epctx) { 2137 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 2138 epid, slotid); 2139 return; 2140 } 2141 2142 xhci_kick_epctx(epctx, streamid); 2143 } 2144 2145 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid) 2146 { 2147 XHCIState *xhci = epctx->xhci; 2148 XHCIStreamContext *stctx; 2149 XHCITransfer *xfer; 2150 XHCIRing *ring; 2151 USBEndpoint *ep = NULL; 2152 uint64_t mfindex; 2153 int length; 2154 int i; 2155 2156 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid); 2157 2158 /* If the device has been detached, but the guest has not noticed this 2159 yet the 2 above checks will succeed, but we must NOT continue */ 2160 if (!xhci->slots[epctx->slotid - 1].uport || 2161 !xhci->slots[epctx->slotid - 1].uport->dev || 2162 !xhci->slots[epctx->slotid - 1].uport->dev->attached) { 2163 return; 2164 } 2165 2166 if (epctx->retry) { 2167 XHCITransfer *xfer = epctx->retry; 2168 2169 trace_usb_xhci_xfer_retry(xfer); 2170 assert(xfer->running_retry); 2171 if (xfer->timed_xfer) { 2172 /* time to kick the transfer? */ 2173 mfindex = xhci_mfindex_get(xhci); 2174 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2175 if (xfer->running_retry) { 2176 return; 2177 } 2178 xfer->timed_xfer = 0; 2179 xfer->running_retry = 1; 2180 } 2181 if (xfer->iso_xfer) { 2182 /* retry iso transfer */ 2183 if (xhci_setup_packet(xfer) < 0) { 2184 return; 2185 } 2186 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2187 assert(xfer->packet.status != USB_RET_NAK); 2188 xhci_complete_packet(xfer); 2189 } else { 2190 /* retry nak'ed transfer */ 2191 if (xhci_setup_packet(xfer) < 0) { 2192 return; 2193 } 2194 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2195 if (xfer->packet.status == USB_RET_NAK) { 2196 return; 2197 } 2198 xhci_complete_packet(xfer); 2199 } 2200 assert(!xfer->running_retry); 2201 if (xfer->complete) { 2202 xhci_ep_free_xfer(epctx->retry); 2203 } 2204 epctx->retry = NULL; 2205 } 2206 2207 if (epctx->state == EP_HALTED) { 2208 DPRINTF("xhci: ep halted, not running schedule\n"); 2209 return; 2210 } 2211 2212 2213 if (epctx->nr_pstreams) { 2214 uint32_t err; 2215 stctx = xhci_find_stream(epctx, streamid, &err); 2216 if (stctx == NULL) { 2217 return; 2218 } 2219 ring = &stctx->ring; 2220 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2221 } else { 2222 ring = &epctx->ring; 2223 streamid = 0; 2224 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2225 } 2226 assert(ring->dequeue != 0); 2227 2228 while (1) { 2229 length = xhci_ring_chain_length(xhci, ring); 2230 if (length <= 0) { 2231 break; 2232 } 2233 xfer = xhci_ep_alloc_xfer(epctx, length); 2234 if (xfer == NULL) { 2235 break; 2236 } 2237 2238 for (i = 0; i < length; i++) { 2239 TRBType type; 2240 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL); 2241 assert(type); 2242 } 2243 xfer->streamid = streamid; 2244 2245 if (epctx->epid == 1) { 2246 xhci_fire_ctl_transfer(xhci, xfer); 2247 } else { 2248 xhci_fire_transfer(xhci, xfer, epctx); 2249 } 2250 if (xfer->complete) { 2251 xhci_ep_free_xfer(xfer); 2252 xfer = NULL; 2253 } 2254 2255 if (epctx->state == EP_HALTED) { 2256 break; 2257 } 2258 if (xfer != NULL && xfer->running_retry) { 2259 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2260 epctx->retry = xfer; 2261 break; 2262 } 2263 } 2264 2265 ep = xhci_epid_to_usbep(epctx); 2266 if (ep) { 2267 usb_device_flush_ep_queue(ep->dev, ep); 2268 } 2269 } 2270 2271 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2272 { 2273 trace_usb_xhci_slot_enable(slotid); 2274 assert(slotid >= 1 && slotid <= xhci->numslots); 2275 xhci->slots[slotid-1].enabled = 1; 2276 xhci->slots[slotid-1].uport = NULL; 2277 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2278 2279 return CC_SUCCESS; 2280 } 2281 2282 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2283 { 2284 int i; 2285 2286 trace_usb_xhci_slot_disable(slotid); 2287 assert(slotid >= 1 && slotid <= xhci->numslots); 2288 2289 for (i = 1; i <= 31; i++) { 2290 if (xhci->slots[slotid-1].eps[i-1]) { 2291 xhci_disable_ep(xhci, slotid, i); 2292 } 2293 } 2294 2295 xhci->slots[slotid-1].enabled = 0; 2296 xhci->slots[slotid-1].addressed = 0; 2297 xhci->slots[slotid-1].uport = NULL; 2298 return CC_SUCCESS; 2299 } 2300 2301 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2302 { 2303 USBPort *uport; 2304 char path[32]; 2305 int i, pos, port; 2306 2307 port = (slot_ctx[1]>>16) & 0xFF; 2308 if (port < 1 || port > xhci->numports) { 2309 return NULL; 2310 } 2311 port = xhci->ports[port-1].uport->index+1; 2312 pos = snprintf(path, sizeof(path), "%d", port); 2313 for (i = 0; i < 5; i++) { 2314 port = (slot_ctx[0] >> 4*i) & 0x0f; 2315 if (!port) { 2316 break; 2317 } 2318 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2319 } 2320 2321 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2322 if (strcmp(uport->path, path) == 0) { 2323 return uport; 2324 } 2325 } 2326 return NULL; 2327 } 2328 2329 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2330 uint64_t pictx, bool bsr) 2331 { 2332 XHCISlot *slot; 2333 USBPort *uport; 2334 USBDevice *dev; 2335 dma_addr_t ictx, octx, dcbaap; 2336 uint64_t poctx; 2337 uint32_t ictl_ctx[2]; 2338 uint32_t slot_ctx[4]; 2339 uint32_t ep0_ctx[5]; 2340 int i; 2341 TRBCCode res; 2342 2343 assert(slotid >= 1 && slotid <= xhci->numslots); 2344 2345 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2346 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2347 ictx = xhci_mask64(pictx); 2348 octx = xhci_mask64(poctx); 2349 2350 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2351 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2352 2353 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2354 2355 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2356 DPRINTF("xhci: invalid input context control %08x %08x\n", 2357 ictl_ctx[0], ictl_ctx[1]); 2358 return CC_TRB_ERROR; 2359 } 2360 2361 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2362 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2363 2364 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2365 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2366 2367 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2368 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2369 2370 uport = xhci_lookup_uport(xhci, slot_ctx); 2371 if (uport == NULL) { 2372 DPRINTF("xhci: port not found\n"); 2373 return CC_TRB_ERROR; 2374 } 2375 trace_usb_xhci_slot_address(slotid, uport->path); 2376 2377 dev = uport->dev; 2378 if (!dev || !dev->attached) { 2379 DPRINTF("xhci: port %s not connected\n", uport->path); 2380 return CC_USB_TRANSACTION_ERROR; 2381 } 2382 2383 for (i = 0; i < xhci->numslots; i++) { 2384 if (i == slotid-1) { 2385 continue; 2386 } 2387 if (xhci->slots[i].uport == uport) { 2388 DPRINTF("xhci: port %s already assigned to slot %d\n", 2389 uport->path, i+1); 2390 return CC_TRB_ERROR; 2391 } 2392 } 2393 2394 slot = &xhci->slots[slotid-1]; 2395 slot->uport = uport; 2396 slot->ctx = octx; 2397 2398 /* Make sure device is in USB_STATE_DEFAULT state */ 2399 usb_device_reset(dev); 2400 if (bsr) { 2401 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2402 } else { 2403 USBPacket p; 2404 uint8_t buf[1]; 2405 2406 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2407 memset(&p, 0, sizeof(p)); 2408 usb_packet_addbuf(&p, buf, sizeof(buf)); 2409 usb_packet_setup(&p, USB_TOKEN_OUT, 2410 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2411 0, false, false); 2412 usb_device_handle_control(dev, &p, 2413 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2414 slotid, 0, 0, NULL); 2415 assert(p.status != USB_RET_ASYNC); 2416 } 2417 2418 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2419 2420 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2421 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2422 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2423 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2424 2425 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2426 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2427 2428 xhci->slots[slotid-1].addressed = 1; 2429 return res; 2430 } 2431 2432 2433 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2434 uint64_t pictx, bool dc) 2435 { 2436 dma_addr_t ictx, octx; 2437 uint32_t ictl_ctx[2]; 2438 uint32_t slot_ctx[4]; 2439 uint32_t islot_ctx[4]; 2440 uint32_t ep_ctx[5]; 2441 int i; 2442 TRBCCode res; 2443 2444 trace_usb_xhci_slot_configure(slotid); 2445 assert(slotid >= 1 && slotid <= xhci->numslots); 2446 2447 ictx = xhci_mask64(pictx); 2448 octx = xhci->slots[slotid-1].ctx; 2449 2450 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2451 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2452 2453 if (dc) { 2454 for (i = 2; i <= 31; i++) { 2455 if (xhci->slots[slotid-1].eps[i-1]) { 2456 xhci_disable_ep(xhci, slotid, i); 2457 } 2458 } 2459 2460 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2461 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2462 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2463 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2464 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2465 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2466 2467 return CC_SUCCESS; 2468 } 2469 2470 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2471 2472 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2473 DPRINTF("xhci: invalid input context control %08x %08x\n", 2474 ictl_ctx[0], ictl_ctx[1]); 2475 return CC_TRB_ERROR; 2476 } 2477 2478 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2479 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2480 2481 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2482 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2483 return CC_CONTEXT_STATE_ERROR; 2484 } 2485 2486 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2487 2488 for (i = 2; i <= 31; i++) { 2489 if (ictl_ctx[0] & (1<<i)) { 2490 xhci_disable_ep(xhci, slotid, i); 2491 } 2492 if (ictl_ctx[1] & (1<<i)) { 2493 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2494 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2495 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2496 ep_ctx[3], ep_ctx[4]); 2497 xhci_disable_ep(xhci, slotid, i); 2498 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2499 if (res != CC_SUCCESS) { 2500 return res; 2501 } 2502 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2503 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2504 ep_ctx[3], ep_ctx[4]); 2505 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2506 } 2507 } 2508 2509 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2510 if (res != CC_SUCCESS) { 2511 for (i = 2; i <= 31; i++) { 2512 if (ictl_ctx[1] & (1u << i)) { 2513 xhci_disable_ep(xhci, slotid, i); 2514 } 2515 } 2516 return res; 2517 } 2518 2519 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2520 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2521 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2522 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2523 SLOT_CONTEXT_ENTRIES_SHIFT); 2524 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2525 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2526 2527 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2528 2529 return CC_SUCCESS; 2530 } 2531 2532 2533 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2534 uint64_t pictx) 2535 { 2536 dma_addr_t ictx, octx; 2537 uint32_t ictl_ctx[2]; 2538 uint32_t iep0_ctx[5]; 2539 uint32_t ep0_ctx[5]; 2540 uint32_t islot_ctx[4]; 2541 uint32_t slot_ctx[4]; 2542 2543 trace_usb_xhci_slot_evaluate(slotid); 2544 assert(slotid >= 1 && slotid <= xhci->numslots); 2545 2546 ictx = xhci_mask64(pictx); 2547 octx = xhci->slots[slotid-1].ctx; 2548 2549 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2550 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2551 2552 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2553 2554 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2555 DPRINTF("xhci: invalid input context control %08x %08x\n", 2556 ictl_ctx[0], ictl_ctx[1]); 2557 return CC_TRB_ERROR; 2558 } 2559 2560 if (ictl_ctx[1] & 0x1) { 2561 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2562 2563 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2564 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2565 2566 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2567 2568 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2569 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2570 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2571 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2572 2573 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2574 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2575 2576 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2577 } 2578 2579 if (ictl_ctx[1] & 0x2) { 2580 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2581 2582 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2583 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2584 iep0_ctx[3], iep0_ctx[4]); 2585 2586 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2587 2588 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2589 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2590 2591 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2592 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2593 2594 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2595 } 2596 2597 return CC_SUCCESS; 2598 } 2599 2600 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2601 { 2602 uint32_t slot_ctx[4]; 2603 dma_addr_t octx; 2604 int i; 2605 2606 trace_usb_xhci_slot_reset(slotid); 2607 assert(slotid >= 1 && slotid <= xhci->numslots); 2608 2609 octx = xhci->slots[slotid-1].ctx; 2610 2611 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2612 2613 for (i = 2; i <= 31; i++) { 2614 if (xhci->slots[slotid-1].eps[i-1]) { 2615 xhci_disable_ep(xhci, slotid, i); 2616 } 2617 } 2618 2619 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2620 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2621 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2622 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2623 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2624 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2625 2626 return CC_SUCCESS; 2627 } 2628 2629 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2630 { 2631 unsigned int slotid; 2632 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2633 if (slotid < 1 || slotid > xhci->numslots) { 2634 DPRINTF("xhci: bad slot id %d\n", slotid); 2635 event->ccode = CC_TRB_ERROR; 2636 return 0; 2637 } else if (!xhci->slots[slotid-1].enabled) { 2638 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2639 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2640 return 0; 2641 } 2642 return slotid; 2643 } 2644 2645 /* cleanup slot state on usb device detach */ 2646 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2647 { 2648 int slot, ep; 2649 2650 for (slot = 0; slot < xhci->numslots; slot++) { 2651 if (xhci->slots[slot].uport == uport) { 2652 break; 2653 } 2654 } 2655 if (slot == xhci->numslots) { 2656 return; 2657 } 2658 2659 for (ep = 0; ep < 31; ep++) { 2660 if (xhci->slots[slot].eps[ep]) { 2661 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2662 } 2663 } 2664 xhci->slots[slot].uport = NULL; 2665 } 2666 2667 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2668 { 2669 dma_addr_t ctx; 2670 uint8_t bw_ctx[xhci->numports+1]; 2671 2672 DPRINTF("xhci_get_port_bandwidth()\n"); 2673 2674 ctx = xhci_mask64(pctx); 2675 2676 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2677 2678 /* TODO: actually implement real values here */ 2679 bw_ctx[0] = 0; 2680 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2681 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2682 2683 return CC_SUCCESS; 2684 } 2685 2686 static uint32_t rotl(uint32_t v, unsigned count) 2687 { 2688 count &= 31; 2689 return (v << count) | (v >> (32 - count)); 2690 } 2691 2692 2693 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2694 { 2695 uint32_t val; 2696 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2697 val += rotl(lo + 0x49434878, hi & 0x1F); 2698 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2699 return ~val; 2700 } 2701 2702 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2703 { 2704 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2705 uint32_t buf[8]; 2706 uint32_t obuf[8]; 2707 dma_addr_t paddr = xhci_mask64(addr); 2708 2709 pci_dma_read(pci_dev, paddr, &buf, 32); 2710 2711 memcpy(obuf, buf, sizeof(obuf)); 2712 2713 if ((buf[0] & 0xff) == 2) { 2714 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2715 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2716 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2717 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2718 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2719 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2720 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2721 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2722 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2723 } 2724 2725 pci_dma_write(pci_dev, paddr, &obuf, 32); 2726 } 2727 2728 static void xhci_process_commands(XHCIState *xhci) 2729 { 2730 XHCITRB trb; 2731 TRBType type; 2732 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2733 dma_addr_t addr; 2734 unsigned int i, slotid = 0; 2735 2736 DPRINTF("xhci_process_commands()\n"); 2737 if (!xhci_running(xhci)) { 2738 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2739 return; 2740 } 2741 2742 xhci->crcr_low |= CRCR_CRR; 2743 2744 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2745 event.ptr = addr; 2746 switch (type) { 2747 case CR_ENABLE_SLOT: 2748 for (i = 0; i < xhci->numslots; i++) { 2749 if (!xhci->slots[i].enabled) { 2750 break; 2751 } 2752 } 2753 if (i >= xhci->numslots) { 2754 DPRINTF("xhci: no device slots available\n"); 2755 event.ccode = CC_NO_SLOTS_ERROR; 2756 } else { 2757 slotid = i+1; 2758 event.ccode = xhci_enable_slot(xhci, slotid); 2759 } 2760 break; 2761 case CR_DISABLE_SLOT: 2762 slotid = xhci_get_slot(xhci, &event, &trb); 2763 if (slotid) { 2764 event.ccode = xhci_disable_slot(xhci, slotid); 2765 } 2766 break; 2767 case CR_ADDRESS_DEVICE: 2768 slotid = xhci_get_slot(xhci, &event, &trb); 2769 if (slotid) { 2770 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2771 trb.control & TRB_CR_BSR); 2772 } 2773 break; 2774 case CR_CONFIGURE_ENDPOINT: 2775 slotid = xhci_get_slot(xhci, &event, &trb); 2776 if (slotid) { 2777 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2778 trb.control & TRB_CR_DC); 2779 } 2780 break; 2781 case CR_EVALUATE_CONTEXT: 2782 slotid = xhci_get_slot(xhci, &event, &trb); 2783 if (slotid) { 2784 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2785 } 2786 break; 2787 case CR_STOP_ENDPOINT: 2788 slotid = xhci_get_slot(xhci, &event, &trb); 2789 if (slotid) { 2790 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2791 & TRB_CR_EPID_MASK; 2792 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2793 } 2794 break; 2795 case CR_RESET_ENDPOINT: 2796 slotid = xhci_get_slot(xhci, &event, &trb); 2797 if (slotid) { 2798 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2799 & TRB_CR_EPID_MASK; 2800 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2801 } 2802 break; 2803 case CR_SET_TR_DEQUEUE: 2804 slotid = xhci_get_slot(xhci, &event, &trb); 2805 if (slotid) { 2806 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2807 & TRB_CR_EPID_MASK; 2808 unsigned int streamid = (trb.status >> 16) & 0xffff; 2809 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2810 epid, streamid, 2811 trb.parameter); 2812 } 2813 break; 2814 case CR_RESET_DEVICE: 2815 slotid = xhci_get_slot(xhci, &event, &trb); 2816 if (slotid) { 2817 event.ccode = xhci_reset_slot(xhci, slotid); 2818 } 2819 break; 2820 case CR_GET_PORT_BANDWIDTH: 2821 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2822 break; 2823 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2824 xhci_via_challenge(xhci, trb.parameter); 2825 break; 2826 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2827 event.type = 48; /* NEC reply */ 2828 event.length = 0x3025; 2829 break; 2830 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2831 { 2832 uint32_t chi = trb.parameter >> 32; 2833 uint32_t clo = trb.parameter; 2834 uint32_t val = xhci_nec_challenge(chi, clo); 2835 event.length = val & 0xFFFF; 2836 event.epid = val >> 16; 2837 slotid = val >> 24; 2838 event.type = 48; /* NEC reply */ 2839 } 2840 break; 2841 default: 2842 trace_usb_xhci_unimplemented("command", type); 2843 event.ccode = CC_TRB_ERROR; 2844 break; 2845 } 2846 event.slotid = slotid; 2847 xhci_event(xhci, &event, 0); 2848 } 2849 } 2850 2851 static bool xhci_port_have_device(XHCIPort *port) 2852 { 2853 if (!port->uport->dev || !port->uport->dev->attached) { 2854 return false; /* no device present */ 2855 } 2856 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2857 return false; /* speed mismatch */ 2858 } 2859 return true; 2860 } 2861 2862 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2863 { 2864 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2865 port->portnr << 24 }; 2866 2867 if ((port->portsc & bits) == bits) { 2868 return; 2869 } 2870 trace_usb_xhci_port_notify(port->portnr, bits); 2871 port->portsc |= bits; 2872 if (!xhci_running(port->xhci)) { 2873 return; 2874 } 2875 xhci_event(port->xhci, &ev, 0); 2876 } 2877 2878 static void xhci_port_update(XHCIPort *port, int is_detach) 2879 { 2880 uint32_t pls = PLS_RX_DETECT; 2881 2882 port->portsc = PORTSC_PP; 2883 if (!is_detach && xhci_port_have_device(port)) { 2884 port->portsc |= PORTSC_CCS; 2885 switch (port->uport->dev->speed) { 2886 case USB_SPEED_LOW: 2887 port->portsc |= PORTSC_SPEED_LOW; 2888 pls = PLS_POLLING; 2889 break; 2890 case USB_SPEED_FULL: 2891 port->portsc |= PORTSC_SPEED_FULL; 2892 pls = PLS_POLLING; 2893 break; 2894 case USB_SPEED_HIGH: 2895 port->portsc |= PORTSC_SPEED_HIGH; 2896 pls = PLS_POLLING; 2897 break; 2898 case USB_SPEED_SUPER: 2899 port->portsc |= PORTSC_SPEED_SUPER; 2900 port->portsc |= PORTSC_PED; 2901 pls = PLS_U0; 2902 break; 2903 } 2904 } 2905 set_field(&port->portsc, pls, PORTSC_PLS); 2906 trace_usb_xhci_port_link(port->portnr, pls); 2907 xhci_port_notify(port, PORTSC_CSC); 2908 } 2909 2910 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2911 { 2912 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2913 2914 if (!xhci_port_have_device(port)) { 2915 return; 2916 } 2917 2918 usb_device_reset(port->uport->dev); 2919 2920 switch (port->uport->dev->speed) { 2921 case USB_SPEED_SUPER: 2922 if (warm_reset) { 2923 port->portsc |= PORTSC_WRC; 2924 } 2925 /* fall through */ 2926 case USB_SPEED_LOW: 2927 case USB_SPEED_FULL: 2928 case USB_SPEED_HIGH: 2929 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2930 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2931 port->portsc |= PORTSC_PED; 2932 break; 2933 } 2934 2935 port->portsc &= ~PORTSC_PR; 2936 xhci_port_notify(port, PORTSC_PRC); 2937 } 2938 2939 static void xhci_reset(DeviceState *dev) 2940 { 2941 XHCIState *xhci = XHCI(dev); 2942 int i; 2943 2944 trace_usb_xhci_reset(); 2945 if (!(xhci->usbsts & USBSTS_HCH)) { 2946 DPRINTF("xhci: reset while running!\n"); 2947 } 2948 2949 xhci->usbcmd = 0; 2950 xhci->usbsts = USBSTS_HCH; 2951 xhci->dnctrl = 0; 2952 xhci->crcr_low = 0; 2953 xhci->crcr_high = 0; 2954 xhci->dcbaap_low = 0; 2955 xhci->dcbaap_high = 0; 2956 xhci->config = 0; 2957 2958 for (i = 0; i < xhci->numslots; i++) { 2959 xhci_disable_slot(xhci, i+1); 2960 } 2961 2962 for (i = 0; i < xhci->numports; i++) { 2963 xhci_port_update(xhci->ports + i, 0); 2964 } 2965 2966 for (i = 0; i < xhci->numintrs; i++) { 2967 xhci->intr[i].iman = 0; 2968 xhci->intr[i].imod = 0; 2969 xhci->intr[i].erstsz = 0; 2970 xhci->intr[i].erstba_low = 0; 2971 xhci->intr[i].erstba_high = 0; 2972 xhci->intr[i].erdp_low = 0; 2973 xhci->intr[i].erdp_high = 0; 2974 xhci->intr[i].msix_used = 0; 2975 2976 xhci->intr[i].er_ep_idx = 0; 2977 xhci->intr[i].er_pcs = 1; 2978 xhci->intr[i].er_full = 0; 2979 xhci->intr[i].ev_buffer_put = 0; 2980 xhci->intr[i].ev_buffer_get = 0; 2981 } 2982 2983 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2984 xhci_mfwrap_update(xhci); 2985 } 2986 2987 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2988 { 2989 XHCIState *xhci = ptr; 2990 uint32_t ret; 2991 2992 switch (reg) { 2993 case 0x00: /* HCIVERSION, CAPLENGTH */ 2994 ret = 0x01000000 | LEN_CAP; 2995 break; 2996 case 0x04: /* HCSPARAMS 1 */ 2997 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2998 | (xhci->numintrs<<8) | xhci->numslots; 2999 break; 3000 case 0x08: /* HCSPARAMS 2 */ 3001 ret = 0x0000000f; 3002 break; 3003 case 0x0c: /* HCSPARAMS 3 */ 3004 ret = 0x00000000; 3005 break; 3006 case 0x10: /* HCCPARAMS */ 3007 if (sizeof(dma_addr_t) == 4) { 3008 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 3009 } else { 3010 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 3011 } 3012 break; 3013 case 0x14: /* DBOFF */ 3014 ret = OFF_DOORBELL; 3015 break; 3016 case 0x18: /* RTSOFF */ 3017 ret = OFF_RUNTIME; 3018 break; 3019 3020 /* extended capabilities */ 3021 case 0x20: /* Supported Protocol:00 */ 3022 ret = 0x02000402; /* USB 2.0 */ 3023 break; 3024 case 0x24: /* Supported Protocol:04 */ 3025 ret = 0x20425355; /* "USB " */ 3026 break; 3027 case 0x28: /* Supported Protocol:08 */ 3028 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3029 ret = (xhci->numports_2<<8) | (xhci->numports_3+1); 3030 } else { 3031 ret = (xhci->numports_2<<8) | 1; 3032 } 3033 break; 3034 case 0x2c: /* Supported Protocol:0c */ 3035 ret = 0x00000000; /* reserved */ 3036 break; 3037 case 0x30: /* Supported Protocol:00 */ 3038 ret = 0x03000002; /* USB 3.0 */ 3039 break; 3040 case 0x34: /* Supported Protocol:04 */ 3041 ret = 0x20425355; /* "USB " */ 3042 break; 3043 case 0x38: /* Supported Protocol:08 */ 3044 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3045 ret = (xhci->numports_3<<8) | 1; 3046 } else { 3047 ret = (xhci->numports_3<<8) | (xhci->numports_2+1); 3048 } 3049 break; 3050 case 0x3c: /* Supported Protocol:0c */ 3051 ret = 0x00000000; /* reserved */ 3052 break; 3053 default: 3054 trace_usb_xhci_unimplemented("cap read", reg); 3055 ret = 0; 3056 } 3057 3058 trace_usb_xhci_cap_read(reg, ret); 3059 return ret; 3060 } 3061 3062 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 3063 { 3064 XHCIPort *port = ptr; 3065 uint32_t ret; 3066 3067 switch (reg) { 3068 case 0x00: /* PORTSC */ 3069 ret = port->portsc; 3070 break; 3071 case 0x04: /* PORTPMSC */ 3072 case 0x08: /* PORTLI */ 3073 ret = 0; 3074 break; 3075 case 0x0c: /* reserved */ 3076 default: 3077 trace_usb_xhci_unimplemented("port read", reg); 3078 ret = 0; 3079 } 3080 3081 trace_usb_xhci_port_read(port->portnr, reg, ret); 3082 return ret; 3083 } 3084 3085 static void xhci_port_write(void *ptr, hwaddr reg, 3086 uint64_t val, unsigned size) 3087 { 3088 XHCIPort *port = ptr; 3089 uint32_t portsc, notify; 3090 3091 trace_usb_xhci_port_write(port->portnr, reg, val); 3092 3093 switch (reg) { 3094 case 0x00: /* PORTSC */ 3095 /* write-1-to-start bits */ 3096 if (val & PORTSC_WPR) { 3097 xhci_port_reset(port, true); 3098 break; 3099 } 3100 if (val & PORTSC_PR) { 3101 xhci_port_reset(port, false); 3102 break; 3103 } 3104 3105 portsc = port->portsc; 3106 notify = 0; 3107 /* write-1-to-clear bits*/ 3108 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 3109 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 3110 if (val & PORTSC_LWS) { 3111 /* overwrite PLS only when LWS=1 */ 3112 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 3113 uint32_t new_pls = get_field(val, PORTSC_PLS); 3114 switch (new_pls) { 3115 case PLS_U0: 3116 if (old_pls != PLS_U0) { 3117 set_field(&portsc, new_pls, PORTSC_PLS); 3118 trace_usb_xhci_port_link(port->portnr, new_pls); 3119 notify = PORTSC_PLC; 3120 } 3121 break; 3122 case PLS_U3: 3123 if (old_pls < PLS_U3) { 3124 set_field(&portsc, new_pls, PORTSC_PLS); 3125 trace_usb_xhci_port_link(port->portnr, new_pls); 3126 } 3127 break; 3128 case PLS_RESUME: 3129 /* windows does this for some reason, don't spam stderr */ 3130 break; 3131 default: 3132 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 3133 __func__, old_pls, new_pls); 3134 break; 3135 } 3136 } 3137 /* read/write bits */ 3138 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 3139 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 3140 port->portsc = portsc; 3141 if (notify) { 3142 xhci_port_notify(port, notify); 3143 } 3144 break; 3145 case 0x04: /* PORTPMSC */ 3146 case 0x08: /* PORTLI */ 3147 default: 3148 trace_usb_xhci_unimplemented("port write", reg); 3149 } 3150 } 3151 3152 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 3153 { 3154 XHCIState *xhci = ptr; 3155 uint32_t ret; 3156 3157 switch (reg) { 3158 case 0x00: /* USBCMD */ 3159 ret = xhci->usbcmd; 3160 break; 3161 case 0x04: /* USBSTS */ 3162 ret = xhci->usbsts; 3163 break; 3164 case 0x08: /* PAGESIZE */ 3165 ret = 1; /* 4KiB */ 3166 break; 3167 case 0x14: /* DNCTRL */ 3168 ret = xhci->dnctrl; 3169 break; 3170 case 0x18: /* CRCR low */ 3171 ret = xhci->crcr_low & ~0xe; 3172 break; 3173 case 0x1c: /* CRCR high */ 3174 ret = xhci->crcr_high; 3175 break; 3176 case 0x30: /* DCBAAP low */ 3177 ret = xhci->dcbaap_low; 3178 break; 3179 case 0x34: /* DCBAAP high */ 3180 ret = xhci->dcbaap_high; 3181 break; 3182 case 0x38: /* CONFIG */ 3183 ret = xhci->config; 3184 break; 3185 default: 3186 trace_usb_xhci_unimplemented("oper read", reg); 3187 ret = 0; 3188 } 3189 3190 trace_usb_xhci_oper_read(reg, ret); 3191 return ret; 3192 } 3193 3194 static void xhci_oper_write(void *ptr, hwaddr reg, 3195 uint64_t val, unsigned size) 3196 { 3197 XHCIState *xhci = ptr; 3198 DeviceState *d = DEVICE(ptr); 3199 3200 trace_usb_xhci_oper_write(reg, val); 3201 3202 switch (reg) { 3203 case 0x00: /* USBCMD */ 3204 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3205 xhci_run(xhci); 3206 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3207 xhci_stop(xhci); 3208 } 3209 if (val & USBCMD_CSS) { 3210 /* save state */ 3211 xhci->usbsts &= ~USBSTS_SRE; 3212 } 3213 if (val & USBCMD_CRS) { 3214 /* restore state */ 3215 xhci->usbsts |= USBSTS_SRE; 3216 } 3217 xhci->usbcmd = val & 0xc0f; 3218 xhci_mfwrap_update(xhci); 3219 if (val & USBCMD_HCRST) { 3220 xhci_reset(d); 3221 } 3222 xhci_intx_update(xhci); 3223 break; 3224 3225 case 0x04: /* USBSTS */ 3226 /* these bits are write-1-to-clear */ 3227 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3228 xhci_intx_update(xhci); 3229 break; 3230 3231 case 0x14: /* DNCTRL */ 3232 xhci->dnctrl = val & 0xffff; 3233 break; 3234 case 0x18: /* CRCR low */ 3235 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3236 break; 3237 case 0x1c: /* CRCR high */ 3238 xhci->crcr_high = val; 3239 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3240 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3241 xhci->crcr_low &= ~CRCR_CRR; 3242 xhci_event(xhci, &event, 0); 3243 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3244 } else { 3245 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3246 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3247 } 3248 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3249 break; 3250 case 0x30: /* DCBAAP low */ 3251 xhci->dcbaap_low = val & 0xffffffc0; 3252 break; 3253 case 0x34: /* DCBAAP high */ 3254 xhci->dcbaap_high = val; 3255 break; 3256 case 0x38: /* CONFIG */ 3257 xhci->config = val & 0xff; 3258 break; 3259 default: 3260 trace_usb_xhci_unimplemented("oper write", reg); 3261 } 3262 } 3263 3264 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3265 unsigned size) 3266 { 3267 XHCIState *xhci = ptr; 3268 uint32_t ret = 0; 3269 3270 if (reg < 0x20) { 3271 switch (reg) { 3272 case 0x00: /* MFINDEX */ 3273 ret = xhci_mfindex_get(xhci) & 0x3fff; 3274 break; 3275 default: 3276 trace_usb_xhci_unimplemented("runtime read", reg); 3277 break; 3278 } 3279 } else { 3280 int v = (reg - 0x20) / 0x20; 3281 XHCIInterrupter *intr = &xhci->intr[v]; 3282 switch (reg & 0x1f) { 3283 case 0x00: /* IMAN */ 3284 ret = intr->iman; 3285 break; 3286 case 0x04: /* IMOD */ 3287 ret = intr->imod; 3288 break; 3289 case 0x08: /* ERSTSZ */ 3290 ret = intr->erstsz; 3291 break; 3292 case 0x10: /* ERSTBA low */ 3293 ret = intr->erstba_low; 3294 break; 3295 case 0x14: /* ERSTBA high */ 3296 ret = intr->erstba_high; 3297 break; 3298 case 0x18: /* ERDP low */ 3299 ret = intr->erdp_low; 3300 break; 3301 case 0x1c: /* ERDP high */ 3302 ret = intr->erdp_high; 3303 break; 3304 } 3305 } 3306 3307 trace_usb_xhci_runtime_read(reg, ret); 3308 return ret; 3309 } 3310 3311 static void xhci_runtime_write(void *ptr, hwaddr reg, 3312 uint64_t val, unsigned size) 3313 { 3314 XHCIState *xhci = ptr; 3315 int v = (reg - 0x20) / 0x20; 3316 XHCIInterrupter *intr = &xhci->intr[v]; 3317 trace_usb_xhci_runtime_write(reg, val); 3318 3319 if (reg < 0x20) { 3320 trace_usb_xhci_unimplemented("runtime write", reg); 3321 return; 3322 } 3323 3324 switch (reg & 0x1f) { 3325 case 0x00: /* IMAN */ 3326 if (val & IMAN_IP) { 3327 intr->iman &= ~IMAN_IP; 3328 } 3329 intr->iman &= ~IMAN_IE; 3330 intr->iman |= val & IMAN_IE; 3331 if (v == 0) { 3332 xhci_intx_update(xhci); 3333 } 3334 xhci_msix_update(xhci, v); 3335 break; 3336 case 0x04: /* IMOD */ 3337 intr->imod = val; 3338 break; 3339 case 0x08: /* ERSTSZ */ 3340 intr->erstsz = val & 0xffff; 3341 break; 3342 case 0x10: /* ERSTBA low */ 3343 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3344 intr->erstba_low = val & 0xffffffc0; */ 3345 intr->erstba_low = val & 0xfffffff0; 3346 break; 3347 case 0x14: /* ERSTBA high */ 3348 intr->erstba_high = val; 3349 xhci_er_reset(xhci, v); 3350 break; 3351 case 0x18: /* ERDP low */ 3352 if (val & ERDP_EHB) { 3353 intr->erdp_low &= ~ERDP_EHB; 3354 } 3355 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3356 break; 3357 case 0x1c: /* ERDP high */ 3358 intr->erdp_high = val; 3359 xhci_events_update(xhci, v); 3360 break; 3361 default: 3362 trace_usb_xhci_unimplemented("oper write", reg); 3363 } 3364 } 3365 3366 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3367 unsigned size) 3368 { 3369 /* doorbells always read as 0 */ 3370 trace_usb_xhci_doorbell_read(reg, 0); 3371 return 0; 3372 } 3373 3374 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3375 uint64_t val, unsigned size) 3376 { 3377 XHCIState *xhci = ptr; 3378 unsigned int epid, streamid; 3379 3380 trace_usb_xhci_doorbell_write(reg, val); 3381 3382 if (!xhci_running(xhci)) { 3383 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3384 return; 3385 } 3386 3387 reg >>= 2; 3388 3389 if (reg == 0) { 3390 if (val == 0) { 3391 xhci_process_commands(xhci); 3392 } else { 3393 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3394 (uint32_t)val); 3395 } 3396 } else { 3397 epid = val & 0xff; 3398 streamid = (val >> 16) & 0xffff; 3399 if (reg > xhci->numslots) { 3400 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3401 } else if (epid > 31) { 3402 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3403 (int)reg, (uint32_t)val); 3404 } else { 3405 xhci_kick_ep(xhci, reg, epid, streamid); 3406 } 3407 } 3408 } 3409 3410 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3411 unsigned width) 3412 { 3413 /* nothing */ 3414 } 3415 3416 static const MemoryRegionOps xhci_cap_ops = { 3417 .read = xhci_cap_read, 3418 .write = xhci_cap_write, 3419 .valid.min_access_size = 1, 3420 .valid.max_access_size = 4, 3421 .impl.min_access_size = 4, 3422 .impl.max_access_size = 4, 3423 .endianness = DEVICE_LITTLE_ENDIAN, 3424 }; 3425 3426 static const MemoryRegionOps xhci_oper_ops = { 3427 .read = xhci_oper_read, 3428 .write = xhci_oper_write, 3429 .valid.min_access_size = 4, 3430 .valid.max_access_size = 4, 3431 .endianness = DEVICE_LITTLE_ENDIAN, 3432 }; 3433 3434 static const MemoryRegionOps xhci_port_ops = { 3435 .read = xhci_port_read, 3436 .write = xhci_port_write, 3437 .valid.min_access_size = 4, 3438 .valid.max_access_size = 4, 3439 .endianness = DEVICE_LITTLE_ENDIAN, 3440 }; 3441 3442 static const MemoryRegionOps xhci_runtime_ops = { 3443 .read = xhci_runtime_read, 3444 .write = xhci_runtime_write, 3445 .valid.min_access_size = 4, 3446 .valid.max_access_size = 4, 3447 .endianness = DEVICE_LITTLE_ENDIAN, 3448 }; 3449 3450 static const MemoryRegionOps xhci_doorbell_ops = { 3451 .read = xhci_doorbell_read, 3452 .write = xhci_doorbell_write, 3453 .valid.min_access_size = 4, 3454 .valid.max_access_size = 4, 3455 .endianness = DEVICE_LITTLE_ENDIAN, 3456 }; 3457 3458 static void xhci_attach(USBPort *usbport) 3459 { 3460 XHCIState *xhci = usbport->opaque; 3461 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3462 3463 xhci_port_update(port, 0); 3464 } 3465 3466 static void xhci_detach(USBPort *usbport) 3467 { 3468 XHCIState *xhci = usbport->opaque; 3469 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3470 3471 xhci_detach_slot(xhci, usbport); 3472 xhci_port_update(port, 1); 3473 } 3474 3475 static void xhci_wakeup(USBPort *usbport) 3476 { 3477 XHCIState *xhci = usbport->opaque; 3478 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3479 3480 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3481 return; 3482 } 3483 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3484 xhci_port_notify(port, PORTSC_PLC); 3485 } 3486 3487 static void xhci_complete(USBPort *port, USBPacket *packet) 3488 { 3489 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3490 3491 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3492 xhci_ep_nuke_one_xfer(xfer, 0); 3493 return; 3494 } 3495 xhci_complete_packet(xfer); 3496 xhci_kick_epctx(xfer->epctx, xfer->streamid); 3497 if (xfer->complete) { 3498 xhci_ep_free_xfer(xfer); 3499 } 3500 } 3501 3502 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3503 { 3504 USBBus *bus = usb_bus_from_device(child); 3505 XHCIState *xhci = container_of(bus, XHCIState, bus); 3506 3507 xhci_detach_slot(xhci, child->port); 3508 } 3509 3510 static USBPortOps xhci_uport_ops = { 3511 .attach = xhci_attach, 3512 .detach = xhci_detach, 3513 .wakeup = xhci_wakeup, 3514 .complete = xhci_complete, 3515 .child_detach = xhci_child_detach, 3516 }; 3517 3518 static int xhci_find_epid(USBEndpoint *ep) 3519 { 3520 if (ep->nr == 0) { 3521 return 1; 3522 } 3523 if (ep->pid == USB_TOKEN_IN) { 3524 return ep->nr * 2 + 1; 3525 } else { 3526 return ep->nr * 2; 3527 } 3528 } 3529 3530 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx) 3531 { 3532 USBPort *uport; 3533 uint32_t token; 3534 3535 if (!epctx) { 3536 return NULL; 3537 } 3538 uport = epctx->xhci->slots[epctx->slotid - 1].uport; 3539 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; 3540 if (!uport) { 3541 return NULL; 3542 } 3543 return usb_ep_get(uport->dev, token, epctx->epid >> 1); 3544 } 3545 3546 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3547 unsigned int stream) 3548 { 3549 XHCIState *xhci = container_of(bus, XHCIState, bus); 3550 int slotid; 3551 3552 DPRINTF("%s\n", __func__); 3553 slotid = ep->dev->addr; 3554 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3555 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3556 return; 3557 } 3558 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3559 } 3560 3561 static USBBusOps xhci_bus_ops = { 3562 .wakeup_endpoint = xhci_wakeup_endpoint, 3563 }; 3564 3565 static void usb_xhci_init(XHCIState *xhci) 3566 { 3567 DeviceState *dev = DEVICE(xhci); 3568 XHCIPort *port; 3569 int i, usbports, speedmask; 3570 3571 xhci->usbsts = USBSTS_HCH; 3572 3573 if (xhci->numports_2 > MAXPORTS_2) { 3574 xhci->numports_2 = MAXPORTS_2; 3575 } 3576 if (xhci->numports_3 > MAXPORTS_3) { 3577 xhci->numports_3 = MAXPORTS_3; 3578 } 3579 usbports = MAX(xhci->numports_2, xhci->numports_3); 3580 xhci->numports = xhci->numports_2 + xhci->numports_3; 3581 3582 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3583 3584 for (i = 0; i < usbports; i++) { 3585 speedmask = 0; 3586 if (i < xhci->numports_2) { 3587 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3588 port = &xhci->ports[i + xhci->numports_3]; 3589 port->portnr = i + 1 + xhci->numports_3; 3590 } else { 3591 port = &xhci->ports[i]; 3592 port->portnr = i + 1; 3593 } 3594 port->uport = &xhci->uports[i]; 3595 port->speedmask = 3596 USB_SPEED_MASK_LOW | 3597 USB_SPEED_MASK_FULL | 3598 USB_SPEED_MASK_HIGH; 3599 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3600 speedmask |= port->speedmask; 3601 } 3602 if (i < xhci->numports_3) { 3603 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3604 port = &xhci->ports[i]; 3605 port->portnr = i + 1; 3606 } else { 3607 port = &xhci->ports[i + xhci->numports_2]; 3608 port->portnr = i + 1 + xhci->numports_2; 3609 } 3610 port->uport = &xhci->uports[i]; 3611 port->speedmask = USB_SPEED_MASK_SUPER; 3612 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3613 speedmask |= port->speedmask; 3614 } 3615 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3616 &xhci_uport_ops, speedmask); 3617 } 3618 } 3619 3620 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) 3621 { 3622 int i, ret; 3623 Error *err = NULL; 3624 3625 XHCIState *xhci = XHCI(dev); 3626 3627 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3628 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3629 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3630 dev->config[0x60] = 0x30; /* release number */ 3631 3632 if (xhci->numintrs > MAXINTRS) { 3633 xhci->numintrs = MAXINTRS; 3634 } 3635 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3636 xhci->numintrs++; 3637 } 3638 if (xhci->numintrs < 1) { 3639 xhci->numintrs = 1; 3640 } 3641 if (xhci->numslots > MAXSLOTS) { 3642 xhci->numslots = MAXSLOTS; 3643 } 3644 if (xhci->numslots < 1) { 3645 xhci->numslots = 1; 3646 } 3647 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3648 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3649 } else { 3650 xhci->max_pstreams_mask = 0; 3651 } 3652 3653 if (xhci->msi != ON_OFF_AUTO_OFF) { 3654 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); 3655 /* Any error other than -ENOTSUP(board's MSI support is broken) 3656 * is a programming error */ 3657 assert(!ret || ret == -ENOTSUP); 3658 if (ret && xhci->msi == ON_OFF_AUTO_ON) { 3659 /* Can't satisfy user's explicit msi=on request, fail */ 3660 error_append_hint(&err, "You have to use msi=auto (default) or " 3661 "msi=off with this machine type.\n"); 3662 error_propagate(errp, err); 3663 return; 3664 } 3665 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); 3666 /* With msi=auto, we fall back to MSI off silently */ 3667 error_free(err); 3668 } 3669 3670 usb_xhci_init(xhci); 3671 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3672 3673 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3674 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3675 "capabilities", LEN_CAP); 3676 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3677 "operational", 0x400); 3678 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3679 "runtime", LEN_RUNTIME); 3680 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3681 "doorbell", LEN_DOORBELL); 3682 3683 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3684 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3685 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3686 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3687 3688 for (i = 0; i < xhci->numports; i++) { 3689 XHCIPort *port = &xhci->ports[i]; 3690 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3691 port->xhci = xhci; 3692 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3693 port->name, 0x10); 3694 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3695 } 3696 3697 pci_register_bar(dev, 0, 3698 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3699 &xhci->mem); 3700 3701 if (pci_bus_is_express(dev->bus) || 3702 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 3703 ret = pcie_endpoint_cap_init(dev, 0xa0); 3704 assert(ret >= 0); 3705 } 3706 3707 if (xhci->msix != ON_OFF_AUTO_OFF) { 3708 /* TODO check for errors, and should fail when msix=on */ 3709 msix_init(dev, xhci->numintrs, 3710 &xhci->mem, 0, OFF_MSIX_TABLE, 3711 &xhci->mem, 0, OFF_MSIX_PBA, 3712 0x90, NULL); 3713 } 3714 } 3715 3716 static void usb_xhci_exit(PCIDevice *dev) 3717 { 3718 int i; 3719 XHCIState *xhci = XHCI(dev); 3720 3721 trace_usb_xhci_exit(); 3722 3723 for (i = 0; i < xhci->numslots; i++) { 3724 xhci_disable_slot(xhci, i + 1); 3725 } 3726 3727 if (xhci->mfwrap_timer) { 3728 timer_del(xhci->mfwrap_timer); 3729 timer_free(xhci->mfwrap_timer); 3730 xhci->mfwrap_timer = NULL; 3731 } 3732 3733 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3734 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3735 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3736 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3737 3738 for (i = 0; i < xhci->numports; i++) { 3739 XHCIPort *port = &xhci->ports[i]; 3740 memory_region_del_subregion(&xhci->mem, &port->mem); 3741 } 3742 3743 /* destroy msix memory region */ 3744 if (dev->msix_table && dev->msix_pba 3745 && dev->msix_entry_used) { 3746 msix_uninit(dev, &xhci->mem, &xhci->mem); 3747 } 3748 3749 usb_bus_release(&xhci->bus); 3750 } 3751 3752 static int usb_xhci_post_load(void *opaque, int version_id) 3753 { 3754 XHCIState *xhci = opaque; 3755 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3756 XHCISlot *slot; 3757 XHCIEPContext *epctx; 3758 dma_addr_t dcbaap, pctx; 3759 uint32_t slot_ctx[4]; 3760 uint32_t ep_ctx[5]; 3761 int slotid, epid, state, intr; 3762 3763 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3764 3765 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3766 slot = &xhci->slots[slotid-1]; 3767 if (!slot->addressed) { 3768 continue; 3769 } 3770 slot->ctx = 3771 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3772 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3773 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3774 if (!slot->uport) { 3775 /* should not happen, but may trigger on guest bugs */ 3776 slot->enabled = 0; 3777 slot->addressed = 0; 3778 continue; 3779 } 3780 assert(slot->uport && slot->uport->dev); 3781 3782 for (epid = 1; epid <= 31; epid++) { 3783 pctx = slot->ctx + 32 * epid; 3784 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3785 state = ep_ctx[0] & EP_STATE_MASK; 3786 if (state == EP_DISABLED) { 3787 continue; 3788 } 3789 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3790 slot->eps[epid-1] = epctx; 3791 xhci_init_epctx(epctx, pctx, ep_ctx); 3792 epctx->state = state; 3793 if (state == EP_RUNNING) { 3794 /* kick endpoint after vmload is finished */ 3795 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3796 } 3797 } 3798 } 3799 3800 for (intr = 0; intr < xhci->numintrs; intr++) { 3801 if (xhci->intr[intr].msix_used) { 3802 msix_vector_use(pci_dev, intr); 3803 } else { 3804 msix_vector_unuse(pci_dev, intr); 3805 } 3806 } 3807 3808 return 0; 3809 } 3810 3811 static const VMStateDescription vmstate_xhci_ring = { 3812 .name = "xhci-ring", 3813 .version_id = 1, 3814 .fields = (VMStateField[]) { 3815 VMSTATE_UINT64(dequeue, XHCIRing), 3816 VMSTATE_BOOL(ccs, XHCIRing), 3817 VMSTATE_END_OF_LIST() 3818 } 3819 }; 3820 3821 static const VMStateDescription vmstate_xhci_port = { 3822 .name = "xhci-port", 3823 .version_id = 1, 3824 .fields = (VMStateField[]) { 3825 VMSTATE_UINT32(portsc, XHCIPort), 3826 VMSTATE_END_OF_LIST() 3827 } 3828 }; 3829 3830 static const VMStateDescription vmstate_xhci_slot = { 3831 .name = "xhci-slot", 3832 .version_id = 1, 3833 .fields = (VMStateField[]) { 3834 VMSTATE_BOOL(enabled, XHCISlot), 3835 VMSTATE_BOOL(addressed, XHCISlot), 3836 VMSTATE_END_OF_LIST() 3837 } 3838 }; 3839 3840 static const VMStateDescription vmstate_xhci_event = { 3841 .name = "xhci-event", 3842 .version_id = 1, 3843 .fields = (VMStateField[]) { 3844 VMSTATE_UINT32(type, XHCIEvent), 3845 VMSTATE_UINT32(ccode, XHCIEvent), 3846 VMSTATE_UINT64(ptr, XHCIEvent), 3847 VMSTATE_UINT32(length, XHCIEvent), 3848 VMSTATE_UINT32(flags, XHCIEvent), 3849 VMSTATE_UINT8(slotid, XHCIEvent), 3850 VMSTATE_UINT8(epid, XHCIEvent), 3851 VMSTATE_END_OF_LIST() 3852 } 3853 }; 3854 3855 static bool xhci_er_full(void *opaque, int version_id) 3856 { 3857 struct XHCIInterrupter *intr = opaque; 3858 return intr->er_full; 3859 } 3860 3861 static const VMStateDescription vmstate_xhci_intr = { 3862 .name = "xhci-intr", 3863 .version_id = 1, 3864 .fields = (VMStateField[]) { 3865 /* registers */ 3866 VMSTATE_UINT32(iman, XHCIInterrupter), 3867 VMSTATE_UINT32(imod, XHCIInterrupter), 3868 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3869 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3870 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3871 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3872 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3873 3874 /* state */ 3875 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3876 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3877 VMSTATE_UINT64(er_start, XHCIInterrupter), 3878 VMSTATE_UINT32(er_size, XHCIInterrupter), 3879 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3880 3881 /* event queue (used if ring is full) */ 3882 VMSTATE_BOOL(er_full, XHCIInterrupter), 3883 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3884 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3885 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3886 xhci_er_full, 1, 3887 vmstate_xhci_event, XHCIEvent), 3888 3889 VMSTATE_END_OF_LIST() 3890 } 3891 }; 3892 3893 static const VMStateDescription vmstate_xhci = { 3894 .name = "xhci", 3895 .version_id = 1, 3896 .post_load = usb_xhci_post_load, 3897 .fields = (VMStateField[]) { 3898 VMSTATE_PCI_DEVICE(parent_obj, XHCIState), 3899 VMSTATE_MSIX(parent_obj, XHCIState), 3900 3901 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3902 vmstate_xhci_port, XHCIPort), 3903 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3904 vmstate_xhci_slot, XHCISlot), 3905 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3906 vmstate_xhci_intr, XHCIInterrupter), 3907 3908 /* Operational Registers */ 3909 VMSTATE_UINT32(usbcmd, XHCIState), 3910 VMSTATE_UINT32(usbsts, XHCIState), 3911 VMSTATE_UINT32(dnctrl, XHCIState), 3912 VMSTATE_UINT32(crcr_low, XHCIState), 3913 VMSTATE_UINT32(crcr_high, XHCIState), 3914 VMSTATE_UINT32(dcbaap_low, XHCIState), 3915 VMSTATE_UINT32(dcbaap_high, XHCIState), 3916 VMSTATE_UINT32(config, XHCIState), 3917 3918 /* Runtime Registers & state */ 3919 VMSTATE_INT64(mfindex_start, XHCIState), 3920 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3921 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3922 3923 VMSTATE_END_OF_LIST() 3924 } 3925 }; 3926 3927 static Property xhci_properties[] = { 3928 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO), 3929 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO), 3930 DEFINE_PROP_BIT("superspeed-ports-first", 3931 XHCIState, flags, XHCI_FLAG_SS_FIRST, true), 3932 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, 3933 XHCI_FLAG_FORCE_PCIE_ENDCAP, false), 3934 DEFINE_PROP_BIT("streams", XHCIState, flags, 3935 XHCI_FLAG_ENABLE_STREAMS, true), 3936 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3937 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3938 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3939 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3940 DEFINE_PROP_END_OF_LIST(), 3941 }; 3942 3943 static void xhci_class_init(ObjectClass *klass, void *data) 3944 { 3945 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3946 DeviceClass *dc = DEVICE_CLASS(klass); 3947 3948 dc->vmsd = &vmstate_xhci; 3949 dc->props = xhci_properties; 3950 dc->reset = xhci_reset; 3951 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3952 k->realize = usb_xhci_realize; 3953 k->exit = usb_xhci_exit; 3954 k->vendor_id = PCI_VENDOR_ID_NEC; 3955 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3956 k->class_id = PCI_CLASS_SERIAL_USB; 3957 k->revision = 0x03; 3958 k->is_express = 1; 3959 } 3960 3961 static const TypeInfo xhci_info = { 3962 .name = TYPE_XHCI, 3963 .parent = TYPE_PCI_DEVICE, 3964 .instance_size = sizeof(XHCIState), 3965 .class_init = xhci_class_init, 3966 }; 3967 3968 static void xhci_register_types(void) 3969 { 3970 type_register_static(&xhci_info); 3971 } 3972 3973 type_init(xhci_register_types) 3974