1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 150 typedef enum TRBType { 151 TRB_RESERVED = 0, 152 TR_NORMAL, 153 TR_SETUP, 154 TR_DATA, 155 TR_STATUS, 156 TR_ISOCH, 157 TR_LINK, 158 TR_EVDATA, 159 TR_NOOP, 160 CR_ENABLE_SLOT, 161 CR_DISABLE_SLOT, 162 CR_ADDRESS_DEVICE, 163 CR_CONFIGURE_ENDPOINT, 164 CR_EVALUATE_CONTEXT, 165 CR_RESET_ENDPOINT, 166 CR_STOP_ENDPOINT, 167 CR_SET_TR_DEQUEUE, 168 CR_RESET_DEVICE, 169 CR_FORCE_EVENT, 170 CR_NEGOTIATE_BW, 171 CR_SET_LATENCY_TOLERANCE, 172 CR_GET_PORT_BANDWIDTH, 173 CR_FORCE_HEADER, 174 CR_NOOP, 175 ER_TRANSFER = 32, 176 ER_COMMAND_COMPLETE, 177 ER_PORT_STATUS_CHANGE, 178 ER_BANDWIDTH_REQUEST, 179 ER_DOORBELL, 180 ER_HOST_CONTROLLER, 181 ER_DEVICE_NOTIFICATION, 182 ER_MFINDEX_WRAP, 183 /* vendor specific bits */ 184 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 185 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 186 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 187 } TRBType; 188 189 #define CR_LINK TR_LINK 190 191 typedef enum TRBCCode { 192 CC_INVALID = 0, 193 CC_SUCCESS, 194 CC_DATA_BUFFER_ERROR, 195 CC_BABBLE_DETECTED, 196 CC_USB_TRANSACTION_ERROR, 197 CC_TRB_ERROR, 198 CC_STALL_ERROR, 199 CC_RESOURCE_ERROR, 200 CC_BANDWIDTH_ERROR, 201 CC_NO_SLOTS_ERROR, 202 CC_INVALID_STREAM_TYPE_ERROR, 203 CC_SLOT_NOT_ENABLED_ERROR, 204 CC_EP_NOT_ENABLED_ERROR, 205 CC_SHORT_PACKET, 206 CC_RING_UNDERRUN, 207 CC_RING_OVERRUN, 208 CC_VF_ER_FULL, 209 CC_PARAMETER_ERROR, 210 CC_BANDWIDTH_OVERRUN, 211 CC_CONTEXT_STATE_ERROR, 212 CC_NO_PING_RESPONSE_ERROR, 213 CC_EVENT_RING_FULL_ERROR, 214 CC_INCOMPATIBLE_DEVICE_ERROR, 215 CC_MISSED_SERVICE_ERROR, 216 CC_COMMAND_RING_STOPPED, 217 CC_COMMAND_ABORTED, 218 CC_STOPPED, 219 CC_STOPPED_LENGTH_INVALID, 220 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 221 CC_ISOCH_BUFFER_OVERRUN = 31, 222 CC_EVENT_LOST_ERROR, 223 CC_UNDEFINED_ERROR, 224 CC_INVALID_STREAM_ID_ERROR, 225 CC_SECONDARY_BANDWIDTH_ERROR, 226 CC_SPLIT_TRANSACTION_ERROR 227 } TRBCCode; 228 229 #define TRB_C (1<<0) 230 #define TRB_TYPE_SHIFT 10 231 #define TRB_TYPE_MASK 0x3f 232 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 233 234 #define TRB_EV_ED (1<<2) 235 236 #define TRB_TR_ENT (1<<1) 237 #define TRB_TR_ISP (1<<2) 238 #define TRB_TR_NS (1<<3) 239 #define TRB_TR_CH (1<<4) 240 #define TRB_TR_IOC (1<<5) 241 #define TRB_TR_IDT (1<<6) 242 #define TRB_TR_TBC_SHIFT 7 243 #define TRB_TR_TBC_MASK 0x3 244 #define TRB_TR_BEI (1<<9) 245 #define TRB_TR_TLBPC_SHIFT 16 246 #define TRB_TR_TLBPC_MASK 0xf 247 #define TRB_TR_FRAMEID_SHIFT 20 248 #define TRB_TR_FRAMEID_MASK 0x7ff 249 #define TRB_TR_SIA (1<<31) 250 251 #define TRB_TR_DIR (1<<16) 252 253 #define TRB_CR_SLOTID_SHIFT 24 254 #define TRB_CR_SLOTID_MASK 0xff 255 #define TRB_CR_EPID_SHIFT 16 256 #define TRB_CR_EPID_MASK 0x1f 257 258 #define TRB_CR_BSR (1<<9) 259 #define TRB_CR_DC (1<<9) 260 261 #define TRB_LK_TC (1<<1) 262 263 #define TRB_INTR_SHIFT 22 264 #define TRB_INTR_MASK 0x3ff 265 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef struct XHCIState XHCIState; 289 290 typedef enum EPType { 291 ET_INVALID = 0, 292 ET_ISO_OUT, 293 ET_BULK_OUT, 294 ET_INTR_OUT, 295 ET_CONTROL, 296 ET_ISO_IN, 297 ET_BULK_IN, 298 ET_INTR_IN, 299 } EPType; 300 301 typedef struct XHCIRing { 302 dma_addr_t base; 303 dma_addr_t dequeue; 304 bool ccs; 305 } XHCIRing; 306 307 typedef struct XHCIPort { 308 XHCIState *xhci; 309 uint32_t portsc; 310 uint32_t portnr; 311 USBPort *uport; 312 uint32_t speedmask; 313 char name[16]; 314 MemoryRegion mem; 315 } XHCIPort; 316 317 typedef struct XHCITransfer { 318 XHCIState *xhci; 319 USBPacket packet; 320 QEMUSGList sgl; 321 bool running_async; 322 bool running_retry; 323 bool cancelled; 324 bool complete; 325 bool int_req; 326 unsigned int iso_pkts; 327 unsigned int slotid; 328 unsigned int epid; 329 bool in_xfer; 330 bool iso_xfer; 331 332 unsigned int trb_count; 333 unsigned int trb_alloced; 334 XHCITRB *trbs; 335 336 TRBCCode status; 337 338 unsigned int pkts; 339 unsigned int pktsize; 340 unsigned int cur_pkt; 341 342 uint64_t mfindex_kick; 343 } XHCITransfer; 344 345 typedef struct XHCIEPContext { 346 XHCIState *xhci; 347 unsigned int slotid; 348 unsigned int epid; 349 350 XHCIRing ring; 351 unsigned int next_xfer; 352 unsigned int comp_xfer; 353 XHCITransfer transfers[TD_QUEUE]; 354 XHCITransfer *retry; 355 EPType type; 356 dma_addr_t pctx; 357 unsigned int max_psize; 358 uint32_t state; 359 360 /* iso xfer scheduling */ 361 unsigned int interval; 362 int64_t mfindex_last; 363 QEMUTimer *kick_timer; 364 } XHCIEPContext; 365 366 typedef struct XHCISlot { 367 bool enabled; 368 dma_addr_t ctx; 369 USBPort *uport; 370 unsigned int devaddr; 371 XHCIEPContext * eps[31]; 372 } XHCISlot; 373 374 typedef struct XHCIEvent { 375 TRBType type; 376 TRBCCode ccode; 377 uint64_t ptr; 378 uint32_t length; 379 uint32_t flags; 380 uint8_t slotid; 381 uint8_t epid; 382 } XHCIEvent; 383 384 typedef struct XHCIInterrupter { 385 uint32_t iman; 386 uint32_t imod; 387 uint32_t erstsz; 388 uint32_t erstba_low; 389 uint32_t erstba_high; 390 uint32_t erdp_low; 391 uint32_t erdp_high; 392 393 bool msix_used, er_pcs, er_full; 394 395 dma_addr_t er_start; 396 uint32_t er_size; 397 unsigned int er_ep_idx; 398 399 XHCIEvent ev_buffer[EV_QUEUE]; 400 unsigned int ev_buffer_put; 401 unsigned int ev_buffer_get; 402 403 } XHCIInterrupter; 404 405 struct XHCIState { 406 PCIDevice pci_dev; 407 USBBus bus; 408 qemu_irq irq; 409 MemoryRegion mem; 410 MemoryRegion mem_cap; 411 MemoryRegion mem_oper; 412 MemoryRegion mem_runtime; 413 MemoryRegion mem_doorbell; 414 const char *name; 415 unsigned int devaddr; 416 417 /* properties */ 418 uint32_t numports_2; 419 uint32_t numports_3; 420 uint32_t flags; 421 422 /* Operational Registers */ 423 uint32_t usbcmd; 424 uint32_t usbsts; 425 uint32_t dnctrl; 426 uint32_t crcr_low; 427 uint32_t crcr_high; 428 uint32_t dcbaap_low; 429 uint32_t dcbaap_high; 430 uint32_t config; 431 432 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 433 XHCIPort ports[MAXPORTS]; 434 XHCISlot slots[MAXSLOTS]; 435 uint32_t numports; 436 437 /* Runtime Registers */ 438 int64_t mfindex_start; 439 QEMUTimer *mfwrap_timer; 440 XHCIInterrupter intr[MAXINTRS]; 441 442 XHCIRing cmd_ring; 443 }; 444 445 typedef struct XHCIEvRingSeg { 446 uint32_t addr_low; 447 uint32_t addr_high; 448 uint32_t size; 449 uint32_t rsvd; 450 } XHCIEvRingSeg; 451 452 enum xhci_flags { 453 XHCI_FLAG_USE_MSI = 1, 454 XHCI_FLAG_USE_MSI_X, 455 }; 456 457 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 458 unsigned int epid); 459 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 460 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 461 462 static const char *TRBType_names[] = { 463 [TRB_RESERVED] = "TRB_RESERVED", 464 [TR_NORMAL] = "TR_NORMAL", 465 [TR_SETUP] = "TR_SETUP", 466 [TR_DATA] = "TR_DATA", 467 [TR_STATUS] = "TR_STATUS", 468 [TR_ISOCH] = "TR_ISOCH", 469 [TR_LINK] = "TR_LINK", 470 [TR_EVDATA] = "TR_EVDATA", 471 [TR_NOOP] = "TR_NOOP", 472 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 473 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 474 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 475 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 476 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 477 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 478 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 479 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 480 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 481 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 482 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 483 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 484 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 485 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 486 [CR_NOOP] = "CR_NOOP", 487 [ER_TRANSFER] = "ER_TRANSFER", 488 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 489 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 490 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 491 [ER_DOORBELL] = "ER_DOORBELL", 492 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 493 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 494 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 495 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 496 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 497 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 498 }; 499 500 static const char *TRBCCode_names[] = { 501 [CC_INVALID] = "CC_INVALID", 502 [CC_SUCCESS] = "CC_SUCCESS", 503 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 504 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 505 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 506 [CC_TRB_ERROR] = "CC_TRB_ERROR", 507 [CC_STALL_ERROR] = "CC_STALL_ERROR", 508 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 509 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 510 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 511 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 512 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 513 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 514 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 515 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 516 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 517 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 518 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 519 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 520 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 521 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 522 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 523 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 524 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 525 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 526 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 527 [CC_STOPPED] = "CC_STOPPED", 528 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 529 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 530 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 531 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 532 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 533 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 534 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 535 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 536 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 537 }; 538 539 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 540 { 541 if (index >= llen || list[index] == NULL) { 542 return "???"; 543 } 544 return list[index]; 545 } 546 547 static const char *trb_name(XHCITRB *trb) 548 { 549 return lookup_name(TRB_TYPE(*trb), TRBType_names, 550 ARRAY_SIZE(TRBType_names)); 551 } 552 553 static const char *event_name(XHCIEvent *event) 554 { 555 return lookup_name(event->ccode, TRBCCode_names, 556 ARRAY_SIZE(TRBCCode_names)); 557 } 558 559 static uint64_t xhci_mfindex_get(XHCIState *xhci) 560 { 561 int64_t now = qemu_get_clock_ns(vm_clock); 562 return (now - xhci->mfindex_start) / 125000; 563 } 564 565 static void xhci_mfwrap_update(XHCIState *xhci) 566 { 567 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 568 uint32_t mfindex, left; 569 int64_t now; 570 571 if ((xhci->usbcmd & bits) == bits) { 572 now = qemu_get_clock_ns(vm_clock); 573 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 574 left = 0x4000 - mfindex; 575 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 576 } else { 577 qemu_del_timer(xhci->mfwrap_timer); 578 } 579 } 580 581 static void xhci_mfwrap_timer(void *opaque) 582 { 583 XHCIState *xhci = opaque; 584 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 585 586 xhci_event(xhci, &wrap, 0); 587 xhci_mfwrap_update(xhci); 588 } 589 590 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 591 { 592 if (sizeof(dma_addr_t) == 4) { 593 return low; 594 } else { 595 return low | (((dma_addr_t)high << 16) << 16); 596 } 597 } 598 599 static inline dma_addr_t xhci_mask64(uint64_t addr) 600 { 601 if (sizeof(dma_addr_t) == 4) { 602 return addr & 0xffffffff; 603 } else { 604 return addr; 605 } 606 } 607 608 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 609 { 610 int index; 611 612 if (!uport->dev) { 613 return NULL; 614 } 615 switch (uport->dev->speed) { 616 case USB_SPEED_LOW: 617 case USB_SPEED_FULL: 618 case USB_SPEED_HIGH: 619 index = uport->index; 620 break; 621 case USB_SPEED_SUPER: 622 index = uport->index + xhci->numports_2; 623 break; 624 default: 625 return NULL; 626 } 627 return &xhci->ports[index]; 628 } 629 630 static void xhci_intx_update(XHCIState *xhci) 631 { 632 int level = 0; 633 634 if (msix_enabled(&xhci->pci_dev) || 635 msi_enabled(&xhci->pci_dev)) { 636 return; 637 } 638 639 if (xhci->intr[0].iman & IMAN_IP && 640 xhci->intr[0].iman & IMAN_IE && 641 xhci->usbcmd & USBCMD_INTE) { 642 level = 1; 643 } 644 645 trace_usb_xhci_irq_intx(level); 646 qemu_set_irq(xhci->irq, level); 647 } 648 649 static void xhci_msix_update(XHCIState *xhci, int v) 650 { 651 bool enabled; 652 653 if (!msix_enabled(&xhci->pci_dev)) { 654 return; 655 } 656 657 enabled = xhci->intr[v].iman & IMAN_IE; 658 if (enabled == xhci->intr[v].msix_used) { 659 return; 660 } 661 662 if (enabled) { 663 trace_usb_xhci_irq_msix_use(v); 664 msix_vector_use(&xhci->pci_dev, v); 665 xhci->intr[v].msix_used = true; 666 } else { 667 trace_usb_xhci_irq_msix_unuse(v); 668 msix_vector_unuse(&xhci->pci_dev, v); 669 xhci->intr[v].msix_used = false; 670 } 671 } 672 673 static void xhci_intr_raise(XHCIState *xhci, int v) 674 { 675 xhci->intr[v].erdp_low |= ERDP_EHB; 676 xhci->intr[v].iman |= IMAN_IP; 677 xhci->usbsts |= USBSTS_EINT; 678 679 if (!(xhci->intr[v].iman & IMAN_IE)) { 680 return; 681 } 682 683 if (!(xhci->usbcmd & USBCMD_INTE)) { 684 return; 685 } 686 687 if (msix_enabled(&xhci->pci_dev)) { 688 trace_usb_xhci_irq_msix(v); 689 msix_notify(&xhci->pci_dev, v); 690 return; 691 } 692 693 if (msi_enabled(&xhci->pci_dev)) { 694 trace_usb_xhci_irq_msi(v); 695 msi_notify(&xhci->pci_dev, v); 696 return; 697 } 698 699 if (v == 0) { 700 trace_usb_xhci_irq_intx(1); 701 qemu_set_irq(xhci->irq, 1); 702 } 703 } 704 705 static inline int xhci_running(XHCIState *xhci) 706 { 707 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 708 } 709 710 static void xhci_die(XHCIState *xhci) 711 { 712 xhci->usbsts |= USBSTS_HCE; 713 fprintf(stderr, "xhci: asserted controller error\n"); 714 } 715 716 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 717 { 718 XHCIInterrupter *intr = &xhci->intr[v]; 719 XHCITRB ev_trb; 720 dma_addr_t addr; 721 722 ev_trb.parameter = cpu_to_le64(event->ptr); 723 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 724 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 725 event->flags | (event->type << TRB_TYPE_SHIFT); 726 if (intr->er_pcs) { 727 ev_trb.control |= TRB_C; 728 } 729 ev_trb.control = cpu_to_le32(ev_trb.control); 730 731 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 732 event_name(event), ev_trb.parameter, 733 ev_trb.status, ev_trb.control); 734 735 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 736 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 737 738 intr->er_ep_idx++; 739 if (intr->er_ep_idx >= intr->er_size) { 740 intr->er_ep_idx = 0; 741 intr->er_pcs = !intr->er_pcs; 742 } 743 } 744 745 static void xhci_events_update(XHCIState *xhci, int v) 746 { 747 XHCIInterrupter *intr = &xhci->intr[v]; 748 dma_addr_t erdp; 749 unsigned int dp_idx; 750 bool do_irq = 0; 751 752 if (xhci->usbsts & USBSTS_HCH) { 753 return; 754 } 755 756 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 757 if (erdp < intr->er_start || 758 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 759 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 760 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 761 v, intr->er_start, intr->er_size); 762 xhci_die(xhci); 763 return; 764 } 765 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 766 assert(dp_idx < intr->er_size); 767 768 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 769 * deadlocks when the ER is full. Hack it by holding off events until 770 * the driver decides to free at least half of the ring */ 771 if (intr->er_full) { 772 int er_free = dp_idx - intr->er_ep_idx; 773 if (er_free <= 0) { 774 er_free += intr->er_size; 775 } 776 if (er_free < (intr->er_size/2)) { 777 DPRINTF("xhci_events_update(): event ring still " 778 "more than half full (hack)\n"); 779 return; 780 } 781 } 782 783 while (intr->ev_buffer_put != intr->ev_buffer_get) { 784 assert(intr->er_full); 785 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 786 DPRINTF("xhci_events_update(): event ring full again\n"); 787 #ifndef ER_FULL_HACK 788 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 789 xhci_write_event(xhci, &full, v); 790 #endif 791 do_irq = 1; 792 break; 793 } 794 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 795 xhci_write_event(xhci, event, v); 796 intr->ev_buffer_get++; 797 do_irq = 1; 798 if (intr->ev_buffer_get == EV_QUEUE) { 799 intr->ev_buffer_get = 0; 800 } 801 } 802 803 if (do_irq) { 804 xhci_intr_raise(xhci, v); 805 } 806 807 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 808 DPRINTF("xhci_events_update(): event ring no longer full\n"); 809 intr->er_full = 0; 810 } 811 } 812 813 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 814 { 815 XHCIInterrupter *intr; 816 dma_addr_t erdp; 817 unsigned int dp_idx; 818 819 if (v >= MAXINTRS) { 820 DPRINTF("intr nr out of range (%d >= %d)\n", v, MAXINTRS); 821 return; 822 } 823 intr = &xhci->intr[v]; 824 825 if (intr->er_full) { 826 DPRINTF("xhci_event(): ER full, queueing\n"); 827 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 828 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 829 return; 830 } 831 intr->ev_buffer[intr->ev_buffer_put++] = *event; 832 if (intr->ev_buffer_put == EV_QUEUE) { 833 intr->ev_buffer_put = 0; 834 } 835 return; 836 } 837 838 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 839 if (erdp < intr->er_start || 840 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 841 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 842 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 843 v, intr->er_start, intr->er_size); 844 xhci_die(xhci); 845 return; 846 } 847 848 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 849 assert(dp_idx < intr->er_size); 850 851 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 852 DPRINTF("xhci_event(): ER full, queueing\n"); 853 #ifndef ER_FULL_HACK 854 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 855 xhci_write_event(xhci, &full); 856 #endif 857 intr->er_full = 1; 858 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 859 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 860 return; 861 } 862 intr->ev_buffer[intr->ev_buffer_put++] = *event; 863 if (intr->ev_buffer_put == EV_QUEUE) { 864 intr->ev_buffer_put = 0; 865 } 866 } else { 867 xhci_write_event(xhci, event, v); 868 } 869 870 xhci_intr_raise(xhci, v); 871 } 872 873 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 874 dma_addr_t base) 875 { 876 ring->base = base; 877 ring->dequeue = base; 878 ring->ccs = 1; 879 } 880 881 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 882 dma_addr_t *addr) 883 { 884 while (1) { 885 TRBType type; 886 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 887 trb->addr = ring->dequeue; 888 trb->ccs = ring->ccs; 889 le64_to_cpus(&trb->parameter); 890 le32_to_cpus(&trb->status); 891 le32_to_cpus(&trb->control); 892 893 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 894 trb->parameter, trb->status, trb->control); 895 896 if ((trb->control & TRB_C) != ring->ccs) { 897 return 0; 898 } 899 900 type = TRB_TYPE(*trb); 901 902 if (type != TR_LINK) { 903 if (addr) { 904 *addr = ring->dequeue; 905 } 906 ring->dequeue += TRB_SIZE; 907 return type; 908 } else { 909 ring->dequeue = xhci_mask64(trb->parameter); 910 if (trb->control & TRB_LK_TC) { 911 ring->ccs = !ring->ccs; 912 } 913 } 914 } 915 } 916 917 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 918 { 919 XHCITRB trb; 920 int length = 0; 921 dma_addr_t dequeue = ring->dequeue; 922 bool ccs = ring->ccs; 923 /* hack to bundle together the two/three TDs that make a setup transfer */ 924 bool control_td_set = 0; 925 926 while (1) { 927 TRBType type; 928 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 929 le64_to_cpus(&trb.parameter); 930 le32_to_cpus(&trb.status); 931 le32_to_cpus(&trb.control); 932 933 if ((trb.control & TRB_C) != ccs) { 934 return -length; 935 } 936 937 type = TRB_TYPE(trb); 938 939 if (type == TR_LINK) { 940 dequeue = xhci_mask64(trb.parameter); 941 if (trb.control & TRB_LK_TC) { 942 ccs = !ccs; 943 } 944 continue; 945 } 946 947 length += 1; 948 dequeue += TRB_SIZE; 949 950 if (type == TR_SETUP) { 951 control_td_set = 1; 952 } else if (type == TR_STATUS) { 953 control_td_set = 0; 954 } 955 956 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 957 return length; 958 } 959 } 960 } 961 962 static void xhci_er_reset(XHCIState *xhci, int v) 963 { 964 XHCIInterrupter *intr = &xhci->intr[v]; 965 XHCIEvRingSeg seg; 966 967 if (intr->erstsz == 0) { 968 /* disabled */ 969 intr->er_start = 0; 970 intr->er_size = 0; 971 return; 972 } 973 /* cache the (sole) event ring segment location */ 974 if (intr->erstsz != 1) { 975 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 976 xhci_die(xhci); 977 return; 978 } 979 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 980 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 981 le32_to_cpus(&seg.addr_low); 982 le32_to_cpus(&seg.addr_high); 983 le32_to_cpus(&seg.size); 984 if (seg.size < 16 || seg.size > 4096) { 985 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 986 xhci_die(xhci); 987 return; 988 } 989 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 990 intr->er_size = seg.size; 991 992 intr->er_ep_idx = 0; 993 intr->er_pcs = 1; 994 intr->er_full = 0; 995 996 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 997 v, intr->er_start, intr->er_size); 998 } 999 1000 static void xhci_run(XHCIState *xhci) 1001 { 1002 trace_usb_xhci_run(); 1003 xhci->usbsts &= ~USBSTS_HCH; 1004 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1005 } 1006 1007 static void xhci_stop(XHCIState *xhci) 1008 { 1009 trace_usb_xhci_stop(); 1010 xhci->usbsts |= USBSTS_HCH; 1011 xhci->crcr_low &= ~CRCR_CRR; 1012 } 1013 1014 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1015 uint32_t state) 1016 { 1017 uint32_t ctx[5]; 1018 1019 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1020 ctx[0] &= ~EP_STATE_MASK; 1021 ctx[0] |= state; 1022 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1023 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1024 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1025 epctx->pctx, state, ctx[3], ctx[2]); 1026 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1027 epctx->state = state; 1028 } 1029 1030 static void xhci_ep_kick_timer(void *opaque) 1031 { 1032 XHCIEPContext *epctx = opaque; 1033 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1034 } 1035 1036 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1037 unsigned int epid, dma_addr_t pctx, 1038 uint32_t *ctx) 1039 { 1040 XHCISlot *slot; 1041 XHCIEPContext *epctx; 1042 dma_addr_t dequeue; 1043 int i; 1044 1045 trace_usb_xhci_ep_enable(slotid, epid); 1046 assert(slotid >= 1 && slotid <= MAXSLOTS); 1047 assert(epid >= 1 && epid <= 31); 1048 1049 slot = &xhci->slots[slotid-1]; 1050 if (slot->eps[epid-1]) { 1051 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1052 return CC_TRB_ERROR; 1053 } 1054 1055 epctx = g_malloc(sizeof(XHCIEPContext)); 1056 memset(epctx, 0, sizeof(XHCIEPContext)); 1057 epctx->xhci = xhci; 1058 epctx->slotid = slotid; 1059 epctx->epid = epid; 1060 1061 slot->eps[epid-1] = epctx; 1062 1063 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1064 xhci_ring_init(xhci, &epctx->ring, dequeue); 1065 epctx->ring.ccs = ctx[2] & 1; 1066 1067 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1068 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1069 epctx->pctx = pctx; 1070 epctx->max_psize = ctx[1]>>16; 1071 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1072 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1073 epid/2, epid%2, epctx->max_psize); 1074 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1075 usb_packet_init(&epctx->transfers[i].packet); 1076 } 1077 1078 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1079 epctx->mfindex_last = 0; 1080 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1081 1082 epctx->state = EP_RUNNING; 1083 ctx[0] &= ~EP_STATE_MASK; 1084 ctx[0] |= EP_RUNNING; 1085 1086 return CC_SUCCESS; 1087 } 1088 1089 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1090 { 1091 int killed = 0; 1092 1093 if (t->running_async) { 1094 usb_cancel_packet(&t->packet); 1095 t->running_async = 0; 1096 t->cancelled = 1; 1097 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1098 killed = 1; 1099 } 1100 if (t->running_retry) { 1101 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1102 if (epctx) { 1103 epctx->retry = NULL; 1104 qemu_del_timer(epctx->kick_timer); 1105 } 1106 t->running_retry = 0; 1107 } 1108 if (t->trbs) { 1109 g_free(t->trbs); 1110 } 1111 1112 t->trbs = NULL; 1113 t->trb_count = t->trb_alloced = 0; 1114 1115 return killed; 1116 } 1117 1118 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1119 unsigned int epid) 1120 { 1121 XHCISlot *slot; 1122 XHCIEPContext *epctx; 1123 int i, xferi, killed = 0; 1124 assert(slotid >= 1 && slotid <= MAXSLOTS); 1125 assert(epid >= 1 && epid <= 31); 1126 1127 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1128 1129 slot = &xhci->slots[slotid-1]; 1130 1131 if (!slot->eps[epid-1]) { 1132 return 0; 1133 } 1134 1135 epctx = slot->eps[epid-1]; 1136 1137 xferi = epctx->next_xfer; 1138 for (i = 0; i < TD_QUEUE; i++) { 1139 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1140 xferi = (xferi + 1) % TD_QUEUE; 1141 } 1142 return killed; 1143 } 1144 1145 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1146 unsigned int epid) 1147 { 1148 XHCISlot *slot; 1149 XHCIEPContext *epctx; 1150 1151 trace_usb_xhci_ep_disable(slotid, epid); 1152 assert(slotid >= 1 && slotid <= MAXSLOTS); 1153 assert(epid >= 1 && epid <= 31); 1154 1155 slot = &xhci->slots[slotid-1]; 1156 1157 if (!slot->eps[epid-1]) { 1158 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1159 return CC_SUCCESS; 1160 } 1161 1162 xhci_ep_nuke_xfers(xhci, slotid, epid); 1163 1164 epctx = slot->eps[epid-1]; 1165 1166 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1167 1168 qemu_free_timer(epctx->kick_timer); 1169 g_free(epctx); 1170 slot->eps[epid-1] = NULL; 1171 1172 return CC_SUCCESS; 1173 } 1174 1175 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1176 unsigned int epid) 1177 { 1178 XHCISlot *slot; 1179 XHCIEPContext *epctx; 1180 1181 trace_usb_xhci_ep_stop(slotid, epid); 1182 assert(slotid >= 1 && slotid <= MAXSLOTS); 1183 1184 if (epid < 1 || epid > 31) { 1185 fprintf(stderr, "xhci: bad ep %d\n", epid); 1186 return CC_TRB_ERROR; 1187 } 1188 1189 slot = &xhci->slots[slotid-1]; 1190 1191 if (!slot->eps[epid-1]) { 1192 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1193 return CC_EP_NOT_ENABLED_ERROR; 1194 } 1195 1196 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1197 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1198 "data might be lost\n"); 1199 } 1200 1201 epctx = slot->eps[epid-1]; 1202 1203 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1204 1205 return CC_SUCCESS; 1206 } 1207 1208 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1209 unsigned int epid) 1210 { 1211 XHCISlot *slot; 1212 XHCIEPContext *epctx; 1213 USBDevice *dev; 1214 1215 trace_usb_xhci_ep_reset(slotid, epid); 1216 assert(slotid >= 1 && slotid <= MAXSLOTS); 1217 1218 if (epid < 1 || epid > 31) { 1219 fprintf(stderr, "xhci: bad ep %d\n", epid); 1220 return CC_TRB_ERROR; 1221 } 1222 1223 slot = &xhci->slots[slotid-1]; 1224 1225 if (!slot->eps[epid-1]) { 1226 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1227 return CC_EP_NOT_ENABLED_ERROR; 1228 } 1229 1230 epctx = slot->eps[epid-1]; 1231 1232 if (epctx->state != EP_HALTED) { 1233 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1234 epid, epctx->state); 1235 return CC_CONTEXT_STATE_ERROR; 1236 } 1237 1238 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1239 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1240 "data might be lost\n"); 1241 } 1242 1243 uint8_t ep = epid>>1; 1244 1245 if (epid & 1) { 1246 ep |= 0x80; 1247 } 1248 1249 dev = xhci->slots[slotid-1].uport->dev; 1250 if (!dev) { 1251 return CC_USB_TRANSACTION_ERROR; 1252 } 1253 1254 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1255 1256 return CC_SUCCESS; 1257 } 1258 1259 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1260 unsigned int epid, uint64_t pdequeue) 1261 { 1262 XHCISlot *slot; 1263 XHCIEPContext *epctx; 1264 dma_addr_t dequeue; 1265 1266 assert(slotid >= 1 && slotid <= MAXSLOTS); 1267 1268 if (epid < 1 || epid > 31) { 1269 fprintf(stderr, "xhci: bad ep %d\n", epid); 1270 return CC_TRB_ERROR; 1271 } 1272 1273 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1274 dequeue = xhci_mask64(pdequeue); 1275 1276 slot = &xhci->slots[slotid-1]; 1277 1278 if (!slot->eps[epid-1]) { 1279 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1280 return CC_EP_NOT_ENABLED_ERROR; 1281 } 1282 1283 epctx = slot->eps[epid-1]; 1284 1285 1286 if (epctx->state != EP_STOPPED) { 1287 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1288 return CC_CONTEXT_STATE_ERROR; 1289 } 1290 1291 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1292 epctx->ring.ccs = dequeue & 1; 1293 1294 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1295 1296 return CC_SUCCESS; 1297 } 1298 1299 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1300 { 1301 XHCIState *xhci = xfer->xhci; 1302 int i; 1303 1304 xfer->int_req = false; 1305 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1306 for (i = 0; i < xfer->trb_count; i++) { 1307 XHCITRB *trb = &xfer->trbs[i]; 1308 dma_addr_t addr; 1309 unsigned int chunk = 0; 1310 1311 if (trb->control & TRB_TR_IOC) { 1312 xfer->int_req = true; 1313 } 1314 1315 switch (TRB_TYPE(*trb)) { 1316 case TR_DATA: 1317 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1318 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1319 goto err; 1320 } 1321 /* fallthrough */ 1322 case TR_NORMAL: 1323 case TR_ISOCH: 1324 addr = xhci_mask64(trb->parameter); 1325 chunk = trb->status & 0x1ffff; 1326 if (trb->control & TRB_TR_IDT) { 1327 if (chunk > 8 || in_xfer) { 1328 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1329 goto err; 1330 } 1331 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1332 } else { 1333 qemu_sglist_add(&xfer->sgl, addr, chunk); 1334 } 1335 break; 1336 } 1337 } 1338 1339 return 0; 1340 1341 err: 1342 qemu_sglist_destroy(&xfer->sgl); 1343 xhci_die(xhci); 1344 return -1; 1345 } 1346 1347 static void xhci_xfer_unmap(XHCITransfer *xfer) 1348 { 1349 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1350 qemu_sglist_destroy(&xfer->sgl); 1351 } 1352 1353 static void xhci_xfer_report(XHCITransfer *xfer) 1354 { 1355 uint32_t edtla = 0; 1356 unsigned int left; 1357 bool reported = 0; 1358 bool shortpkt = 0; 1359 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1360 XHCIState *xhci = xfer->xhci; 1361 int i; 1362 1363 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1364 1365 for (i = 0; i < xfer->trb_count; i++) { 1366 XHCITRB *trb = &xfer->trbs[i]; 1367 unsigned int chunk = 0; 1368 1369 switch (TRB_TYPE(*trb)) { 1370 case TR_DATA: 1371 case TR_NORMAL: 1372 case TR_ISOCH: 1373 chunk = trb->status & 0x1ffff; 1374 if (chunk > left) { 1375 chunk = left; 1376 if (xfer->status == CC_SUCCESS) { 1377 shortpkt = 1; 1378 } 1379 } 1380 left -= chunk; 1381 edtla += chunk; 1382 break; 1383 case TR_STATUS: 1384 reported = 0; 1385 shortpkt = 0; 1386 break; 1387 } 1388 1389 if (!reported && ((trb->control & TRB_TR_IOC) || 1390 (shortpkt && (trb->control & TRB_TR_ISP)) || 1391 (xfer->status != CC_SUCCESS))) { 1392 event.slotid = xfer->slotid; 1393 event.epid = xfer->epid; 1394 event.length = (trb->status & 0x1ffff) - chunk; 1395 event.flags = 0; 1396 event.ptr = trb->addr; 1397 if (xfer->status == CC_SUCCESS) { 1398 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1399 } else { 1400 event.ccode = xfer->status; 1401 } 1402 if (TRB_TYPE(*trb) == TR_EVDATA) { 1403 event.ptr = trb->parameter; 1404 event.flags |= TRB_EV_ED; 1405 event.length = edtla & 0xffffff; 1406 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1407 edtla = 0; 1408 } 1409 xhci_event(xhci, &event, TRB_INTR(*trb)); 1410 reported = 1; 1411 if (xfer->status != CC_SUCCESS) { 1412 return; 1413 } 1414 } 1415 } 1416 } 1417 1418 static void xhci_stall_ep(XHCITransfer *xfer) 1419 { 1420 XHCIState *xhci = xfer->xhci; 1421 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1422 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1423 1424 epctx->ring.dequeue = xfer->trbs[0].addr; 1425 epctx->ring.ccs = xfer->trbs[0].ccs; 1426 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1427 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1428 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1429 } 1430 1431 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1432 XHCIEPContext *epctx); 1433 1434 static int xhci_setup_packet(XHCITransfer *xfer) 1435 { 1436 XHCIState *xhci = xfer->xhci; 1437 USBDevice *dev; 1438 USBEndpoint *ep; 1439 int dir; 1440 1441 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1442 1443 if (xfer->packet.ep) { 1444 ep = xfer->packet.ep; 1445 dev = ep->dev; 1446 } else { 1447 if (!xhci->slots[xfer->slotid-1].uport) { 1448 fprintf(stderr, "xhci: slot %d has no device\n", 1449 xfer->slotid); 1450 return -1; 1451 } 1452 dev = xhci->slots[xfer->slotid-1].uport->dev; 1453 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1454 } 1455 1456 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1457 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr, false, 1458 xfer->int_req); 1459 usb_packet_map(&xfer->packet, &xfer->sgl); 1460 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1461 xfer->packet.pid, dev->addr, ep->nr); 1462 return 0; 1463 } 1464 1465 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1466 { 1467 if (ret == USB_RET_ASYNC) { 1468 trace_usb_xhci_xfer_async(xfer); 1469 xfer->running_async = 1; 1470 xfer->running_retry = 0; 1471 xfer->complete = 0; 1472 xfer->cancelled = 0; 1473 return 0; 1474 } else if (ret == USB_RET_NAK) { 1475 trace_usb_xhci_xfer_nak(xfer); 1476 xfer->running_async = 0; 1477 xfer->running_retry = 1; 1478 xfer->complete = 0; 1479 xfer->cancelled = 0; 1480 return 0; 1481 } else { 1482 xfer->running_async = 0; 1483 xfer->running_retry = 0; 1484 xfer->complete = 1; 1485 xhci_xfer_unmap(xfer); 1486 } 1487 1488 if (ret >= 0) { 1489 trace_usb_xhci_xfer_success(xfer, ret); 1490 xfer->status = CC_SUCCESS; 1491 xhci_xfer_report(xfer); 1492 return 0; 1493 } 1494 1495 /* error */ 1496 trace_usb_xhci_xfer_error(xfer, ret); 1497 switch (ret) { 1498 case USB_RET_NODEV: 1499 xfer->status = CC_USB_TRANSACTION_ERROR; 1500 xhci_xfer_report(xfer); 1501 xhci_stall_ep(xfer); 1502 break; 1503 case USB_RET_STALL: 1504 xfer->status = CC_STALL_ERROR; 1505 xhci_xfer_report(xfer); 1506 xhci_stall_ep(xfer); 1507 break; 1508 default: 1509 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1510 FIXME(); 1511 } 1512 return 0; 1513 } 1514 1515 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1516 { 1517 XHCITRB *trb_setup, *trb_status; 1518 uint8_t bmRequestType; 1519 int ret; 1520 1521 trb_setup = &xfer->trbs[0]; 1522 trb_status = &xfer->trbs[xfer->trb_count-1]; 1523 1524 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1525 1526 /* at most one Event Data TRB allowed after STATUS */ 1527 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1528 trb_status--; 1529 } 1530 1531 /* do some sanity checks */ 1532 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1533 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1534 TRB_TYPE(*trb_setup)); 1535 return -1; 1536 } 1537 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1538 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1539 TRB_TYPE(*trb_status)); 1540 return -1; 1541 } 1542 if (!(trb_setup->control & TRB_TR_IDT)) { 1543 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1544 return -1; 1545 } 1546 if ((trb_setup->status & 0x1ffff) != 8) { 1547 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1548 (trb_setup->status & 0x1ffff)); 1549 return -1; 1550 } 1551 1552 bmRequestType = trb_setup->parameter; 1553 1554 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1555 xfer->iso_xfer = false; 1556 1557 if (xhci_setup_packet(xfer) < 0) { 1558 return -1; 1559 } 1560 xfer->packet.parameter = trb_setup->parameter; 1561 1562 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1563 1564 xhci_complete_packet(xfer, ret); 1565 if (!xfer->running_async && !xfer->running_retry) { 1566 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1567 } 1568 return 0; 1569 } 1570 1571 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1572 XHCIEPContext *epctx, uint64_t mfindex) 1573 { 1574 if (xfer->trbs[0].control & TRB_TR_SIA) { 1575 uint64_t asap = ((mfindex + epctx->interval - 1) & 1576 ~(epctx->interval-1)); 1577 if (asap >= epctx->mfindex_last && 1578 asap <= epctx->mfindex_last + epctx->interval * 4) { 1579 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1580 } else { 1581 xfer->mfindex_kick = asap; 1582 } 1583 } else { 1584 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1585 & TRB_TR_FRAMEID_MASK; 1586 xfer->mfindex_kick |= mfindex & ~0x3fff; 1587 if (xfer->mfindex_kick < mfindex) { 1588 xfer->mfindex_kick += 0x4000; 1589 } 1590 } 1591 } 1592 1593 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1594 XHCIEPContext *epctx, uint64_t mfindex) 1595 { 1596 if (xfer->mfindex_kick > mfindex) { 1597 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1598 (xfer->mfindex_kick - mfindex) * 125000); 1599 xfer->running_retry = 1; 1600 } else { 1601 epctx->mfindex_last = xfer->mfindex_kick; 1602 qemu_del_timer(epctx->kick_timer); 1603 xfer->running_retry = 0; 1604 } 1605 } 1606 1607 1608 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1609 { 1610 uint64_t mfindex; 1611 int ret; 1612 1613 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1614 1615 xfer->in_xfer = epctx->type>>2; 1616 1617 switch(epctx->type) { 1618 case ET_INTR_OUT: 1619 case ET_INTR_IN: 1620 case ET_BULK_OUT: 1621 case ET_BULK_IN: 1622 xfer->pkts = 0; 1623 xfer->iso_xfer = false; 1624 break; 1625 case ET_ISO_OUT: 1626 case ET_ISO_IN: 1627 xfer->pkts = 1; 1628 xfer->iso_xfer = true; 1629 mfindex = xhci_mfindex_get(xhci); 1630 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1631 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1632 if (xfer->running_retry) { 1633 return -1; 1634 } 1635 break; 1636 default: 1637 fprintf(stderr, "xhci: unknown or unhandled EP " 1638 "(type %d, in %d, ep %02x)\n", 1639 epctx->type, xfer->in_xfer, xfer->epid); 1640 return -1; 1641 } 1642 1643 if (xhci_setup_packet(xfer) < 0) { 1644 return -1; 1645 } 1646 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1647 1648 xhci_complete_packet(xfer, ret); 1649 if (!xfer->running_async && !xfer->running_retry) { 1650 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1651 } 1652 return 0; 1653 } 1654 1655 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1656 { 1657 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1658 return xhci_submit(xhci, xfer, epctx); 1659 } 1660 1661 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1662 { 1663 XHCIEPContext *epctx; 1664 USBEndpoint *ep = NULL; 1665 uint64_t mfindex; 1666 int length; 1667 int i; 1668 1669 trace_usb_xhci_ep_kick(slotid, epid); 1670 assert(slotid >= 1 && slotid <= MAXSLOTS); 1671 assert(epid >= 1 && epid <= 31); 1672 1673 if (!xhci->slots[slotid-1].enabled) { 1674 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1675 return; 1676 } 1677 epctx = xhci->slots[slotid-1].eps[epid-1]; 1678 if (!epctx) { 1679 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1680 epid, slotid); 1681 return; 1682 } 1683 1684 if (epctx->retry) { 1685 XHCITransfer *xfer = epctx->retry; 1686 int result; 1687 1688 trace_usb_xhci_xfer_retry(xfer); 1689 assert(xfer->running_retry); 1690 if (xfer->iso_xfer) { 1691 /* retry delayed iso transfer */ 1692 mfindex = xhci_mfindex_get(xhci); 1693 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1694 if (xfer->running_retry) { 1695 return; 1696 } 1697 if (xhci_setup_packet(xfer) < 0) { 1698 return; 1699 } 1700 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1701 assert(result != USB_RET_NAK); 1702 xhci_complete_packet(xfer, result); 1703 } else { 1704 /* retry nak'ed transfer */ 1705 if (xhci_setup_packet(xfer) < 0) { 1706 return; 1707 } 1708 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1709 if (result == USB_RET_NAK) { 1710 return; 1711 } 1712 xhci_complete_packet(xfer, result); 1713 } 1714 assert(!xfer->running_retry); 1715 epctx->retry = NULL; 1716 } 1717 1718 if (epctx->state == EP_HALTED) { 1719 DPRINTF("xhci: ep halted, not running schedule\n"); 1720 return; 1721 } 1722 1723 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1724 1725 while (1) { 1726 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1727 if (xfer->running_async || xfer->running_retry) { 1728 break; 1729 } 1730 length = xhci_ring_chain_length(xhci, &epctx->ring); 1731 if (length < 0) { 1732 break; 1733 } else if (length == 0) { 1734 break; 1735 } 1736 if (xfer->trbs && xfer->trb_alloced < length) { 1737 xfer->trb_count = 0; 1738 xfer->trb_alloced = 0; 1739 g_free(xfer->trbs); 1740 xfer->trbs = NULL; 1741 } 1742 if (!xfer->trbs) { 1743 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1744 xfer->trb_alloced = length; 1745 } 1746 xfer->trb_count = length; 1747 1748 for (i = 0; i < length; i++) { 1749 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1750 } 1751 xfer->xhci = xhci; 1752 xfer->epid = epid; 1753 xfer->slotid = slotid; 1754 1755 if (epid == 1) { 1756 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1757 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1758 ep = xfer->packet.ep; 1759 } else { 1760 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1761 } 1762 } else { 1763 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1764 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1765 ep = xfer->packet.ep; 1766 } else { 1767 if (!xfer->iso_xfer) { 1768 fprintf(stderr, "xhci: error firing data transfer\n"); 1769 } 1770 } 1771 } 1772 1773 if (epctx->state == EP_HALTED) { 1774 break; 1775 } 1776 if (xfer->running_retry) { 1777 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1778 epctx->retry = xfer; 1779 break; 1780 } 1781 } 1782 if (ep) { 1783 usb_device_flush_ep_queue(ep->dev, ep); 1784 } 1785 } 1786 1787 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1788 { 1789 trace_usb_xhci_slot_enable(slotid); 1790 assert(slotid >= 1 && slotid <= MAXSLOTS); 1791 xhci->slots[slotid-1].enabled = 1; 1792 xhci->slots[slotid-1].uport = NULL; 1793 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1794 1795 return CC_SUCCESS; 1796 } 1797 1798 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1799 { 1800 int i; 1801 1802 trace_usb_xhci_slot_disable(slotid); 1803 assert(slotid >= 1 && slotid <= MAXSLOTS); 1804 1805 for (i = 1; i <= 31; i++) { 1806 if (xhci->slots[slotid-1].eps[i-1]) { 1807 xhci_disable_ep(xhci, slotid, i); 1808 } 1809 } 1810 1811 xhci->slots[slotid-1].enabled = 0; 1812 return CC_SUCCESS; 1813 } 1814 1815 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1816 { 1817 USBPort *uport; 1818 char path[32]; 1819 int i, pos, port; 1820 1821 port = (slot_ctx[1]>>16) & 0xFF; 1822 port = xhci->ports[port-1].uport->index+1; 1823 pos = snprintf(path, sizeof(path), "%d", port); 1824 for (i = 0; i < 5; i++) { 1825 port = (slot_ctx[0] >> 4*i) & 0x0f; 1826 if (!port) { 1827 break; 1828 } 1829 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1830 } 1831 1832 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1833 if (strcmp(uport->path, path) == 0) { 1834 return uport; 1835 } 1836 } 1837 return NULL; 1838 } 1839 1840 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1841 uint64_t pictx, bool bsr) 1842 { 1843 XHCISlot *slot; 1844 USBPort *uport; 1845 USBDevice *dev; 1846 dma_addr_t ictx, octx, dcbaap; 1847 uint64_t poctx; 1848 uint32_t ictl_ctx[2]; 1849 uint32_t slot_ctx[4]; 1850 uint32_t ep0_ctx[5]; 1851 int i; 1852 TRBCCode res; 1853 1854 trace_usb_xhci_slot_address(slotid); 1855 assert(slotid >= 1 && slotid <= MAXSLOTS); 1856 1857 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1858 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1859 ictx = xhci_mask64(pictx); 1860 octx = xhci_mask64(le64_to_cpu(poctx)); 1861 1862 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1863 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1864 1865 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1866 1867 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1868 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1869 ictl_ctx[0], ictl_ctx[1]); 1870 return CC_TRB_ERROR; 1871 } 1872 1873 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1874 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1875 1876 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1877 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1878 1879 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1880 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1881 1882 uport = xhci_lookup_uport(xhci, slot_ctx); 1883 if (uport == NULL) { 1884 fprintf(stderr, "xhci: port not found\n"); 1885 return CC_TRB_ERROR; 1886 } 1887 1888 dev = uport->dev; 1889 if (!dev) { 1890 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1891 return CC_USB_TRANSACTION_ERROR; 1892 } 1893 1894 for (i = 0; i < MAXSLOTS; i++) { 1895 if (xhci->slots[i].uport == uport) { 1896 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1897 uport->path, i+1); 1898 return CC_TRB_ERROR; 1899 } 1900 } 1901 1902 slot = &xhci->slots[slotid-1]; 1903 slot->uport = uport; 1904 slot->ctx = octx; 1905 1906 if (bsr) { 1907 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1908 } else { 1909 slot->devaddr = xhci->devaddr++; 1910 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1911 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1912 usb_device_handle_control(dev, NULL, 1913 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1914 slot->devaddr, 0, 0, NULL); 1915 } 1916 1917 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1918 1919 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1920 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1921 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1922 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1923 1924 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1925 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1926 1927 return res; 1928 } 1929 1930 1931 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1932 uint64_t pictx, bool dc) 1933 { 1934 dma_addr_t ictx, octx; 1935 uint32_t ictl_ctx[2]; 1936 uint32_t slot_ctx[4]; 1937 uint32_t islot_ctx[4]; 1938 uint32_t ep_ctx[5]; 1939 int i; 1940 TRBCCode res; 1941 1942 trace_usb_xhci_slot_configure(slotid); 1943 assert(slotid >= 1 && slotid <= MAXSLOTS); 1944 1945 ictx = xhci_mask64(pictx); 1946 octx = xhci->slots[slotid-1].ctx; 1947 1948 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1949 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1950 1951 if (dc) { 1952 for (i = 2; i <= 31; i++) { 1953 if (xhci->slots[slotid-1].eps[i-1]) { 1954 xhci_disable_ep(xhci, slotid, i); 1955 } 1956 } 1957 1958 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1959 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1960 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1961 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1962 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1963 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1964 1965 return CC_SUCCESS; 1966 } 1967 1968 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1969 1970 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1971 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1972 ictl_ctx[0], ictl_ctx[1]); 1973 return CC_TRB_ERROR; 1974 } 1975 1976 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1977 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1978 1979 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1980 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1981 return CC_CONTEXT_STATE_ERROR; 1982 } 1983 1984 for (i = 2; i <= 31; i++) { 1985 if (ictl_ctx[0] & (1<<i)) { 1986 xhci_disable_ep(xhci, slotid, i); 1987 } 1988 if (ictl_ctx[1] & (1<<i)) { 1989 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1990 sizeof(ep_ctx)); 1991 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1992 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1993 ep_ctx[3], ep_ctx[4]); 1994 xhci_disable_ep(xhci, slotid, i); 1995 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1996 if (res != CC_SUCCESS) { 1997 return res; 1998 } 1999 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2000 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2001 ep_ctx[3], ep_ctx[4]); 2002 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2003 } 2004 } 2005 2006 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2007 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2008 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2009 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2010 SLOT_CONTEXT_ENTRIES_SHIFT); 2011 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2012 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2013 2014 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2015 2016 return CC_SUCCESS; 2017 } 2018 2019 2020 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2021 uint64_t pictx) 2022 { 2023 dma_addr_t ictx, octx; 2024 uint32_t ictl_ctx[2]; 2025 uint32_t iep0_ctx[5]; 2026 uint32_t ep0_ctx[5]; 2027 uint32_t islot_ctx[4]; 2028 uint32_t slot_ctx[4]; 2029 2030 trace_usb_xhci_slot_evaluate(slotid); 2031 assert(slotid >= 1 && slotid <= MAXSLOTS); 2032 2033 ictx = xhci_mask64(pictx); 2034 octx = xhci->slots[slotid-1].ctx; 2035 2036 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2037 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2038 2039 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 2040 2041 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2042 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2043 ictl_ctx[0], ictl_ctx[1]); 2044 return CC_TRB_ERROR; 2045 } 2046 2047 if (ictl_ctx[1] & 0x1) { 2048 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2049 2050 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2051 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2052 2053 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2054 2055 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2056 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2057 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2058 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2059 2060 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2061 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2062 2063 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2064 } 2065 2066 if (ictl_ctx[1] & 0x2) { 2067 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2068 2069 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2070 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2071 iep0_ctx[3], iep0_ctx[4]); 2072 2073 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2074 2075 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2076 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2077 2078 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2079 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2080 2081 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2082 } 2083 2084 return CC_SUCCESS; 2085 } 2086 2087 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2088 { 2089 uint32_t slot_ctx[4]; 2090 dma_addr_t octx; 2091 int i; 2092 2093 trace_usb_xhci_slot_reset(slotid); 2094 assert(slotid >= 1 && slotid <= MAXSLOTS); 2095 2096 octx = xhci->slots[slotid-1].ctx; 2097 2098 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2099 2100 for (i = 2; i <= 31; i++) { 2101 if (xhci->slots[slotid-1].eps[i-1]) { 2102 xhci_disable_ep(xhci, slotid, i); 2103 } 2104 } 2105 2106 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2107 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2108 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2109 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2110 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2111 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2112 2113 return CC_SUCCESS; 2114 } 2115 2116 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2117 { 2118 unsigned int slotid; 2119 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2120 if (slotid < 1 || slotid > MAXSLOTS) { 2121 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2122 event->ccode = CC_TRB_ERROR; 2123 return 0; 2124 } else if (!xhci->slots[slotid-1].enabled) { 2125 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2126 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2127 return 0; 2128 } 2129 return slotid; 2130 } 2131 2132 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2133 { 2134 dma_addr_t ctx; 2135 uint8_t bw_ctx[xhci->numports+1]; 2136 2137 DPRINTF("xhci_get_port_bandwidth()\n"); 2138 2139 ctx = xhci_mask64(pctx); 2140 2141 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2142 2143 /* TODO: actually implement real values here */ 2144 bw_ctx[0] = 0; 2145 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2146 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2147 2148 return CC_SUCCESS; 2149 } 2150 2151 static uint32_t rotl(uint32_t v, unsigned count) 2152 { 2153 count &= 31; 2154 return (v << count) | (v >> (32 - count)); 2155 } 2156 2157 2158 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2159 { 2160 uint32_t val; 2161 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2162 val += rotl(lo + 0x49434878, hi & 0x1F); 2163 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2164 return ~val; 2165 } 2166 2167 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2168 { 2169 uint32_t buf[8]; 2170 uint32_t obuf[8]; 2171 dma_addr_t paddr = xhci_mask64(addr); 2172 2173 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2174 2175 memcpy(obuf, buf, sizeof(obuf)); 2176 2177 if ((buf[0] & 0xff) == 2) { 2178 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2179 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2180 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2181 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2182 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2183 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2184 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2185 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2186 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2187 } 2188 2189 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2190 } 2191 2192 static void xhci_process_commands(XHCIState *xhci) 2193 { 2194 XHCITRB trb; 2195 TRBType type; 2196 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2197 dma_addr_t addr; 2198 unsigned int i, slotid = 0; 2199 2200 DPRINTF("xhci_process_commands()\n"); 2201 if (!xhci_running(xhci)) { 2202 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2203 return; 2204 } 2205 2206 xhci->crcr_low |= CRCR_CRR; 2207 2208 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2209 event.ptr = addr; 2210 switch (type) { 2211 case CR_ENABLE_SLOT: 2212 for (i = 0; i < MAXSLOTS; i++) { 2213 if (!xhci->slots[i].enabled) { 2214 break; 2215 } 2216 } 2217 if (i >= MAXSLOTS) { 2218 fprintf(stderr, "xhci: no device slots available\n"); 2219 event.ccode = CC_NO_SLOTS_ERROR; 2220 } else { 2221 slotid = i+1; 2222 event.ccode = xhci_enable_slot(xhci, slotid); 2223 } 2224 break; 2225 case CR_DISABLE_SLOT: 2226 slotid = xhci_get_slot(xhci, &event, &trb); 2227 if (slotid) { 2228 event.ccode = xhci_disable_slot(xhci, slotid); 2229 } 2230 break; 2231 case CR_ADDRESS_DEVICE: 2232 slotid = xhci_get_slot(xhci, &event, &trb); 2233 if (slotid) { 2234 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2235 trb.control & TRB_CR_BSR); 2236 } 2237 break; 2238 case CR_CONFIGURE_ENDPOINT: 2239 slotid = xhci_get_slot(xhci, &event, &trb); 2240 if (slotid) { 2241 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2242 trb.control & TRB_CR_DC); 2243 } 2244 break; 2245 case CR_EVALUATE_CONTEXT: 2246 slotid = xhci_get_slot(xhci, &event, &trb); 2247 if (slotid) { 2248 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2249 } 2250 break; 2251 case CR_STOP_ENDPOINT: 2252 slotid = xhci_get_slot(xhci, &event, &trb); 2253 if (slotid) { 2254 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2255 & TRB_CR_EPID_MASK; 2256 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2257 } 2258 break; 2259 case CR_RESET_ENDPOINT: 2260 slotid = xhci_get_slot(xhci, &event, &trb); 2261 if (slotid) { 2262 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2263 & TRB_CR_EPID_MASK; 2264 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2265 } 2266 break; 2267 case CR_SET_TR_DEQUEUE: 2268 slotid = xhci_get_slot(xhci, &event, &trb); 2269 if (slotid) { 2270 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2271 & TRB_CR_EPID_MASK; 2272 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2273 trb.parameter); 2274 } 2275 break; 2276 case CR_RESET_DEVICE: 2277 slotid = xhci_get_slot(xhci, &event, &trb); 2278 if (slotid) { 2279 event.ccode = xhci_reset_slot(xhci, slotid); 2280 } 2281 break; 2282 case CR_GET_PORT_BANDWIDTH: 2283 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2284 break; 2285 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2286 xhci_via_challenge(xhci, trb.parameter); 2287 break; 2288 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2289 event.type = 48; /* NEC reply */ 2290 event.length = 0x3025; 2291 break; 2292 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2293 { 2294 uint32_t chi = trb.parameter >> 32; 2295 uint32_t clo = trb.parameter; 2296 uint32_t val = xhci_nec_challenge(chi, clo); 2297 event.length = val & 0xFFFF; 2298 event.epid = val >> 16; 2299 slotid = val >> 24; 2300 event.type = 48; /* NEC reply */ 2301 } 2302 break; 2303 default: 2304 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2305 event.ccode = CC_TRB_ERROR; 2306 break; 2307 } 2308 event.slotid = slotid; 2309 xhci_event(xhci, &event, 0); 2310 } 2311 } 2312 2313 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2314 { 2315 port->portsc = PORTSC_PP; 2316 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2317 (1 << port->uport->dev->speed) & port->speedmask) { 2318 port->portsc |= PORTSC_CCS; 2319 switch (port->uport->dev->speed) { 2320 case USB_SPEED_LOW: 2321 port->portsc |= PORTSC_SPEED_LOW; 2322 break; 2323 case USB_SPEED_FULL: 2324 port->portsc |= PORTSC_SPEED_FULL; 2325 break; 2326 case USB_SPEED_HIGH: 2327 port->portsc |= PORTSC_SPEED_HIGH; 2328 break; 2329 case USB_SPEED_SUPER: 2330 port->portsc |= PORTSC_SPEED_SUPER; 2331 break; 2332 } 2333 } 2334 2335 if (xhci_running(xhci)) { 2336 port->portsc |= PORTSC_CSC; 2337 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2338 port->portnr << 24}; 2339 xhci_event(xhci, &ev, 0); 2340 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2341 } 2342 } 2343 2344 static void xhci_reset(DeviceState *dev) 2345 { 2346 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2347 int i; 2348 2349 trace_usb_xhci_reset(); 2350 if (!(xhci->usbsts & USBSTS_HCH)) { 2351 fprintf(stderr, "xhci: reset while running!\n"); 2352 } 2353 2354 xhci->usbcmd = 0; 2355 xhci->usbsts = USBSTS_HCH; 2356 xhci->dnctrl = 0; 2357 xhci->crcr_low = 0; 2358 xhci->crcr_high = 0; 2359 xhci->dcbaap_low = 0; 2360 xhci->dcbaap_high = 0; 2361 xhci->config = 0; 2362 xhci->devaddr = 2; 2363 2364 for (i = 0; i < MAXSLOTS; i++) { 2365 xhci_disable_slot(xhci, i+1); 2366 } 2367 2368 for (i = 0; i < xhci->numports; i++) { 2369 xhci_update_port(xhci, xhci->ports + i, 0); 2370 } 2371 2372 for (i = 0; i < MAXINTRS; i++) { 2373 xhci->intr[i].iman = 0; 2374 xhci->intr[i].imod = 0; 2375 xhci->intr[i].erstsz = 0; 2376 xhci->intr[i].erstba_low = 0; 2377 xhci->intr[i].erstba_high = 0; 2378 xhci->intr[i].erdp_low = 0; 2379 xhci->intr[i].erdp_high = 0; 2380 xhci->intr[i].msix_used = 0; 2381 2382 xhci->intr[i].er_ep_idx = 0; 2383 xhci->intr[i].er_pcs = 1; 2384 xhci->intr[i].er_full = 0; 2385 xhci->intr[i].ev_buffer_put = 0; 2386 xhci->intr[i].ev_buffer_get = 0; 2387 } 2388 2389 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2390 xhci_mfwrap_update(xhci); 2391 } 2392 2393 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2394 { 2395 XHCIState *xhci = ptr; 2396 uint32_t ret; 2397 2398 switch (reg) { 2399 case 0x00: /* HCIVERSION, CAPLENGTH */ 2400 ret = 0x01000000 | LEN_CAP; 2401 break; 2402 case 0x04: /* HCSPARAMS 1 */ 2403 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2404 | (MAXINTRS<<8) | MAXSLOTS; 2405 break; 2406 case 0x08: /* HCSPARAMS 2 */ 2407 ret = 0x0000000f; 2408 break; 2409 case 0x0c: /* HCSPARAMS 3 */ 2410 ret = 0x00000000; 2411 break; 2412 case 0x10: /* HCCPARAMS */ 2413 if (sizeof(dma_addr_t) == 4) { 2414 ret = 0x00081000; 2415 } else { 2416 ret = 0x00081001; 2417 } 2418 break; 2419 case 0x14: /* DBOFF */ 2420 ret = OFF_DOORBELL; 2421 break; 2422 case 0x18: /* RTSOFF */ 2423 ret = OFF_RUNTIME; 2424 break; 2425 2426 /* extended capabilities */ 2427 case 0x20: /* Supported Protocol:00 */ 2428 ret = 0x02000402; /* USB 2.0 */ 2429 break; 2430 case 0x24: /* Supported Protocol:04 */ 2431 ret = 0x20425455; /* "USB " */ 2432 break; 2433 case 0x28: /* Supported Protocol:08 */ 2434 ret = 0x00000001 | (xhci->numports_2<<8); 2435 break; 2436 case 0x2c: /* Supported Protocol:0c */ 2437 ret = 0x00000000; /* reserved */ 2438 break; 2439 case 0x30: /* Supported Protocol:00 */ 2440 ret = 0x03000002; /* USB 3.0 */ 2441 break; 2442 case 0x34: /* Supported Protocol:04 */ 2443 ret = 0x20425455; /* "USB " */ 2444 break; 2445 case 0x38: /* Supported Protocol:08 */ 2446 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2447 break; 2448 case 0x3c: /* Supported Protocol:0c */ 2449 ret = 0x00000000; /* reserved */ 2450 break; 2451 default: 2452 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2453 ret = 0; 2454 } 2455 2456 trace_usb_xhci_cap_read(reg, ret); 2457 return ret; 2458 } 2459 2460 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2461 { 2462 XHCIPort *port = ptr; 2463 uint32_t ret; 2464 2465 switch (reg) { 2466 case 0x00: /* PORTSC */ 2467 ret = port->portsc; 2468 break; 2469 case 0x04: /* PORTPMSC */ 2470 case 0x08: /* PORTLI */ 2471 ret = 0; 2472 break; 2473 case 0x0c: /* reserved */ 2474 default: 2475 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2476 port->portnr, (uint32_t)reg); 2477 ret = 0; 2478 } 2479 2480 trace_usb_xhci_port_read(port->portnr, reg, ret); 2481 return ret; 2482 } 2483 2484 static void xhci_port_write(void *ptr, hwaddr reg, 2485 uint64_t val, unsigned size) 2486 { 2487 XHCIPort *port = ptr; 2488 uint32_t portsc; 2489 2490 trace_usb_xhci_port_write(port->portnr, reg, val); 2491 2492 switch (reg) { 2493 case 0x00: /* PORTSC */ 2494 portsc = port->portsc; 2495 /* write-1-to-clear bits*/ 2496 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2497 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2498 if (val & PORTSC_LWS) { 2499 /* overwrite PLS only when LWS=1 */ 2500 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2501 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2502 } 2503 /* read/write bits */ 2504 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2505 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2506 /* write-1-to-start bits */ 2507 if (val & PORTSC_PR) { 2508 DPRINTF("xhci: port %d reset\n", port); 2509 usb_device_reset(port->uport->dev); 2510 portsc |= PORTSC_PRC | PORTSC_PED; 2511 } 2512 port->portsc = portsc; 2513 break; 2514 case 0x04: /* PORTPMSC */ 2515 case 0x08: /* PORTLI */ 2516 default: 2517 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2518 port->portnr, (uint32_t)reg); 2519 } 2520 } 2521 2522 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2523 { 2524 XHCIState *xhci = ptr; 2525 uint32_t ret; 2526 2527 switch (reg) { 2528 case 0x00: /* USBCMD */ 2529 ret = xhci->usbcmd; 2530 break; 2531 case 0x04: /* USBSTS */ 2532 ret = xhci->usbsts; 2533 break; 2534 case 0x08: /* PAGESIZE */ 2535 ret = 1; /* 4KiB */ 2536 break; 2537 case 0x14: /* DNCTRL */ 2538 ret = xhci->dnctrl; 2539 break; 2540 case 0x18: /* CRCR low */ 2541 ret = xhci->crcr_low & ~0xe; 2542 break; 2543 case 0x1c: /* CRCR high */ 2544 ret = xhci->crcr_high; 2545 break; 2546 case 0x30: /* DCBAAP low */ 2547 ret = xhci->dcbaap_low; 2548 break; 2549 case 0x34: /* DCBAAP high */ 2550 ret = xhci->dcbaap_high; 2551 break; 2552 case 0x38: /* CONFIG */ 2553 ret = xhci->config; 2554 break; 2555 default: 2556 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2557 ret = 0; 2558 } 2559 2560 trace_usb_xhci_oper_read(reg, ret); 2561 return ret; 2562 } 2563 2564 static void xhci_oper_write(void *ptr, hwaddr reg, 2565 uint64_t val, unsigned size) 2566 { 2567 XHCIState *xhci = ptr; 2568 2569 trace_usb_xhci_oper_write(reg, val); 2570 2571 switch (reg) { 2572 case 0x00: /* USBCMD */ 2573 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2574 xhci_run(xhci); 2575 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2576 xhci_stop(xhci); 2577 } 2578 xhci->usbcmd = val & 0xc0f; 2579 xhci_mfwrap_update(xhci); 2580 if (val & USBCMD_HCRST) { 2581 xhci_reset(&xhci->pci_dev.qdev); 2582 } 2583 xhci_intx_update(xhci); 2584 break; 2585 2586 case 0x04: /* USBSTS */ 2587 /* these bits are write-1-to-clear */ 2588 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2589 xhci_intx_update(xhci); 2590 break; 2591 2592 case 0x14: /* DNCTRL */ 2593 xhci->dnctrl = val & 0xffff; 2594 break; 2595 case 0x18: /* CRCR low */ 2596 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2597 break; 2598 case 0x1c: /* CRCR high */ 2599 xhci->crcr_high = val; 2600 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2601 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2602 xhci->crcr_low &= ~CRCR_CRR; 2603 xhci_event(xhci, &event, 0); 2604 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2605 } else { 2606 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2607 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2608 } 2609 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2610 break; 2611 case 0x30: /* DCBAAP low */ 2612 xhci->dcbaap_low = val & 0xffffffc0; 2613 break; 2614 case 0x34: /* DCBAAP high */ 2615 xhci->dcbaap_high = val; 2616 break; 2617 case 0x38: /* CONFIG */ 2618 xhci->config = val & 0xff; 2619 break; 2620 default: 2621 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2622 } 2623 } 2624 2625 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2626 unsigned size) 2627 { 2628 XHCIState *xhci = ptr; 2629 uint32_t ret = 0; 2630 2631 if (reg < 0x20) { 2632 switch (reg) { 2633 case 0x00: /* MFINDEX */ 2634 ret = xhci_mfindex_get(xhci) & 0x3fff; 2635 break; 2636 default: 2637 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2638 (int)reg); 2639 break; 2640 } 2641 } else { 2642 int v = (reg - 0x20) / 0x20; 2643 XHCIInterrupter *intr = &xhci->intr[v]; 2644 switch (reg & 0x1f) { 2645 case 0x00: /* IMAN */ 2646 ret = intr->iman; 2647 break; 2648 case 0x04: /* IMOD */ 2649 ret = intr->imod; 2650 break; 2651 case 0x08: /* ERSTSZ */ 2652 ret = intr->erstsz; 2653 break; 2654 case 0x10: /* ERSTBA low */ 2655 ret = intr->erstba_low; 2656 break; 2657 case 0x14: /* ERSTBA high */ 2658 ret = intr->erstba_high; 2659 break; 2660 case 0x18: /* ERDP low */ 2661 ret = intr->erdp_low; 2662 break; 2663 case 0x1c: /* ERDP high */ 2664 ret = intr->erdp_high; 2665 break; 2666 } 2667 } 2668 2669 trace_usb_xhci_runtime_read(reg, ret); 2670 return ret; 2671 } 2672 2673 static void xhci_runtime_write(void *ptr, hwaddr reg, 2674 uint64_t val, unsigned size) 2675 { 2676 XHCIState *xhci = ptr; 2677 int v = (reg - 0x20) / 0x20; 2678 XHCIInterrupter *intr = &xhci->intr[v]; 2679 trace_usb_xhci_runtime_write(reg, val); 2680 2681 if (reg < 0x20) { 2682 fprintf(stderr, "%s: reg 0x%x unimplemented\n", __func__, (int)reg); 2683 return; 2684 } 2685 2686 switch (reg & 0x1f) { 2687 case 0x00: /* IMAN */ 2688 if (val & IMAN_IP) { 2689 intr->iman &= ~IMAN_IP; 2690 } 2691 intr->iman &= ~IMAN_IE; 2692 intr->iman |= val & IMAN_IE; 2693 if (v == 0) { 2694 xhci_intx_update(xhci); 2695 } 2696 xhci_msix_update(xhci, v); 2697 break; 2698 case 0x04: /* IMOD */ 2699 intr->imod = val; 2700 break; 2701 case 0x08: /* ERSTSZ */ 2702 intr->erstsz = val & 0xffff; 2703 break; 2704 case 0x10: /* ERSTBA low */ 2705 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2706 intr->erstba_low = val & 0xffffffc0; */ 2707 intr->erstba_low = val & 0xfffffff0; 2708 break; 2709 case 0x14: /* ERSTBA high */ 2710 intr->erstba_high = val; 2711 xhci_er_reset(xhci, v); 2712 break; 2713 case 0x18: /* ERDP low */ 2714 if (val & ERDP_EHB) { 2715 intr->erdp_low &= ~ERDP_EHB; 2716 } 2717 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2718 break; 2719 case 0x1c: /* ERDP high */ 2720 intr->erdp_high = val; 2721 xhci_events_update(xhci, v); 2722 break; 2723 default: 2724 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2725 (int)reg); 2726 } 2727 } 2728 2729 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 2730 unsigned size) 2731 { 2732 /* doorbells always read as 0 */ 2733 trace_usb_xhci_doorbell_read(reg, 0); 2734 return 0; 2735 } 2736 2737 static void xhci_doorbell_write(void *ptr, hwaddr reg, 2738 uint64_t val, unsigned size) 2739 { 2740 XHCIState *xhci = ptr; 2741 2742 trace_usb_xhci_doorbell_write(reg, val); 2743 2744 if (!xhci_running(xhci)) { 2745 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2746 return; 2747 } 2748 2749 reg >>= 2; 2750 2751 if (reg == 0) { 2752 if (val == 0) { 2753 xhci_process_commands(xhci); 2754 } else { 2755 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2756 (uint32_t)val); 2757 } 2758 } else { 2759 if (reg > MAXSLOTS) { 2760 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2761 } else if (val > 31) { 2762 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2763 (int)reg, (uint32_t)val); 2764 } else { 2765 xhci_kick_ep(xhci, reg, val); 2766 } 2767 } 2768 } 2769 2770 static const MemoryRegionOps xhci_cap_ops = { 2771 .read = xhci_cap_read, 2772 .valid.min_access_size = 1, 2773 .valid.max_access_size = 4, 2774 .impl.min_access_size = 4, 2775 .impl.max_access_size = 4, 2776 .endianness = DEVICE_LITTLE_ENDIAN, 2777 }; 2778 2779 static const MemoryRegionOps xhci_oper_ops = { 2780 .read = xhci_oper_read, 2781 .write = xhci_oper_write, 2782 .valid.min_access_size = 4, 2783 .valid.max_access_size = 4, 2784 .endianness = DEVICE_LITTLE_ENDIAN, 2785 }; 2786 2787 static const MemoryRegionOps xhci_port_ops = { 2788 .read = xhci_port_read, 2789 .write = xhci_port_write, 2790 .valid.min_access_size = 4, 2791 .valid.max_access_size = 4, 2792 .endianness = DEVICE_LITTLE_ENDIAN, 2793 }; 2794 2795 static const MemoryRegionOps xhci_runtime_ops = { 2796 .read = xhci_runtime_read, 2797 .write = xhci_runtime_write, 2798 .valid.min_access_size = 4, 2799 .valid.max_access_size = 4, 2800 .endianness = DEVICE_LITTLE_ENDIAN, 2801 }; 2802 2803 static const MemoryRegionOps xhci_doorbell_ops = { 2804 .read = xhci_doorbell_read, 2805 .write = xhci_doorbell_write, 2806 .valid.min_access_size = 4, 2807 .valid.max_access_size = 4, 2808 .endianness = DEVICE_LITTLE_ENDIAN, 2809 }; 2810 2811 static void xhci_attach(USBPort *usbport) 2812 { 2813 XHCIState *xhci = usbport->opaque; 2814 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2815 2816 xhci_update_port(xhci, port, 0); 2817 } 2818 2819 static void xhci_detach(USBPort *usbport) 2820 { 2821 XHCIState *xhci = usbport->opaque; 2822 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2823 2824 xhci_update_port(xhci, port, 1); 2825 } 2826 2827 static void xhci_wakeup(USBPort *usbport) 2828 { 2829 XHCIState *xhci = usbport->opaque; 2830 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2831 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2832 port->portnr << 24}; 2833 uint32_t pls; 2834 2835 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2836 if (pls != 3) { 2837 return; 2838 } 2839 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2840 if (port->portsc & PORTSC_PLC) { 2841 return; 2842 } 2843 port->portsc |= PORTSC_PLC; 2844 xhci_event(xhci, &ev, 0); 2845 } 2846 2847 static void xhci_complete(USBPort *port, USBPacket *packet) 2848 { 2849 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2850 2851 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) { 2852 xhci_ep_nuke_one_xfer(xfer); 2853 return; 2854 } 2855 xhci_complete_packet(xfer, packet->result); 2856 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2857 } 2858 2859 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2860 { 2861 USBBus *bus = usb_bus_from_device(child); 2862 XHCIState *xhci = container_of(bus, XHCIState, bus); 2863 int i; 2864 2865 for (i = 0; i < MAXSLOTS; i++) { 2866 if (xhci->slots[i].uport == uport) { 2867 xhci->slots[i].uport = NULL; 2868 } 2869 } 2870 } 2871 2872 static USBPortOps xhci_uport_ops = { 2873 .attach = xhci_attach, 2874 .detach = xhci_detach, 2875 .wakeup = xhci_wakeup, 2876 .complete = xhci_complete, 2877 .child_detach = xhci_child_detach, 2878 }; 2879 2880 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2881 { 2882 XHCISlot *slot; 2883 int slotid; 2884 2885 for (slotid = 1; slotid <= MAXSLOTS; slotid++) { 2886 slot = &xhci->slots[slotid-1]; 2887 if (slot->devaddr == dev->addr) { 2888 return slotid; 2889 } 2890 } 2891 return 0; 2892 } 2893 2894 static int xhci_find_epid(USBEndpoint *ep) 2895 { 2896 if (ep->nr == 0) { 2897 return 1; 2898 } 2899 if (ep->pid == USB_TOKEN_IN) { 2900 return ep->nr * 2 + 1; 2901 } else { 2902 return ep->nr * 2; 2903 } 2904 } 2905 2906 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2907 { 2908 XHCIState *xhci = container_of(bus, XHCIState, bus); 2909 int slotid; 2910 2911 DPRINTF("%s\n", __func__); 2912 slotid = xhci_find_slotid(xhci, ep->dev); 2913 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2914 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2915 return; 2916 } 2917 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2918 } 2919 2920 static USBBusOps xhci_bus_ops = { 2921 .wakeup_endpoint = xhci_wakeup_endpoint, 2922 }; 2923 2924 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2925 { 2926 XHCIPort *port; 2927 int i, usbports, speedmask; 2928 2929 xhci->usbsts = USBSTS_HCH; 2930 2931 if (xhci->numports_2 > MAXPORTS_2) { 2932 xhci->numports_2 = MAXPORTS_2; 2933 } 2934 if (xhci->numports_3 > MAXPORTS_3) { 2935 xhci->numports_3 = MAXPORTS_3; 2936 } 2937 usbports = MAX(xhci->numports_2, xhci->numports_3); 2938 xhci->numports = xhci->numports_2 + xhci->numports_3; 2939 2940 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2941 2942 for (i = 0; i < usbports; i++) { 2943 speedmask = 0; 2944 if (i < xhci->numports_2) { 2945 port = &xhci->ports[i]; 2946 port->portnr = i + 1; 2947 port->uport = &xhci->uports[i]; 2948 port->speedmask = 2949 USB_SPEED_MASK_LOW | 2950 USB_SPEED_MASK_FULL | 2951 USB_SPEED_MASK_HIGH; 2952 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 2953 speedmask |= port->speedmask; 2954 } 2955 if (i < xhci->numports_3) { 2956 port = &xhci->ports[i + xhci->numports_2]; 2957 port->portnr = i + 1 + xhci->numports_2; 2958 port->uport = &xhci->uports[i]; 2959 port->speedmask = USB_SPEED_MASK_SUPER; 2960 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 2961 speedmask |= port->speedmask; 2962 } 2963 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2964 &xhci_uport_ops, speedmask); 2965 } 2966 } 2967 2968 static int usb_xhci_initfn(struct PCIDevice *dev) 2969 { 2970 int i, ret; 2971 2972 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2973 2974 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2975 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2976 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2977 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2978 2979 usb_xhci_init(xhci, &dev->qdev); 2980 2981 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2982 2983 xhci->irq = xhci->pci_dev.irq[0]; 2984 2985 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 2986 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 2987 "capabilities", LEN_CAP); 2988 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 2989 "operational", 0x400); 2990 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 2991 "runtime", LEN_RUNTIME); 2992 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 2993 "doorbell", LEN_DOORBELL); 2994 2995 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 2996 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 2997 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 2998 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 2999 3000 for (i = 0; i < xhci->numports; i++) { 3001 XHCIPort *port = &xhci->ports[i]; 3002 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3003 port->xhci = xhci; 3004 memory_region_init_io(&port->mem, &xhci_port_ops, port, 3005 port->name, 0x10); 3006 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3007 } 3008 3009 pci_register_bar(&xhci->pci_dev, 0, 3010 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3011 &xhci->mem); 3012 3013 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 3014 assert(ret >= 0); 3015 3016 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3017 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); 3018 } 3019 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3020 msix_init(&xhci->pci_dev, MAXINTRS, 3021 &xhci->mem, 0, OFF_MSIX_TABLE, 3022 &xhci->mem, 0, OFF_MSIX_PBA, 3023 0x90); 3024 } 3025 3026 return 0; 3027 } 3028 3029 static const VMStateDescription vmstate_xhci = { 3030 .name = "xhci", 3031 .unmigratable = 1, 3032 }; 3033 3034 static Property xhci_properties[] = { 3035 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3036 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3037 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3038 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3039 DEFINE_PROP_END_OF_LIST(), 3040 }; 3041 3042 static void xhci_class_init(ObjectClass *klass, void *data) 3043 { 3044 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3045 DeviceClass *dc = DEVICE_CLASS(klass); 3046 3047 dc->vmsd = &vmstate_xhci; 3048 dc->props = xhci_properties; 3049 dc->reset = xhci_reset; 3050 k->init = usb_xhci_initfn; 3051 k->vendor_id = PCI_VENDOR_ID_NEC; 3052 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3053 k->class_id = PCI_CLASS_SERIAL_USB; 3054 k->revision = 0x03; 3055 k->is_express = 1; 3056 } 3057 3058 static TypeInfo xhci_info = { 3059 .name = "nec-usb-xhci", 3060 .parent = TYPE_PCI_DEVICE, 3061 .instance_size = sizeof(XHCIState), 3062 .class_init = xhci_class_init, 3063 }; 3064 3065 static void xhci_register_types(void) 3066 { 3067 type_register_static(&xhci_info); 3068 } 3069 3070 type_init(xhci_register_types) 3071