1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool cancelled; 350 bool complete; 351 bool int_req; 352 unsigned int iso_pkts; 353 unsigned int slotid; 354 unsigned int epid; 355 unsigned int streamid; 356 bool in_xfer; 357 bool iso_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 XHCIStreamContext *sstreams; 377 }; 378 379 struct XHCIEPContext { 380 XHCIState *xhci; 381 unsigned int slotid; 382 unsigned int epid; 383 384 XHCIRing ring; 385 unsigned int next_xfer; 386 unsigned int comp_xfer; 387 XHCITransfer transfers[TD_QUEUE]; 388 XHCITransfer *retry; 389 EPType type; 390 dma_addr_t pctx; 391 unsigned int max_psize; 392 uint32_t state; 393 394 /* streams */ 395 unsigned int max_pstreams; 396 bool lsa; 397 unsigned int nr_pstreams; 398 XHCIStreamContext *pstreams; 399 400 /* iso xfer scheduling */ 401 unsigned int interval; 402 int64_t mfindex_last; 403 QEMUTimer *kick_timer; 404 }; 405 406 typedef struct XHCISlot { 407 bool enabled; 408 bool addressed; 409 dma_addr_t ctx; 410 USBPort *uport; 411 XHCIEPContext * eps[31]; 412 } XHCISlot; 413 414 typedef struct XHCIEvent { 415 TRBType type; 416 TRBCCode ccode; 417 uint64_t ptr; 418 uint32_t length; 419 uint32_t flags; 420 uint8_t slotid; 421 uint8_t epid; 422 } XHCIEvent; 423 424 typedef struct XHCIInterrupter { 425 uint32_t iman; 426 uint32_t imod; 427 uint32_t erstsz; 428 uint32_t erstba_low; 429 uint32_t erstba_high; 430 uint32_t erdp_low; 431 uint32_t erdp_high; 432 433 bool msix_used, er_pcs, er_full; 434 435 dma_addr_t er_start; 436 uint32_t er_size; 437 unsigned int er_ep_idx; 438 439 XHCIEvent ev_buffer[EV_QUEUE]; 440 unsigned int ev_buffer_put; 441 unsigned int ev_buffer_get; 442 443 } XHCIInterrupter; 444 445 struct XHCIState { 446 PCIDevice pci_dev; 447 USBBus bus; 448 qemu_irq irq; 449 MemoryRegion mem; 450 MemoryRegion mem_cap; 451 MemoryRegion mem_oper; 452 MemoryRegion mem_runtime; 453 MemoryRegion mem_doorbell; 454 455 /* properties */ 456 uint32_t numports_2; 457 uint32_t numports_3; 458 uint32_t numintrs; 459 uint32_t numslots; 460 uint32_t flags; 461 462 /* Operational Registers */ 463 uint32_t usbcmd; 464 uint32_t usbsts; 465 uint32_t dnctrl; 466 uint32_t crcr_low; 467 uint32_t crcr_high; 468 uint32_t dcbaap_low; 469 uint32_t dcbaap_high; 470 uint32_t config; 471 472 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 473 XHCIPort ports[MAXPORTS]; 474 XHCISlot slots[MAXSLOTS]; 475 uint32_t numports; 476 477 /* Runtime Registers */ 478 int64_t mfindex_start; 479 QEMUTimer *mfwrap_timer; 480 XHCIInterrupter intr[MAXINTRS]; 481 482 XHCIRing cmd_ring; 483 }; 484 485 typedef struct XHCIEvRingSeg { 486 uint32_t addr_low; 487 uint32_t addr_high; 488 uint32_t size; 489 uint32_t rsvd; 490 } XHCIEvRingSeg; 491 492 enum xhci_flags { 493 XHCI_FLAG_USE_MSI = 1, 494 XHCI_FLAG_USE_MSI_X, 495 }; 496 497 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 498 unsigned int epid, unsigned int streamid); 499 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 500 unsigned int epid); 501 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 502 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 503 504 static const char *TRBType_names[] = { 505 [TRB_RESERVED] = "TRB_RESERVED", 506 [TR_NORMAL] = "TR_NORMAL", 507 [TR_SETUP] = "TR_SETUP", 508 [TR_DATA] = "TR_DATA", 509 [TR_STATUS] = "TR_STATUS", 510 [TR_ISOCH] = "TR_ISOCH", 511 [TR_LINK] = "TR_LINK", 512 [TR_EVDATA] = "TR_EVDATA", 513 [TR_NOOP] = "TR_NOOP", 514 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 515 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 516 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 517 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 518 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 519 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 520 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 521 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 522 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 523 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 524 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 525 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 526 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 527 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 528 [CR_NOOP] = "CR_NOOP", 529 [ER_TRANSFER] = "ER_TRANSFER", 530 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 531 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 532 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 533 [ER_DOORBELL] = "ER_DOORBELL", 534 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 535 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 536 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 537 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 538 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 539 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 540 }; 541 542 static const char *TRBCCode_names[] = { 543 [CC_INVALID] = "CC_INVALID", 544 [CC_SUCCESS] = "CC_SUCCESS", 545 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 546 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 547 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 548 [CC_TRB_ERROR] = "CC_TRB_ERROR", 549 [CC_STALL_ERROR] = "CC_STALL_ERROR", 550 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 551 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 552 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 553 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 554 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 555 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 556 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 557 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 558 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 559 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 560 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 561 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 562 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 563 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 564 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 565 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 566 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 567 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 568 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 569 [CC_STOPPED] = "CC_STOPPED", 570 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 571 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 572 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 573 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 574 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 575 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 576 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 577 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 578 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 579 }; 580 581 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 582 { 583 if (index >= llen || list[index] == NULL) { 584 return "???"; 585 } 586 return list[index]; 587 } 588 589 static const char *trb_name(XHCITRB *trb) 590 { 591 return lookup_name(TRB_TYPE(*trb), TRBType_names, 592 ARRAY_SIZE(TRBType_names)); 593 } 594 595 static const char *event_name(XHCIEvent *event) 596 { 597 return lookup_name(event->ccode, TRBCCode_names, 598 ARRAY_SIZE(TRBCCode_names)); 599 } 600 601 static uint64_t xhci_mfindex_get(XHCIState *xhci) 602 { 603 int64_t now = qemu_get_clock_ns(vm_clock); 604 return (now - xhci->mfindex_start) / 125000; 605 } 606 607 static void xhci_mfwrap_update(XHCIState *xhci) 608 { 609 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 610 uint32_t mfindex, left; 611 int64_t now; 612 613 if ((xhci->usbcmd & bits) == bits) { 614 now = qemu_get_clock_ns(vm_clock); 615 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 616 left = 0x4000 - mfindex; 617 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 618 } else { 619 qemu_del_timer(xhci->mfwrap_timer); 620 } 621 } 622 623 static void xhci_mfwrap_timer(void *opaque) 624 { 625 XHCIState *xhci = opaque; 626 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 627 628 xhci_event(xhci, &wrap, 0); 629 xhci_mfwrap_update(xhci); 630 } 631 632 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 633 { 634 if (sizeof(dma_addr_t) == 4) { 635 return low; 636 } else { 637 return low | (((dma_addr_t)high << 16) << 16); 638 } 639 } 640 641 static inline dma_addr_t xhci_mask64(uint64_t addr) 642 { 643 if (sizeof(dma_addr_t) == 4) { 644 return addr & 0xffffffff; 645 } else { 646 return addr; 647 } 648 } 649 650 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 651 uint32_t *buf, size_t len) 652 { 653 int i; 654 655 assert((len % sizeof(uint32_t)) == 0); 656 657 pci_dma_read(&xhci->pci_dev, addr, buf, len); 658 659 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 660 buf[i] = le32_to_cpu(buf[i]); 661 } 662 } 663 664 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 665 uint32_t *buf, size_t len) 666 { 667 int i; 668 uint32_t tmp[len / sizeof(uint32_t)]; 669 670 assert((len % sizeof(uint32_t)) == 0); 671 672 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 673 tmp[i] = cpu_to_le32(buf[i]); 674 } 675 pci_dma_write(&xhci->pci_dev, addr, tmp, len); 676 } 677 678 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 679 { 680 int index; 681 682 if (!uport->dev) { 683 return NULL; 684 } 685 switch (uport->dev->speed) { 686 case USB_SPEED_LOW: 687 case USB_SPEED_FULL: 688 case USB_SPEED_HIGH: 689 index = uport->index; 690 break; 691 case USB_SPEED_SUPER: 692 index = uport->index + xhci->numports_2; 693 break; 694 default: 695 return NULL; 696 } 697 return &xhci->ports[index]; 698 } 699 700 static void xhci_intx_update(XHCIState *xhci) 701 { 702 int level = 0; 703 704 if (msix_enabled(&xhci->pci_dev) || 705 msi_enabled(&xhci->pci_dev)) { 706 return; 707 } 708 709 if (xhci->intr[0].iman & IMAN_IP && 710 xhci->intr[0].iman & IMAN_IE && 711 xhci->usbcmd & USBCMD_INTE) { 712 level = 1; 713 } 714 715 trace_usb_xhci_irq_intx(level); 716 qemu_set_irq(xhci->irq, level); 717 } 718 719 static void xhci_msix_update(XHCIState *xhci, int v) 720 { 721 bool enabled; 722 723 if (!msix_enabled(&xhci->pci_dev)) { 724 return; 725 } 726 727 enabled = xhci->intr[v].iman & IMAN_IE; 728 if (enabled == xhci->intr[v].msix_used) { 729 return; 730 } 731 732 if (enabled) { 733 trace_usb_xhci_irq_msix_use(v); 734 msix_vector_use(&xhci->pci_dev, v); 735 xhci->intr[v].msix_used = true; 736 } else { 737 trace_usb_xhci_irq_msix_unuse(v); 738 msix_vector_unuse(&xhci->pci_dev, v); 739 xhci->intr[v].msix_used = false; 740 } 741 } 742 743 static void xhci_intr_raise(XHCIState *xhci, int v) 744 { 745 xhci->intr[v].erdp_low |= ERDP_EHB; 746 xhci->intr[v].iman |= IMAN_IP; 747 xhci->usbsts |= USBSTS_EINT; 748 749 if (!(xhci->intr[v].iman & IMAN_IE)) { 750 return; 751 } 752 753 if (!(xhci->usbcmd & USBCMD_INTE)) { 754 return; 755 } 756 757 if (msix_enabled(&xhci->pci_dev)) { 758 trace_usb_xhci_irq_msix(v); 759 msix_notify(&xhci->pci_dev, v); 760 return; 761 } 762 763 if (msi_enabled(&xhci->pci_dev)) { 764 trace_usb_xhci_irq_msi(v); 765 msi_notify(&xhci->pci_dev, v); 766 return; 767 } 768 769 if (v == 0) { 770 trace_usb_xhci_irq_intx(1); 771 qemu_set_irq(xhci->irq, 1); 772 } 773 } 774 775 static inline int xhci_running(XHCIState *xhci) 776 { 777 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 778 } 779 780 static void xhci_die(XHCIState *xhci) 781 { 782 xhci->usbsts |= USBSTS_HCE; 783 fprintf(stderr, "xhci: asserted controller error\n"); 784 } 785 786 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 787 { 788 XHCIInterrupter *intr = &xhci->intr[v]; 789 XHCITRB ev_trb; 790 dma_addr_t addr; 791 792 ev_trb.parameter = cpu_to_le64(event->ptr); 793 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 794 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 795 event->flags | (event->type << TRB_TYPE_SHIFT); 796 if (intr->er_pcs) { 797 ev_trb.control |= TRB_C; 798 } 799 ev_trb.control = cpu_to_le32(ev_trb.control); 800 801 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 802 event_name(event), ev_trb.parameter, 803 ev_trb.status, ev_trb.control); 804 805 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 806 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 807 808 intr->er_ep_idx++; 809 if (intr->er_ep_idx >= intr->er_size) { 810 intr->er_ep_idx = 0; 811 intr->er_pcs = !intr->er_pcs; 812 } 813 } 814 815 static void xhci_events_update(XHCIState *xhci, int v) 816 { 817 XHCIInterrupter *intr = &xhci->intr[v]; 818 dma_addr_t erdp; 819 unsigned int dp_idx; 820 bool do_irq = 0; 821 822 if (xhci->usbsts & USBSTS_HCH) { 823 return; 824 } 825 826 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 827 if (erdp < intr->er_start || 828 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 829 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 830 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 831 v, intr->er_start, intr->er_size); 832 xhci_die(xhci); 833 return; 834 } 835 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 836 assert(dp_idx < intr->er_size); 837 838 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 839 * deadlocks when the ER is full. Hack it by holding off events until 840 * the driver decides to free at least half of the ring */ 841 if (intr->er_full) { 842 int er_free = dp_idx - intr->er_ep_idx; 843 if (er_free <= 0) { 844 er_free += intr->er_size; 845 } 846 if (er_free < (intr->er_size/2)) { 847 DPRINTF("xhci_events_update(): event ring still " 848 "more than half full (hack)\n"); 849 return; 850 } 851 } 852 853 while (intr->ev_buffer_put != intr->ev_buffer_get) { 854 assert(intr->er_full); 855 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 856 DPRINTF("xhci_events_update(): event ring full again\n"); 857 #ifndef ER_FULL_HACK 858 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 859 xhci_write_event(xhci, &full, v); 860 #endif 861 do_irq = 1; 862 break; 863 } 864 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 865 xhci_write_event(xhci, event, v); 866 intr->ev_buffer_get++; 867 do_irq = 1; 868 if (intr->ev_buffer_get == EV_QUEUE) { 869 intr->ev_buffer_get = 0; 870 } 871 } 872 873 if (do_irq) { 874 xhci_intr_raise(xhci, v); 875 } 876 877 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 878 DPRINTF("xhci_events_update(): event ring no longer full\n"); 879 intr->er_full = 0; 880 } 881 } 882 883 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 884 { 885 XHCIInterrupter *intr; 886 dma_addr_t erdp; 887 unsigned int dp_idx; 888 889 if (v >= xhci->numintrs) { 890 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 891 return; 892 } 893 intr = &xhci->intr[v]; 894 895 if (intr->er_full) { 896 DPRINTF("xhci_event(): ER full, queueing\n"); 897 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 898 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 899 return; 900 } 901 intr->ev_buffer[intr->ev_buffer_put++] = *event; 902 if (intr->ev_buffer_put == EV_QUEUE) { 903 intr->ev_buffer_put = 0; 904 } 905 return; 906 } 907 908 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 909 if (erdp < intr->er_start || 910 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 911 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 912 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 913 v, intr->er_start, intr->er_size); 914 xhci_die(xhci); 915 return; 916 } 917 918 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 919 assert(dp_idx < intr->er_size); 920 921 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 922 DPRINTF("xhci_event(): ER full, queueing\n"); 923 #ifndef ER_FULL_HACK 924 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 925 xhci_write_event(xhci, &full); 926 #endif 927 intr->er_full = 1; 928 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 929 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 930 return; 931 } 932 intr->ev_buffer[intr->ev_buffer_put++] = *event; 933 if (intr->ev_buffer_put == EV_QUEUE) { 934 intr->ev_buffer_put = 0; 935 } 936 } else { 937 xhci_write_event(xhci, event, v); 938 } 939 940 xhci_intr_raise(xhci, v); 941 } 942 943 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 944 dma_addr_t base) 945 { 946 ring->dequeue = base; 947 ring->ccs = 1; 948 } 949 950 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 951 dma_addr_t *addr) 952 { 953 while (1) { 954 TRBType type; 955 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 956 trb->addr = ring->dequeue; 957 trb->ccs = ring->ccs; 958 le64_to_cpus(&trb->parameter); 959 le32_to_cpus(&trb->status); 960 le32_to_cpus(&trb->control); 961 962 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 963 trb->parameter, trb->status, trb->control); 964 965 if ((trb->control & TRB_C) != ring->ccs) { 966 return 0; 967 } 968 969 type = TRB_TYPE(*trb); 970 971 if (type != TR_LINK) { 972 if (addr) { 973 *addr = ring->dequeue; 974 } 975 ring->dequeue += TRB_SIZE; 976 return type; 977 } else { 978 ring->dequeue = xhci_mask64(trb->parameter); 979 if (trb->control & TRB_LK_TC) { 980 ring->ccs = !ring->ccs; 981 } 982 } 983 } 984 } 985 986 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 987 { 988 XHCITRB trb; 989 int length = 0; 990 dma_addr_t dequeue = ring->dequeue; 991 bool ccs = ring->ccs; 992 /* hack to bundle together the two/three TDs that make a setup transfer */ 993 bool control_td_set = 0; 994 995 while (1) { 996 TRBType type; 997 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 998 le64_to_cpus(&trb.parameter); 999 le32_to_cpus(&trb.status); 1000 le32_to_cpus(&trb.control); 1001 1002 if ((trb.control & TRB_C) != ccs) { 1003 return -length; 1004 } 1005 1006 type = TRB_TYPE(trb); 1007 1008 if (type == TR_LINK) { 1009 dequeue = xhci_mask64(trb.parameter); 1010 if (trb.control & TRB_LK_TC) { 1011 ccs = !ccs; 1012 } 1013 continue; 1014 } 1015 1016 length += 1; 1017 dequeue += TRB_SIZE; 1018 1019 if (type == TR_SETUP) { 1020 control_td_set = 1; 1021 } else if (type == TR_STATUS) { 1022 control_td_set = 0; 1023 } 1024 1025 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1026 return length; 1027 } 1028 } 1029 } 1030 1031 static void xhci_er_reset(XHCIState *xhci, int v) 1032 { 1033 XHCIInterrupter *intr = &xhci->intr[v]; 1034 XHCIEvRingSeg seg; 1035 1036 if (intr->erstsz == 0) { 1037 /* disabled */ 1038 intr->er_start = 0; 1039 intr->er_size = 0; 1040 return; 1041 } 1042 /* cache the (sole) event ring segment location */ 1043 if (intr->erstsz != 1) { 1044 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1045 xhci_die(xhci); 1046 return; 1047 } 1048 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1049 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 1050 le32_to_cpus(&seg.addr_low); 1051 le32_to_cpus(&seg.addr_high); 1052 le32_to_cpus(&seg.size); 1053 if (seg.size < 16 || seg.size > 4096) { 1054 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1055 xhci_die(xhci); 1056 return; 1057 } 1058 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1059 intr->er_size = seg.size; 1060 1061 intr->er_ep_idx = 0; 1062 intr->er_pcs = 1; 1063 intr->er_full = 0; 1064 1065 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1066 v, intr->er_start, intr->er_size); 1067 } 1068 1069 static void xhci_run(XHCIState *xhci) 1070 { 1071 trace_usb_xhci_run(); 1072 xhci->usbsts &= ~USBSTS_HCH; 1073 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1074 } 1075 1076 static void xhci_stop(XHCIState *xhci) 1077 { 1078 trace_usb_xhci_stop(); 1079 xhci->usbsts |= USBSTS_HCH; 1080 xhci->crcr_low &= ~CRCR_CRR; 1081 } 1082 1083 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1084 dma_addr_t base) 1085 { 1086 XHCIStreamContext *stctx; 1087 unsigned int i; 1088 1089 stctx = g_new0(XHCIStreamContext, count); 1090 for (i = 0; i < count; i++) { 1091 stctx[i].pctx = base + i * 16; 1092 stctx[i].sct = -1; 1093 } 1094 return stctx; 1095 } 1096 1097 static void xhci_reset_streams(XHCIEPContext *epctx) 1098 { 1099 unsigned int i; 1100 1101 for (i = 0; i < epctx->nr_pstreams; i++) { 1102 epctx->pstreams[i].sct = -1; 1103 g_free(epctx->pstreams[i].sstreams); 1104 } 1105 } 1106 1107 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1108 { 1109 assert(epctx->pstreams == NULL); 1110 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1111 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1112 } 1113 1114 static void xhci_free_streams(XHCIEPContext *epctx) 1115 { 1116 int i; 1117 1118 assert(epctx->pstreams != NULL); 1119 1120 if (!epctx->lsa) { 1121 for (i = 0; i < epctx->nr_pstreams; i++) { 1122 g_free(epctx->pstreams[i].sstreams); 1123 } 1124 } 1125 g_free(epctx->pstreams); 1126 epctx->pstreams = NULL; 1127 epctx->nr_pstreams = 0; 1128 } 1129 1130 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1131 unsigned int streamid, 1132 uint32_t *cc_error) 1133 { 1134 XHCIStreamContext *sctx; 1135 dma_addr_t base; 1136 uint32_t ctx[2], sct; 1137 1138 assert(streamid != 0); 1139 if (epctx->lsa) { 1140 if (streamid >= epctx->nr_pstreams) { 1141 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1142 return NULL; 1143 } 1144 sctx = epctx->pstreams + streamid; 1145 } else { 1146 FIXME("secondary streams not implemented yet"); 1147 } 1148 1149 if (sctx->sct == -1) { 1150 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1151 fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n", 1152 __func__, streamid, sctx->pctx, ctx[0], ctx[1]); 1153 sct = (ctx[0] >> 1) & 0x07; 1154 if (epctx->lsa && sct != 1) { 1155 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1156 return NULL; 1157 } 1158 sctx->sct = sct; 1159 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1160 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1161 } 1162 return sctx; 1163 } 1164 1165 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1166 XHCIStreamContext *sctx, uint32_t state) 1167 { 1168 uint32_t ctx[5]; 1169 uint32_t ctx2[2]; 1170 1171 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1172 ctx[0] &= ~EP_STATE_MASK; 1173 ctx[0] |= state; 1174 1175 /* update ring dequeue ptr */ 1176 if (epctx->nr_pstreams) { 1177 if (sctx != NULL) { 1178 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1179 ctx2[0] &= 0xe; 1180 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1181 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1182 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1183 } 1184 } else { 1185 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1186 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1187 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1188 epctx->pctx, state, ctx[3], ctx[2]); 1189 } 1190 1191 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1192 epctx->state = state; 1193 } 1194 1195 static void xhci_ep_kick_timer(void *opaque) 1196 { 1197 XHCIEPContext *epctx = opaque; 1198 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1199 } 1200 1201 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1202 unsigned int slotid, 1203 unsigned int epid) 1204 { 1205 XHCIEPContext *epctx; 1206 int i; 1207 1208 epctx = g_new0(XHCIEPContext, 1); 1209 epctx->xhci = xhci; 1210 epctx->slotid = slotid; 1211 epctx->epid = epid; 1212 1213 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1214 usb_packet_init(&epctx->transfers[i].packet); 1215 } 1216 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1217 1218 return epctx; 1219 } 1220 1221 static void xhci_init_epctx(XHCIEPContext *epctx, 1222 dma_addr_t pctx, uint32_t *ctx) 1223 { 1224 dma_addr_t dequeue; 1225 1226 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1227 1228 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1229 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1230 epctx->pctx = pctx; 1231 epctx->max_psize = ctx[1]>>16; 1232 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1233 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1234 epctx->lsa = (ctx[0] >> 15) & 1; 1235 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1236 epid/2, epid%2, epctx->max_psize); 1237 if (epctx->max_pstreams) { 1238 xhci_alloc_streams(epctx, dequeue); 1239 } else { 1240 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1241 epctx->ring.ccs = ctx[2] & 1; 1242 } 1243 1244 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1245 } 1246 1247 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1248 unsigned int epid, dma_addr_t pctx, 1249 uint32_t *ctx) 1250 { 1251 XHCISlot *slot; 1252 XHCIEPContext *epctx; 1253 1254 trace_usb_xhci_ep_enable(slotid, epid); 1255 assert(slotid >= 1 && slotid <= xhci->numslots); 1256 assert(epid >= 1 && epid <= 31); 1257 1258 slot = &xhci->slots[slotid-1]; 1259 if (slot->eps[epid-1]) { 1260 xhci_disable_ep(xhci, slotid, epid); 1261 } 1262 1263 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1264 slot->eps[epid-1] = epctx; 1265 xhci_init_epctx(epctx, pctx, ctx); 1266 1267 epctx->mfindex_last = 0; 1268 1269 epctx->state = EP_RUNNING; 1270 ctx[0] &= ~EP_STATE_MASK; 1271 ctx[0] |= EP_RUNNING; 1272 1273 return CC_SUCCESS; 1274 } 1275 1276 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1277 { 1278 int killed = 0; 1279 1280 if (t->running_async) { 1281 usb_cancel_packet(&t->packet); 1282 t->running_async = 0; 1283 t->cancelled = 1; 1284 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1285 killed = 1; 1286 } 1287 if (t->running_retry) { 1288 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1289 if (epctx) { 1290 epctx->retry = NULL; 1291 qemu_del_timer(epctx->kick_timer); 1292 } 1293 t->running_retry = 0; 1294 } 1295 if (t->trbs) { 1296 g_free(t->trbs); 1297 } 1298 1299 t->trbs = NULL; 1300 t->trb_count = t->trb_alloced = 0; 1301 1302 return killed; 1303 } 1304 1305 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1306 unsigned int epid) 1307 { 1308 XHCISlot *slot; 1309 XHCIEPContext *epctx; 1310 int i, xferi, killed = 0; 1311 USBEndpoint *ep = NULL; 1312 assert(slotid >= 1 && slotid <= xhci->numslots); 1313 assert(epid >= 1 && epid <= 31); 1314 1315 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1316 1317 slot = &xhci->slots[slotid-1]; 1318 1319 if (!slot->eps[epid-1]) { 1320 return 0; 1321 } 1322 1323 epctx = slot->eps[epid-1]; 1324 1325 xferi = epctx->next_xfer; 1326 for (i = 0; i < TD_QUEUE; i++) { 1327 if (epctx->transfers[xferi].packet.ep) { 1328 ep = epctx->transfers[xferi].packet.ep; 1329 } 1330 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1331 epctx->transfers[xferi].packet.ep = NULL; 1332 xferi = (xferi + 1) % TD_QUEUE; 1333 } 1334 if (ep) { 1335 usb_device_ep_stopped(ep->dev, ep); 1336 } 1337 return killed; 1338 } 1339 1340 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1341 unsigned int epid) 1342 { 1343 XHCISlot *slot; 1344 XHCIEPContext *epctx; 1345 1346 trace_usb_xhci_ep_disable(slotid, epid); 1347 assert(slotid >= 1 && slotid <= xhci->numslots); 1348 assert(epid >= 1 && epid <= 31); 1349 1350 slot = &xhci->slots[slotid-1]; 1351 1352 if (!slot->eps[epid-1]) { 1353 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1354 return CC_SUCCESS; 1355 } 1356 1357 xhci_ep_nuke_xfers(xhci, slotid, epid); 1358 1359 epctx = slot->eps[epid-1]; 1360 1361 if (epctx->nr_pstreams) { 1362 xhci_free_streams(epctx); 1363 } 1364 1365 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1366 1367 qemu_free_timer(epctx->kick_timer); 1368 g_free(epctx); 1369 slot->eps[epid-1] = NULL; 1370 1371 return CC_SUCCESS; 1372 } 1373 1374 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1375 unsigned int epid) 1376 { 1377 XHCISlot *slot; 1378 XHCIEPContext *epctx; 1379 1380 trace_usb_xhci_ep_stop(slotid, epid); 1381 assert(slotid >= 1 && slotid <= xhci->numslots); 1382 1383 if (epid < 1 || epid > 31) { 1384 fprintf(stderr, "xhci: bad ep %d\n", epid); 1385 return CC_TRB_ERROR; 1386 } 1387 1388 slot = &xhci->slots[slotid-1]; 1389 1390 if (!slot->eps[epid-1]) { 1391 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1392 return CC_EP_NOT_ENABLED_ERROR; 1393 } 1394 1395 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1396 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1397 "data might be lost\n"); 1398 } 1399 1400 epctx = slot->eps[epid-1]; 1401 1402 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1403 1404 if (epctx->nr_pstreams) { 1405 xhci_reset_streams(epctx); 1406 } 1407 1408 return CC_SUCCESS; 1409 } 1410 1411 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1412 unsigned int epid) 1413 { 1414 XHCISlot *slot; 1415 XHCIEPContext *epctx; 1416 USBDevice *dev; 1417 1418 trace_usb_xhci_ep_reset(slotid, epid); 1419 assert(slotid >= 1 && slotid <= xhci->numslots); 1420 1421 if (epid < 1 || epid > 31) { 1422 fprintf(stderr, "xhci: bad ep %d\n", epid); 1423 return CC_TRB_ERROR; 1424 } 1425 1426 slot = &xhci->slots[slotid-1]; 1427 1428 if (!slot->eps[epid-1]) { 1429 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1430 return CC_EP_NOT_ENABLED_ERROR; 1431 } 1432 1433 epctx = slot->eps[epid-1]; 1434 1435 if (epctx->state != EP_HALTED) { 1436 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1437 epid, epctx->state); 1438 return CC_CONTEXT_STATE_ERROR; 1439 } 1440 1441 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1442 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1443 "data might be lost\n"); 1444 } 1445 1446 uint8_t ep = epid>>1; 1447 1448 if (epid & 1) { 1449 ep |= 0x80; 1450 } 1451 1452 dev = xhci->slots[slotid-1].uport->dev; 1453 if (!dev) { 1454 return CC_USB_TRANSACTION_ERROR; 1455 } 1456 1457 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1458 1459 if (epctx->nr_pstreams) { 1460 xhci_reset_streams(epctx); 1461 } 1462 1463 return CC_SUCCESS; 1464 } 1465 1466 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1467 unsigned int epid, unsigned int streamid, 1468 uint64_t pdequeue) 1469 { 1470 XHCISlot *slot; 1471 XHCIEPContext *epctx; 1472 XHCIStreamContext *sctx; 1473 dma_addr_t dequeue; 1474 1475 assert(slotid >= 1 && slotid <= xhci->numslots); 1476 1477 if (epid < 1 || epid > 31) { 1478 fprintf(stderr, "xhci: bad ep %d\n", epid); 1479 return CC_TRB_ERROR; 1480 } 1481 1482 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1483 dequeue = xhci_mask64(pdequeue); 1484 1485 slot = &xhci->slots[slotid-1]; 1486 1487 if (!slot->eps[epid-1]) { 1488 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1489 return CC_EP_NOT_ENABLED_ERROR; 1490 } 1491 1492 epctx = slot->eps[epid-1]; 1493 1494 if (epctx->state != EP_STOPPED) { 1495 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1496 return CC_CONTEXT_STATE_ERROR; 1497 } 1498 1499 if (epctx->nr_pstreams) { 1500 uint32_t err; 1501 sctx = xhci_find_stream(epctx, streamid, &err); 1502 if (sctx == NULL) { 1503 return err; 1504 } 1505 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1506 sctx->ring.ccs = dequeue & 1; 1507 } else { 1508 sctx = NULL; 1509 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1510 epctx->ring.ccs = dequeue & 1; 1511 } 1512 1513 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1514 1515 return CC_SUCCESS; 1516 } 1517 1518 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1519 { 1520 XHCIState *xhci = xfer->xhci; 1521 int i; 1522 1523 xfer->int_req = false; 1524 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1525 for (i = 0; i < xfer->trb_count; i++) { 1526 XHCITRB *trb = &xfer->trbs[i]; 1527 dma_addr_t addr; 1528 unsigned int chunk = 0; 1529 1530 if (trb->control & TRB_TR_IOC) { 1531 xfer->int_req = true; 1532 } 1533 1534 switch (TRB_TYPE(*trb)) { 1535 case TR_DATA: 1536 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1537 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1538 goto err; 1539 } 1540 /* fallthrough */ 1541 case TR_NORMAL: 1542 case TR_ISOCH: 1543 addr = xhci_mask64(trb->parameter); 1544 chunk = trb->status & 0x1ffff; 1545 if (trb->control & TRB_TR_IDT) { 1546 if (chunk > 8 || in_xfer) { 1547 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1548 goto err; 1549 } 1550 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1551 } else { 1552 qemu_sglist_add(&xfer->sgl, addr, chunk); 1553 } 1554 break; 1555 } 1556 } 1557 1558 return 0; 1559 1560 err: 1561 qemu_sglist_destroy(&xfer->sgl); 1562 xhci_die(xhci); 1563 return -1; 1564 } 1565 1566 static void xhci_xfer_unmap(XHCITransfer *xfer) 1567 { 1568 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1569 qemu_sglist_destroy(&xfer->sgl); 1570 } 1571 1572 static void xhci_xfer_report(XHCITransfer *xfer) 1573 { 1574 uint32_t edtla = 0; 1575 unsigned int left; 1576 bool reported = 0; 1577 bool shortpkt = 0; 1578 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1579 XHCIState *xhci = xfer->xhci; 1580 int i; 1581 1582 left = xfer->packet.actual_length; 1583 1584 for (i = 0; i < xfer->trb_count; i++) { 1585 XHCITRB *trb = &xfer->trbs[i]; 1586 unsigned int chunk = 0; 1587 1588 switch (TRB_TYPE(*trb)) { 1589 case TR_DATA: 1590 case TR_NORMAL: 1591 case TR_ISOCH: 1592 chunk = trb->status & 0x1ffff; 1593 if (chunk > left) { 1594 chunk = left; 1595 if (xfer->status == CC_SUCCESS) { 1596 shortpkt = 1; 1597 } 1598 } 1599 left -= chunk; 1600 edtla += chunk; 1601 break; 1602 case TR_STATUS: 1603 reported = 0; 1604 shortpkt = 0; 1605 break; 1606 } 1607 1608 if (!reported && ((trb->control & TRB_TR_IOC) || 1609 (shortpkt && (trb->control & TRB_TR_ISP)) || 1610 (xfer->status != CC_SUCCESS && left == 0))) { 1611 event.slotid = xfer->slotid; 1612 event.epid = xfer->epid; 1613 event.length = (trb->status & 0x1ffff) - chunk; 1614 event.flags = 0; 1615 event.ptr = trb->addr; 1616 if (xfer->status == CC_SUCCESS) { 1617 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1618 } else { 1619 event.ccode = xfer->status; 1620 } 1621 if (TRB_TYPE(*trb) == TR_EVDATA) { 1622 event.ptr = trb->parameter; 1623 event.flags |= TRB_EV_ED; 1624 event.length = edtla & 0xffffff; 1625 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1626 edtla = 0; 1627 } 1628 xhci_event(xhci, &event, TRB_INTR(*trb)); 1629 reported = 1; 1630 if (xfer->status != CC_SUCCESS) { 1631 return; 1632 } 1633 } 1634 } 1635 } 1636 1637 static void xhci_stall_ep(XHCITransfer *xfer) 1638 { 1639 XHCIState *xhci = xfer->xhci; 1640 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1641 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1642 uint32_t err; 1643 XHCIStreamContext *sctx; 1644 1645 if (epctx->nr_pstreams) { 1646 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1647 if (sctx == NULL) { 1648 return; 1649 } 1650 sctx->ring.dequeue = xfer->trbs[0].addr; 1651 sctx->ring.ccs = xfer->trbs[0].ccs; 1652 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1653 } else { 1654 epctx->ring.dequeue = xfer->trbs[0].addr; 1655 epctx->ring.ccs = xfer->trbs[0].ccs; 1656 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1657 } 1658 } 1659 1660 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1661 XHCIEPContext *epctx); 1662 1663 static int xhci_setup_packet(XHCITransfer *xfer) 1664 { 1665 XHCIState *xhci = xfer->xhci; 1666 USBDevice *dev; 1667 USBEndpoint *ep; 1668 int dir; 1669 1670 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1671 1672 if (xfer->packet.ep) { 1673 ep = xfer->packet.ep; 1674 dev = ep->dev; 1675 } else { 1676 if (!xhci->slots[xfer->slotid-1].uport) { 1677 fprintf(stderr, "xhci: slot %d has no device\n", 1678 xfer->slotid); 1679 return -1; 1680 } 1681 dev = xhci->slots[xfer->slotid-1].uport->dev; 1682 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1683 } 1684 1685 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1686 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1687 xfer->trbs[0].addr, false, xfer->int_req); 1688 usb_packet_map(&xfer->packet, &xfer->sgl); 1689 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1690 xfer->packet.pid, dev->addr, ep->nr); 1691 return 0; 1692 } 1693 1694 static int xhci_complete_packet(XHCITransfer *xfer) 1695 { 1696 if (xfer->packet.status == USB_RET_ASYNC) { 1697 trace_usb_xhci_xfer_async(xfer); 1698 xfer->running_async = 1; 1699 xfer->running_retry = 0; 1700 xfer->complete = 0; 1701 xfer->cancelled = 0; 1702 return 0; 1703 } else if (xfer->packet.status == USB_RET_NAK) { 1704 trace_usb_xhci_xfer_nak(xfer); 1705 xfer->running_async = 0; 1706 xfer->running_retry = 1; 1707 xfer->complete = 0; 1708 xfer->cancelled = 0; 1709 return 0; 1710 } else { 1711 xfer->running_async = 0; 1712 xfer->running_retry = 0; 1713 xfer->complete = 1; 1714 xhci_xfer_unmap(xfer); 1715 } 1716 1717 if (xfer->packet.status == USB_RET_SUCCESS) { 1718 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1719 xfer->status = CC_SUCCESS; 1720 xhci_xfer_report(xfer); 1721 return 0; 1722 } 1723 1724 /* error */ 1725 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1726 switch (xfer->packet.status) { 1727 case USB_RET_NODEV: 1728 xfer->status = CC_USB_TRANSACTION_ERROR; 1729 xhci_xfer_report(xfer); 1730 xhci_stall_ep(xfer); 1731 break; 1732 case USB_RET_STALL: 1733 xfer->status = CC_STALL_ERROR; 1734 xhci_xfer_report(xfer); 1735 xhci_stall_ep(xfer); 1736 break; 1737 case USB_RET_BABBLE: 1738 xfer->status = CC_BABBLE_DETECTED; 1739 xhci_xfer_report(xfer); 1740 xhci_stall_ep(xfer); 1741 break; 1742 default: 1743 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1744 xfer->packet.status); 1745 FIXME("unhandled USB_RET_*"); 1746 } 1747 return 0; 1748 } 1749 1750 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1751 { 1752 XHCITRB *trb_setup, *trb_status; 1753 uint8_t bmRequestType; 1754 1755 trb_setup = &xfer->trbs[0]; 1756 trb_status = &xfer->trbs[xfer->trb_count-1]; 1757 1758 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1759 1760 /* at most one Event Data TRB allowed after STATUS */ 1761 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1762 trb_status--; 1763 } 1764 1765 /* do some sanity checks */ 1766 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1767 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1768 TRB_TYPE(*trb_setup)); 1769 return -1; 1770 } 1771 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1772 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1773 TRB_TYPE(*trb_status)); 1774 return -1; 1775 } 1776 if (!(trb_setup->control & TRB_TR_IDT)) { 1777 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1778 return -1; 1779 } 1780 if ((trb_setup->status & 0x1ffff) != 8) { 1781 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1782 (trb_setup->status & 0x1ffff)); 1783 return -1; 1784 } 1785 1786 bmRequestType = trb_setup->parameter; 1787 1788 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1789 xfer->iso_xfer = false; 1790 1791 if (xhci_setup_packet(xfer) < 0) { 1792 return -1; 1793 } 1794 xfer->packet.parameter = trb_setup->parameter; 1795 1796 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1797 1798 xhci_complete_packet(xfer); 1799 if (!xfer->running_async && !xfer->running_retry) { 1800 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1801 } 1802 return 0; 1803 } 1804 1805 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1806 XHCIEPContext *epctx, uint64_t mfindex) 1807 { 1808 if (xfer->trbs[0].control & TRB_TR_SIA) { 1809 uint64_t asap = ((mfindex + epctx->interval - 1) & 1810 ~(epctx->interval-1)); 1811 if (asap >= epctx->mfindex_last && 1812 asap <= epctx->mfindex_last + epctx->interval * 4) { 1813 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1814 } else { 1815 xfer->mfindex_kick = asap; 1816 } 1817 } else { 1818 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1819 & TRB_TR_FRAMEID_MASK; 1820 xfer->mfindex_kick |= mfindex & ~0x3fff; 1821 if (xfer->mfindex_kick < mfindex) { 1822 xfer->mfindex_kick += 0x4000; 1823 } 1824 } 1825 } 1826 1827 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1828 XHCIEPContext *epctx, uint64_t mfindex) 1829 { 1830 if (xfer->mfindex_kick > mfindex) { 1831 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1832 (xfer->mfindex_kick - mfindex) * 125000); 1833 xfer->running_retry = 1; 1834 } else { 1835 epctx->mfindex_last = xfer->mfindex_kick; 1836 qemu_del_timer(epctx->kick_timer); 1837 xfer->running_retry = 0; 1838 } 1839 } 1840 1841 1842 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1843 { 1844 uint64_t mfindex; 1845 1846 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1847 1848 xfer->in_xfer = epctx->type>>2; 1849 1850 switch(epctx->type) { 1851 case ET_INTR_OUT: 1852 case ET_INTR_IN: 1853 case ET_BULK_OUT: 1854 case ET_BULK_IN: 1855 xfer->pkts = 0; 1856 xfer->iso_xfer = false; 1857 break; 1858 case ET_ISO_OUT: 1859 case ET_ISO_IN: 1860 xfer->pkts = 1; 1861 xfer->iso_xfer = true; 1862 mfindex = xhci_mfindex_get(xhci); 1863 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1864 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1865 if (xfer->running_retry) { 1866 return -1; 1867 } 1868 break; 1869 default: 1870 fprintf(stderr, "xhci: unknown or unhandled EP " 1871 "(type %d, in %d, ep %02x)\n", 1872 epctx->type, xfer->in_xfer, xfer->epid); 1873 return -1; 1874 } 1875 1876 if (xhci_setup_packet(xfer) < 0) { 1877 return -1; 1878 } 1879 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1880 1881 xhci_complete_packet(xfer); 1882 if (!xfer->running_async && !xfer->running_retry) { 1883 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1884 } 1885 return 0; 1886 } 1887 1888 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1889 { 1890 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1891 return xhci_submit(xhci, xfer, epctx); 1892 } 1893 1894 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1895 unsigned int epid, unsigned int streamid) 1896 { 1897 XHCIStreamContext *stctx; 1898 XHCIEPContext *epctx; 1899 XHCIRing *ring; 1900 USBEndpoint *ep = NULL; 1901 uint64_t mfindex; 1902 int length; 1903 int i; 1904 1905 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1906 assert(slotid >= 1 && slotid <= xhci->numslots); 1907 assert(epid >= 1 && epid <= 31); 1908 1909 if (!xhci->slots[slotid-1].enabled) { 1910 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1911 return; 1912 } 1913 epctx = xhci->slots[slotid-1].eps[epid-1]; 1914 if (!epctx) { 1915 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1916 epid, slotid); 1917 return; 1918 } 1919 1920 if (epctx->retry) { 1921 XHCITransfer *xfer = epctx->retry; 1922 1923 trace_usb_xhci_xfer_retry(xfer); 1924 assert(xfer->running_retry); 1925 if (xfer->iso_xfer) { 1926 /* retry delayed iso transfer */ 1927 mfindex = xhci_mfindex_get(xhci); 1928 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1929 if (xfer->running_retry) { 1930 return; 1931 } 1932 if (xhci_setup_packet(xfer) < 0) { 1933 return; 1934 } 1935 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1936 assert(xfer->packet.status != USB_RET_NAK); 1937 xhci_complete_packet(xfer); 1938 } else { 1939 /* retry nak'ed transfer */ 1940 if (xhci_setup_packet(xfer) < 0) { 1941 return; 1942 } 1943 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1944 if (xfer->packet.status == USB_RET_NAK) { 1945 return; 1946 } 1947 xhci_complete_packet(xfer); 1948 } 1949 assert(!xfer->running_retry); 1950 epctx->retry = NULL; 1951 } 1952 1953 if (epctx->state == EP_HALTED) { 1954 DPRINTF("xhci: ep halted, not running schedule\n"); 1955 return; 1956 } 1957 1958 1959 if (epctx->nr_pstreams) { 1960 uint32_t err; 1961 stctx = xhci_find_stream(epctx, streamid, &err); 1962 if (stctx == NULL) { 1963 return; 1964 } 1965 ring = &stctx->ring; 1966 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 1967 } else { 1968 ring = &epctx->ring; 1969 streamid = 0; 1970 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 1971 } 1972 assert(ring->dequeue != 0); 1973 1974 while (1) { 1975 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1976 if (xfer->running_async || xfer->running_retry) { 1977 break; 1978 } 1979 length = xhci_ring_chain_length(xhci, ring); 1980 if (length < 0) { 1981 break; 1982 } else if (length == 0) { 1983 break; 1984 } 1985 if (xfer->trbs && xfer->trb_alloced < length) { 1986 xfer->trb_count = 0; 1987 xfer->trb_alloced = 0; 1988 g_free(xfer->trbs); 1989 xfer->trbs = NULL; 1990 } 1991 if (!xfer->trbs) { 1992 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1993 xfer->trb_alloced = length; 1994 } 1995 xfer->trb_count = length; 1996 1997 for (i = 0; i < length; i++) { 1998 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 1999 } 2000 xfer->xhci = xhci; 2001 xfer->epid = epid; 2002 xfer->slotid = slotid; 2003 xfer->streamid = streamid; 2004 2005 if (epid == 1) { 2006 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2007 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2008 ep = xfer->packet.ep; 2009 } else { 2010 fprintf(stderr, "xhci: error firing CTL transfer\n"); 2011 } 2012 } else { 2013 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2014 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2015 ep = xfer->packet.ep; 2016 } else { 2017 if (!xfer->iso_xfer) { 2018 fprintf(stderr, "xhci: error firing data transfer\n"); 2019 } 2020 } 2021 } 2022 2023 if (epctx->state == EP_HALTED) { 2024 break; 2025 } 2026 if (xfer->running_retry) { 2027 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2028 epctx->retry = xfer; 2029 break; 2030 } 2031 } 2032 if (ep) { 2033 usb_device_flush_ep_queue(ep->dev, ep); 2034 } 2035 } 2036 2037 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2038 { 2039 trace_usb_xhci_slot_enable(slotid); 2040 assert(slotid >= 1 && slotid <= xhci->numslots); 2041 xhci->slots[slotid-1].enabled = 1; 2042 xhci->slots[slotid-1].uport = NULL; 2043 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2044 2045 return CC_SUCCESS; 2046 } 2047 2048 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2049 { 2050 int i; 2051 2052 trace_usb_xhci_slot_disable(slotid); 2053 assert(slotid >= 1 && slotid <= xhci->numslots); 2054 2055 for (i = 1; i <= 31; i++) { 2056 if (xhci->slots[slotid-1].eps[i-1]) { 2057 xhci_disable_ep(xhci, slotid, i); 2058 } 2059 } 2060 2061 xhci->slots[slotid-1].enabled = 0; 2062 xhci->slots[slotid-1].addressed = 0; 2063 return CC_SUCCESS; 2064 } 2065 2066 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2067 { 2068 USBPort *uport; 2069 char path[32]; 2070 int i, pos, port; 2071 2072 port = (slot_ctx[1]>>16) & 0xFF; 2073 port = xhci->ports[port-1].uport->index+1; 2074 pos = snprintf(path, sizeof(path), "%d", port); 2075 for (i = 0; i < 5; i++) { 2076 port = (slot_ctx[0] >> 4*i) & 0x0f; 2077 if (!port) { 2078 break; 2079 } 2080 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2081 } 2082 2083 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2084 if (strcmp(uport->path, path) == 0) { 2085 return uport; 2086 } 2087 } 2088 return NULL; 2089 } 2090 2091 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2092 uint64_t pictx, bool bsr) 2093 { 2094 XHCISlot *slot; 2095 USBPort *uport; 2096 USBDevice *dev; 2097 dma_addr_t ictx, octx, dcbaap; 2098 uint64_t poctx; 2099 uint32_t ictl_ctx[2]; 2100 uint32_t slot_ctx[4]; 2101 uint32_t ep0_ctx[5]; 2102 int i; 2103 TRBCCode res; 2104 2105 trace_usb_xhci_slot_address(slotid); 2106 assert(slotid >= 1 && slotid <= xhci->numslots); 2107 2108 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2109 poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid); 2110 ictx = xhci_mask64(pictx); 2111 octx = xhci_mask64(poctx); 2112 2113 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2114 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2115 2116 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2117 2118 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2119 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2120 ictl_ctx[0], ictl_ctx[1]); 2121 return CC_TRB_ERROR; 2122 } 2123 2124 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2125 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2126 2127 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2128 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2129 2130 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2131 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2132 2133 uport = xhci_lookup_uport(xhci, slot_ctx); 2134 if (uport == NULL) { 2135 fprintf(stderr, "xhci: port not found\n"); 2136 return CC_TRB_ERROR; 2137 } 2138 2139 dev = uport->dev; 2140 if (!dev) { 2141 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2142 return CC_USB_TRANSACTION_ERROR; 2143 } 2144 2145 for (i = 0; i < xhci->numslots; i++) { 2146 if (i == slotid-1) { 2147 continue; 2148 } 2149 if (xhci->slots[i].uport == uport) { 2150 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2151 uport->path, i+1); 2152 return CC_TRB_ERROR; 2153 } 2154 } 2155 2156 slot = &xhci->slots[slotid-1]; 2157 slot->uport = uport; 2158 slot->ctx = octx; 2159 2160 if (bsr) { 2161 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2162 } else { 2163 USBPacket p; 2164 uint8_t buf[1]; 2165 2166 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2167 usb_device_reset(dev); 2168 memset(&p, 0, sizeof(p)); 2169 usb_packet_addbuf(&p, buf, sizeof(buf)); 2170 usb_packet_setup(&p, USB_TOKEN_OUT, 2171 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2172 0, false, false); 2173 usb_device_handle_control(dev, &p, 2174 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2175 slotid, 0, 0, NULL); 2176 assert(p.status != USB_RET_ASYNC); 2177 } 2178 2179 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2180 2181 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2182 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2183 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2184 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2185 2186 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2187 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2188 2189 xhci->slots[slotid-1].addressed = 1; 2190 return res; 2191 } 2192 2193 2194 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2195 uint64_t pictx, bool dc) 2196 { 2197 dma_addr_t ictx, octx; 2198 uint32_t ictl_ctx[2]; 2199 uint32_t slot_ctx[4]; 2200 uint32_t islot_ctx[4]; 2201 uint32_t ep_ctx[5]; 2202 int i; 2203 TRBCCode res; 2204 2205 trace_usb_xhci_slot_configure(slotid); 2206 assert(slotid >= 1 && slotid <= xhci->numslots); 2207 2208 ictx = xhci_mask64(pictx); 2209 octx = xhci->slots[slotid-1].ctx; 2210 2211 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2212 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2213 2214 if (dc) { 2215 for (i = 2; i <= 31; i++) { 2216 if (xhci->slots[slotid-1].eps[i-1]) { 2217 xhci_disable_ep(xhci, slotid, i); 2218 } 2219 } 2220 2221 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2222 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2223 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2224 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2225 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2226 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2227 2228 return CC_SUCCESS; 2229 } 2230 2231 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2232 2233 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2234 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2235 ictl_ctx[0], ictl_ctx[1]); 2236 return CC_TRB_ERROR; 2237 } 2238 2239 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2240 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2241 2242 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2243 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2244 return CC_CONTEXT_STATE_ERROR; 2245 } 2246 2247 for (i = 2; i <= 31; i++) { 2248 if (ictl_ctx[0] & (1<<i)) { 2249 xhci_disable_ep(xhci, slotid, i); 2250 } 2251 if (ictl_ctx[1] & (1<<i)) { 2252 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2253 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2254 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2255 ep_ctx[3], ep_ctx[4]); 2256 xhci_disable_ep(xhci, slotid, i); 2257 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2258 if (res != CC_SUCCESS) { 2259 return res; 2260 } 2261 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2262 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2263 ep_ctx[3], ep_ctx[4]); 2264 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2265 } 2266 } 2267 2268 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2269 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2270 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2271 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2272 SLOT_CONTEXT_ENTRIES_SHIFT); 2273 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2274 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2275 2276 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2277 2278 return CC_SUCCESS; 2279 } 2280 2281 2282 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2283 uint64_t pictx) 2284 { 2285 dma_addr_t ictx, octx; 2286 uint32_t ictl_ctx[2]; 2287 uint32_t iep0_ctx[5]; 2288 uint32_t ep0_ctx[5]; 2289 uint32_t islot_ctx[4]; 2290 uint32_t slot_ctx[4]; 2291 2292 trace_usb_xhci_slot_evaluate(slotid); 2293 assert(slotid >= 1 && slotid <= xhci->numslots); 2294 2295 ictx = xhci_mask64(pictx); 2296 octx = xhci->slots[slotid-1].ctx; 2297 2298 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2299 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2300 2301 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2302 2303 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2304 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2305 ictl_ctx[0], ictl_ctx[1]); 2306 return CC_TRB_ERROR; 2307 } 2308 2309 if (ictl_ctx[1] & 0x1) { 2310 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2311 2312 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2313 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2314 2315 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2316 2317 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2318 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2319 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2320 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2321 2322 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2323 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2324 2325 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2326 } 2327 2328 if (ictl_ctx[1] & 0x2) { 2329 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2330 2331 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2332 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2333 iep0_ctx[3], iep0_ctx[4]); 2334 2335 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2336 2337 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2338 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2339 2340 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2341 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2342 2343 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2344 } 2345 2346 return CC_SUCCESS; 2347 } 2348 2349 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2350 { 2351 uint32_t slot_ctx[4]; 2352 dma_addr_t octx; 2353 int i; 2354 2355 trace_usb_xhci_slot_reset(slotid); 2356 assert(slotid >= 1 && slotid <= xhci->numslots); 2357 2358 octx = xhci->slots[slotid-1].ctx; 2359 2360 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2361 2362 for (i = 2; i <= 31; i++) { 2363 if (xhci->slots[slotid-1].eps[i-1]) { 2364 xhci_disable_ep(xhci, slotid, i); 2365 } 2366 } 2367 2368 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2369 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2370 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2371 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2372 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2373 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2374 2375 return CC_SUCCESS; 2376 } 2377 2378 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2379 { 2380 unsigned int slotid; 2381 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2382 if (slotid < 1 || slotid > xhci->numslots) { 2383 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2384 event->ccode = CC_TRB_ERROR; 2385 return 0; 2386 } else if (!xhci->slots[slotid-1].enabled) { 2387 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2388 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2389 return 0; 2390 } 2391 return slotid; 2392 } 2393 2394 /* cleanup slot state on usb device detach */ 2395 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2396 { 2397 int slot, ep; 2398 2399 for (slot = 0; slot < xhci->numslots; slot++) { 2400 if (xhci->slots[slot].uport == uport) { 2401 break; 2402 } 2403 } 2404 if (slot == xhci->numslots) { 2405 return; 2406 } 2407 2408 for (ep = 0; ep < 31; ep++) { 2409 if (xhci->slots[slot].eps[ep]) { 2410 xhci_ep_nuke_xfers(xhci, slot+1, ep+1); 2411 } 2412 } 2413 xhci->slots[slot].uport = NULL; 2414 } 2415 2416 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2417 { 2418 dma_addr_t ctx; 2419 uint8_t bw_ctx[xhci->numports+1]; 2420 2421 DPRINTF("xhci_get_port_bandwidth()\n"); 2422 2423 ctx = xhci_mask64(pctx); 2424 2425 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2426 2427 /* TODO: actually implement real values here */ 2428 bw_ctx[0] = 0; 2429 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2430 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2431 2432 return CC_SUCCESS; 2433 } 2434 2435 static uint32_t rotl(uint32_t v, unsigned count) 2436 { 2437 count &= 31; 2438 return (v << count) | (v >> (32 - count)); 2439 } 2440 2441 2442 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2443 { 2444 uint32_t val; 2445 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2446 val += rotl(lo + 0x49434878, hi & 0x1F); 2447 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2448 return ~val; 2449 } 2450 2451 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2452 { 2453 uint32_t buf[8]; 2454 uint32_t obuf[8]; 2455 dma_addr_t paddr = xhci_mask64(addr); 2456 2457 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2458 2459 memcpy(obuf, buf, sizeof(obuf)); 2460 2461 if ((buf[0] & 0xff) == 2) { 2462 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2463 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2464 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2465 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2466 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2467 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2468 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2469 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2470 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2471 } 2472 2473 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2474 } 2475 2476 static void xhci_process_commands(XHCIState *xhci) 2477 { 2478 XHCITRB trb; 2479 TRBType type; 2480 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2481 dma_addr_t addr; 2482 unsigned int i, slotid = 0; 2483 2484 DPRINTF("xhci_process_commands()\n"); 2485 if (!xhci_running(xhci)) { 2486 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2487 return; 2488 } 2489 2490 xhci->crcr_low |= CRCR_CRR; 2491 2492 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2493 event.ptr = addr; 2494 switch (type) { 2495 case CR_ENABLE_SLOT: 2496 for (i = 0; i < xhci->numslots; i++) { 2497 if (!xhci->slots[i].enabled) { 2498 break; 2499 } 2500 } 2501 if (i >= xhci->numslots) { 2502 fprintf(stderr, "xhci: no device slots available\n"); 2503 event.ccode = CC_NO_SLOTS_ERROR; 2504 } else { 2505 slotid = i+1; 2506 event.ccode = xhci_enable_slot(xhci, slotid); 2507 } 2508 break; 2509 case CR_DISABLE_SLOT: 2510 slotid = xhci_get_slot(xhci, &event, &trb); 2511 if (slotid) { 2512 event.ccode = xhci_disable_slot(xhci, slotid); 2513 } 2514 break; 2515 case CR_ADDRESS_DEVICE: 2516 slotid = xhci_get_slot(xhci, &event, &trb); 2517 if (slotid) { 2518 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2519 trb.control & TRB_CR_BSR); 2520 } 2521 break; 2522 case CR_CONFIGURE_ENDPOINT: 2523 slotid = xhci_get_slot(xhci, &event, &trb); 2524 if (slotid) { 2525 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2526 trb.control & TRB_CR_DC); 2527 } 2528 break; 2529 case CR_EVALUATE_CONTEXT: 2530 slotid = xhci_get_slot(xhci, &event, &trb); 2531 if (slotid) { 2532 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2533 } 2534 break; 2535 case CR_STOP_ENDPOINT: 2536 slotid = xhci_get_slot(xhci, &event, &trb); 2537 if (slotid) { 2538 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2539 & TRB_CR_EPID_MASK; 2540 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2541 } 2542 break; 2543 case CR_RESET_ENDPOINT: 2544 slotid = xhci_get_slot(xhci, &event, &trb); 2545 if (slotid) { 2546 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2547 & TRB_CR_EPID_MASK; 2548 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2549 } 2550 break; 2551 case CR_SET_TR_DEQUEUE: 2552 slotid = xhci_get_slot(xhci, &event, &trb); 2553 if (slotid) { 2554 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2555 & TRB_CR_EPID_MASK; 2556 unsigned int streamid = (trb.status >> 16) & 0xffff; 2557 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2558 epid, streamid, 2559 trb.parameter); 2560 } 2561 break; 2562 case CR_RESET_DEVICE: 2563 slotid = xhci_get_slot(xhci, &event, &trb); 2564 if (slotid) { 2565 event.ccode = xhci_reset_slot(xhci, slotid); 2566 } 2567 break; 2568 case CR_GET_PORT_BANDWIDTH: 2569 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2570 break; 2571 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2572 xhci_via_challenge(xhci, trb.parameter); 2573 break; 2574 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2575 event.type = 48; /* NEC reply */ 2576 event.length = 0x3025; 2577 break; 2578 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2579 { 2580 uint32_t chi = trb.parameter >> 32; 2581 uint32_t clo = trb.parameter; 2582 uint32_t val = xhci_nec_challenge(chi, clo); 2583 event.length = val & 0xFFFF; 2584 event.epid = val >> 16; 2585 slotid = val >> 24; 2586 event.type = 48; /* NEC reply */ 2587 } 2588 break; 2589 default: 2590 trace_usb_xhci_unimplemented("command", type); 2591 event.ccode = CC_TRB_ERROR; 2592 break; 2593 } 2594 event.slotid = slotid; 2595 xhci_event(xhci, &event, 0); 2596 } 2597 } 2598 2599 static bool xhci_port_have_device(XHCIPort *port) 2600 { 2601 if (!port->uport->dev || !port->uport->dev->attached) { 2602 return false; /* no device present */ 2603 } 2604 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2605 return false; /* speed mismatch */ 2606 } 2607 return true; 2608 } 2609 2610 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2611 { 2612 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2613 port->portnr << 24 }; 2614 2615 if ((port->portsc & bits) == bits) { 2616 return; 2617 } 2618 trace_usb_xhci_port_notify(port->portnr, bits); 2619 port->portsc |= bits; 2620 if (!xhci_running(port->xhci)) { 2621 return; 2622 } 2623 xhci_event(port->xhci, &ev, 0); 2624 } 2625 2626 static void xhci_port_update(XHCIPort *port, int is_detach) 2627 { 2628 uint32_t pls = PLS_RX_DETECT; 2629 2630 port->portsc = PORTSC_PP; 2631 if (!is_detach && xhci_port_have_device(port)) { 2632 port->portsc |= PORTSC_CCS; 2633 switch (port->uport->dev->speed) { 2634 case USB_SPEED_LOW: 2635 port->portsc |= PORTSC_SPEED_LOW; 2636 pls = PLS_POLLING; 2637 break; 2638 case USB_SPEED_FULL: 2639 port->portsc |= PORTSC_SPEED_FULL; 2640 pls = PLS_POLLING; 2641 break; 2642 case USB_SPEED_HIGH: 2643 port->portsc |= PORTSC_SPEED_HIGH; 2644 pls = PLS_POLLING; 2645 break; 2646 case USB_SPEED_SUPER: 2647 port->portsc |= PORTSC_SPEED_SUPER; 2648 port->portsc |= PORTSC_PED; 2649 pls = PLS_U0; 2650 break; 2651 } 2652 } 2653 set_field(&port->portsc, pls, PORTSC_PLS); 2654 trace_usb_xhci_port_link(port->portnr, pls); 2655 xhci_port_notify(port, PORTSC_CSC); 2656 } 2657 2658 static void xhci_port_reset(XHCIPort *port) 2659 { 2660 trace_usb_xhci_port_reset(port->portnr); 2661 2662 if (!xhci_port_have_device(port)) { 2663 return; 2664 } 2665 2666 usb_device_reset(port->uport->dev); 2667 2668 switch (port->uport->dev->speed) { 2669 case USB_SPEED_LOW: 2670 case USB_SPEED_FULL: 2671 case USB_SPEED_HIGH: 2672 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2673 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2674 port->portsc |= PORTSC_PED; 2675 break; 2676 } 2677 2678 port->portsc &= ~PORTSC_PR; 2679 xhci_port_notify(port, PORTSC_PRC); 2680 } 2681 2682 static void xhci_reset(DeviceState *dev) 2683 { 2684 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2685 int i; 2686 2687 trace_usb_xhci_reset(); 2688 if (!(xhci->usbsts & USBSTS_HCH)) { 2689 fprintf(stderr, "xhci: reset while running!\n"); 2690 } 2691 2692 xhci->usbcmd = 0; 2693 xhci->usbsts = USBSTS_HCH; 2694 xhci->dnctrl = 0; 2695 xhci->crcr_low = 0; 2696 xhci->crcr_high = 0; 2697 xhci->dcbaap_low = 0; 2698 xhci->dcbaap_high = 0; 2699 xhci->config = 0; 2700 2701 for (i = 0; i < xhci->numslots; i++) { 2702 xhci_disable_slot(xhci, i+1); 2703 } 2704 2705 for (i = 0; i < xhci->numports; i++) { 2706 xhci_port_update(xhci->ports + i, 0); 2707 } 2708 2709 for (i = 0; i < xhci->numintrs; i++) { 2710 xhci->intr[i].iman = 0; 2711 xhci->intr[i].imod = 0; 2712 xhci->intr[i].erstsz = 0; 2713 xhci->intr[i].erstba_low = 0; 2714 xhci->intr[i].erstba_high = 0; 2715 xhci->intr[i].erdp_low = 0; 2716 xhci->intr[i].erdp_high = 0; 2717 xhci->intr[i].msix_used = 0; 2718 2719 xhci->intr[i].er_ep_idx = 0; 2720 xhci->intr[i].er_pcs = 1; 2721 xhci->intr[i].er_full = 0; 2722 xhci->intr[i].ev_buffer_put = 0; 2723 xhci->intr[i].ev_buffer_get = 0; 2724 } 2725 2726 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2727 xhci_mfwrap_update(xhci); 2728 } 2729 2730 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2731 { 2732 XHCIState *xhci = ptr; 2733 uint32_t ret; 2734 2735 switch (reg) { 2736 case 0x00: /* HCIVERSION, CAPLENGTH */ 2737 ret = 0x01000000 | LEN_CAP; 2738 break; 2739 case 0x04: /* HCSPARAMS 1 */ 2740 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2741 | (xhci->numintrs<<8) | xhci->numslots; 2742 break; 2743 case 0x08: /* HCSPARAMS 2 */ 2744 ret = 0x0000000f; 2745 break; 2746 case 0x0c: /* HCSPARAMS 3 */ 2747 ret = 0x00000000; 2748 break; 2749 case 0x10: /* HCCPARAMS */ 2750 if (sizeof(dma_addr_t) == 4) { 2751 ret = 0x00087000; 2752 } else { 2753 ret = 0x00087001; 2754 } 2755 break; 2756 case 0x14: /* DBOFF */ 2757 ret = OFF_DOORBELL; 2758 break; 2759 case 0x18: /* RTSOFF */ 2760 ret = OFF_RUNTIME; 2761 break; 2762 2763 /* extended capabilities */ 2764 case 0x20: /* Supported Protocol:00 */ 2765 ret = 0x02000402; /* USB 2.0 */ 2766 break; 2767 case 0x24: /* Supported Protocol:04 */ 2768 ret = 0x20425355; /* "USB " */ 2769 break; 2770 case 0x28: /* Supported Protocol:08 */ 2771 ret = 0x00000001 | (xhci->numports_2<<8); 2772 break; 2773 case 0x2c: /* Supported Protocol:0c */ 2774 ret = 0x00000000; /* reserved */ 2775 break; 2776 case 0x30: /* Supported Protocol:00 */ 2777 ret = 0x03000002; /* USB 3.0 */ 2778 break; 2779 case 0x34: /* Supported Protocol:04 */ 2780 ret = 0x20425355; /* "USB " */ 2781 break; 2782 case 0x38: /* Supported Protocol:08 */ 2783 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2784 break; 2785 case 0x3c: /* Supported Protocol:0c */ 2786 ret = 0x00000000; /* reserved */ 2787 break; 2788 default: 2789 trace_usb_xhci_unimplemented("cap read", reg); 2790 ret = 0; 2791 } 2792 2793 trace_usb_xhci_cap_read(reg, ret); 2794 return ret; 2795 } 2796 2797 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2798 { 2799 XHCIPort *port = ptr; 2800 uint32_t ret; 2801 2802 switch (reg) { 2803 case 0x00: /* PORTSC */ 2804 ret = port->portsc; 2805 break; 2806 case 0x04: /* PORTPMSC */ 2807 case 0x08: /* PORTLI */ 2808 ret = 0; 2809 break; 2810 case 0x0c: /* reserved */ 2811 default: 2812 trace_usb_xhci_unimplemented("port read", reg); 2813 ret = 0; 2814 } 2815 2816 trace_usb_xhci_port_read(port->portnr, reg, ret); 2817 return ret; 2818 } 2819 2820 static void xhci_port_write(void *ptr, hwaddr reg, 2821 uint64_t val, unsigned size) 2822 { 2823 XHCIPort *port = ptr; 2824 uint32_t portsc, notify; 2825 2826 trace_usb_xhci_port_write(port->portnr, reg, val); 2827 2828 switch (reg) { 2829 case 0x00: /* PORTSC */ 2830 /* write-1-to-start bits */ 2831 if (val & PORTSC_PR) { 2832 xhci_port_reset(port); 2833 break; 2834 } 2835 2836 portsc = port->portsc; 2837 notify = 0; 2838 /* write-1-to-clear bits*/ 2839 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2840 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2841 if (val & PORTSC_LWS) { 2842 /* overwrite PLS only when LWS=1 */ 2843 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2844 uint32_t new_pls = get_field(val, PORTSC_PLS); 2845 switch (new_pls) { 2846 case PLS_U0: 2847 if (old_pls != PLS_U0) { 2848 set_field(&portsc, new_pls, PORTSC_PLS); 2849 trace_usb_xhci_port_link(port->portnr, new_pls); 2850 notify = PORTSC_PLC; 2851 } 2852 break; 2853 case PLS_U3: 2854 if (old_pls < PLS_U3) { 2855 set_field(&portsc, new_pls, PORTSC_PLS); 2856 trace_usb_xhci_port_link(port->portnr, new_pls); 2857 } 2858 break; 2859 case PLS_RESUME: 2860 /* windows does this for some reason, don't spam stderr */ 2861 break; 2862 default: 2863 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2864 __func__, old_pls, new_pls); 2865 break; 2866 } 2867 } 2868 /* read/write bits */ 2869 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2870 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2871 port->portsc = portsc; 2872 if (notify) { 2873 xhci_port_notify(port, notify); 2874 } 2875 break; 2876 case 0x04: /* PORTPMSC */ 2877 case 0x08: /* PORTLI */ 2878 default: 2879 trace_usb_xhci_unimplemented("port write", reg); 2880 } 2881 } 2882 2883 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2884 { 2885 XHCIState *xhci = ptr; 2886 uint32_t ret; 2887 2888 switch (reg) { 2889 case 0x00: /* USBCMD */ 2890 ret = xhci->usbcmd; 2891 break; 2892 case 0x04: /* USBSTS */ 2893 ret = xhci->usbsts; 2894 break; 2895 case 0x08: /* PAGESIZE */ 2896 ret = 1; /* 4KiB */ 2897 break; 2898 case 0x14: /* DNCTRL */ 2899 ret = xhci->dnctrl; 2900 break; 2901 case 0x18: /* CRCR low */ 2902 ret = xhci->crcr_low & ~0xe; 2903 break; 2904 case 0x1c: /* CRCR high */ 2905 ret = xhci->crcr_high; 2906 break; 2907 case 0x30: /* DCBAAP low */ 2908 ret = xhci->dcbaap_low; 2909 break; 2910 case 0x34: /* DCBAAP high */ 2911 ret = xhci->dcbaap_high; 2912 break; 2913 case 0x38: /* CONFIG */ 2914 ret = xhci->config; 2915 break; 2916 default: 2917 trace_usb_xhci_unimplemented("oper read", reg); 2918 ret = 0; 2919 } 2920 2921 trace_usb_xhci_oper_read(reg, ret); 2922 return ret; 2923 } 2924 2925 static void xhci_oper_write(void *ptr, hwaddr reg, 2926 uint64_t val, unsigned size) 2927 { 2928 XHCIState *xhci = ptr; 2929 2930 trace_usb_xhci_oper_write(reg, val); 2931 2932 switch (reg) { 2933 case 0x00: /* USBCMD */ 2934 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2935 xhci_run(xhci); 2936 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2937 xhci_stop(xhci); 2938 } 2939 xhci->usbcmd = val & 0xc0f; 2940 xhci_mfwrap_update(xhci); 2941 if (val & USBCMD_HCRST) { 2942 xhci_reset(&xhci->pci_dev.qdev); 2943 } 2944 xhci_intx_update(xhci); 2945 break; 2946 2947 case 0x04: /* USBSTS */ 2948 /* these bits are write-1-to-clear */ 2949 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2950 xhci_intx_update(xhci); 2951 break; 2952 2953 case 0x14: /* DNCTRL */ 2954 xhci->dnctrl = val & 0xffff; 2955 break; 2956 case 0x18: /* CRCR low */ 2957 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2958 break; 2959 case 0x1c: /* CRCR high */ 2960 xhci->crcr_high = val; 2961 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2962 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2963 xhci->crcr_low &= ~CRCR_CRR; 2964 xhci_event(xhci, &event, 0); 2965 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2966 } else { 2967 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2968 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2969 } 2970 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2971 break; 2972 case 0x30: /* DCBAAP low */ 2973 xhci->dcbaap_low = val & 0xffffffc0; 2974 break; 2975 case 0x34: /* DCBAAP high */ 2976 xhci->dcbaap_high = val; 2977 break; 2978 case 0x38: /* CONFIG */ 2979 xhci->config = val & 0xff; 2980 break; 2981 default: 2982 trace_usb_xhci_unimplemented("oper write", reg); 2983 } 2984 } 2985 2986 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2987 unsigned size) 2988 { 2989 XHCIState *xhci = ptr; 2990 uint32_t ret = 0; 2991 2992 if (reg < 0x20) { 2993 switch (reg) { 2994 case 0x00: /* MFINDEX */ 2995 ret = xhci_mfindex_get(xhci) & 0x3fff; 2996 break; 2997 default: 2998 trace_usb_xhci_unimplemented("runtime read", reg); 2999 break; 3000 } 3001 } else { 3002 int v = (reg - 0x20) / 0x20; 3003 XHCIInterrupter *intr = &xhci->intr[v]; 3004 switch (reg & 0x1f) { 3005 case 0x00: /* IMAN */ 3006 ret = intr->iman; 3007 break; 3008 case 0x04: /* IMOD */ 3009 ret = intr->imod; 3010 break; 3011 case 0x08: /* ERSTSZ */ 3012 ret = intr->erstsz; 3013 break; 3014 case 0x10: /* ERSTBA low */ 3015 ret = intr->erstba_low; 3016 break; 3017 case 0x14: /* ERSTBA high */ 3018 ret = intr->erstba_high; 3019 break; 3020 case 0x18: /* ERDP low */ 3021 ret = intr->erdp_low; 3022 break; 3023 case 0x1c: /* ERDP high */ 3024 ret = intr->erdp_high; 3025 break; 3026 } 3027 } 3028 3029 trace_usb_xhci_runtime_read(reg, ret); 3030 return ret; 3031 } 3032 3033 static void xhci_runtime_write(void *ptr, hwaddr reg, 3034 uint64_t val, unsigned size) 3035 { 3036 XHCIState *xhci = ptr; 3037 int v = (reg - 0x20) / 0x20; 3038 XHCIInterrupter *intr = &xhci->intr[v]; 3039 trace_usb_xhci_runtime_write(reg, val); 3040 3041 if (reg < 0x20) { 3042 trace_usb_xhci_unimplemented("runtime write", reg); 3043 return; 3044 } 3045 3046 switch (reg & 0x1f) { 3047 case 0x00: /* IMAN */ 3048 if (val & IMAN_IP) { 3049 intr->iman &= ~IMAN_IP; 3050 } 3051 intr->iman &= ~IMAN_IE; 3052 intr->iman |= val & IMAN_IE; 3053 if (v == 0) { 3054 xhci_intx_update(xhci); 3055 } 3056 xhci_msix_update(xhci, v); 3057 break; 3058 case 0x04: /* IMOD */ 3059 intr->imod = val; 3060 break; 3061 case 0x08: /* ERSTSZ */ 3062 intr->erstsz = val & 0xffff; 3063 break; 3064 case 0x10: /* ERSTBA low */ 3065 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3066 intr->erstba_low = val & 0xffffffc0; */ 3067 intr->erstba_low = val & 0xfffffff0; 3068 break; 3069 case 0x14: /* ERSTBA high */ 3070 intr->erstba_high = val; 3071 xhci_er_reset(xhci, v); 3072 break; 3073 case 0x18: /* ERDP low */ 3074 if (val & ERDP_EHB) { 3075 intr->erdp_low &= ~ERDP_EHB; 3076 } 3077 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3078 break; 3079 case 0x1c: /* ERDP high */ 3080 intr->erdp_high = val; 3081 xhci_events_update(xhci, v); 3082 break; 3083 default: 3084 trace_usb_xhci_unimplemented("oper write", reg); 3085 } 3086 } 3087 3088 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3089 unsigned size) 3090 { 3091 /* doorbells always read as 0 */ 3092 trace_usb_xhci_doorbell_read(reg, 0); 3093 return 0; 3094 } 3095 3096 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3097 uint64_t val, unsigned size) 3098 { 3099 XHCIState *xhci = ptr; 3100 unsigned int epid, streamid; 3101 3102 trace_usb_xhci_doorbell_write(reg, val); 3103 3104 if (!xhci_running(xhci)) { 3105 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3106 return; 3107 } 3108 3109 reg >>= 2; 3110 3111 if (reg == 0) { 3112 if (val == 0) { 3113 xhci_process_commands(xhci); 3114 } else { 3115 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3116 (uint32_t)val); 3117 } 3118 } else { 3119 epid = val & 0xff; 3120 streamid = (val >> 16) & 0xffff; 3121 if (reg > xhci->numslots) { 3122 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3123 } else if (epid > 31) { 3124 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3125 (int)reg, (uint32_t)val); 3126 } else { 3127 xhci_kick_ep(xhci, reg, epid, streamid); 3128 } 3129 } 3130 } 3131 3132 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3133 unsigned width) 3134 { 3135 /* nothing */ 3136 } 3137 3138 static const MemoryRegionOps xhci_cap_ops = { 3139 .read = xhci_cap_read, 3140 .write = xhci_cap_write, 3141 .valid.min_access_size = 1, 3142 .valid.max_access_size = 4, 3143 .impl.min_access_size = 4, 3144 .impl.max_access_size = 4, 3145 .endianness = DEVICE_LITTLE_ENDIAN, 3146 }; 3147 3148 static const MemoryRegionOps xhci_oper_ops = { 3149 .read = xhci_oper_read, 3150 .write = xhci_oper_write, 3151 .valid.min_access_size = 4, 3152 .valid.max_access_size = 4, 3153 .endianness = DEVICE_LITTLE_ENDIAN, 3154 }; 3155 3156 static const MemoryRegionOps xhci_port_ops = { 3157 .read = xhci_port_read, 3158 .write = xhci_port_write, 3159 .valid.min_access_size = 4, 3160 .valid.max_access_size = 4, 3161 .endianness = DEVICE_LITTLE_ENDIAN, 3162 }; 3163 3164 static const MemoryRegionOps xhci_runtime_ops = { 3165 .read = xhci_runtime_read, 3166 .write = xhci_runtime_write, 3167 .valid.min_access_size = 4, 3168 .valid.max_access_size = 4, 3169 .endianness = DEVICE_LITTLE_ENDIAN, 3170 }; 3171 3172 static const MemoryRegionOps xhci_doorbell_ops = { 3173 .read = xhci_doorbell_read, 3174 .write = xhci_doorbell_write, 3175 .valid.min_access_size = 4, 3176 .valid.max_access_size = 4, 3177 .endianness = DEVICE_LITTLE_ENDIAN, 3178 }; 3179 3180 static void xhci_attach(USBPort *usbport) 3181 { 3182 XHCIState *xhci = usbport->opaque; 3183 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3184 3185 xhci_port_update(port, 0); 3186 } 3187 3188 static void xhci_detach(USBPort *usbport) 3189 { 3190 XHCIState *xhci = usbport->opaque; 3191 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3192 3193 xhci_detach_slot(xhci, usbport); 3194 xhci_port_update(port, 1); 3195 } 3196 3197 static void xhci_wakeup(USBPort *usbport) 3198 { 3199 XHCIState *xhci = usbport->opaque; 3200 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3201 3202 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3203 return; 3204 } 3205 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3206 xhci_port_notify(port, PORTSC_PLC); 3207 } 3208 3209 static void xhci_complete(USBPort *port, USBPacket *packet) 3210 { 3211 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3212 3213 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3214 xhci_ep_nuke_one_xfer(xfer); 3215 return; 3216 } 3217 xhci_complete_packet(xfer); 3218 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3219 } 3220 3221 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3222 { 3223 USBBus *bus = usb_bus_from_device(child); 3224 XHCIState *xhci = container_of(bus, XHCIState, bus); 3225 3226 xhci_detach_slot(xhci, uport); 3227 } 3228 3229 static USBPortOps xhci_uport_ops = { 3230 .attach = xhci_attach, 3231 .detach = xhci_detach, 3232 .wakeup = xhci_wakeup, 3233 .complete = xhci_complete, 3234 .child_detach = xhci_child_detach, 3235 }; 3236 3237 static int xhci_find_epid(USBEndpoint *ep) 3238 { 3239 if (ep->nr == 0) { 3240 return 1; 3241 } 3242 if (ep->pid == USB_TOKEN_IN) { 3243 return ep->nr * 2 + 1; 3244 } else { 3245 return ep->nr * 2; 3246 } 3247 } 3248 3249 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3250 unsigned int stream) 3251 { 3252 XHCIState *xhci = container_of(bus, XHCIState, bus); 3253 int slotid; 3254 3255 DPRINTF("%s\n", __func__); 3256 slotid = ep->dev->addr; 3257 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3258 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3259 return; 3260 } 3261 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3262 } 3263 3264 static USBBusOps xhci_bus_ops = { 3265 .wakeup_endpoint = xhci_wakeup_endpoint, 3266 }; 3267 3268 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 3269 { 3270 XHCIPort *port; 3271 int i, usbports, speedmask; 3272 3273 xhci->usbsts = USBSTS_HCH; 3274 3275 if (xhci->numports_2 > MAXPORTS_2) { 3276 xhci->numports_2 = MAXPORTS_2; 3277 } 3278 if (xhci->numports_3 > MAXPORTS_3) { 3279 xhci->numports_3 = MAXPORTS_3; 3280 } 3281 usbports = MAX(xhci->numports_2, xhci->numports_3); 3282 xhci->numports = xhci->numports_2 + xhci->numports_3; 3283 3284 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 3285 3286 for (i = 0; i < usbports; i++) { 3287 speedmask = 0; 3288 if (i < xhci->numports_2) { 3289 port = &xhci->ports[i]; 3290 port->portnr = i + 1; 3291 port->uport = &xhci->uports[i]; 3292 port->speedmask = 3293 USB_SPEED_MASK_LOW | 3294 USB_SPEED_MASK_FULL | 3295 USB_SPEED_MASK_HIGH; 3296 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3297 speedmask |= port->speedmask; 3298 } 3299 if (i < xhci->numports_3) { 3300 port = &xhci->ports[i + xhci->numports_2]; 3301 port->portnr = i + 1 + xhci->numports_2; 3302 port->uport = &xhci->uports[i]; 3303 port->speedmask = USB_SPEED_MASK_SUPER; 3304 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3305 speedmask |= port->speedmask; 3306 } 3307 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3308 &xhci_uport_ops, speedmask); 3309 } 3310 } 3311 3312 static int usb_xhci_initfn(struct PCIDevice *dev) 3313 { 3314 int i, ret; 3315 3316 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 3317 3318 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3319 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3320 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 3321 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 3322 3323 usb_xhci_init(xhci, &dev->qdev); 3324 3325 if (xhci->numintrs > MAXINTRS) { 3326 xhci->numintrs = MAXINTRS; 3327 } 3328 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3329 xhci->numintrs++; 3330 } 3331 if (xhci->numintrs < 1) { 3332 xhci->numintrs = 1; 3333 } 3334 if (xhci->numslots > MAXSLOTS) { 3335 xhci->numslots = MAXSLOTS; 3336 } 3337 if (xhci->numslots < 1) { 3338 xhci->numslots = 1; 3339 } 3340 3341 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 3342 3343 xhci->irq = xhci->pci_dev.irq[0]; 3344 3345 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3346 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3347 "capabilities", LEN_CAP); 3348 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3349 "operational", 0x400); 3350 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3351 "runtime", LEN_RUNTIME); 3352 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3353 "doorbell", LEN_DOORBELL); 3354 3355 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3356 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3357 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3358 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3359 3360 for (i = 0; i < xhci->numports; i++) { 3361 XHCIPort *port = &xhci->ports[i]; 3362 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3363 port->xhci = xhci; 3364 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3365 port->name, 0x10); 3366 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3367 } 3368 3369 pci_register_bar(&xhci->pci_dev, 0, 3370 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3371 &xhci->mem); 3372 3373 ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0); 3374 assert(ret >= 0); 3375 3376 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3377 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); 3378 } 3379 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3380 msix_init(&xhci->pci_dev, xhci->numintrs, 3381 &xhci->mem, 0, OFF_MSIX_TABLE, 3382 &xhci->mem, 0, OFF_MSIX_PBA, 3383 0x90); 3384 } 3385 3386 return 0; 3387 } 3388 3389 static int usb_xhci_post_load(void *opaque, int version_id) 3390 { 3391 XHCIState *xhci = opaque; 3392 XHCISlot *slot; 3393 XHCIEPContext *epctx; 3394 dma_addr_t dcbaap, pctx; 3395 uint32_t slot_ctx[4]; 3396 uint32_t ep_ctx[5]; 3397 int slotid, epid, state, intr; 3398 3399 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3400 3401 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3402 slot = &xhci->slots[slotid-1]; 3403 if (!slot->addressed) { 3404 continue; 3405 } 3406 slot->ctx = 3407 xhci_mask64(ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid)); 3408 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3409 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3410 assert(slot->uport && slot->uport->dev); 3411 3412 for (epid = 1; epid <= 32; epid++) { 3413 pctx = slot->ctx + 32 * epid; 3414 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3415 state = ep_ctx[0] & EP_STATE_MASK; 3416 if (state == EP_DISABLED) { 3417 continue; 3418 } 3419 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3420 slot->eps[epid-1] = epctx; 3421 xhci_init_epctx(epctx, pctx, ep_ctx); 3422 epctx->state = state; 3423 if (state == EP_RUNNING) { 3424 /* kick endpoint after vmload is finished */ 3425 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock)); 3426 } 3427 } 3428 } 3429 3430 for (intr = 0; intr < xhci->numintrs; intr++) { 3431 if (xhci->intr[intr].msix_used) { 3432 msix_vector_use(&xhci->pci_dev, intr); 3433 } else { 3434 msix_vector_unuse(&xhci->pci_dev, intr); 3435 } 3436 } 3437 3438 return 0; 3439 } 3440 3441 static const VMStateDescription vmstate_xhci_ring = { 3442 .name = "xhci-ring", 3443 .version_id = 1, 3444 .fields = (VMStateField[]) { 3445 VMSTATE_UINT64(dequeue, XHCIRing), 3446 VMSTATE_BOOL(ccs, XHCIRing), 3447 VMSTATE_END_OF_LIST() 3448 } 3449 }; 3450 3451 static const VMStateDescription vmstate_xhci_port = { 3452 .name = "xhci-port", 3453 .version_id = 1, 3454 .fields = (VMStateField[]) { 3455 VMSTATE_UINT32(portsc, XHCIPort), 3456 VMSTATE_END_OF_LIST() 3457 } 3458 }; 3459 3460 static const VMStateDescription vmstate_xhci_slot = { 3461 .name = "xhci-slot", 3462 .version_id = 1, 3463 .fields = (VMStateField[]) { 3464 VMSTATE_BOOL(enabled, XHCISlot), 3465 VMSTATE_BOOL(addressed, XHCISlot), 3466 VMSTATE_END_OF_LIST() 3467 } 3468 }; 3469 3470 static const VMStateDescription vmstate_xhci_event = { 3471 .name = "xhci-event", 3472 .version_id = 1, 3473 .fields = (VMStateField[]) { 3474 VMSTATE_UINT32(type, XHCIEvent), 3475 VMSTATE_UINT32(ccode, XHCIEvent), 3476 VMSTATE_UINT64(ptr, XHCIEvent), 3477 VMSTATE_UINT32(length, XHCIEvent), 3478 VMSTATE_UINT32(flags, XHCIEvent), 3479 VMSTATE_UINT8(slotid, XHCIEvent), 3480 VMSTATE_UINT8(epid, XHCIEvent), 3481 } 3482 }; 3483 3484 static bool xhci_er_full(void *opaque, int version_id) 3485 { 3486 struct XHCIInterrupter *intr = opaque; 3487 return intr->er_full; 3488 } 3489 3490 static const VMStateDescription vmstate_xhci_intr = { 3491 .name = "xhci-intr", 3492 .version_id = 1, 3493 .fields = (VMStateField[]) { 3494 /* registers */ 3495 VMSTATE_UINT32(iman, XHCIInterrupter), 3496 VMSTATE_UINT32(imod, XHCIInterrupter), 3497 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3498 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3499 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3500 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3501 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3502 3503 /* state */ 3504 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3505 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3506 VMSTATE_UINT64(er_start, XHCIInterrupter), 3507 VMSTATE_UINT32(er_size, XHCIInterrupter), 3508 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3509 3510 /* event queue (used if ring is full) */ 3511 VMSTATE_BOOL(er_full, XHCIInterrupter), 3512 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3513 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3514 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3515 xhci_er_full, 1, 3516 vmstate_xhci_event, XHCIEvent), 3517 3518 VMSTATE_END_OF_LIST() 3519 } 3520 }; 3521 3522 static const VMStateDescription vmstate_xhci = { 3523 .name = "xhci", 3524 .version_id = 1, 3525 .post_load = usb_xhci_post_load, 3526 .fields = (VMStateField[]) { 3527 VMSTATE_PCIE_DEVICE(pci_dev, XHCIState), 3528 VMSTATE_MSIX(pci_dev, XHCIState), 3529 3530 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3531 vmstate_xhci_port, XHCIPort), 3532 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3533 vmstate_xhci_slot, XHCISlot), 3534 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3535 vmstate_xhci_intr, XHCIInterrupter), 3536 3537 /* Operational Registers */ 3538 VMSTATE_UINT32(usbcmd, XHCIState), 3539 VMSTATE_UINT32(usbsts, XHCIState), 3540 VMSTATE_UINT32(dnctrl, XHCIState), 3541 VMSTATE_UINT32(crcr_low, XHCIState), 3542 VMSTATE_UINT32(crcr_high, XHCIState), 3543 VMSTATE_UINT32(dcbaap_low, XHCIState), 3544 VMSTATE_UINT32(dcbaap_high, XHCIState), 3545 VMSTATE_UINT32(config, XHCIState), 3546 3547 /* Runtime Registers & state */ 3548 VMSTATE_INT64(mfindex_start, XHCIState), 3549 VMSTATE_TIMER(mfwrap_timer, XHCIState), 3550 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3551 3552 VMSTATE_END_OF_LIST() 3553 } 3554 }; 3555 3556 static Property xhci_properties[] = { 3557 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3558 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3559 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3560 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3561 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3562 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3563 DEFINE_PROP_END_OF_LIST(), 3564 }; 3565 3566 static void xhci_class_init(ObjectClass *klass, void *data) 3567 { 3568 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3569 DeviceClass *dc = DEVICE_CLASS(klass); 3570 3571 dc->vmsd = &vmstate_xhci; 3572 dc->props = xhci_properties; 3573 dc->reset = xhci_reset; 3574 k->init = usb_xhci_initfn; 3575 k->vendor_id = PCI_VENDOR_ID_NEC; 3576 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3577 k->class_id = PCI_CLASS_SERIAL_USB; 3578 k->revision = 0x03; 3579 k->is_express = 1; 3580 k->no_hotplug = 1; 3581 } 3582 3583 static const TypeInfo xhci_info = { 3584 .name = "nec-usb-xhci", 3585 .parent = TYPE_PCI_DEVICE, 3586 .instance_size = sizeof(XHCIState), 3587 .class_init = xhci_class_init, 3588 }; 3589 3590 static void xhci_register_types(void) 3591 { 3592 type_register_static(&xhci_info); 3593 } 3594 3595 type_init(xhci_register_types) 3596