1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 150 typedef enum TRBType { 151 TRB_RESERVED = 0, 152 TR_NORMAL, 153 TR_SETUP, 154 TR_DATA, 155 TR_STATUS, 156 TR_ISOCH, 157 TR_LINK, 158 TR_EVDATA, 159 TR_NOOP, 160 CR_ENABLE_SLOT, 161 CR_DISABLE_SLOT, 162 CR_ADDRESS_DEVICE, 163 CR_CONFIGURE_ENDPOINT, 164 CR_EVALUATE_CONTEXT, 165 CR_RESET_ENDPOINT, 166 CR_STOP_ENDPOINT, 167 CR_SET_TR_DEQUEUE, 168 CR_RESET_DEVICE, 169 CR_FORCE_EVENT, 170 CR_NEGOTIATE_BW, 171 CR_SET_LATENCY_TOLERANCE, 172 CR_GET_PORT_BANDWIDTH, 173 CR_FORCE_HEADER, 174 CR_NOOP, 175 ER_TRANSFER = 32, 176 ER_COMMAND_COMPLETE, 177 ER_PORT_STATUS_CHANGE, 178 ER_BANDWIDTH_REQUEST, 179 ER_DOORBELL, 180 ER_HOST_CONTROLLER, 181 ER_DEVICE_NOTIFICATION, 182 ER_MFINDEX_WRAP, 183 /* vendor specific bits */ 184 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 185 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 186 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 187 } TRBType; 188 189 #define CR_LINK TR_LINK 190 191 typedef enum TRBCCode { 192 CC_INVALID = 0, 193 CC_SUCCESS, 194 CC_DATA_BUFFER_ERROR, 195 CC_BABBLE_DETECTED, 196 CC_USB_TRANSACTION_ERROR, 197 CC_TRB_ERROR, 198 CC_STALL_ERROR, 199 CC_RESOURCE_ERROR, 200 CC_BANDWIDTH_ERROR, 201 CC_NO_SLOTS_ERROR, 202 CC_INVALID_STREAM_TYPE_ERROR, 203 CC_SLOT_NOT_ENABLED_ERROR, 204 CC_EP_NOT_ENABLED_ERROR, 205 CC_SHORT_PACKET, 206 CC_RING_UNDERRUN, 207 CC_RING_OVERRUN, 208 CC_VF_ER_FULL, 209 CC_PARAMETER_ERROR, 210 CC_BANDWIDTH_OVERRUN, 211 CC_CONTEXT_STATE_ERROR, 212 CC_NO_PING_RESPONSE_ERROR, 213 CC_EVENT_RING_FULL_ERROR, 214 CC_INCOMPATIBLE_DEVICE_ERROR, 215 CC_MISSED_SERVICE_ERROR, 216 CC_COMMAND_RING_STOPPED, 217 CC_COMMAND_ABORTED, 218 CC_STOPPED, 219 CC_STOPPED_LENGTH_INVALID, 220 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 221 CC_ISOCH_BUFFER_OVERRUN = 31, 222 CC_EVENT_LOST_ERROR, 223 CC_UNDEFINED_ERROR, 224 CC_INVALID_STREAM_ID_ERROR, 225 CC_SECONDARY_BANDWIDTH_ERROR, 226 CC_SPLIT_TRANSACTION_ERROR 227 } TRBCCode; 228 229 #define TRB_C (1<<0) 230 #define TRB_TYPE_SHIFT 10 231 #define TRB_TYPE_MASK 0x3f 232 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 233 234 #define TRB_EV_ED (1<<2) 235 236 #define TRB_TR_ENT (1<<1) 237 #define TRB_TR_ISP (1<<2) 238 #define TRB_TR_NS (1<<3) 239 #define TRB_TR_CH (1<<4) 240 #define TRB_TR_IOC (1<<5) 241 #define TRB_TR_IDT (1<<6) 242 #define TRB_TR_TBC_SHIFT 7 243 #define TRB_TR_TBC_MASK 0x3 244 #define TRB_TR_BEI (1<<9) 245 #define TRB_TR_TLBPC_SHIFT 16 246 #define TRB_TR_TLBPC_MASK 0xf 247 #define TRB_TR_FRAMEID_SHIFT 20 248 #define TRB_TR_FRAMEID_MASK 0x7ff 249 #define TRB_TR_SIA (1<<31) 250 251 #define TRB_TR_DIR (1<<16) 252 253 #define TRB_CR_SLOTID_SHIFT 24 254 #define TRB_CR_SLOTID_MASK 0xff 255 #define TRB_CR_EPID_SHIFT 16 256 #define TRB_CR_EPID_MASK 0x1f 257 258 #define TRB_CR_BSR (1<<9) 259 #define TRB_CR_DC (1<<9) 260 261 #define TRB_LK_TC (1<<1) 262 263 #define TRB_INTR_SHIFT 22 264 #define TRB_INTR_MASK 0x3ff 265 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef enum EPType { 289 ET_INVALID = 0, 290 ET_ISO_OUT, 291 ET_BULK_OUT, 292 ET_INTR_OUT, 293 ET_CONTROL, 294 ET_ISO_IN, 295 ET_BULK_IN, 296 ET_INTR_IN, 297 } EPType; 298 299 typedef struct XHCIRing { 300 dma_addr_t base; 301 dma_addr_t dequeue; 302 bool ccs; 303 } XHCIRing; 304 305 typedef struct XHCIPort { 306 uint32_t portsc; 307 uint32_t portnr; 308 USBPort *uport; 309 uint32_t speedmask; 310 } XHCIPort; 311 312 struct XHCIState; 313 typedef struct XHCIState XHCIState; 314 315 typedef struct XHCITransfer { 316 XHCIState *xhci; 317 USBPacket packet; 318 QEMUSGList sgl; 319 bool running_async; 320 bool running_retry; 321 bool cancelled; 322 bool complete; 323 unsigned int iso_pkts; 324 unsigned int slotid; 325 unsigned int epid; 326 bool in_xfer; 327 bool iso_xfer; 328 329 unsigned int trb_count; 330 unsigned int trb_alloced; 331 XHCITRB *trbs; 332 333 TRBCCode status; 334 335 unsigned int pkts; 336 unsigned int pktsize; 337 unsigned int cur_pkt; 338 339 uint64_t mfindex_kick; 340 } XHCITransfer; 341 342 typedef struct XHCIEPContext { 343 XHCIState *xhci; 344 unsigned int slotid; 345 unsigned int epid; 346 347 XHCIRing ring; 348 unsigned int next_xfer; 349 unsigned int comp_xfer; 350 XHCITransfer transfers[TD_QUEUE]; 351 XHCITransfer *retry; 352 EPType type; 353 dma_addr_t pctx; 354 unsigned int max_psize; 355 uint32_t state; 356 357 /* iso xfer scheduling */ 358 unsigned int interval; 359 int64_t mfindex_last; 360 QEMUTimer *kick_timer; 361 } XHCIEPContext; 362 363 typedef struct XHCISlot { 364 bool enabled; 365 dma_addr_t ctx; 366 USBPort *uport; 367 unsigned int devaddr; 368 XHCIEPContext * eps[31]; 369 } XHCISlot; 370 371 typedef struct XHCIEvent { 372 TRBType type; 373 TRBCCode ccode; 374 uint64_t ptr; 375 uint32_t length; 376 uint32_t flags; 377 uint8_t slotid; 378 uint8_t epid; 379 } XHCIEvent; 380 381 typedef struct XHCIInterrupter { 382 uint32_t iman; 383 uint32_t imod; 384 uint32_t erstsz; 385 uint32_t erstba_low; 386 uint32_t erstba_high; 387 uint32_t erdp_low; 388 uint32_t erdp_high; 389 390 bool msix_used, er_pcs, er_full; 391 392 dma_addr_t er_start; 393 uint32_t er_size; 394 unsigned int er_ep_idx; 395 396 XHCIEvent ev_buffer[EV_QUEUE]; 397 unsigned int ev_buffer_put; 398 unsigned int ev_buffer_get; 399 400 } XHCIInterrupter; 401 402 struct XHCIState { 403 PCIDevice pci_dev; 404 USBBus bus; 405 qemu_irq irq; 406 MemoryRegion mem; 407 MemoryRegion mem_cap; 408 MemoryRegion mem_oper; 409 MemoryRegion mem_runtime; 410 MemoryRegion mem_doorbell; 411 const char *name; 412 unsigned int devaddr; 413 414 /* properties */ 415 uint32_t numports_2; 416 uint32_t numports_3; 417 uint32_t flags; 418 419 /* Operational Registers */ 420 uint32_t usbcmd; 421 uint32_t usbsts; 422 uint32_t dnctrl; 423 uint32_t crcr_low; 424 uint32_t crcr_high; 425 uint32_t dcbaap_low; 426 uint32_t dcbaap_high; 427 uint32_t config; 428 429 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 430 XHCIPort ports[MAXPORTS]; 431 XHCISlot slots[MAXSLOTS]; 432 uint32_t numports; 433 434 /* Runtime Registers */ 435 int64_t mfindex_start; 436 QEMUTimer *mfwrap_timer; 437 XHCIInterrupter intr[MAXINTRS]; 438 439 XHCIRing cmd_ring; 440 }; 441 442 typedef struct XHCIEvRingSeg { 443 uint32_t addr_low; 444 uint32_t addr_high; 445 uint32_t size; 446 uint32_t rsvd; 447 } XHCIEvRingSeg; 448 449 enum xhci_flags { 450 XHCI_FLAG_USE_MSI = 1, 451 XHCI_FLAG_USE_MSI_X, 452 }; 453 454 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 455 unsigned int epid); 456 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 457 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 458 459 static const char *TRBType_names[] = { 460 [TRB_RESERVED] = "TRB_RESERVED", 461 [TR_NORMAL] = "TR_NORMAL", 462 [TR_SETUP] = "TR_SETUP", 463 [TR_DATA] = "TR_DATA", 464 [TR_STATUS] = "TR_STATUS", 465 [TR_ISOCH] = "TR_ISOCH", 466 [TR_LINK] = "TR_LINK", 467 [TR_EVDATA] = "TR_EVDATA", 468 [TR_NOOP] = "TR_NOOP", 469 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 470 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 471 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 472 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 473 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 474 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 475 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 476 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 477 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 478 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 479 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 480 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 481 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 482 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 483 [CR_NOOP] = "CR_NOOP", 484 [ER_TRANSFER] = "ER_TRANSFER", 485 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 486 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 487 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 488 [ER_DOORBELL] = "ER_DOORBELL", 489 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 490 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 491 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 492 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 493 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 494 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 495 }; 496 497 static const char *TRBCCode_names[] = { 498 [CC_INVALID] = "CC_INVALID", 499 [CC_SUCCESS] = "CC_SUCCESS", 500 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 501 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 502 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 503 [CC_TRB_ERROR] = "CC_TRB_ERROR", 504 [CC_STALL_ERROR] = "CC_STALL_ERROR", 505 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 506 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 507 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 508 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 509 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 510 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 511 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 512 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 513 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 514 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 515 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 516 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 517 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 518 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 519 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 520 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 521 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 522 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 523 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 524 [CC_STOPPED] = "CC_STOPPED", 525 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 526 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 527 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 528 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 529 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 530 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 531 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 532 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 533 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 534 }; 535 536 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 537 { 538 if (index >= llen || list[index] == NULL) { 539 return "???"; 540 } 541 return list[index]; 542 } 543 544 static const char *trb_name(XHCITRB *trb) 545 { 546 return lookup_name(TRB_TYPE(*trb), TRBType_names, 547 ARRAY_SIZE(TRBType_names)); 548 } 549 550 static const char *event_name(XHCIEvent *event) 551 { 552 return lookup_name(event->ccode, TRBCCode_names, 553 ARRAY_SIZE(TRBCCode_names)); 554 } 555 556 static uint64_t xhci_mfindex_get(XHCIState *xhci) 557 { 558 int64_t now = qemu_get_clock_ns(vm_clock); 559 return (now - xhci->mfindex_start) / 125000; 560 } 561 562 static void xhci_mfwrap_update(XHCIState *xhci) 563 { 564 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 565 uint32_t mfindex, left; 566 int64_t now; 567 568 if ((xhci->usbcmd & bits) == bits) { 569 now = qemu_get_clock_ns(vm_clock); 570 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 571 left = 0x4000 - mfindex; 572 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 573 } else { 574 qemu_del_timer(xhci->mfwrap_timer); 575 } 576 } 577 578 static void xhci_mfwrap_timer(void *opaque) 579 { 580 XHCIState *xhci = opaque; 581 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 582 583 xhci_event(xhci, &wrap, 0); 584 xhci_mfwrap_update(xhci); 585 } 586 587 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 588 { 589 if (sizeof(dma_addr_t) == 4) { 590 return low; 591 } else { 592 return low | (((dma_addr_t)high << 16) << 16); 593 } 594 } 595 596 static inline dma_addr_t xhci_mask64(uint64_t addr) 597 { 598 if (sizeof(dma_addr_t) == 4) { 599 return addr & 0xffffffff; 600 } else { 601 return addr; 602 } 603 } 604 605 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 606 { 607 int index; 608 609 if (!uport->dev) { 610 return NULL; 611 } 612 switch (uport->dev->speed) { 613 case USB_SPEED_LOW: 614 case USB_SPEED_FULL: 615 case USB_SPEED_HIGH: 616 index = uport->index; 617 break; 618 case USB_SPEED_SUPER: 619 index = uport->index + xhci->numports_2; 620 break; 621 default: 622 return NULL; 623 } 624 return &xhci->ports[index]; 625 } 626 627 static void xhci_intx_update(XHCIState *xhci) 628 { 629 int level = 0; 630 631 if (msix_enabled(&xhci->pci_dev) || 632 msi_enabled(&xhci->pci_dev)) { 633 return; 634 } 635 636 if (xhci->intr[0].iman & IMAN_IP && 637 xhci->intr[0].iman & IMAN_IE && 638 xhci->usbcmd & USBCMD_INTE) { 639 level = 1; 640 } 641 642 trace_usb_xhci_irq_intx(level); 643 qemu_set_irq(xhci->irq, level); 644 } 645 646 static void xhci_msix_update(XHCIState *xhci, int v) 647 { 648 bool enabled; 649 650 if (!msix_enabled(&xhci->pci_dev)) { 651 return; 652 } 653 654 enabled = xhci->intr[v].iman & IMAN_IE; 655 if (enabled == xhci->intr[v].msix_used) { 656 return; 657 } 658 659 if (enabled) { 660 trace_usb_xhci_irq_msix_use(v); 661 msix_vector_use(&xhci->pci_dev, v); 662 xhci->intr[v].msix_used = true; 663 } else { 664 trace_usb_xhci_irq_msix_unuse(v); 665 msix_vector_unuse(&xhci->pci_dev, v); 666 xhci->intr[v].msix_used = false; 667 } 668 } 669 670 static void xhci_intr_raise(XHCIState *xhci, int v) 671 { 672 xhci->intr[v].erdp_low |= ERDP_EHB; 673 xhci->intr[v].iman |= IMAN_IP; 674 xhci->usbsts |= USBSTS_EINT; 675 676 if (!(xhci->intr[v].iman & IMAN_IE)) { 677 return; 678 } 679 680 if (!(xhci->usbcmd & USBCMD_INTE)) { 681 return; 682 } 683 684 if (msix_enabled(&xhci->pci_dev)) { 685 trace_usb_xhci_irq_msix(v); 686 msix_notify(&xhci->pci_dev, v); 687 return; 688 } 689 690 if (msi_enabled(&xhci->pci_dev)) { 691 trace_usb_xhci_irq_msi(v); 692 msi_notify(&xhci->pci_dev, v); 693 return; 694 } 695 696 if (v == 0) { 697 trace_usb_xhci_irq_intx(1); 698 qemu_set_irq(xhci->irq, 1); 699 } 700 } 701 702 static inline int xhci_running(XHCIState *xhci) 703 { 704 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 705 } 706 707 static void xhci_die(XHCIState *xhci) 708 { 709 xhci->usbsts |= USBSTS_HCE; 710 fprintf(stderr, "xhci: asserted controller error\n"); 711 } 712 713 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 714 { 715 XHCIInterrupter *intr = &xhci->intr[v]; 716 XHCITRB ev_trb; 717 dma_addr_t addr; 718 719 ev_trb.parameter = cpu_to_le64(event->ptr); 720 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 721 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 722 event->flags | (event->type << TRB_TYPE_SHIFT); 723 if (intr->er_pcs) { 724 ev_trb.control |= TRB_C; 725 } 726 ev_trb.control = cpu_to_le32(ev_trb.control); 727 728 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 729 event_name(event), ev_trb.parameter, 730 ev_trb.status, ev_trb.control); 731 732 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 733 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 734 735 intr->er_ep_idx++; 736 if (intr->er_ep_idx >= intr->er_size) { 737 intr->er_ep_idx = 0; 738 intr->er_pcs = !intr->er_pcs; 739 } 740 } 741 742 static void xhci_events_update(XHCIState *xhci, int v) 743 { 744 XHCIInterrupter *intr = &xhci->intr[v]; 745 dma_addr_t erdp; 746 unsigned int dp_idx; 747 bool do_irq = 0; 748 749 if (xhci->usbsts & USBSTS_HCH) { 750 return; 751 } 752 753 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 754 if (erdp < intr->er_start || 755 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 756 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 757 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 758 v, intr->er_start, intr->er_size); 759 xhci_die(xhci); 760 return; 761 } 762 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 763 assert(dp_idx < intr->er_size); 764 765 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 766 * deadlocks when the ER is full. Hack it by holding off events until 767 * the driver decides to free at least half of the ring */ 768 if (intr->er_full) { 769 int er_free = dp_idx - intr->er_ep_idx; 770 if (er_free <= 0) { 771 er_free += intr->er_size; 772 } 773 if (er_free < (intr->er_size/2)) { 774 DPRINTF("xhci_events_update(): event ring still " 775 "more than half full (hack)\n"); 776 return; 777 } 778 } 779 780 while (intr->ev_buffer_put != intr->ev_buffer_get) { 781 assert(intr->er_full); 782 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 783 DPRINTF("xhci_events_update(): event ring full again\n"); 784 #ifndef ER_FULL_HACK 785 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 786 xhci_write_event(xhci, &full, v); 787 #endif 788 do_irq = 1; 789 break; 790 } 791 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 792 xhci_write_event(xhci, event, v); 793 intr->ev_buffer_get++; 794 do_irq = 1; 795 if (intr->ev_buffer_get == EV_QUEUE) { 796 intr->ev_buffer_get = 0; 797 } 798 } 799 800 if (do_irq) { 801 xhci_intr_raise(xhci, v); 802 } 803 804 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 805 DPRINTF("xhci_events_update(): event ring no longer full\n"); 806 intr->er_full = 0; 807 } 808 return; 809 } 810 811 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 812 { 813 XHCIInterrupter *intr; 814 dma_addr_t erdp; 815 unsigned int dp_idx; 816 817 if (v >= MAXINTRS) { 818 DPRINTF("intr nr out of range (%d >= %d)\n", v, MAXINTRS); 819 return; 820 } 821 intr = &xhci->intr[v]; 822 823 if (intr->er_full) { 824 DPRINTF("xhci_event(): ER full, queueing\n"); 825 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 826 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 827 return; 828 } 829 intr->ev_buffer[intr->ev_buffer_put++] = *event; 830 if (intr->ev_buffer_put == EV_QUEUE) { 831 intr->ev_buffer_put = 0; 832 } 833 return; 834 } 835 836 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 837 if (erdp < intr->er_start || 838 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 839 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 840 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 841 v, intr->er_start, intr->er_size); 842 xhci_die(xhci); 843 return; 844 } 845 846 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 847 assert(dp_idx < intr->er_size); 848 849 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 850 DPRINTF("xhci_event(): ER full, queueing\n"); 851 #ifndef ER_FULL_HACK 852 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 853 xhci_write_event(xhci, &full); 854 #endif 855 intr->er_full = 1; 856 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 857 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 858 return; 859 } 860 intr->ev_buffer[intr->ev_buffer_put++] = *event; 861 if (intr->ev_buffer_put == EV_QUEUE) { 862 intr->ev_buffer_put = 0; 863 } 864 } else { 865 xhci_write_event(xhci, event, v); 866 } 867 868 xhci_intr_raise(xhci, v); 869 } 870 871 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 872 dma_addr_t base) 873 { 874 ring->base = base; 875 ring->dequeue = base; 876 ring->ccs = 1; 877 } 878 879 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 880 dma_addr_t *addr) 881 { 882 while (1) { 883 TRBType type; 884 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 885 trb->addr = ring->dequeue; 886 trb->ccs = ring->ccs; 887 le64_to_cpus(&trb->parameter); 888 le32_to_cpus(&trb->status); 889 le32_to_cpus(&trb->control); 890 891 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 892 trb->parameter, trb->status, trb->control); 893 894 if ((trb->control & TRB_C) != ring->ccs) { 895 return 0; 896 } 897 898 type = TRB_TYPE(*trb); 899 900 if (type != TR_LINK) { 901 if (addr) { 902 *addr = ring->dequeue; 903 } 904 ring->dequeue += TRB_SIZE; 905 return type; 906 } else { 907 ring->dequeue = xhci_mask64(trb->parameter); 908 if (trb->control & TRB_LK_TC) { 909 ring->ccs = !ring->ccs; 910 } 911 } 912 } 913 } 914 915 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 916 { 917 XHCITRB trb; 918 int length = 0; 919 dma_addr_t dequeue = ring->dequeue; 920 bool ccs = ring->ccs; 921 /* hack to bundle together the two/three TDs that make a setup transfer */ 922 bool control_td_set = 0; 923 924 while (1) { 925 TRBType type; 926 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 927 le64_to_cpus(&trb.parameter); 928 le32_to_cpus(&trb.status); 929 le32_to_cpus(&trb.control); 930 931 if ((trb.control & TRB_C) != ccs) { 932 return -length; 933 } 934 935 type = TRB_TYPE(trb); 936 937 if (type == TR_LINK) { 938 dequeue = xhci_mask64(trb.parameter); 939 if (trb.control & TRB_LK_TC) { 940 ccs = !ccs; 941 } 942 continue; 943 } 944 945 length += 1; 946 dequeue += TRB_SIZE; 947 948 if (type == TR_SETUP) { 949 control_td_set = 1; 950 } else if (type == TR_STATUS) { 951 control_td_set = 0; 952 } 953 954 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 955 return length; 956 } 957 } 958 } 959 960 static void xhci_er_reset(XHCIState *xhci, int v) 961 { 962 XHCIInterrupter *intr = &xhci->intr[v]; 963 XHCIEvRingSeg seg; 964 965 /* cache the (sole) event ring segment location */ 966 if (intr->erstsz != 1) { 967 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 968 xhci_die(xhci); 969 return; 970 } 971 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 972 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 973 le32_to_cpus(&seg.addr_low); 974 le32_to_cpus(&seg.addr_high); 975 le32_to_cpus(&seg.size); 976 if (seg.size < 16 || seg.size > 4096) { 977 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 978 xhci_die(xhci); 979 return; 980 } 981 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 982 intr->er_size = seg.size; 983 984 intr->er_ep_idx = 0; 985 intr->er_pcs = 1; 986 intr->er_full = 0; 987 988 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 989 v, intr->er_start, intr->er_size); 990 } 991 992 static void xhci_run(XHCIState *xhci) 993 { 994 trace_usb_xhci_run(); 995 xhci->usbsts &= ~USBSTS_HCH; 996 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 997 } 998 999 static void xhci_stop(XHCIState *xhci) 1000 { 1001 trace_usb_xhci_stop(); 1002 xhci->usbsts |= USBSTS_HCH; 1003 xhci->crcr_low &= ~CRCR_CRR; 1004 } 1005 1006 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1007 uint32_t state) 1008 { 1009 uint32_t ctx[5]; 1010 if (epctx->state == state) { 1011 return; 1012 } 1013 1014 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1015 ctx[0] &= ~EP_STATE_MASK; 1016 ctx[0] |= state; 1017 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1018 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1019 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1020 epctx->pctx, state, ctx[3], ctx[2]); 1021 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1022 epctx->state = state; 1023 } 1024 1025 static void xhci_ep_kick_timer(void *opaque) 1026 { 1027 XHCIEPContext *epctx = opaque; 1028 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1029 } 1030 1031 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1032 unsigned int epid, dma_addr_t pctx, 1033 uint32_t *ctx) 1034 { 1035 XHCISlot *slot; 1036 XHCIEPContext *epctx; 1037 dma_addr_t dequeue; 1038 int i; 1039 1040 trace_usb_xhci_ep_enable(slotid, epid); 1041 assert(slotid >= 1 && slotid <= MAXSLOTS); 1042 assert(epid >= 1 && epid <= 31); 1043 1044 slot = &xhci->slots[slotid-1]; 1045 if (slot->eps[epid-1]) { 1046 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1047 return CC_TRB_ERROR; 1048 } 1049 1050 epctx = g_malloc(sizeof(XHCIEPContext)); 1051 memset(epctx, 0, sizeof(XHCIEPContext)); 1052 epctx->xhci = xhci; 1053 epctx->slotid = slotid; 1054 epctx->epid = epid; 1055 1056 slot->eps[epid-1] = epctx; 1057 1058 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1059 xhci_ring_init(xhci, &epctx->ring, dequeue); 1060 epctx->ring.ccs = ctx[2] & 1; 1061 1062 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1063 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1064 epctx->pctx = pctx; 1065 epctx->max_psize = ctx[1]>>16; 1066 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1067 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1068 epid/2, epid%2, epctx->max_psize); 1069 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1070 usb_packet_init(&epctx->transfers[i].packet); 1071 } 1072 1073 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1074 epctx->mfindex_last = 0; 1075 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1076 1077 epctx->state = EP_RUNNING; 1078 ctx[0] &= ~EP_STATE_MASK; 1079 ctx[0] |= EP_RUNNING; 1080 1081 return CC_SUCCESS; 1082 } 1083 1084 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1085 unsigned int epid) 1086 { 1087 XHCISlot *slot; 1088 XHCIEPContext *epctx; 1089 int i, xferi, killed = 0; 1090 assert(slotid >= 1 && slotid <= MAXSLOTS); 1091 assert(epid >= 1 && epid <= 31); 1092 1093 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1094 1095 slot = &xhci->slots[slotid-1]; 1096 1097 if (!slot->eps[epid-1]) { 1098 return 0; 1099 } 1100 1101 epctx = slot->eps[epid-1]; 1102 1103 xferi = epctx->next_xfer; 1104 for (i = 0; i < TD_QUEUE; i++) { 1105 XHCITransfer *t = &epctx->transfers[xferi]; 1106 if (t->running_async) { 1107 usb_cancel_packet(&t->packet); 1108 t->running_async = 0; 1109 t->cancelled = 1; 1110 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i); 1111 killed++; 1112 } 1113 if (t->running_retry) { 1114 t->running_retry = 0; 1115 epctx->retry = NULL; 1116 qemu_del_timer(epctx->kick_timer); 1117 } 1118 if (t->trbs) { 1119 g_free(t->trbs); 1120 } 1121 1122 t->trbs = NULL; 1123 t->trb_count = t->trb_alloced = 0; 1124 xferi = (xferi + 1) % TD_QUEUE; 1125 } 1126 return killed; 1127 } 1128 1129 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1130 unsigned int epid) 1131 { 1132 XHCISlot *slot; 1133 XHCIEPContext *epctx; 1134 1135 trace_usb_xhci_ep_disable(slotid, epid); 1136 assert(slotid >= 1 && slotid <= MAXSLOTS); 1137 assert(epid >= 1 && epid <= 31); 1138 1139 slot = &xhci->slots[slotid-1]; 1140 1141 if (!slot->eps[epid-1]) { 1142 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1143 return CC_SUCCESS; 1144 } 1145 1146 xhci_ep_nuke_xfers(xhci, slotid, epid); 1147 1148 epctx = slot->eps[epid-1]; 1149 1150 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1151 1152 qemu_free_timer(epctx->kick_timer); 1153 g_free(epctx); 1154 slot->eps[epid-1] = NULL; 1155 1156 return CC_SUCCESS; 1157 } 1158 1159 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1160 unsigned int epid) 1161 { 1162 XHCISlot *slot; 1163 XHCIEPContext *epctx; 1164 1165 trace_usb_xhci_ep_stop(slotid, epid); 1166 assert(slotid >= 1 && slotid <= MAXSLOTS); 1167 1168 if (epid < 1 || epid > 31) { 1169 fprintf(stderr, "xhci: bad ep %d\n", epid); 1170 return CC_TRB_ERROR; 1171 } 1172 1173 slot = &xhci->slots[slotid-1]; 1174 1175 if (!slot->eps[epid-1]) { 1176 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1177 return CC_EP_NOT_ENABLED_ERROR; 1178 } 1179 1180 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1181 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1182 "data might be lost\n"); 1183 } 1184 1185 epctx = slot->eps[epid-1]; 1186 1187 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1188 1189 return CC_SUCCESS; 1190 } 1191 1192 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1193 unsigned int epid) 1194 { 1195 XHCISlot *slot; 1196 XHCIEPContext *epctx; 1197 USBDevice *dev; 1198 1199 trace_usb_xhci_ep_reset(slotid, epid); 1200 assert(slotid >= 1 && slotid <= MAXSLOTS); 1201 1202 if (epid < 1 || epid > 31) { 1203 fprintf(stderr, "xhci: bad ep %d\n", epid); 1204 return CC_TRB_ERROR; 1205 } 1206 1207 slot = &xhci->slots[slotid-1]; 1208 1209 if (!slot->eps[epid-1]) { 1210 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1211 return CC_EP_NOT_ENABLED_ERROR; 1212 } 1213 1214 epctx = slot->eps[epid-1]; 1215 1216 if (epctx->state != EP_HALTED) { 1217 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1218 epid, epctx->state); 1219 return CC_CONTEXT_STATE_ERROR; 1220 } 1221 1222 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1223 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1224 "data might be lost\n"); 1225 } 1226 1227 uint8_t ep = epid>>1; 1228 1229 if (epid & 1) { 1230 ep |= 0x80; 1231 } 1232 1233 dev = xhci->slots[slotid-1].uport->dev; 1234 if (!dev) { 1235 return CC_USB_TRANSACTION_ERROR; 1236 } 1237 1238 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1239 1240 return CC_SUCCESS; 1241 } 1242 1243 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1244 unsigned int epid, uint64_t pdequeue) 1245 { 1246 XHCISlot *slot; 1247 XHCIEPContext *epctx; 1248 dma_addr_t dequeue; 1249 1250 assert(slotid >= 1 && slotid <= MAXSLOTS); 1251 1252 if (epid < 1 || epid > 31) { 1253 fprintf(stderr, "xhci: bad ep %d\n", epid); 1254 return CC_TRB_ERROR; 1255 } 1256 1257 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1258 dequeue = xhci_mask64(pdequeue); 1259 1260 slot = &xhci->slots[slotid-1]; 1261 1262 if (!slot->eps[epid-1]) { 1263 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1264 return CC_EP_NOT_ENABLED_ERROR; 1265 } 1266 1267 epctx = slot->eps[epid-1]; 1268 1269 1270 if (epctx->state != EP_STOPPED) { 1271 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1272 return CC_CONTEXT_STATE_ERROR; 1273 } 1274 1275 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1276 epctx->ring.ccs = dequeue & 1; 1277 1278 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1279 1280 return CC_SUCCESS; 1281 } 1282 1283 static int xhci_xfer_map(XHCITransfer *xfer) 1284 { 1285 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN); 1286 XHCIState *xhci = xfer->xhci; 1287 int i; 1288 1289 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1290 for (i = 0; i < xfer->trb_count; i++) { 1291 XHCITRB *trb = &xfer->trbs[i]; 1292 dma_addr_t addr; 1293 unsigned int chunk = 0; 1294 1295 switch (TRB_TYPE(*trb)) { 1296 case TR_DATA: 1297 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1298 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1299 goto err; 1300 } 1301 /* fallthrough */ 1302 case TR_NORMAL: 1303 case TR_ISOCH: 1304 addr = xhci_mask64(trb->parameter); 1305 chunk = trb->status & 0x1ffff; 1306 if (trb->control & TRB_TR_IDT) { 1307 if (chunk > 8 || in_xfer) { 1308 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1309 goto err; 1310 } 1311 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1312 } else { 1313 qemu_sglist_add(&xfer->sgl, addr, chunk); 1314 } 1315 break; 1316 } 1317 } 1318 1319 usb_packet_map(&xfer->packet, &xfer->sgl); 1320 return 0; 1321 1322 err: 1323 qemu_sglist_destroy(&xfer->sgl); 1324 xhci_die(xhci); 1325 return -1; 1326 } 1327 1328 static void xhci_xfer_unmap(XHCITransfer *xfer) 1329 { 1330 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1331 qemu_sglist_destroy(&xfer->sgl); 1332 } 1333 1334 static void xhci_xfer_report(XHCITransfer *xfer) 1335 { 1336 uint32_t edtla = 0; 1337 unsigned int left; 1338 bool reported = 0; 1339 bool shortpkt = 0; 1340 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1341 XHCIState *xhci = xfer->xhci; 1342 int i; 1343 1344 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1345 1346 for (i = 0; i < xfer->trb_count; i++) { 1347 XHCITRB *trb = &xfer->trbs[i]; 1348 unsigned int chunk = 0; 1349 1350 switch (TRB_TYPE(*trb)) { 1351 case TR_DATA: 1352 case TR_NORMAL: 1353 case TR_ISOCH: 1354 chunk = trb->status & 0x1ffff; 1355 if (chunk > left) { 1356 chunk = left; 1357 if (xfer->status == CC_SUCCESS) { 1358 shortpkt = 1; 1359 } 1360 } 1361 left -= chunk; 1362 edtla += chunk; 1363 break; 1364 case TR_STATUS: 1365 reported = 0; 1366 shortpkt = 0; 1367 break; 1368 } 1369 1370 if (!reported && ((trb->control & TRB_TR_IOC) || 1371 (shortpkt && (trb->control & TRB_TR_ISP)) || 1372 (xfer->status != CC_SUCCESS))) { 1373 event.slotid = xfer->slotid; 1374 event.epid = xfer->epid; 1375 event.length = (trb->status & 0x1ffff) - chunk; 1376 event.flags = 0; 1377 event.ptr = trb->addr; 1378 if (xfer->status == CC_SUCCESS) { 1379 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1380 } else { 1381 event.ccode = xfer->status; 1382 } 1383 if (TRB_TYPE(*trb) == TR_EVDATA) { 1384 event.ptr = trb->parameter; 1385 event.flags |= TRB_EV_ED; 1386 event.length = edtla & 0xffffff; 1387 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1388 edtla = 0; 1389 } 1390 xhci_event(xhci, &event, TRB_INTR(*trb)); 1391 reported = 1; 1392 if (xfer->status != CC_SUCCESS) { 1393 return; 1394 } 1395 } 1396 } 1397 } 1398 1399 static void xhci_stall_ep(XHCITransfer *xfer) 1400 { 1401 XHCIState *xhci = xfer->xhci; 1402 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1403 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1404 1405 epctx->ring.dequeue = xfer->trbs[0].addr; 1406 epctx->ring.ccs = xfer->trbs[0].ccs; 1407 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1408 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1409 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1410 } 1411 1412 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1413 XHCIEPContext *epctx); 1414 1415 static int xhci_setup_packet(XHCITransfer *xfer) 1416 { 1417 XHCIState *xhci = xfer->xhci; 1418 USBDevice *dev; 1419 USBEndpoint *ep; 1420 int dir; 1421 1422 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1423 1424 if (xfer->packet.ep) { 1425 ep = xfer->packet.ep; 1426 dev = ep->dev; 1427 } else { 1428 if (!xhci->slots[xfer->slotid-1].uport) { 1429 fprintf(stderr, "xhci: slot %d has no device\n", 1430 xfer->slotid); 1431 return -1; 1432 } 1433 dev = xhci->slots[xfer->slotid-1].uport->dev; 1434 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1435 } 1436 1437 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr); 1438 xhci_xfer_map(xfer); 1439 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1440 xfer->packet.pid, dev->addr, ep->nr); 1441 return 0; 1442 } 1443 1444 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1445 { 1446 if (ret == USB_RET_ASYNC) { 1447 trace_usb_xhci_xfer_async(xfer); 1448 xfer->running_async = 1; 1449 xfer->running_retry = 0; 1450 xfer->complete = 0; 1451 xfer->cancelled = 0; 1452 return 0; 1453 } else if (ret == USB_RET_NAK) { 1454 trace_usb_xhci_xfer_nak(xfer); 1455 xfer->running_async = 0; 1456 xfer->running_retry = 1; 1457 xfer->complete = 0; 1458 xfer->cancelled = 0; 1459 return 0; 1460 } else { 1461 xfer->running_async = 0; 1462 xfer->running_retry = 0; 1463 xfer->complete = 1; 1464 xhci_xfer_unmap(xfer); 1465 } 1466 1467 if (ret >= 0) { 1468 trace_usb_xhci_xfer_success(xfer, ret); 1469 xfer->status = CC_SUCCESS; 1470 xhci_xfer_report(xfer); 1471 return 0; 1472 } 1473 1474 /* error */ 1475 trace_usb_xhci_xfer_error(xfer, ret); 1476 switch (ret) { 1477 case USB_RET_NODEV: 1478 xfer->status = CC_USB_TRANSACTION_ERROR; 1479 xhci_xfer_report(xfer); 1480 xhci_stall_ep(xfer); 1481 break; 1482 case USB_RET_STALL: 1483 xfer->status = CC_STALL_ERROR; 1484 xhci_xfer_report(xfer); 1485 xhci_stall_ep(xfer); 1486 break; 1487 default: 1488 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1489 FIXME(); 1490 } 1491 return 0; 1492 } 1493 1494 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1495 { 1496 XHCITRB *trb_setup, *trb_status; 1497 uint8_t bmRequestType; 1498 int ret; 1499 1500 trb_setup = &xfer->trbs[0]; 1501 trb_status = &xfer->trbs[xfer->trb_count-1]; 1502 1503 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1504 1505 /* at most one Event Data TRB allowed after STATUS */ 1506 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1507 trb_status--; 1508 } 1509 1510 /* do some sanity checks */ 1511 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1512 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1513 TRB_TYPE(*trb_setup)); 1514 return -1; 1515 } 1516 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1517 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1518 TRB_TYPE(*trb_status)); 1519 return -1; 1520 } 1521 if (!(trb_setup->control & TRB_TR_IDT)) { 1522 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1523 return -1; 1524 } 1525 if ((trb_setup->status & 0x1ffff) != 8) { 1526 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1527 (trb_setup->status & 0x1ffff)); 1528 return -1; 1529 } 1530 1531 bmRequestType = trb_setup->parameter; 1532 1533 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1534 xfer->iso_xfer = false; 1535 1536 if (xhci_setup_packet(xfer) < 0) { 1537 return -1; 1538 } 1539 xfer->packet.parameter = trb_setup->parameter; 1540 1541 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1542 1543 xhci_complete_packet(xfer, ret); 1544 if (!xfer->running_async && !xfer->running_retry) { 1545 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1546 } 1547 return 0; 1548 } 1549 1550 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1551 XHCIEPContext *epctx, uint64_t mfindex) 1552 { 1553 if (xfer->trbs[0].control & TRB_TR_SIA) { 1554 uint64_t asap = ((mfindex + epctx->interval - 1) & 1555 ~(epctx->interval-1)); 1556 if (asap >= epctx->mfindex_last && 1557 asap <= epctx->mfindex_last + epctx->interval * 4) { 1558 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1559 } else { 1560 xfer->mfindex_kick = asap; 1561 } 1562 } else { 1563 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1564 & TRB_TR_FRAMEID_MASK; 1565 xfer->mfindex_kick |= mfindex & ~0x3fff; 1566 if (xfer->mfindex_kick < mfindex) { 1567 xfer->mfindex_kick += 0x4000; 1568 } 1569 } 1570 } 1571 1572 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1573 XHCIEPContext *epctx, uint64_t mfindex) 1574 { 1575 if (xfer->mfindex_kick > mfindex) { 1576 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1577 (xfer->mfindex_kick - mfindex) * 125000); 1578 xfer->running_retry = 1; 1579 } else { 1580 epctx->mfindex_last = xfer->mfindex_kick; 1581 qemu_del_timer(epctx->kick_timer); 1582 xfer->running_retry = 0; 1583 } 1584 } 1585 1586 1587 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1588 { 1589 uint64_t mfindex; 1590 int ret; 1591 1592 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1593 1594 xfer->in_xfer = epctx->type>>2; 1595 1596 switch(epctx->type) { 1597 case ET_INTR_OUT: 1598 case ET_INTR_IN: 1599 case ET_BULK_OUT: 1600 case ET_BULK_IN: 1601 xfer->pkts = 0; 1602 xfer->iso_xfer = false; 1603 break; 1604 case ET_ISO_OUT: 1605 case ET_ISO_IN: 1606 xfer->pkts = 1; 1607 xfer->iso_xfer = true; 1608 mfindex = xhci_mfindex_get(xhci); 1609 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1610 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1611 if (xfer->running_retry) { 1612 return -1; 1613 } 1614 break; 1615 default: 1616 fprintf(stderr, "xhci: unknown or unhandled EP " 1617 "(type %d, in %d, ep %02x)\n", 1618 epctx->type, xfer->in_xfer, xfer->epid); 1619 return -1; 1620 } 1621 1622 if (xhci_setup_packet(xfer) < 0) { 1623 return -1; 1624 } 1625 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1626 1627 xhci_complete_packet(xfer, ret); 1628 if (!xfer->running_async && !xfer->running_retry) { 1629 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1630 } 1631 return 0; 1632 } 1633 1634 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1635 { 1636 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1637 return xhci_submit(xhci, xfer, epctx); 1638 } 1639 1640 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1641 { 1642 XHCIEPContext *epctx; 1643 uint64_t mfindex; 1644 int length; 1645 int i; 1646 1647 trace_usb_xhci_ep_kick(slotid, epid); 1648 assert(slotid >= 1 && slotid <= MAXSLOTS); 1649 assert(epid >= 1 && epid <= 31); 1650 1651 if (!xhci->slots[slotid-1].enabled) { 1652 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1653 return; 1654 } 1655 epctx = xhci->slots[slotid-1].eps[epid-1]; 1656 if (!epctx) { 1657 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1658 epid, slotid); 1659 return; 1660 } 1661 1662 if (epctx->retry) { 1663 XHCITransfer *xfer = epctx->retry; 1664 int result; 1665 1666 trace_usb_xhci_xfer_retry(xfer); 1667 assert(xfer->running_retry); 1668 if (xfer->iso_xfer) { 1669 /* retry delayed iso transfer */ 1670 mfindex = xhci_mfindex_get(xhci); 1671 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1672 if (xfer->running_retry) { 1673 return; 1674 } 1675 if (xhci_setup_packet(xfer) < 0) { 1676 return; 1677 } 1678 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1679 assert(result != USB_RET_NAK); 1680 xhci_complete_packet(xfer, result); 1681 } else { 1682 /* retry nak'ed transfer */ 1683 if (xhci_setup_packet(xfer) < 0) { 1684 return; 1685 } 1686 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1687 if (result == USB_RET_NAK) { 1688 return; 1689 } 1690 xhci_complete_packet(xfer, result); 1691 } 1692 assert(!xfer->running_retry); 1693 epctx->retry = NULL; 1694 } 1695 1696 if (epctx->state == EP_HALTED) { 1697 DPRINTF("xhci: ep halted, not running schedule\n"); 1698 return; 1699 } 1700 1701 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1702 1703 while (1) { 1704 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1705 if (xfer->running_async || xfer->running_retry) { 1706 break; 1707 } 1708 length = xhci_ring_chain_length(xhci, &epctx->ring); 1709 if (length < 0) { 1710 break; 1711 } else if (length == 0) { 1712 break; 1713 } 1714 if (xfer->trbs && xfer->trb_alloced < length) { 1715 xfer->trb_count = 0; 1716 xfer->trb_alloced = 0; 1717 g_free(xfer->trbs); 1718 xfer->trbs = NULL; 1719 } 1720 if (!xfer->trbs) { 1721 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1722 xfer->trb_alloced = length; 1723 } 1724 xfer->trb_count = length; 1725 1726 for (i = 0; i < length; i++) { 1727 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1728 } 1729 xfer->xhci = xhci; 1730 xfer->epid = epid; 1731 xfer->slotid = slotid; 1732 1733 if (epid == 1) { 1734 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1735 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1736 } else { 1737 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1738 } 1739 } else { 1740 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1741 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1742 } else { 1743 if (!xfer->iso_xfer) { 1744 fprintf(stderr, "xhci: error firing data transfer\n"); 1745 } 1746 } 1747 } 1748 1749 if (epctx->state == EP_HALTED) { 1750 break; 1751 } 1752 if (xfer->running_retry) { 1753 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1754 epctx->retry = xfer; 1755 break; 1756 } 1757 } 1758 } 1759 1760 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1761 { 1762 trace_usb_xhci_slot_enable(slotid); 1763 assert(slotid >= 1 && slotid <= MAXSLOTS); 1764 xhci->slots[slotid-1].enabled = 1; 1765 xhci->slots[slotid-1].uport = NULL; 1766 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1767 1768 return CC_SUCCESS; 1769 } 1770 1771 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1772 { 1773 int i; 1774 1775 trace_usb_xhci_slot_disable(slotid); 1776 assert(slotid >= 1 && slotid <= MAXSLOTS); 1777 1778 for (i = 1; i <= 31; i++) { 1779 if (xhci->slots[slotid-1].eps[i-1]) { 1780 xhci_disable_ep(xhci, slotid, i); 1781 } 1782 } 1783 1784 xhci->slots[slotid-1].enabled = 0; 1785 return CC_SUCCESS; 1786 } 1787 1788 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1789 { 1790 USBPort *uport; 1791 char path[32]; 1792 int i, pos, port; 1793 1794 port = (slot_ctx[1]>>16) & 0xFF; 1795 port = xhci->ports[port-1].uport->index+1; 1796 pos = snprintf(path, sizeof(path), "%d", port); 1797 for (i = 0; i < 5; i++) { 1798 port = (slot_ctx[0] >> 4*i) & 0x0f; 1799 if (!port) { 1800 break; 1801 } 1802 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1803 } 1804 1805 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1806 if (strcmp(uport->path, path) == 0) { 1807 return uport; 1808 } 1809 } 1810 return NULL; 1811 } 1812 1813 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1814 uint64_t pictx, bool bsr) 1815 { 1816 XHCISlot *slot; 1817 USBPort *uport; 1818 USBDevice *dev; 1819 dma_addr_t ictx, octx, dcbaap; 1820 uint64_t poctx; 1821 uint32_t ictl_ctx[2]; 1822 uint32_t slot_ctx[4]; 1823 uint32_t ep0_ctx[5]; 1824 int i; 1825 TRBCCode res; 1826 1827 trace_usb_xhci_slot_address(slotid); 1828 assert(slotid >= 1 && slotid <= MAXSLOTS); 1829 1830 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1831 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1832 ictx = xhci_mask64(pictx); 1833 octx = xhci_mask64(le64_to_cpu(poctx)); 1834 1835 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1836 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1837 1838 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1839 1840 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1841 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1842 ictl_ctx[0], ictl_ctx[1]); 1843 return CC_TRB_ERROR; 1844 } 1845 1846 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1847 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1848 1849 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1850 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1851 1852 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1853 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1854 1855 uport = xhci_lookup_uport(xhci, slot_ctx); 1856 if (uport == NULL) { 1857 fprintf(stderr, "xhci: port not found\n"); 1858 return CC_TRB_ERROR; 1859 } 1860 1861 dev = uport->dev; 1862 if (!dev) { 1863 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1864 return CC_USB_TRANSACTION_ERROR; 1865 } 1866 1867 for (i = 0; i < MAXSLOTS; i++) { 1868 if (xhci->slots[i].uport == uport) { 1869 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1870 uport->path, i+1); 1871 return CC_TRB_ERROR; 1872 } 1873 } 1874 1875 slot = &xhci->slots[slotid-1]; 1876 slot->uport = uport; 1877 slot->ctx = octx; 1878 1879 if (bsr) { 1880 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1881 } else { 1882 slot->devaddr = xhci->devaddr++; 1883 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1884 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1885 usb_device_handle_control(dev, NULL, 1886 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1887 slot->devaddr, 0, 0, NULL); 1888 } 1889 1890 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1891 1892 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1893 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1894 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1895 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1896 1897 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1898 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1899 1900 return res; 1901 } 1902 1903 1904 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1905 uint64_t pictx, bool dc) 1906 { 1907 dma_addr_t ictx, octx; 1908 uint32_t ictl_ctx[2]; 1909 uint32_t slot_ctx[4]; 1910 uint32_t islot_ctx[4]; 1911 uint32_t ep_ctx[5]; 1912 int i; 1913 TRBCCode res; 1914 1915 trace_usb_xhci_slot_configure(slotid); 1916 assert(slotid >= 1 && slotid <= MAXSLOTS); 1917 1918 ictx = xhci_mask64(pictx); 1919 octx = xhci->slots[slotid-1].ctx; 1920 1921 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1922 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1923 1924 if (dc) { 1925 for (i = 2; i <= 31; i++) { 1926 if (xhci->slots[slotid-1].eps[i-1]) { 1927 xhci_disable_ep(xhci, slotid, i); 1928 } 1929 } 1930 1931 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1932 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1933 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1934 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1935 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1936 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1937 1938 return CC_SUCCESS; 1939 } 1940 1941 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1942 1943 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1944 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1945 ictl_ctx[0], ictl_ctx[1]); 1946 return CC_TRB_ERROR; 1947 } 1948 1949 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1950 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1951 1952 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1953 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1954 return CC_CONTEXT_STATE_ERROR; 1955 } 1956 1957 for (i = 2; i <= 31; i++) { 1958 if (ictl_ctx[0] & (1<<i)) { 1959 xhci_disable_ep(xhci, slotid, i); 1960 } 1961 if (ictl_ctx[1] & (1<<i)) { 1962 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1963 sizeof(ep_ctx)); 1964 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1965 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1966 ep_ctx[3], ep_ctx[4]); 1967 xhci_disable_ep(xhci, slotid, i); 1968 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1969 if (res != CC_SUCCESS) { 1970 return res; 1971 } 1972 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 1973 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1974 ep_ctx[3], ep_ctx[4]); 1975 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 1976 } 1977 } 1978 1979 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1980 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 1981 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 1982 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 1983 SLOT_CONTEXT_ENTRIES_SHIFT); 1984 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1985 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1986 1987 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1988 1989 return CC_SUCCESS; 1990 } 1991 1992 1993 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 1994 uint64_t pictx) 1995 { 1996 dma_addr_t ictx, octx; 1997 uint32_t ictl_ctx[2]; 1998 uint32_t iep0_ctx[5]; 1999 uint32_t ep0_ctx[5]; 2000 uint32_t islot_ctx[4]; 2001 uint32_t slot_ctx[4]; 2002 2003 trace_usb_xhci_slot_evaluate(slotid); 2004 assert(slotid >= 1 && slotid <= MAXSLOTS); 2005 2006 ictx = xhci_mask64(pictx); 2007 octx = xhci->slots[slotid-1].ctx; 2008 2009 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2010 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2011 2012 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 2013 2014 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2015 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2016 ictl_ctx[0], ictl_ctx[1]); 2017 return CC_TRB_ERROR; 2018 } 2019 2020 if (ictl_ctx[1] & 0x1) { 2021 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2022 2023 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2024 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2025 2026 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2027 2028 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2029 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2030 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2031 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2032 2033 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2034 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2035 2036 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2037 } 2038 2039 if (ictl_ctx[1] & 0x2) { 2040 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2041 2042 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2043 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2044 iep0_ctx[3], iep0_ctx[4]); 2045 2046 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2047 2048 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2049 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2050 2051 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2052 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2053 2054 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2055 } 2056 2057 return CC_SUCCESS; 2058 } 2059 2060 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2061 { 2062 uint32_t slot_ctx[4]; 2063 dma_addr_t octx; 2064 int i; 2065 2066 trace_usb_xhci_slot_reset(slotid); 2067 assert(slotid >= 1 && slotid <= MAXSLOTS); 2068 2069 octx = xhci->slots[slotid-1].ctx; 2070 2071 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2072 2073 for (i = 2; i <= 31; i++) { 2074 if (xhci->slots[slotid-1].eps[i-1]) { 2075 xhci_disable_ep(xhci, slotid, i); 2076 } 2077 } 2078 2079 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2080 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2081 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2082 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2083 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2084 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2085 2086 return CC_SUCCESS; 2087 } 2088 2089 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2090 { 2091 unsigned int slotid; 2092 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2093 if (slotid < 1 || slotid > MAXSLOTS) { 2094 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2095 event->ccode = CC_TRB_ERROR; 2096 return 0; 2097 } else if (!xhci->slots[slotid-1].enabled) { 2098 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2099 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2100 return 0; 2101 } 2102 return slotid; 2103 } 2104 2105 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2106 { 2107 dma_addr_t ctx; 2108 uint8_t bw_ctx[xhci->numports+1]; 2109 2110 DPRINTF("xhci_get_port_bandwidth()\n"); 2111 2112 ctx = xhci_mask64(pctx); 2113 2114 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2115 2116 /* TODO: actually implement real values here */ 2117 bw_ctx[0] = 0; 2118 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2119 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2120 2121 return CC_SUCCESS; 2122 } 2123 2124 static uint32_t rotl(uint32_t v, unsigned count) 2125 { 2126 count &= 31; 2127 return (v << count) | (v >> (32 - count)); 2128 } 2129 2130 2131 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2132 { 2133 uint32_t val; 2134 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2135 val += rotl(lo + 0x49434878, hi & 0x1F); 2136 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2137 return ~val; 2138 } 2139 2140 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2141 { 2142 uint32_t buf[8]; 2143 uint32_t obuf[8]; 2144 dma_addr_t paddr = xhci_mask64(addr); 2145 2146 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2147 2148 memcpy(obuf, buf, sizeof(obuf)); 2149 2150 if ((buf[0] & 0xff) == 2) { 2151 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2152 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2153 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2154 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2155 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2156 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2157 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2158 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2159 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2160 } 2161 2162 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2163 } 2164 2165 static void xhci_process_commands(XHCIState *xhci) 2166 { 2167 XHCITRB trb; 2168 TRBType type; 2169 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2170 dma_addr_t addr; 2171 unsigned int i, slotid = 0; 2172 2173 DPRINTF("xhci_process_commands()\n"); 2174 if (!xhci_running(xhci)) { 2175 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2176 return; 2177 } 2178 2179 xhci->crcr_low |= CRCR_CRR; 2180 2181 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2182 event.ptr = addr; 2183 switch (type) { 2184 case CR_ENABLE_SLOT: 2185 for (i = 0; i < MAXSLOTS; i++) { 2186 if (!xhci->slots[i].enabled) { 2187 break; 2188 } 2189 } 2190 if (i >= MAXSLOTS) { 2191 fprintf(stderr, "xhci: no device slots available\n"); 2192 event.ccode = CC_NO_SLOTS_ERROR; 2193 } else { 2194 slotid = i+1; 2195 event.ccode = xhci_enable_slot(xhci, slotid); 2196 } 2197 break; 2198 case CR_DISABLE_SLOT: 2199 slotid = xhci_get_slot(xhci, &event, &trb); 2200 if (slotid) { 2201 event.ccode = xhci_disable_slot(xhci, slotid); 2202 } 2203 break; 2204 case CR_ADDRESS_DEVICE: 2205 slotid = xhci_get_slot(xhci, &event, &trb); 2206 if (slotid) { 2207 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2208 trb.control & TRB_CR_BSR); 2209 } 2210 break; 2211 case CR_CONFIGURE_ENDPOINT: 2212 slotid = xhci_get_slot(xhci, &event, &trb); 2213 if (slotid) { 2214 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2215 trb.control & TRB_CR_DC); 2216 } 2217 break; 2218 case CR_EVALUATE_CONTEXT: 2219 slotid = xhci_get_slot(xhci, &event, &trb); 2220 if (slotid) { 2221 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2222 } 2223 break; 2224 case CR_STOP_ENDPOINT: 2225 slotid = xhci_get_slot(xhci, &event, &trb); 2226 if (slotid) { 2227 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2228 & TRB_CR_EPID_MASK; 2229 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2230 } 2231 break; 2232 case CR_RESET_ENDPOINT: 2233 slotid = xhci_get_slot(xhci, &event, &trb); 2234 if (slotid) { 2235 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2236 & TRB_CR_EPID_MASK; 2237 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2238 } 2239 break; 2240 case CR_SET_TR_DEQUEUE: 2241 slotid = xhci_get_slot(xhci, &event, &trb); 2242 if (slotid) { 2243 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2244 & TRB_CR_EPID_MASK; 2245 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2246 trb.parameter); 2247 } 2248 break; 2249 case CR_RESET_DEVICE: 2250 slotid = xhci_get_slot(xhci, &event, &trb); 2251 if (slotid) { 2252 event.ccode = xhci_reset_slot(xhci, slotid); 2253 } 2254 break; 2255 case CR_GET_PORT_BANDWIDTH: 2256 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2257 break; 2258 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2259 xhci_via_challenge(xhci, trb.parameter); 2260 break; 2261 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2262 event.type = 48; /* NEC reply */ 2263 event.length = 0x3025; 2264 break; 2265 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2266 { 2267 uint32_t chi = trb.parameter >> 32; 2268 uint32_t clo = trb.parameter; 2269 uint32_t val = xhci_nec_challenge(chi, clo); 2270 event.length = val & 0xFFFF; 2271 event.epid = val >> 16; 2272 slotid = val >> 24; 2273 event.type = 48; /* NEC reply */ 2274 } 2275 break; 2276 default: 2277 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2278 event.ccode = CC_TRB_ERROR; 2279 break; 2280 } 2281 event.slotid = slotid; 2282 xhci_event(xhci, &event, 0); 2283 } 2284 } 2285 2286 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2287 { 2288 port->portsc = PORTSC_PP; 2289 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2290 (1 << port->uport->dev->speed) & port->speedmask) { 2291 port->portsc |= PORTSC_CCS; 2292 switch (port->uport->dev->speed) { 2293 case USB_SPEED_LOW: 2294 port->portsc |= PORTSC_SPEED_LOW; 2295 break; 2296 case USB_SPEED_FULL: 2297 port->portsc |= PORTSC_SPEED_FULL; 2298 break; 2299 case USB_SPEED_HIGH: 2300 port->portsc |= PORTSC_SPEED_HIGH; 2301 break; 2302 case USB_SPEED_SUPER: 2303 port->portsc |= PORTSC_SPEED_SUPER; 2304 break; 2305 } 2306 } 2307 2308 if (xhci_running(xhci)) { 2309 port->portsc |= PORTSC_CSC; 2310 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2311 port->portnr << 24}; 2312 xhci_event(xhci, &ev, 0); 2313 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2314 } 2315 } 2316 2317 static void xhci_reset(DeviceState *dev) 2318 { 2319 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2320 int i; 2321 2322 trace_usb_xhci_reset(); 2323 if (!(xhci->usbsts & USBSTS_HCH)) { 2324 fprintf(stderr, "xhci: reset while running!\n"); 2325 } 2326 2327 xhci->usbcmd = 0; 2328 xhci->usbsts = USBSTS_HCH; 2329 xhci->dnctrl = 0; 2330 xhci->crcr_low = 0; 2331 xhci->crcr_high = 0; 2332 xhci->dcbaap_low = 0; 2333 xhci->dcbaap_high = 0; 2334 xhci->config = 0; 2335 xhci->devaddr = 2; 2336 2337 for (i = 0; i < MAXSLOTS; i++) { 2338 xhci_disable_slot(xhci, i+1); 2339 } 2340 2341 for (i = 0; i < xhci->numports; i++) { 2342 xhci_update_port(xhci, xhci->ports + i, 0); 2343 } 2344 2345 for (i = 0; i < MAXINTRS; i++) { 2346 xhci->intr[i].iman = 0; 2347 xhci->intr[i].imod = 0; 2348 xhci->intr[i].erstsz = 0; 2349 xhci->intr[i].erstba_low = 0; 2350 xhci->intr[i].erstba_high = 0; 2351 xhci->intr[i].erdp_low = 0; 2352 xhci->intr[i].erdp_high = 0; 2353 xhci->intr[i].msix_used = 0; 2354 2355 xhci->intr[i].er_ep_idx = 0; 2356 xhci->intr[i].er_pcs = 1; 2357 xhci->intr[i].er_full = 0; 2358 xhci->intr[i].ev_buffer_put = 0; 2359 xhci->intr[i].ev_buffer_get = 0; 2360 } 2361 2362 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2363 xhci_mfwrap_update(xhci); 2364 } 2365 2366 static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size) 2367 { 2368 XHCIState *xhci = ptr; 2369 uint32_t ret; 2370 2371 switch (reg) { 2372 case 0x00: /* HCIVERSION, CAPLENGTH */ 2373 ret = 0x01000000 | LEN_CAP; 2374 break; 2375 case 0x04: /* HCSPARAMS 1 */ 2376 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2377 | (MAXINTRS<<8) | MAXSLOTS; 2378 break; 2379 case 0x08: /* HCSPARAMS 2 */ 2380 ret = 0x0000000f; 2381 break; 2382 case 0x0c: /* HCSPARAMS 3 */ 2383 ret = 0x00000000; 2384 break; 2385 case 0x10: /* HCCPARAMS */ 2386 if (sizeof(dma_addr_t) == 4) { 2387 ret = 0x00081000; 2388 } else { 2389 ret = 0x00081001; 2390 } 2391 break; 2392 case 0x14: /* DBOFF */ 2393 ret = OFF_DOORBELL; 2394 break; 2395 case 0x18: /* RTSOFF */ 2396 ret = OFF_RUNTIME; 2397 break; 2398 2399 /* extended capabilities */ 2400 case 0x20: /* Supported Protocol:00 */ 2401 ret = 0x02000402; /* USB 2.0 */ 2402 break; 2403 case 0x24: /* Supported Protocol:04 */ 2404 ret = 0x20425455; /* "USB " */ 2405 break; 2406 case 0x28: /* Supported Protocol:08 */ 2407 ret = 0x00000001 | (xhci->numports_2<<8); 2408 break; 2409 case 0x2c: /* Supported Protocol:0c */ 2410 ret = 0x00000000; /* reserved */ 2411 break; 2412 case 0x30: /* Supported Protocol:00 */ 2413 ret = 0x03000002; /* USB 3.0 */ 2414 break; 2415 case 0x34: /* Supported Protocol:04 */ 2416 ret = 0x20425455; /* "USB " */ 2417 break; 2418 case 0x38: /* Supported Protocol:08 */ 2419 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2420 break; 2421 case 0x3c: /* Supported Protocol:0c */ 2422 ret = 0x00000000; /* reserved */ 2423 break; 2424 default: 2425 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2426 ret = 0; 2427 } 2428 2429 trace_usb_xhci_cap_read(reg, ret); 2430 return ret; 2431 } 2432 2433 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg) 2434 { 2435 uint32_t port = reg >> 4; 2436 uint32_t ret; 2437 2438 if (port >= xhci->numports) { 2439 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2440 ret = 0; 2441 goto out; 2442 } 2443 2444 switch (reg & 0xf) { 2445 case 0x00: /* PORTSC */ 2446 ret = xhci->ports[port].portsc; 2447 break; 2448 case 0x04: /* PORTPMSC */ 2449 case 0x08: /* PORTLI */ 2450 ret = 0; 2451 break; 2452 case 0x0c: /* reserved */ 2453 default: 2454 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2455 port, reg); 2456 ret = 0; 2457 } 2458 2459 out: 2460 trace_usb_xhci_port_read(port, reg & 0x0f, ret); 2461 return ret; 2462 } 2463 2464 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2465 { 2466 uint32_t port = reg >> 4; 2467 uint32_t portsc; 2468 2469 trace_usb_xhci_port_write(port, reg & 0x0f, val); 2470 2471 if (port >= xhci->numports) { 2472 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2473 return; 2474 } 2475 2476 switch (reg & 0xf) { 2477 case 0x00: /* PORTSC */ 2478 portsc = xhci->ports[port].portsc; 2479 /* write-1-to-clear bits*/ 2480 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2481 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2482 if (val & PORTSC_LWS) { 2483 /* overwrite PLS only when LWS=1 */ 2484 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2485 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2486 } 2487 /* read/write bits */ 2488 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2489 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2490 /* write-1-to-start bits */ 2491 if (val & PORTSC_PR) { 2492 DPRINTF("xhci: port %d reset\n", port); 2493 usb_device_reset(xhci->ports[port].uport->dev); 2494 portsc |= PORTSC_PRC | PORTSC_PED; 2495 } 2496 xhci->ports[port].portsc = portsc; 2497 break; 2498 case 0x04: /* PORTPMSC */ 2499 case 0x08: /* PORTLI */ 2500 default: 2501 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2502 port, reg); 2503 } 2504 } 2505 2506 static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size) 2507 { 2508 XHCIState *xhci = ptr; 2509 uint32_t ret; 2510 2511 if (reg >= 0x400) { 2512 return xhci_port_read(xhci, reg - 0x400); 2513 } 2514 2515 switch (reg) { 2516 case 0x00: /* USBCMD */ 2517 ret = xhci->usbcmd; 2518 break; 2519 case 0x04: /* USBSTS */ 2520 ret = xhci->usbsts; 2521 break; 2522 case 0x08: /* PAGESIZE */ 2523 ret = 1; /* 4KiB */ 2524 break; 2525 case 0x14: /* DNCTRL */ 2526 ret = xhci->dnctrl; 2527 break; 2528 case 0x18: /* CRCR low */ 2529 ret = xhci->crcr_low & ~0xe; 2530 break; 2531 case 0x1c: /* CRCR high */ 2532 ret = xhci->crcr_high; 2533 break; 2534 case 0x30: /* DCBAAP low */ 2535 ret = xhci->dcbaap_low; 2536 break; 2537 case 0x34: /* DCBAAP high */ 2538 ret = xhci->dcbaap_high; 2539 break; 2540 case 0x38: /* CONFIG */ 2541 ret = xhci->config; 2542 break; 2543 default: 2544 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2545 ret = 0; 2546 } 2547 2548 trace_usb_xhci_oper_read(reg, ret); 2549 return ret; 2550 } 2551 2552 static void xhci_oper_write(void *ptr, target_phys_addr_t reg, 2553 uint64_t val, unsigned size) 2554 { 2555 XHCIState *xhci = ptr; 2556 2557 if (reg >= 0x400) { 2558 xhci_port_write(xhci, reg - 0x400, val); 2559 return; 2560 } 2561 2562 trace_usb_xhci_oper_write(reg, val); 2563 2564 switch (reg) { 2565 case 0x00: /* USBCMD */ 2566 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2567 xhci_run(xhci); 2568 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2569 xhci_stop(xhci); 2570 } 2571 xhci->usbcmd = val & 0xc0f; 2572 xhci_mfwrap_update(xhci); 2573 if (val & USBCMD_HCRST) { 2574 xhci_reset(&xhci->pci_dev.qdev); 2575 } 2576 xhci_intx_update(xhci); 2577 break; 2578 2579 case 0x04: /* USBSTS */ 2580 /* these bits are write-1-to-clear */ 2581 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2582 xhci_intx_update(xhci); 2583 break; 2584 2585 case 0x14: /* DNCTRL */ 2586 xhci->dnctrl = val & 0xffff; 2587 break; 2588 case 0x18: /* CRCR low */ 2589 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2590 break; 2591 case 0x1c: /* CRCR high */ 2592 xhci->crcr_high = val; 2593 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2594 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2595 xhci->crcr_low &= ~CRCR_CRR; 2596 xhci_event(xhci, &event, 0); 2597 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2598 } else { 2599 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2600 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2601 } 2602 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2603 break; 2604 case 0x30: /* DCBAAP low */ 2605 xhci->dcbaap_low = val & 0xffffffc0; 2606 break; 2607 case 0x34: /* DCBAAP high */ 2608 xhci->dcbaap_high = val; 2609 break; 2610 case 0x38: /* CONFIG */ 2611 xhci->config = val & 0xff; 2612 break; 2613 default: 2614 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2615 } 2616 } 2617 2618 static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg, 2619 unsigned size) 2620 { 2621 XHCIState *xhci = ptr; 2622 uint32_t ret = 0; 2623 2624 if (reg < 0x20) { 2625 switch (reg) { 2626 case 0x00: /* MFINDEX */ 2627 ret = xhci_mfindex_get(xhci) & 0x3fff; 2628 break; 2629 default: 2630 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2631 (int)reg); 2632 break; 2633 } 2634 } else { 2635 int v = (reg - 0x20) / 0x20; 2636 XHCIInterrupter *intr = &xhci->intr[v]; 2637 switch (reg & 0x1f) { 2638 case 0x00: /* IMAN */ 2639 ret = intr->iman; 2640 break; 2641 case 0x04: /* IMOD */ 2642 ret = intr->imod; 2643 break; 2644 case 0x08: /* ERSTSZ */ 2645 ret = intr->erstsz; 2646 break; 2647 case 0x10: /* ERSTBA low */ 2648 ret = intr->erstba_low; 2649 break; 2650 case 0x14: /* ERSTBA high */ 2651 ret = intr->erstba_high; 2652 break; 2653 case 0x18: /* ERDP low */ 2654 ret = intr->erdp_low; 2655 break; 2656 case 0x1c: /* ERDP high */ 2657 ret = intr->erdp_high; 2658 break; 2659 } 2660 } 2661 2662 trace_usb_xhci_runtime_read(reg, ret); 2663 return ret; 2664 } 2665 2666 static void xhci_runtime_write(void *ptr, target_phys_addr_t reg, 2667 uint64_t val, unsigned size) 2668 { 2669 XHCIState *xhci = ptr; 2670 int v = (reg - 0x20) / 0x20; 2671 XHCIInterrupter *intr = &xhci->intr[v]; 2672 trace_usb_xhci_runtime_write(reg, val); 2673 2674 if (reg < 0x20) { 2675 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2676 return; 2677 } 2678 2679 switch (reg & 0x1f) { 2680 case 0x00: /* IMAN */ 2681 if (val & IMAN_IP) { 2682 intr->iman &= ~IMAN_IP; 2683 } 2684 intr->iman &= ~IMAN_IE; 2685 intr->iman |= val & IMAN_IE; 2686 if (v == 0) { 2687 xhci_intx_update(xhci); 2688 } 2689 xhci_msix_update(xhci, v); 2690 break; 2691 case 0x04: /* IMOD */ 2692 intr->imod = val; 2693 break; 2694 case 0x08: /* ERSTSZ */ 2695 intr->erstsz = val & 0xffff; 2696 break; 2697 case 0x10: /* ERSTBA low */ 2698 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2699 intr->erstba_low = val & 0xffffffc0; */ 2700 intr->erstba_low = val & 0xfffffff0; 2701 break; 2702 case 0x14: /* ERSTBA high */ 2703 intr->erstba_high = val; 2704 xhci_er_reset(xhci, v); 2705 break; 2706 case 0x18: /* ERDP low */ 2707 if (val & ERDP_EHB) { 2708 intr->erdp_low &= ~ERDP_EHB; 2709 } 2710 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2711 break; 2712 case 0x1c: /* ERDP high */ 2713 intr->erdp_high = val; 2714 xhci_events_update(xhci, v); 2715 break; 2716 default: 2717 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2718 (int)reg); 2719 } 2720 } 2721 2722 static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg, 2723 unsigned size) 2724 { 2725 /* doorbells always read as 0 */ 2726 trace_usb_xhci_doorbell_read(reg, 0); 2727 return 0; 2728 } 2729 2730 static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg, 2731 uint64_t val, unsigned size) 2732 { 2733 XHCIState *xhci = ptr; 2734 2735 trace_usb_xhci_doorbell_write(reg, val); 2736 2737 if (!xhci_running(xhci)) { 2738 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2739 return; 2740 } 2741 2742 reg >>= 2; 2743 2744 if (reg == 0) { 2745 if (val == 0) { 2746 xhci_process_commands(xhci); 2747 } else { 2748 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2749 (uint32_t)val); 2750 } 2751 } else { 2752 if (reg > MAXSLOTS) { 2753 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2754 } else if (val > 31) { 2755 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2756 (int)reg, (uint32_t)val); 2757 } else { 2758 xhci_kick_ep(xhci, reg, val); 2759 } 2760 } 2761 } 2762 2763 static const MemoryRegionOps xhci_cap_ops = { 2764 .read = xhci_cap_read, 2765 .valid.min_access_size = 1, 2766 .valid.max_access_size = 4, 2767 .impl.min_access_size = 4, 2768 .impl.max_access_size = 4, 2769 .endianness = DEVICE_LITTLE_ENDIAN, 2770 }; 2771 2772 static const MemoryRegionOps xhci_oper_ops = { 2773 .read = xhci_oper_read, 2774 .write = xhci_oper_write, 2775 .valid.min_access_size = 4, 2776 .valid.max_access_size = 4, 2777 .endianness = DEVICE_LITTLE_ENDIAN, 2778 }; 2779 2780 static const MemoryRegionOps xhci_runtime_ops = { 2781 .read = xhci_runtime_read, 2782 .write = xhci_runtime_write, 2783 .valid.min_access_size = 4, 2784 .valid.max_access_size = 4, 2785 .endianness = DEVICE_LITTLE_ENDIAN, 2786 }; 2787 2788 static const MemoryRegionOps xhci_doorbell_ops = { 2789 .read = xhci_doorbell_read, 2790 .write = xhci_doorbell_write, 2791 .valid.min_access_size = 4, 2792 .valid.max_access_size = 4, 2793 .endianness = DEVICE_LITTLE_ENDIAN, 2794 }; 2795 2796 static void xhci_attach(USBPort *usbport) 2797 { 2798 XHCIState *xhci = usbport->opaque; 2799 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2800 2801 xhci_update_port(xhci, port, 0); 2802 } 2803 2804 static void xhci_detach(USBPort *usbport) 2805 { 2806 XHCIState *xhci = usbport->opaque; 2807 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2808 2809 xhci_update_port(xhci, port, 1); 2810 } 2811 2812 static void xhci_wakeup(USBPort *usbport) 2813 { 2814 XHCIState *xhci = usbport->opaque; 2815 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2816 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2817 port->portnr << 24}; 2818 uint32_t pls; 2819 2820 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2821 if (pls != 3) { 2822 return; 2823 } 2824 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2825 if (port->portsc & PORTSC_PLC) { 2826 return; 2827 } 2828 port->portsc |= PORTSC_PLC; 2829 xhci_event(xhci, &ev, 0); 2830 } 2831 2832 static void xhci_complete(USBPort *port, USBPacket *packet) 2833 { 2834 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2835 2836 xhci_complete_packet(xfer, packet->result); 2837 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2838 } 2839 2840 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2841 { 2842 USBBus *bus = usb_bus_from_device(child); 2843 XHCIState *xhci = container_of(bus, XHCIState, bus); 2844 int i; 2845 2846 for (i = 0; i < MAXSLOTS; i++) { 2847 if (xhci->slots[i].uport == uport) { 2848 xhci->slots[i].uport = NULL; 2849 } 2850 } 2851 } 2852 2853 static USBPortOps xhci_port_ops = { 2854 .attach = xhci_attach, 2855 .detach = xhci_detach, 2856 .wakeup = xhci_wakeup, 2857 .complete = xhci_complete, 2858 .child_detach = xhci_child_detach, 2859 }; 2860 2861 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2862 { 2863 XHCISlot *slot; 2864 int slotid; 2865 2866 for (slotid = 1; slotid <= MAXSLOTS; slotid++) { 2867 slot = &xhci->slots[slotid-1]; 2868 if (slot->devaddr == dev->addr) { 2869 return slotid; 2870 } 2871 } 2872 return 0; 2873 } 2874 2875 static int xhci_find_epid(USBEndpoint *ep) 2876 { 2877 if (ep->nr == 0) { 2878 return 1; 2879 } 2880 if (ep->pid == USB_TOKEN_IN) { 2881 return ep->nr * 2 + 1; 2882 } else { 2883 return ep->nr * 2; 2884 } 2885 } 2886 2887 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2888 { 2889 XHCIState *xhci = container_of(bus, XHCIState, bus); 2890 int slotid; 2891 2892 DPRINTF("%s\n", __func__); 2893 slotid = xhci_find_slotid(xhci, ep->dev); 2894 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2895 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2896 return; 2897 } 2898 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2899 } 2900 2901 static USBBusOps xhci_bus_ops = { 2902 .wakeup_endpoint = xhci_wakeup_endpoint, 2903 }; 2904 2905 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2906 { 2907 XHCIPort *port; 2908 int i, usbports, speedmask; 2909 2910 xhci->usbsts = USBSTS_HCH; 2911 2912 if (xhci->numports_2 > MAXPORTS_2) { 2913 xhci->numports_2 = MAXPORTS_2; 2914 } 2915 if (xhci->numports_3 > MAXPORTS_3) { 2916 xhci->numports_3 = MAXPORTS_3; 2917 } 2918 usbports = MAX(xhci->numports_2, xhci->numports_3); 2919 xhci->numports = xhci->numports_2 + xhci->numports_3; 2920 2921 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2922 2923 for (i = 0; i < usbports; i++) { 2924 speedmask = 0; 2925 if (i < xhci->numports_2) { 2926 port = &xhci->ports[i]; 2927 port->portnr = i + 1; 2928 port->uport = &xhci->uports[i]; 2929 port->speedmask = 2930 USB_SPEED_MASK_LOW | 2931 USB_SPEED_MASK_FULL | 2932 USB_SPEED_MASK_HIGH; 2933 speedmask |= port->speedmask; 2934 } 2935 if (i < xhci->numports_3) { 2936 port = &xhci->ports[i + xhci->numports_2]; 2937 port->portnr = i + 1 + xhci->numports_2; 2938 port->uport = &xhci->uports[i]; 2939 port->speedmask = USB_SPEED_MASK_SUPER; 2940 speedmask |= port->speedmask; 2941 } 2942 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2943 &xhci_port_ops, speedmask); 2944 } 2945 } 2946 2947 static int usb_xhci_initfn(struct PCIDevice *dev) 2948 { 2949 int ret; 2950 2951 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2952 2953 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2954 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2955 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2956 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2957 2958 usb_xhci_init(xhci, &dev->qdev); 2959 2960 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2961 2962 xhci->irq = xhci->pci_dev.irq[0]; 2963 2964 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 2965 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 2966 "capabilities", LEN_CAP); 2967 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 2968 "operational", 0x400 + 0x10 * xhci->numports); 2969 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 2970 "runtime", LEN_RUNTIME); 2971 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 2972 "doorbell", LEN_DOORBELL); 2973 2974 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 2975 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 2976 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 2977 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 2978 2979 pci_register_bar(&xhci->pci_dev, 0, 2980 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 2981 &xhci->mem); 2982 2983 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 2984 assert(ret >= 0); 2985 2986 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 2987 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); 2988 } 2989 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 2990 msix_init(&xhci->pci_dev, MAXINTRS, 2991 &xhci->mem, 0, OFF_MSIX_TABLE, 2992 &xhci->mem, 0, OFF_MSIX_PBA, 2993 0x90); 2994 } 2995 2996 return 0; 2997 } 2998 2999 static const VMStateDescription vmstate_xhci = { 3000 .name = "xhci", 3001 .unmigratable = 1, 3002 }; 3003 3004 static Property xhci_properties[] = { 3005 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3006 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3007 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3008 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3009 DEFINE_PROP_END_OF_LIST(), 3010 }; 3011 3012 static void xhci_class_init(ObjectClass *klass, void *data) 3013 { 3014 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3015 DeviceClass *dc = DEVICE_CLASS(klass); 3016 3017 dc->vmsd = &vmstate_xhci; 3018 dc->props = xhci_properties; 3019 dc->reset = xhci_reset; 3020 k->init = usb_xhci_initfn; 3021 k->vendor_id = PCI_VENDOR_ID_NEC; 3022 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3023 k->class_id = PCI_CLASS_SERIAL_USB; 3024 k->revision = 0x03; 3025 k->is_express = 1; 3026 } 3027 3028 static TypeInfo xhci_info = { 3029 .name = "nec-usb-xhci", 3030 .parent = TYPE_PCI_DEVICE, 3031 .instance_size = sizeof(XHCIState), 3032 .class_init = xhci_class_init, 3033 }; 3034 3035 static void xhci_register_types(void) 3036 { 3037 type_register_static(&xhci_info); 3038 } 3039 3040 type_init(xhci_register_types) 3041