1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 unsigned int streamid; 355 bool in_xfer; 356 bool iso_xfer; 357 bool timed_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 unsigned int next_xfer; 385 unsigned int comp_xfer; 386 XHCITransfer transfers[TD_QUEUE]; 387 XHCITransfer *retry; 388 EPType type; 389 dma_addr_t pctx; 390 unsigned int max_psize; 391 uint32_t state; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs, er_full; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 XHCIEvent ev_buffer[EV_QUEUE]; 439 unsigned int ev_buffer_put; 440 unsigned int ev_buffer_get; 441 442 } XHCIInterrupter; 443 444 struct XHCIState { 445 /*< private >*/ 446 PCIDevice parent_obj; 447 /*< public >*/ 448 449 USBBus bus; 450 qemu_irq irq; 451 MemoryRegion mem; 452 MemoryRegion mem_cap; 453 MemoryRegion mem_oper; 454 MemoryRegion mem_runtime; 455 MemoryRegion mem_doorbell; 456 457 /* properties */ 458 uint32_t numports_2; 459 uint32_t numports_3; 460 uint32_t numintrs; 461 uint32_t numslots; 462 uint32_t flags; 463 464 /* Operational Registers */ 465 uint32_t usbcmd; 466 uint32_t usbsts; 467 uint32_t dnctrl; 468 uint32_t crcr_low; 469 uint32_t crcr_high; 470 uint32_t dcbaap_low; 471 uint32_t dcbaap_high; 472 uint32_t config; 473 474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 475 XHCIPort ports[MAXPORTS]; 476 XHCISlot slots[MAXSLOTS]; 477 uint32_t numports; 478 479 /* Runtime Registers */ 480 int64_t mfindex_start; 481 QEMUTimer *mfwrap_timer; 482 XHCIInterrupter intr[MAXINTRS]; 483 484 XHCIRing cmd_ring; 485 }; 486 487 #define TYPE_XHCI "nec-usb-xhci" 488 489 #define XHCI(obj) \ 490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 491 492 typedef struct XHCIEvRingSeg { 493 uint32_t addr_low; 494 uint32_t addr_high; 495 uint32_t size; 496 uint32_t rsvd; 497 } XHCIEvRingSeg; 498 499 enum xhci_flags { 500 XHCI_FLAG_USE_MSI = 1, 501 XHCI_FLAG_USE_MSI_X, 502 }; 503 504 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 505 unsigned int epid, unsigned int streamid); 506 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 507 unsigned int epid); 508 static void xhci_xfer_report(XHCITransfer *xfer); 509 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 510 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 511 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 512 unsigned int slotid, unsigned int epid); 513 514 static const char *TRBType_names[] = { 515 [TRB_RESERVED] = "TRB_RESERVED", 516 [TR_NORMAL] = "TR_NORMAL", 517 [TR_SETUP] = "TR_SETUP", 518 [TR_DATA] = "TR_DATA", 519 [TR_STATUS] = "TR_STATUS", 520 [TR_ISOCH] = "TR_ISOCH", 521 [TR_LINK] = "TR_LINK", 522 [TR_EVDATA] = "TR_EVDATA", 523 [TR_NOOP] = "TR_NOOP", 524 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 525 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 526 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 527 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 528 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 529 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 530 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 531 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 532 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 533 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 534 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 535 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 536 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 537 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 538 [CR_NOOP] = "CR_NOOP", 539 [ER_TRANSFER] = "ER_TRANSFER", 540 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 541 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 542 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 543 [ER_DOORBELL] = "ER_DOORBELL", 544 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 545 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 546 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 547 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 548 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 549 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 550 }; 551 552 static const char *TRBCCode_names[] = { 553 [CC_INVALID] = "CC_INVALID", 554 [CC_SUCCESS] = "CC_SUCCESS", 555 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 556 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 557 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 558 [CC_TRB_ERROR] = "CC_TRB_ERROR", 559 [CC_STALL_ERROR] = "CC_STALL_ERROR", 560 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 561 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 562 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 563 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 564 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 565 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 566 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 567 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 568 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 569 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 570 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 571 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 572 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 573 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 574 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 575 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 576 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 577 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 578 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 579 [CC_STOPPED] = "CC_STOPPED", 580 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 581 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 582 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 583 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 584 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 585 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 586 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 587 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 588 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 589 }; 590 591 static const char *ep_state_names[] = { 592 [EP_DISABLED] = "disabled", 593 [EP_RUNNING] = "running", 594 [EP_HALTED] = "halted", 595 [EP_STOPPED] = "stopped", 596 [EP_ERROR] = "error", 597 }; 598 599 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 600 { 601 if (index >= llen || list[index] == NULL) { 602 return "???"; 603 } 604 return list[index]; 605 } 606 607 static const char *trb_name(XHCITRB *trb) 608 { 609 return lookup_name(TRB_TYPE(*trb), TRBType_names, 610 ARRAY_SIZE(TRBType_names)); 611 } 612 613 static const char *event_name(XHCIEvent *event) 614 { 615 return lookup_name(event->ccode, TRBCCode_names, 616 ARRAY_SIZE(TRBCCode_names)); 617 } 618 619 static const char *ep_state_name(uint32_t state) 620 { 621 return lookup_name(state, ep_state_names, 622 ARRAY_SIZE(ep_state_names)); 623 } 624 625 static uint64_t xhci_mfindex_get(XHCIState *xhci) 626 { 627 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 628 return (now - xhci->mfindex_start) / 125000; 629 } 630 631 static void xhci_mfwrap_update(XHCIState *xhci) 632 { 633 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 634 uint32_t mfindex, left; 635 int64_t now; 636 637 if ((xhci->usbcmd & bits) == bits) { 638 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 639 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 640 left = 0x4000 - mfindex; 641 timer_mod(xhci->mfwrap_timer, now + left * 125000); 642 } else { 643 timer_del(xhci->mfwrap_timer); 644 } 645 } 646 647 static void xhci_mfwrap_timer(void *opaque) 648 { 649 XHCIState *xhci = opaque; 650 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 651 652 xhci_event(xhci, &wrap, 0); 653 xhci_mfwrap_update(xhci); 654 } 655 656 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 657 { 658 if (sizeof(dma_addr_t) == 4) { 659 return low; 660 } else { 661 return low | (((dma_addr_t)high << 16) << 16); 662 } 663 } 664 665 static inline dma_addr_t xhci_mask64(uint64_t addr) 666 { 667 if (sizeof(dma_addr_t) == 4) { 668 return addr & 0xffffffff; 669 } else { 670 return addr; 671 } 672 } 673 674 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 675 uint32_t *buf, size_t len) 676 { 677 int i; 678 679 assert((len % sizeof(uint32_t)) == 0); 680 681 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 682 683 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 684 buf[i] = le32_to_cpu(buf[i]); 685 } 686 } 687 688 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 689 uint32_t *buf, size_t len) 690 { 691 int i; 692 uint32_t tmp[len / sizeof(uint32_t)]; 693 694 assert((len % sizeof(uint32_t)) == 0); 695 696 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 697 tmp[i] = cpu_to_le32(buf[i]); 698 } 699 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 700 } 701 702 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 703 { 704 int index; 705 706 if (!uport->dev) { 707 return NULL; 708 } 709 switch (uport->dev->speed) { 710 case USB_SPEED_LOW: 711 case USB_SPEED_FULL: 712 case USB_SPEED_HIGH: 713 index = uport->index; 714 break; 715 case USB_SPEED_SUPER: 716 index = uport->index + xhci->numports_2; 717 break; 718 default: 719 return NULL; 720 } 721 return &xhci->ports[index]; 722 } 723 724 static void xhci_intx_update(XHCIState *xhci) 725 { 726 PCIDevice *pci_dev = PCI_DEVICE(xhci); 727 int level = 0; 728 729 if (msix_enabled(pci_dev) || 730 msi_enabled(pci_dev)) { 731 return; 732 } 733 734 if (xhci->intr[0].iman & IMAN_IP && 735 xhci->intr[0].iman & IMAN_IE && 736 xhci->usbcmd & USBCMD_INTE) { 737 level = 1; 738 } 739 740 trace_usb_xhci_irq_intx(level); 741 qemu_set_irq(xhci->irq, level); 742 } 743 744 static void xhci_msix_update(XHCIState *xhci, int v) 745 { 746 PCIDevice *pci_dev = PCI_DEVICE(xhci); 747 bool enabled; 748 749 if (!msix_enabled(pci_dev)) { 750 return; 751 } 752 753 enabled = xhci->intr[v].iman & IMAN_IE; 754 if (enabled == xhci->intr[v].msix_used) { 755 return; 756 } 757 758 if (enabled) { 759 trace_usb_xhci_irq_msix_use(v); 760 msix_vector_use(pci_dev, v); 761 xhci->intr[v].msix_used = true; 762 } else { 763 trace_usb_xhci_irq_msix_unuse(v); 764 msix_vector_unuse(pci_dev, v); 765 xhci->intr[v].msix_used = false; 766 } 767 } 768 769 static void xhci_intr_raise(XHCIState *xhci, int v) 770 { 771 PCIDevice *pci_dev = PCI_DEVICE(xhci); 772 773 xhci->intr[v].erdp_low |= ERDP_EHB; 774 xhci->intr[v].iman |= IMAN_IP; 775 xhci->usbsts |= USBSTS_EINT; 776 777 if (!(xhci->intr[v].iman & IMAN_IE)) { 778 return; 779 } 780 781 if (!(xhci->usbcmd & USBCMD_INTE)) { 782 return; 783 } 784 785 if (msix_enabled(pci_dev)) { 786 trace_usb_xhci_irq_msix(v); 787 msix_notify(pci_dev, v); 788 return; 789 } 790 791 if (msi_enabled(pci_dev)) { 792 trace_usb_xhci_irq_msi(v); 793 msi_notify(pci_dev, v); 794 return; 795 } 796 797 if (v == 0) { 798 trace_usb_xhci_irq_intx(1); 799 qemu_set_irq(xhci->irq, 1); 800 } 801 } 802 803 static inline int xhci_running(XHCIState *xhci) 804 { 805 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 806 } 807 808 static void xhci_die(XHCIState *xhci) 809 { 810 xhci->usbsts |= USBSTS_HCE; 811 fprintf(stderr, "xhci: asserted controller error\n"); 812 } 813 814 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 815 { 816 PCIDevice *pci_dev = PCI_DEVICE(xhci); 817 XHCIInterrupter *intr = &xhci->intr[v]; 818 XHCITRB ev_trb; 819 dma_addr_t addr; 820 821 ev_trb.parameter = cpu_to_le64(event->ptr); 822 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 823 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 824 event->flags | (event->type << TRB_TYPE_SHIFT); 825 if (intr->er_pcs) { 826 ev_trb.control |= TRB_C; 827 } 828 ev_trb.control = cpu_to_le32(ev_trb.control); 829 830 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 831 event_name(event), ev_trb.parameter, 832 ev_trb.status, ev_trb.control); 833 834 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 835 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 836 837 intr->er_ep_idx++; 838 if (intr->er_ep_idx >= intr->er_size) { 839 intr->er_ep_idx = 0; 840 intr->er_pcs = !intr->er_pcs; 841 } 842 } 843 844 static void xhci_events_update(XHCIState *xhci, int v) 845 { 846 XHCIInterrupter *intr = &xhci->intr[v]; 847 dma_addr_t erdp; 848 unsigned int dp_idx; 849 bool do_irq = 0; 850 851 if (xhci->usbsts & USBSTS_HCH) { 852 return; 853 } 854 855 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 856 if (erdp < intr->er_start || 857 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 858 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 859 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 860 v, intr->er_start, intr->er_size); 861 xhci_die(xhci); 862 return; 863 } 864 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 865 assert(dp_idx < intr->er_size); 866 867 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 868 * deadlocks when the ER is full. Hack it by holding off events until 869 * the driver decides to free at least half of the ring */ 870 if (intr->er_full) { 871 int er_free = dp_idx - intr->er_ep_idx; 872 if (er_free <= 0) { 873 er_free += intr->er_size; 874 } 875 if (er_free < (intr->er_size/2)) { 876 DPRINTF("xhci_events_update(): event ring still " 877 "more than half full (hack)\n"); 878 return; 879 } 880 } 881 882 while (intr->ev_buffer_put != intr->ev_buffer_get) { 883 assert(intr->er_full); 884 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 885 DPRINTF("xhci_events_update(): event ring full again\n"); 886 #ifndef ER_FULL_HACK 887 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 888 xhci_write_event(xhci, &full, v); 889 #endif 890 do_irq = 1; 891 break; 892 } 893 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 894 xhci_write_event(xhci, event, v); 895 intr->ev_buffer_get++; 896 do_irq = 1; 897 if (intr->ev_buffer_get == EV_QUEUE) { 898 intr->ev_buffer_get = 0; 899 } 900 } 901 902 if (do_irq) { 903 xhci_intr_raise(xhci, v); 904 } 905 906 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 907 DPRINTF("xhci_events_update(): event ring no longer full\n"); 908 intr->er_full = 0; 909 } 910 } 911 912 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 913 { 914 XHCIInterrupter *intr; 915 dma_addr_t erdp; 916 unsigned int dp_idx; 917 918 if (v >= xhci->numintrs) { 919 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 920 return; 921 } 922 intr = &xhci->intr[v]; 923 924 if (intr->er_full) { 925 DPRINTF("xhci_event(): ER full, queueing\n"); 926 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 927 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 928 return; 929 } 930 intr->ev_buffer[intr->ev_buffer_put++] = *event; 931 if (intr->ev_buffer_put == EV_QUEUE) { 932 intr->ev_buffer_put = 0; 933 } 934 return; 935 } 936 937 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 938 if (erdp < intr->er_start || 939 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 940 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 941 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 942 v, intr->er_start, intr->er_size); 943 xhci_die(xhci); 944 return; 945 } 946 947 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 948 assert(dp_idx < intr->er_size); 949 950 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 951 DPRINTF("xhci_event(): ER full, queueing\n"); 952 #ifndef ER_FULL_HACK 953 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 954 xhci_write_event(xhci, &full); 955 #endif 956 intr->er_full = 1; 957 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 958 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 959 return; 960 } 961 intr->ev_buffer[intr->ev_buffer_put++] = *event; 962 if (intr->ev_buffer_put == EV_QUEUE) { 963 intr->ev_buffer_put = 0; 964 } 965 } else { 966 xhci_write_event(xhci, event, v); 967 } 968 969 xhci_intr_raise(xhci, v); 970 } 971 972 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 973 dma_addr_t base) 974 { 975 ring->dequeue = base; 976 ring->ccs = 1; 977 } 978 979 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 980 dma_addr_t *addr) 981 { 982 PCIDevice *pci_dev = PCI_DEVICE(xhci); 983 984 while (1) { 985 TRBType type; 986 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 987 trb->addr = ring->dequeue; 988 trb->ccs = ring->ccs; 989 le64_to_cpus(&trb->parameter); 990 le32_to_cpus(&trb->status); 991 le32_to_cpus(&trb->control); 992 993 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 994 trb->parameter, trb->status, trb->control); 995 996 if ((trb->control & TRB_C) != ring->ccs) { 997 return 0; 998 } 999 1000 type = TRB_TYPE(*trb); 1001 1002 if (type != TR_LINK) { 1003 if (addr) { 1004 *addr = ring->dequeue; 1005 } 1006 ring->dequeue += TRB_SIZE; 1007 return type; 1008 } else { 1009 ring->dequeue = xhci_mask64(trb->parameter); 1010 if (trb->control & TRB_LK_TC) { 1011 ring->ccs = !ring->ccs; 1012 } 1013 } 1014 } 1015 } 1016 1017 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1018 { 1019 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1020 XHCITRB trb; 1021 int length = 0; 1022 dma_addr_t dequeue = ring->dequeue; 1023 bool ccs = ring->ccs; 1024 /* hack to bundle together the two/three TDs that make a setup transfer */ 1025 bool control_td_set = 0; 1026 1027 while (1) { 1028 TRBType type; 1029 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1030 le64_to_cpus(&trb.parameter); 1031 le32_to_cpus(&trb.status); 1032 le32_to_cpus(&trb.control); 1033 1034 if ((trb.control & TRB_C) != ccs) { 1035 return -length; 1036 } 1037 1038 type = TRB_TYPE(trb); 1039 1040 if (type == TR_LINK) { 1041 dequeue = xhci_mask64(trb.parameter); 1042 if (trb.control & TRB_LK_TC) { 1043 ccs = !ccs; 1044 } 1045 continue; 1046 } 1047 1048 length += 1; 1049 dequeue += TRB_SIZE; 1050 1051 if (type == TR_SETUP) { 1052 control_td_set = 1; 1053 } else if (type == TR_STATUS) { 1054 control_td_set = 0; 1055 } 1056 1057 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1058 return length; 1059 } 1060 } 1061 } 1062 1063 static void xhci_er_reset(XHCIState *xhci, int v) 1064 { 1065 XHCIInterrupter *intr = &xhci->intr[v]; 1066 XHCIEvRingSeg seg; 1067 1068 if (intr->erstsz == 0) { 1069 /* disabled */ 1070 intr->er_start = 0; 1071 intr->er_size = 0; 1072 return; 1073 } 1074 /* cache the (sole) event ring segment location */ 1075 if (intr->erstsz != 1) { 1076 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1077 xhci_die(xhci); 1078 return; 1079 } 1080 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1081 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1082 le32_to_cpus(&seg.addr_low); 1083 le32_to_cpus(&seg.addr_high); 1084 le32_to_cpus(&seg.size); 1085 if (seg.size < 16 || seg.size > 4096) { 1086 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1087 xhci_die(xhci); 1088 return; 1089 } 1090 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1091 intr->er_size = seg.size; 1092 1093 intr->er_ep_idx = 0; 1094 intr->er_pcs = 1; 1095 intr->er_full = 0; 1096 1097 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1098 v, intr->er_start, intr->er_size); 1099 } 1100 1101 static void xhci_run(XHCIState *xhci) 1102 { 1103 trace_usb_xhci_run(); 1104 xhci->usbsts &= ~USBSTS_HCH; 1105 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1106 } 1107 1108 static void xhci_stop(XHCIState *xhci) 1109 { 1110 trace_usb_xhci_stop(); 1111 xhci->usbsts |= USBSTS_HCH; 1112 xhci->crcr_low &= ~CRCR_CRR; 1113 } 1114 1115 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1116 dma_addr_t base) 1117 { 1118 XHCIStreamContext *stctx; 1119 unsigned int i; 1120 1121 stctx = g_new0(XHCIStreamContext, count); 1122 for (i = 0; i < count; i++) { 1123 stctx[i].pctx = base + i * 16; 1124 stctx[i].sct = -1; 1125 } 1126 return stctx; 1127 } 1128 1129 static void xhci_reset_streams(XHCIEPContext *epctx) 1130 { 1131 unsigned int i; 1132 1133 for (i = 0; i < epctx->nr_pstreams; i++) { 1134 epctx->pstreams[i].sct = -1; 1135 } 1136 } 1137 1138 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1139 { 1140 assert(epctx->pstreams == NULL); 1141 epctx->nr_pstreams = 2 << (epctx->max_pstreams + 1); 1142 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1143 } 1144 1145 static void xhci_free_streams(XHCIEPContext *epctx) 1146 { 1147 assert(epctx->pstreams != NULL); 1148 1149 g_free(epctx->pstreams); 1150 epctx->pstreams = NULL; 1151 epctx->nr_pstreams = 0; 1152 } 1153 1154 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1155 unsigned int streamid, 1156 uint32_t *cc_error) 1157 { 1158 XHCIStreamContext *sctx; 1159 dma_addr_t base; 1160 uint32_t ctx[2], sct; 1161 1162 assert(streamid != 0); 1163 if (epctx->lsa) { 1164 if (streamid >= epctx->nr_pstreams) { 1165 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1166 return NULL; 1167 } 1168 sctx = epctx->pstreams + streamid; 1169 } else { 1170 FIXME("secondary streams not implemented yet"); 1171 } 1172 1173 if (sctx->sct == -1) { 1174 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1175 sct = (ctx[0] >> 1) & 0x07; 1176 if (epctx->lsa && sct != 1) { 1177 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1178 return NULL; 1179 } 1180 sctx->sct = sct; 1181 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1182 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1183 } 1184 return sctx; 1185 } 1186 1187 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1188 XHCIStreamContext *sctx, uint32_t state) 1189 { 1190 XHCIRing *ring = NULL; 1191 uint32_t ctx[5]; 1192 uint32_t ctx2[2]; 1193 1194 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1195 ctx[0] &= ~EP_STATE_MASK; 1196 ctx[0] |= state; 1197 1198 /* update ring dequeue ptr */ 1199 if (epctx->nr_pstreams) { 1200 if (sctx != NULL) { 1201 ring = &sctx->ring; 1202 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1203 ctx2[0] &= 0xe; 1204 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1205 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1206 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1207 } 1208 } else { 1209 ring = &epctx->ring; 1210 } 1211 if (ring) { 1212 ctx[2] = ring->dequeue | ring->ccs; 1213 ctx[3] = (ring->dequeue >> 16) >> 16; 1214 1215 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1216 epctx->pctx, state, ctx[3], ctx[2]); 1217 } 1218 1219 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1220 if (epctx->state != state) { 1221 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1222 ep_state_name(epctx->state), 1223 ep_state_name(state)); 1224 } 1225 epctx->state = state; 1226 } 1227 1228 static void xhci_ep_kick_timer(void *opaque) 1229 { 1230 XHCIEPContext *epctx = opaque; 1231 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1232 } 1233 1234 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1235 unsigned int slotid, 1236 unsigned int epid) 1237 { 1238 XHCIEPContext *epctx; 1239 int i; 1240 1241 epctx = g_new0(XHCIEPContext, 1); 1242 epctx->xhci = xhci; 1243 epctx->slotid = slotid; 1244 epctx->epid = epid; 1245 1246 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1247 epctx->transfers[i].xhci = xhci; 1248 epctx->transfers[i].slotid = slotid; 1249 epctx->transfers[i].epid = epid; 1250 usb_packet_init(&epctx->transfers[i].packet); 1251 } 1252 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1253 1254 return epctx; 1255 } 1256 1257 static void xhci_init_epctx(XHCIEPContext *epctx, 1258 dma_addr_t pctx, uint32_t *ctx) 1259 { 1260 dma_addr_t dequeue; 1261 1262 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1263 1264 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1265 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1266 epctx->pctx = pctx; 1267 epctx->max_psize = ctx[1]>>16; 1268 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1269 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1270 epctx->lsa = (ctx[0] >> 15) & 1; 1271 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1272 epid/2, epid%2, epctx->max_psize); 1273 if (epctx->max_pstreams) { 1274 xhci_alloc_streams(epctx, dequeue); 1275 } else { 1276 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1277 epctx->ring.ccs = ctx[2] & 1; 1278 } 1279 1280 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1281 } 1282 1283 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1284 unsigned int epid, dma_addr_t pctx, 1285 uint32_t *ctx) 1286 { 1287 XHCISlot *slot; 1288 XHCIEPContext *epctx; 1289 1290 trace_usb_xhci_ep_enable(slotid, epid); 1291 assert(slotid >= 1 && slotid <= xhci->numslots); 1292 assert(epid >= 1 && epid <= 31); 1293 1294 slot = &xhci->slots[slotid-1]; 1295 if (slot->eps[epid-1]) { 1296 xhci_disable_ep(xhci, slotid, epid); 1297 } 1298 1299 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1300 slot->eps[epid-1] = epctx; 1301 xhci_init_epctx(epctx, pctx, ctx); 1302 1303 epctx->mfindex_last = 0; 1304 1305 epctx->state = EP_RUNNING; 1306 ctx[0] &= ~EP_STATE_MASK; 1307 ctx[0] |= EP_RUNNING; 1308 1309 return CC_SUCCESS; 1310 } 1311 1312 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1313 { 1314 int killed = 0; 1315 1316 if (report && (t->running_async || t->running_retry)) { 1317 t->status = report; 1318 xhci_xfer_report(t); 1319 } 1320 1321 if (t->running_async) { 1322 usb_cancel_packet(&t->packet); 1323 t->running_async = 0; 1324 killed = 1; 1325 } 1326 if (t->running_retry) { 1327 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1328 if (epctx) { 1329 epctx->retry = NULL; 1330 timer_del(epctx->kick_timer); 1331 } 1332 t->running_retry = 0; 1333 killed = 1; 1334 } 1335 if (t->trbs) { 1336 g_free(t->trbs); 1337 } 1338 1339 t->trbs = NULL; 1340 t->trb_count = t->trb_alloced = 0; 1341 1342 return killed; 1343 } 1344 1345 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1346 unsigned int epid, TRBCCode report) 1347 { 1348 XHCISlot *slot; 1349 XHCIEPContext *epctx; 1350 int i, xferi, killed = 0; 1351 USBEndpoint *ep = NULL; 1352 assert(slotid >= 1 && slotid <= xhci->numslots); 1353 assert(epid >= 1 && epid <= 31); 1354 1355 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1356 1357 slot = &xhci->slots[slotid-1]; 1358 1359 if (!slot->eps[epid-1]) { 1360 return 0; 1361 } 1362 1363 epctx = slot->eps[epid-1]; 1364 1365 xferi = epctx->next_xfer; 1366 for (i = 0; i < TD_QUEUE; i++) { 1367 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report); 1368 if (killed) { 1369 report = 0; /* Only report once */ 1370 } 1371 epctx->transfers[xferi].packet.ep = NULL; 1372 xferi = (xferi + 1) % TD_QUEUE; 1373 } 1374 1375 ep = xhci_epid_to_usbep(xhci, slotid, epid); 1376 if (ep) { 1377 usb_device_ep_stopped(ep->dev, ep); 1378 } 1379 return killed; 1380 } 1381 1382 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1383 unsigned int epid) 1384 { 1385 XHCISlot *slot; 1386 XHCIEPContext *epctx; 1387 int i; 1388 1389 trace_usb_xhci_ep_disable(slotid, epid); 1390 assert(slotid >= 1 && slotid <= xhci->numslots); 1391 assert(epid >= 1 && epid <= 31); 1392 1393 slot = &xhci->slots[slotid-1]; 1394 1395 if (!slot->eps[epid-1]) { 1396 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1397 return CC_SUCCESS; 1398 } 1399 1400 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1401 1402 epctx = slot->eps[epid-1]; 1403 1404 if (epctx->nr_pstreams) { 1405 xhci_free_streams(epctx); 1406 } 1407 1408 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1409 usb_packet_cleanup(&epctx->transfers[i].packet); 1410 } 1411 1412 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1413 1414 timer_free(epctx->kick_timer); 1415 g_free(epctx); 1416 slot->eps[epid-1] = NULL; 1417 1418 return CC_SUCCESS; 1419 } 1420 1421 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1422 unsigned int epid) 1423 { 1424 XHCISlot *slot; 1425 XHCIEPContext *epctx; 1426 1427 trace_usb_xhci_ep_stop(slotid, epid); 1428 assert(slotid >= 1 && slotid <= xhci->numslots); 1429 1430 if (epid < 1 || epid > 31) { 1431 fprintf(stderr, "xhci: bad ep %d\n", epid); 1432 return CC_TRB_ERROR; 1433 } 1434 1435 slot = &xhci->slots[slotid-1]; 1436 1437 if (!slot->eps[epid-1]) { 1438 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1439 return CC_EP_NOT_ENABLED_ERROR; 1440 } 1441 1442 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1443 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1444 "data might be lost\n"); 1445 } 1446 1447 epctx = slot->eps[epid-1]; 1448 1449 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1450 1451 if (epctx->nr_pstreams) { 1452 xhci_reset_streams(epctx); 1453 } 1454 1455 return CC_SUCCESS; 1456 } 1457 1458 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1459 unsigned int epid) 1460 { 1461 XHCISlot *slot; 1462 XHCIEPContext *epctx; 1463 1464 trace_usb_xhci_ep_reset(slotid, epid); 1465 assert(slotid >= 1 && slotid <= xhci->numslots); 1466 1467 if (epid < 1 || epid > 31) { 1468 fprintf(stderr, "xhci: bad ep %d\n", epid); 1469 return CC_TRB_ERROR; 1470 } 1471 1472 slot = &xhci->slots[slotid-1]; 1473 1474 if (!slot->eps[epid-1]) { 1475 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1476 return CC_EP_NOT_ENABLED_ERROR; 1477 } 1478 1479 epctx = slot->eps[epid-1]; 1480 1481 if (epctx->state != EP_HALTED) { 1482 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1483 epid, epctx->state); 1484 return CC_CONTEXT_STATE_ERROR; 1485 } 1486 1487 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1488 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1489 "data might be lost\n"); 1490 } 1491 1492 uint8_t ep = epid>>1; 1493 1494 if (epid & 1) { 1495 ep |= 0x80; 1496 } 1497 1498 if (!xhci->slots[slotid-1].uport || 1499 !xhci->slots[slotid-1].uport->dev) { 1500 return CC_USB_TRANSACTION_ERROR; 1501 } 1502 1503 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1504 1505 if (epctx->nr_pstreams) { 1506 xhci_reset_streams(epctx); 1507 } 1508 1509 return CC_SUCCESS; 1510 } 1511 1512 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1513 unsigned int epid, unsigned int streamid, 1514 uint64_t pdequeue) 1515 { 1516 XHCISlot *slot; 1517 XHCIEPContext *epctx; 1518 XHCIStreamContext *sctx; 1519 dma_addr_t dequeue; 1520 1521 assert(slotid >= 1 && slotid <= xhci->numslots); 1522 1523 if (epid < 1 || epid > 31) { 1524 fprintf(stderr, "xhci: bad ep %d\n", epid); 1525 return CC_TRB_ERROR; 1526 } 1527 1528 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1529 dequeue = xhci_mask64(pdequeue); 1530 1531 slot = &xhci->slots[slotid-1]; 1532 1533 if (!slot->eps[epid-1]) { 1534 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1535 return CC_EP_NOT_ENABLED_ERROR; 1536 } 1537 1538 epctx = slot->eps[epid-1]; 1539 1540 if (epctx->state != EP_STOPPED) { 1541 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1542 return CC_CONTEXT_STATE_ERROR; 1543 } 1544 1545 if (epctx->nr_pstreams) { 1546 uint32_t err; 1547 sctx = xhci_find_stream(epctx, streamid, &err); 1548 if (sctx == NULL) { 1549 return err; 1550 } 1551 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1552 sctx->ring.ccs = dequeue & 1; 1553 } else { 1554 sctx = NULL; 1555 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1556 epctx->ring.ccs = dequeue & 1; 1557 } 1558 1559 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1560 1561 return CC_SUCCESS; 1562 } 1563 1564 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1565 { 1566 XHCIState *xhci = xfer->xhci; 1567 int i; 1568 1569 xfer->int_req = false; 1570 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1571 for (i = 0; i < xfer->trb_count; i++) { 1572 XHCITRB *trb = &xfer->trbs[i]; 1573 dma_addr_t addr; 1574 unsigned int chunk = 0; 1575 1576 if (trb->control & TRB_TR_IOC) { 1577 xfer->int_req = true; 1578 } 1579 1580 switch (TRB_TYPE(*trb)) { 1581 case TR_DATA: 1582 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1583 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1584 goto err; 1585 } 1586 /* fallthrough */ 1587 case TR_NORMAL: 1588 case TR_ISOCH: 1589 addr = xhci_mask64(trb->parameter); 1590 chunk = trb->status & 0x1ffff; 1591 if (trb->control & TRB_TR_IDT) { 1592 if (chunk > 8 || in_xfer) { 1593 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1594 goto err; 1595 } 1596 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1597 } else { 1598 qemu_sglist_add(&xfer->sgl, addr, chunk); 1599 } 1600 break; 1601 } 1602 } 1603 1604 return 0; 1605 1606 err: 1607 qemu_sglist_destroy(&xfer->sgl); 1608 xhci_die(xhci); 1609 return -1; 1610 } 1611 1612 static void xhci_xfer_unmap(XHCITransfer *xfer) 1613 { 1614 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1615 qemu_sglist_destroy(&xfer->sgl); 1616 } 1617 1618 static void xhci_xfer_report(XHCITransfer *xfer) 1619 { 1620 uint32_t edtla = 0; 1621 unsigned int left; 1622 bool reported = 0; 1623 bool shortpkt = 0; 1624 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1625 XHCIState *xhci = xfer->xhci; 1626 int i; 1627 1628 left = xfer->packet.actual_length; 1629 1630 for (i = 0; i < xfer->trb_count; i++) { 1631 XHCITRB *trb = &xfer->trbs[i]; 1632 unsigned int chunk = 0; 1633 1634 switch (TRB_TYPE(*trb)) { 1635 case TR_DATA: 1636 case TR_NORMAL: 1637 case TR_ISOCH: 1638 chunk = trb->status & 0x1ffff; 1639 if (chunk > left) { 1640 chunk = left; 1641 if (xfer->status == CC_SUCCESS) { 1642 shortpkt = 1; 1643 } 1644 } 1645 left -= chunk; 1646 edtla += chunk; 1647 break; 1648 case TR_STATUS: 1649 reported = 0; 1650 shortpkt = 0; 1651 break; 1652 } 1653 1654 if (!reported && ((trb->control & TRB_TR_IOC) || 1655 (shortpkt && (trb->control & TRB_TR_ISP)) || 1656 (xfer->status != CC_SUCCESS && left == 0))) { 1657 event.slotid = xfer->slotid; 1658 event.epid = xfer->epid; 1659 event.length = (trb->status & 0x1ffff) - chunk; 1660 event.flags = 0; 1661 event.ptr = trb->addr; 1662 if (xfer->status == CC_SUCCESS) { 1663 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1664 } else { 1665 event.ccode = xfer->status; 1666 } 1667 if (TRB_TYPE(*trb) == TR_EVDATA) { 1668 event.ptr = trb->parameter; 1669 event.flags |= TRB_EV_ED; 1670 event.length = edtla & 0xffffff; 1671 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1672 edtla = 0; 1673 } 1674 xhci_event(xhci, &event, TRB_INTR(*trb)); 1675 reported = 1; 1676 if (xfer->status != CC_SUCCESS) { 1677 return; 1678 } 1679 } 1680 } 1681 } 1682 1683 static void xhci_stall_ep(XHCITransfer *xfer) 1684 { 1685 XHCIState *xhci = xfer->xhci; 1686 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1687 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1688 uint32_t err; 1689 XHCIStreamContext *sctx; 1690 1691 if (epctx->nr_pstreams) { 1692 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1693 if (sctx == NULL) { 1694 return; 1695 } 1696 sctx->ring.dequeue = xfer->trbs[0].addr; 1697 sctx->ring.ccs = xfer->trbs[0].ccs; 1698 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1699 } else { 1700 epctx->ring.dequeue = xfer->trbs[0].addr; 1701 epctx->ring.ccs = xfer->trbs[0].ccs; 1702 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1703 } 1704 } 1705 1706 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1707 XHCIEPContext *epctx); 1708 1709 static int xhci_setup_packet(XHCITransfer *xfer) 1710 { 1711 XHCIState *xhci = xfer->xhci; 1712 USBEndpoint *ep; 1713 int dir; 1714 1715 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1716 1717 if (xfer->packet.ep) { 1718 ep = xfer->packet.ep; 1719 } else { 1720 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); 1721 if (!ep) { 1722 fprintf(stderr, "xhci: slot %d has no device\n", 1723 xfer->slotid); 1724 return -1; 1725 } 1726 } 1727 1728 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1729 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1730 xfer->trbs[0].addr, false, xfer->int_req); 1731 usb_packet_map(&xfer->packet, &xfer->sgl); 1732 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1733 xfer->packet.pid, ep->dev->addr, ep->nr); 1734 return 0; 1735 } 1736 1737 static int xhci_complete_packet(XHCITransfer *xfer) 1738 { 1739 if (xfer->packet.status == USB_RET_ASYNC) { 1740 trace_usb_xhci_xfer_async(xfer); 1741 xfer->running_async = 1; 1742 xfer->running_retry = 0; 1743 xfer->complete = 0; 1744 return 0; 1745 } else if (xfer->packet.status == USB_RET_NAK) { 1746 trace_usb_xhci_xfer_nak(xfer); 1747 xfer->running_async = 0; 1748 xfer->running_retry = 1; 1749 xfer->complete = 0; 1750 return 0; 1751 } else { 1752 xfer->running_async = 0; 1753 xfer->running_retry = 0; 1754 xfer->complete = 1; 1755 xhci_xfer_unmap(xfer); 1756 } 1757 1758 if (xfer->packet.status == USB_RET_SUCCESS) { 1759 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1760 xfer->status = CC_SUCCESS; 1761 xhci_xfer_report(xfer); 1762 return 0; 1763 } 1764 1765 /* error */ 1766 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1767 switch (xfer->packet.status) { 1768 case USB_RET_NODEV: 1769 case USB_RET_IOERROR: 1770 xfer->status = CC_USB_TRANSACTION_ERROR; 1771 xhci_xfer_report(xfer); 1772 xhci_stall_ep(xfer); 1773 break; 1774 case USB_RET_STALL: 1775 xfer->status = CC_STALL_ERROR; 1776 xhci_xfer_report(xfer); 1777 xhci_stall_ep(xfer); 1778 break; 1779 case USB_RET_BABBLE: 1780 xfer->status = CC_BABBLE_DETECTED; 1781 xhci_xfer_report(xfer); 1782 xhci_stall_ep(xfer); 1783 break; 1784 default: 1785 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1786 xfer->packet.status); 1787 FIXME("unhandled USB_RET_*"); 1788 } 1789 return 0; 1790 } 1791 1792 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1793 { 1794 XHCITRB *trb_setup, *trb_status; 1795 uint8_t bmRequestType; 1796 1797 trb_setup = &xfer->trbs[0]; 1798 trb_status = &xfer->trbs[xfer->trb_count-1]; 1799 1800 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1801 1802 /* at most one Event Data TRB allowed after STATUS */ 1803 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1804 trb_status--; 1805 } 1806 1807 /* do some sanity checks */ 1808 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1809 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1810 TRB_TYPE(*trb_setup)); 1811 return -1; 1812 } 1813 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1814 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1815 TRB_TYPE(*trb_status)); 1816 return -1; 1817 } 1818 if (!(trb_setup->control & TRB_TR_IDT)) { 1819 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1820 return -1; 1821 } 1822 if ((trb_setup->status & 0x1ffff) != 8) { 1823 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1824 (trb_setup->status & 0x1ffff)); 1825 return -1; 1826 } 1827 1828 bmRequestType = trb_setup->parameter; 1829 1830 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1831 xfer->iso_xfer = false; 1832 xfer->timed_xfer = false; 1833 1834 if (xhci_setup_packet(xfer) < 0) { 1835 return -1; 1836 } 1837 xfer->packet.parameter = trb_setup->parameter; 1838 1839 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1840 1841 xhci_complete_packet(xfer); 1842 if (!xfer->running_async && !xfer->running_retry) { 1843 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1844 } 1845 return 0; 1846 } 1847 1848 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1849 XHCIEPContext *epctx, uint64_t mfindex) 1850 { 1851 uint64_t asap = ((mfindex + epctx->interval - 1) & 1852 ~(epctx->interval-1)); 1853 uint64_t kick = epctx->mfindex_last + epctx->interval; 1854 1855 assert(epctx->interval != 0); 1856 xfer->mfindex_kick = MAX(asap, kick); 1857 } 1858 1859 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1860 XHCIEPContext *epctx, uint64_t mfindex) 1861 { 1862 if (xfer->trbs[0].control & TRB_TR_SIA) { 1863 uint64_t asap = ((mfindex + epctx->interval - 1) & 1864 ~(epctx->interval-1)); 1865 if (asap >= epctx->mfindex_last && 1866 asap <= epctx->mfindex_last + epctx->interval * 4) { 1867 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1868 } else { 1869 xfer->mfindex_kick = asap; 1870 } 1871 } else { 1872 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1873 & TRB_TR_FRAMEID_MASK; 1874 xfer->mfindex_kick |= mfindex & ~0x3fff; 1875 if (xfer->mfindex_kick < mfindex) { 1876 xfer->mfindex_kick += 0x4000; 1877 } 1878 } 1879 } 1880 1881 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1882 XHCIEPContext *epctx, uint64_t mfindex) 1883 { 1884 if (xfer->mfindex_kick > mfindex) { 1885 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1886 (xfer->mfindex_kick - mfindex) * 125000); 1887 xfer->running_retry = 1; 1888 } else { 1889 epctx->mfindex_last = xfer->mfindex_kick; 1890 timer_del(epctx->kick_timer); 1891 xfer->running_retry = 0; 1892 } 1893 } 1894 1895 1896 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1897 { 1898 uint64_t mfindex; 1899 1900 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1901 1902 xfer->in_xfer = epctx->type>>2; 1903 1904 switch(epctx->type) { 1905 case ET_INTR_OUT: 1906 case ET_INTR_IN: 1907 xfer->pkts = 0; 1908 xfer->iso_xfer = false; 1909 xfer->timed_xfer = true; 1910 mfindex = xhci_mfindex_get(xhci); 1911 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1912 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1913 if (xfer->running_retry) { 1914 return -1; 1915 } 1916 break; 1917 case ET_BULK_OUT: 1918 case ET_BULK_IN: 1919 xfer->pkts = 0; 1920 xfer->iso_xfer = false; 1921 xfer->timed_xfer = false; 1922 break; 1923 case ET_ISO_OUT: 1924 case ET_ISO_IN: 1925 xfer->pkts = 1; 1926 xfer->iso_xfer = true; 1927 xfer->timed_xfer = true; 1928 mfindex = xhci_mfindex_get(xhci); 1929 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1930 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1931 if (xfer->running_retry) { 1932 return -1; 1933 } 1934 break; 1935 default: 1936 fprintf(stderr, "xhci: unknown or unhandled EP " 1937 "(type %d, in %d, ep %02x)\n", 1938 epctx->type, xfer->in_xfer, xfer->epid); 1939 return -1; 1940 } 1941 1942 if (xhci_setup_packet(xfer) < 0) { 1943 return -1; 1944 } 1945 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1946 1947 xhci_complete_packet(xfer); 1948 if (!xfer->running_async && !xfer->running_retry) { 1949 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1950 } 1951 return 0; 1952 } 1953 1954 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1955 { 1956 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1957 return xhci_submit(xhci, xfer, epctx); 1958 } 1959 1960 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1961 unsigned int epid, unsigned int streamid) 1962 { 1963 XHCIStreamContext *stctx; 1964 XHCIEPContext *epctx; 1965 XHCIRing *ring; 1966 USBEndpoint *ep = NULL; 1967 uint64_t mfindex; 1968 int length; 1969 int i; 1970 1971 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1972 assert(slotid >= 1 && slotid <= xhci->numslots); 1973 assert(epid >= 1 && epid <= 31); 1974 1975 if (!xhci->slots[slotid-1].enabled) { 1976 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1977 return; 1978 } 1979 epctx = xhci->slots[slotid-1].eps[epid-1]; 1980 if (!epctx) { 1981 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1982 epid, slotid); 1983 return; 1984 } 1985 1986 if (epctx->retry) { 1987 XHCITransfer *xfer = epctx->retry; 1988 1989 trace_usb_xhci_xfer_retry(xfer); 1990 assert(xfer->running_retry); 1991 if (xfer->timed_xfer) { 1992 /* time to kick the transfer? */ 1993 mfindex = xhci_mfindex_get(xhci); 1994 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1995 if (xfer->running_retry) { 1996 return; 1997 } 1998 xfer->timed_xfer = 0; 1999 xfer->running_retry = 1; 2000 } 2001 if (xfer->iso_xfer) { 2002 /* retry iso transfer */ 2003 if (xhci_setup_packet(xfer) < 0) { 2004 return; 2005 } 2006 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2007 assert(xfer->packet.status != USB_RET_NAK); 2008 xhci_complete_packet(xfer); 2009 } else { 2010 /* retry nak'ed transfer */ 2011 if (xhci_setup_packet(xfer) < 0) { 2012 return; 2013 } 2014 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2015 if (xfer->packet.status == USB_RET_NAK) { 2016 return; 2017 } 2018 xhci_complete_packet(xfer); 2019 } 2020 assert(!xfer->running_retry); 2021 epctx->retry = NULL; 2022 } 2023 2024 if (epctx->state == EP_HALTED) { 2025 DPRINTF("xhci: ep halted, not running schedule\n"); 2026 return; 2027 } 2028 2029 2030 if (epctx->nr_pstreams) { 2031 uint32_t err; 2032 stctx = xhci_find_stream(epctx, streamid, &err); 2033 if (stctx == NULL) { 2034 return; 2035 } 2036 ring = &stctx->ring; 2037 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2038 } else { 2039 ring = &epctx->ring; 2040 streamid = 0; 2041 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2042 } 2043 assert(ring->dequeue != 0); 2044 2045 while (1) { 2046 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 2047 if (xfer->running_async || xfer->running_retry) { 2048 break; 2049 } 2050 length = xhci_ring_chain_length(xhci, ring); 2051 if (length < 0) { 2052 break; 2053 } else if (length == 0) { 2054 break; 2055 } 2056 if (xfer->trbs && xfer->trb_alloced < length) { 2057 xfer->trb_count = 0; 2058 xfer->trb_alloced = 0; 2059 g_free(xfer->trbs); 2060 xfer->trbs = NULL; 2061 } 2062 if (!xfer->trbs) { 2063 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 2064 xfer->trb_alloced = length; 2065 } 2066 xfer->trb_count = length; 2067 2068 for (i = 0; i < length; i++) { 2069 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2070 } 2071 xfer->streamid = streamid; 2072 2073 if (epid == 1) { 2074 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2075 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2076 ep = xfer->packet.ep; 2077 } else { 2078 fprintf(stderr, "xhci: error firing CTL transfer\n"); 2079 } 2080 } else { 2081 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2082 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2083 } else { 2084 if (!xfer->timed_xfer) { 2085 fprintf(stderr, "xhci: error firing data transfer\n"); 2086 } 2087 } 2088 } 2089 2090 if (epctx->state == EP_HALTED) { 2091 break; 2092 } 2093 if (xfer->running_retry) { 2094 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2095 epctx->retry = xfer; 2096 break; 2097 } 2098 } 2099 2100 ep = xhci_epid_to_usbep(xhci, slotid, epid); 2101 if (ep) { 2102 usb_device_flush_ep_queue(ep->dev, ep); 2103 } 2104 } 2105 2106 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2107 { 2108 trace_usb_xhci_slot_enable(slotid); 2109 assert(slotid >= 1 && slotid <= xhci->numslots); 2110 xhci->slots[slotid-1].enabled = 1; 2111 xhci->slots[slotid-1].uport = NULL; 2112 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2113 2114 return CC_SUCCESS; 2115 } 2116 2117 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2118 { 2119 int i; 2120 2121 trace_usb_xhci_slot_disable(slotid); 2122 assert(slotid >= 1 && slotid <= xhci->numslots); 2123 2124 for (i = 1; i <= 31; i++) { 2125 if (xhci->slots[slotid-1].eps[i-1]) { 2126 xhci_disable_ep(xhci, slotid, i); 2127 } 2128 } 2129 2130 xhci->slots[slotid-1].enabled = 0; 2131 xhci->slots[slotid-1].addressed = 0; 2132 xhci->slots[slotid-1].uport = NULL; 2133 return CC_SUCCESS; 2134 } 2135 2136 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2137 { 2138 USBPort *uport; 2139 char path[32]; 2140 int i, pos, port; 2141 2142 port = (slot_ctx[1]>>16) & 0xFF; 2143 port = xhci->ports[port-1].uport->index+1; 2144 pos = snprintf(path, sizeof(path), "%d", port); 2145 for (i = 0; i < 5; i++) { 2146 port = (slot_ctx[0] >> 4*i) & 0x0f; 2147 if (!port) { 2148 break; 2149 } 2150 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2151 } 2152 2153 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2154 if (strcmp(uport->path, path) == 0) { 2155 return uport; 2156 } 2157 } 2158 return NULL; 2159 } 2160 2161 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2162 uint64_t pictx, bool bsr) 2163 { 2164 XHCISlot *slot; 2165 USBPort *uport; 2166 USBDevice *dev; 2167 dma_addr_t ictx, octx, dcbaap; 2168 uint64_t poctx; 2169 uint32_t ictl_ctx[2]; 2170 uint32_t slot_ctx[4]; 2171 uint32_t ep0_ctx[5]; 2172 int i; 2173 TRBCCode res; 2174 2175 assert(slotid >= 1 && slotid <= xhci->numslots); 2176 2177 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2178 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2179 ictx = xhci_mask64(pictx); 2180 octx = xhci_mask64(poctx); 2181 2182 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2183 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2184 2185 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2186 2187 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2188 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2189 ictl_ctx[0], ictl_ctx[1]); 2190 return CC_TRB_ERROR; 2191 } 2192 2193 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2194 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2195 2196 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2197 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2198 2199 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2200 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2201 2202 uport = xhci_lookup_uport(xhci, slot_ctx); 2203 if (uport == NULL) { 2204 fprintf(stderr, "xhci: port not found\n"); 2205 return CC_TRB_ERROR; 2206 } 2207 trace_usb_xhci_slot_address(slotid, uport->path); 2208 2209 dev = uport->dev; 2210 if (!dev) { 2211 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2212 return CC_USB_TRANSACTION_ERROR; 2213 } 2214 2215 for (i = 0; i < xhci->numslots; i++) { 2216 if (i == slotid-1) { 2217 continue; 2218 } 2219 if (xhci->slots[i].uport == uport) { 2220 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2221 uport->path, i+1); 2222 return CC_TRB_ERROR; 2223 } 2224 } 2225 2226 slot = &xhci->slots[slotid-1]; 2227 slot->uport = uport; 2228 slot->ctx = octx; 2229 2230 if (bsr) { 2231 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2232 } else { 2233 USBPacket p; 2234 uint8_t buf[1]; 2235 2236 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2237 usb_device_reset(dev); 2238 memset(&p, 0, sizeof(p)); 2239 usb_packet_addbuf(&p, buf, sizeof(buf)); 2240 usb_packet_setup(&p, USB_TOKEN_OUT, 2241 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2242 0, false, false); 2243 usb_device_handle_control(dev, &p, 2244 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2245 slotid, 0, 0, NULL); 2246 assert(p.status != USB_RET_ASYNC); 2247 } 2248 2249 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2250 2251 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2252 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2253 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2254 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2255 2256 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2257 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2258 2259 xhci->slots[slotid-1].addressed = 1; 2260 return res; 2261 } 2262 2263 2264 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2265 uint64_t pictx, bool dc) 2266 { 2267 dma_addr_t ictx, octx; 2268 uint32_t ictl_ctx[2]; 2269 uint32_t slot_ctx[4]; 2270 uint32_t islot_ctx[4]; 2271 uint32_t ep_ctx[5]; 2272 int i; 2273 TRBCCode res; 2274 2275 trace_usb_xhci_slot_configure(slotid); 2276 assert(slotid >= 1 && slotid <= xhci->numslots); 2277 2278 ictx = xhci_mask64(pictx); 2279 octx = xhci->slots[slotid-1].ctx; 2280 2281 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2282 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2283 2284 if (dc) { 2285 for (i = 2; i <= 31; i++) { 2286 if (xhci->slots[slotid-1].eps[i-1]) { 2287 xhci_disable_ep(xhci, slotid, i); 2288 } 2289 } 2290 2291 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2292 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2293 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2294 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2295 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2296 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2297 2298 return CC_SUCCESS; 2299 } 2300 2301 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2302 2303 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2304 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2305 ictl_ctx[0], ictl_ctx[1]); 2306 return CC_TRB_ERROR; 2307 } 2308 2309 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2310 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2311 2312 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2313 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2314 return CC_CONTEXT_STATE_ERROR; 2315 } 2316 2317 for (i = 2; i <= 31; i++) { 2318 if (ictl_ctx[0] & (1<<i)) { 2319 xhci_disable_ep(xhci, slotid, i); 2320 } 2321 if (ictl_ctx[1] & (1<<i)) { 2322 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2323 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2324 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2325 ep_ctx[3], ep_ctx[4]); 2326 xhci_disable_ep(xhci, slotid, i); 2327 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2328 if (res != CC_SUCCESS) { 2329 return res; 2330 } 2331 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2332 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2333 ep_ctx[3], ep_ctx[4]); 2334 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2335 } 2336 } 2337 2338 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2339 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2340 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2341 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2342 SLOT_CONTEXT_ENTRIES_SHIFT); 2343 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2344 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2345 2346 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2347 2348 return CC_SUCCESS; 2349 } 2350 2351 2352 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2353 uint64_t pictx) 2354 { 2355 dma_addr_t ictx, octx; 2356 uint32_t ictl_ctx[2]; 2357 uint32_t iep0_ctx[5]; 2358 uint32_t ep0_ctx[5]; 2359 uint32_t islot_ctx[4]; 2360 uint32_t slot_ctx[4]; 2361 2362 trace_usb_xhci_slot_evaluate(slotid); 2363 assert(slotid >= 1 && slotid <= xhci->numslots); 2364 2365 ictx = xhci_mask64(pictx); 2366 octx = xhci->slots[slotid-1].ctx; 2367 2368 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2369 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2370 2371 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2372 2373 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2374 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2375 ictl_ctx[0], ictl_ctx[1]); 2376 return CC_TRB_ERROR; 2377 } 2378 2379 if (ictl_ctx[1] & 0x1) { 2380 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2381 2382 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2383 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2384 2385 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2386 2387 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2388 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2389 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2390 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2391 2392 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2393 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2394 2395 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2396 } 2397 2398 if (ictl_ctx[1] & 0x2) { 2399 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2400 2401 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2402 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2403 iep0_ctx[3], iep0_ctx[4]); 2404 2405 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2406 2407 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2408 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2409 2410 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2411 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2412 2413 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2414 } 2415 2416 return CC_SUCCESS; 2417 } 2418 2419 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2420 { 2421 uint32_t slot_ctx[4]; 2422 dma_addr_t octx; 2423 int i; 2424 2425 trace_usb_xhci_slot_reset(slotid); 2426 assert(slotid >= 1 && slotid <= xhci->numslots); 2427 2428 octx = xhci->slots[slotid-1].ctx; 2429 2430 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2431 2432 for (i = 2; i <= 31; i++) { 2433 if (xhci->slots[slotid-1].eps[i-1]) { 2434 xhci_disable_ep(xhci, slotid, i); 2435 } 2436 } 2437 2438 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2439 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2440 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2441 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2442 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2443 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2444 2445 return CC_SUCCESS; 2446 } 2447 2448 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2449 { 2450 unsigned int slotid; 2451 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2452 if (slotid < 1 || slotid > xhci->numslots) { 2453 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2454 event->ccode = CC_TRB_ERROR; 2455 return 0; 2456 } else if (!xhci->slots[slotid-1].enabled) { 2457 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2458 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2459 return 0; 2460 } 2461 return slotid; 2462 } 2463 2464 /* cleanup slot state on usb device detach */ 2465 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2466 { 2467 int slot, ep; 2468 2469 for (slot = 0; slot < xhci->numslots; slot++) { 2470 if (xhci->slots[slot].uport == uport) { 2471 break; 2472 } 2473 } 2474 if (slot == xhci->numslots) { 2475 return; 2476 } 2477 2478 for (ep = 0; ep < 31; ep++) { 2479 if (xhci->slots[slot].eps[ep]) { 2480 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2481 } 2482 } 2483 xhci->slots[slot].uport = NULL; 2484 } 2485 2486 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2487 { 2488 dma_addr_t ctx; 2489 uint8_t bw_ctx[xhci->numports+1]; 2490 2491 DPRINTF("xhci_get_port_bandwidth()\n"); 2492 2493 ctx = xhci_mask64(pctx); 2494 2495 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2496 2497 /* TODO: actually implement real values here */ 2498 bw_ctx[0] = 0; 2499 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2500 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2501 2502 return CC_SUCCESS; 2503 } 2504 2505 static uint32_t rotl(uint32_t v, unsigned count) 2506 { 2507 count &= 31; 2508 return (v << count) | (v >> (32 - count)); 2509 } 2510 2511 2512 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2513 { 2514 uint32_t val; 2515 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2516 val += rotl(lo + 0x49434878, hi & 0x1F); 2517 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2518 return ~val; 2519 } 2520 2521 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2522 { 2523 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2524 uint32_t buf[8]; 2525 uint32_t obuf[8]; 2526 dma_addr_t paddr = xhci_mask64(addr); 2527 2528 pci_dma_read(pci_dev, paddr, &buf, 32); 2529 2530 memcpy(obuf, buf, sizeof(obuf)); 2531 2532 if ((buf[0] & 0xff) == 2) { 2533 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2534 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2535 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2536 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2537 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2538 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2539 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2540 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2541 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2542 } 2543 2544 pci_dma_write(pci_dev, paddr, &obuf, 32); 2545 } 2546 2547 static void xhci_process_commands(XHCIState *xhci) 2548 { 2549 XHCITRB trb; 2550 TRBType type; 2551 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2552 dma_addr_t addr; 2553 unsigned int i, slotid = 0; 2554 2555 DPRINTF("xhci_process_commands()\n"); 2556 if (!xhci_running(xhci)) { 2557 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2558 return; 2559 } 2560 2561 xhci->crcr_low |= CRCR_CRR; 2562 2563 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2564 event.ptr = addr; 2565 switch (type) { 2566 case CR_ENABLE_SLOT: 2567 for (i = 0; i < xhci->numslots; i++) { 2568 if (!xhci->slots[i].enabled) { 2569 break; 2570 } 2571 } 2572 if (i >= xhci->numslots) { 2573 fprintf(stderr, "xhci: no device slots available\n"); 2574 event.ccode = CC_NO_SLOTS_ERROR; 2575 } else { 2576 slotid = i+1; 2577 event.ccode = xhci_enable_slot(xhci, slotid); 2578 } 2579 break; 2580 case CR_DISABLE_SLOT: 2581 slotid = xhci_get_slot(xhci, &event, &trb); 2582 if (slotid) { 2583 event.ccode = xhci_disable_slot(xhci, slotid); 2584 } 2585 break; 2586 case CR_ADDRESS_DEVICE: 2587 slotid = xhci_get_slot(xhci, &event, &trb); 2588 if (slotid) { 2589 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2590 trb.control & TRB_CR_BSR); 2591 } 2592 break; 2593 case CR_CONFIGURE_ENDPOINT: 2594 slotid = xhci_get_slot(xhci, &event, &trb); 2595 if (slotid) { 2596 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2597 trb.control & TRB_CR_DC); 2598 } 2599 break; 2600 case CR_EVALUATE_CONTEXT: 2601 slotid = xhci_get_slot(xhci, &event, &trb); 2602 if (slotid) { 2603 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2604 } 2605 break; 2606 case CR_STOP_ENDPOINT: 2607 slotid = xhci_get_slot(xhci, &event, &trb); 2608 if (slotid) { 2609 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2610 & TRB_CR_EPID_MASK; 2611 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2612 } 2613 break; 2614 case CR_RESET_ENDPOINT: 2615 slotid = xhci_get_slot(xhci, &event, &trb); 2616 if (slotid) { 2617 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2618 & TRB_CR_EPID_MASK; 2619 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2620 } 2621 break; 2622 case CR_SET_TR_DEQUEUE: 2623 slotid = xhci_get_slot(xhci, &event, &trb); 2624 if (slotid) { 2625 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2626 & TRB_CR_EPID_MASK; 2627 unsigned int streamid = (trb.status >> 16) & 0xffff; 2628 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2629 epid, streamid, 2630 trb.parameter); 2631 } 2632 break; 2633 case CR_RESET_DEVICE: 2634 slotid = xhci_get_slot(xhci, &event, &trb); 2635 if (slotid) { 2636 event.ccode = xhci_reset_slot(xhci, slotid); 2637 } 2638 break; 2639 case CR_GET_PORT_BANDWIDTH: 2640 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2641 break; 2642 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2643 xhci_via_challenge(xhci, trb.parameter); 2644 break; 2645 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2646 event.type = 48; /* NEC reply */ 2647 event.length = 0x3025; 2648 break; 2649 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2650 { 2651 uint32_t chi = trb.parameter >> 32; 2652 uint32_t clo = trb.parameter; 2653 uint32_t val = xhci_nec_challenge(chi, clo); 2654 event.length = val & 0xFFFF; 2655 event.epid = val >> 16; 2656 slotid = val >> 24; 2657 event.type = 48; /* NEC reply */ 2658 } 2659 break; 2660 default: 2661 trace_usb_xhci_unimplemented("command", type); 2662 event.ccode = CC_TRB_ERROR; 2663 break; 2664 } 2665 event.slotid = slotid; 2666 xhci_event(xhci, &event, 0); 2667 } 2668 } 2669 2670 static bool xhci_port_have_device(XHCIPort *port) 2671 { 2672 if (!port->uport->dev || !port->uport->dev->attached) { 2673 return false; /* no device present */ 2674 } 2675 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2676 return false; /* speed mismatch */ 2677 } 2678 return true; 2679 } 2680 2681 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2682 { 2683 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2684 port->portnr << 24 }; 2685 2686 if ((port->portsc & bits) == bits) { 2687 return; 2688 } 2689 trace_usb_xhci_port_notify(port->portnr, bits); 2690 port->portsc |= bits; 2691 if (!xhci_running(port->xhci)) { 2692 return; 2693 } 2694 xhci_event(port->xhci, &ev, 0); 2695 } 2696 2697 static void xhci_port_update(XHCIPort *port, int is_detach) 2698 { 2699 uint32_t pls = PLS_RX_DETECT; 2700 2701 port->portsc = PORTSC_PP; 2702 if (!is_detach && xhci_port_have_device(port)) { 2703 port->portsc |= PORTSC_CCS; 2704 switch (port->uport->dev->speed) { 2705 case USB_SPEED_LOW: 2706 port->portsc |= PORTSC_SPEED_LOW; 2707 pls = PLS_POLLING; 2708 break; 2709 case USB_SPEED_FULL: 2710 port->portsc |= PORTSC_SPEED_FULL; 2711 pls = PLS_POLLING; 2712 break; 2713 case USB_SPEED_HIGH: 2714 port->portsc |= PORTSC_SPEED_HIGH; 2715 pls = PLS_POLLING; 2716 break; 2717 case USB_SPEED_SUPER: 2718 port->portsc |= PORTSC_SPEED_SUPER; 2719 port->portsc |= PORTSC_PED; 2720 pls = PLS_U0; 2721 break; 2722 } 2723 } 2724 set_field(&port->portsc, pls, PORTSC_PLS); 2725 trace_usb_xhci_port_link(port->portnr, pls); 2726 xhci_port_notify(port, PORTSC_CSC); 2727 } 2728 2729 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2730 { 2731 trace_usb_xhci_port_reset(port->portnr); 2732 2733 if (!xhci_port_have_device(port)) { 2734 return; 2735 } 2736 2737 usb_device_reset(port->uport->dev); 2738 2739 switch (port->uport->dev->speed) { 2740 case USB_SPEED_SUPER: 2741 if (warm_reset) { 2742 port->portsc |= PORTSC_WRC; 2743 } 2744 /* fall through */ 2745 case USB_SPEED_LOW: 2746 case USB_SPEED_FULL: 2747 case USB_SPEED_HIGH: 2748 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2749 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2750 port->portsc |= PORTSC_PED; 2751 break; 2752 } 2753 2754 port->portsc &= ~PORTSC_PR; 2755 xhci_port_notify(port, PORTSC_PRC); 2756 } 2757 2758 static void xhci_reset(DeviceState *dev) 2759 { 2760 XHCIState *xhci = XHCI(dev); 2761 int i; 2762 2763 trace_usb_xhci_reset(); 2764 if (!(xhci->usbsts & USBSTS_HCH)) { 2765 fprintf(stderr, "xhci: reset while running!\n"); 2766 } 2767 2768 xhci->usbcmd = 0; 2769 xhci->usbsts = USBSTS_HCH; 2770 xhci->dnctrl = 0; 2771 xhci->crcr_low = 0; 2772 xhci->crcr_high = 0; 2773 xhci->dcbaap_low = 0; 2774 xhci->dcbaap_high = 0; 2775 xhci->config = 0; 2776 2777 for (i = 0; i < xhci->numslots; i++) { 2778 xhci_disable_slot(xhci, i+1); 2779 } 2780 2781 for (i = 0; i < xhci->numports; i++) { 2782 xhci_port_update(xhci->ports + i, 0); 2783 } 2784 2785 for (i = 0; i < xhci->numintrs; i++) { 2786 xhci->intr[i].iman = 0; 2787 xhci->intr[i].imod = 0; 2788 xhci->intr[i].erstsz = 0; 2789 xhci->intr[i].erstba_low = 0; 2790 xhci->intr[i].erstba_high = 0; 2791 xhci->intr[i].erdp_low = 0; 2792 xhci->intr[i].erdp_high = 0; 2793 xhci->intr[i].msix_used = 0; 2794 2795 xhci->intr[i].er_ep_idx = 0; 2796 xhci->intr[i].er_pcs = 1; 2797 xhci->intr[i].er_full = 0; 2798 xhci->intr[i].ev_buffer_put = 0; 2799 xhci->intr[i].ev_buffer_get = 0; 2800 } 2801 2802 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2803 xhci_mfwrap_update(xhci); 2804 } 2805 2806 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2807 { 2808 XHCIState *xhci = ptr; 2809 uint32_t ret; 2810 2811 switch (reg) { 2812 case 0x00: /* HCIVERSION, CAPLENGTH */ 2813 ret = 0x01000000 | LEN_CAP; 2814 break; 2815 case 0x04: /* HCSPARAMS 1 */ 2816 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2817 | (xhci->numintrs<<8) | xhci->numslots; 2818 break; 2819 case 0x08: /* HCSPARAMS 2 */ 2820 ret = 0x0000000f; 2821 break; 2822 case 0x0c: /* HCSPARAMS 3 */ 2823 ret = 0x00000000; 2824 break; 2825 case 0x10: /* HCCPARAMS */ 2826 if (sizeof(dma_addr_t) == 4) { 2827 ret = 0x00087000; 2828 } else { 2829 ret = 0x00087001; 2830 } 2831 break; 2832 case 0x14: /* DBOFF */ 2833 ret = OFF_DOORBELL; 2834 break; 2835 case 0x18: /* RTSOFF */ 2836 ret = OFF_RUNTIME; 2837 break; 2838 2839 /* extended capabilities */ 2840 case 0x20: /* Supported Protocol:00 */ 2841 ret = 0x02000402; /* USB 2.0 */ 2842 break; 2843 case 0x24: /* Supported Protocol:04 */ 2844 ret = 0x20425355; /* "USB " */ 2845 break; 2846 case 0x28: /* Supported Protocol:08 */ 2847 ret = 0x00000001 | (xhci->numports_2<<8); 2848 break; 2849 case 0x2c: /* Supported Protocol:0c */ 2850 ret = 0x00000000; /* reserved */ 2851 break; 2852 case 0x30: /* Supported Protocol:00 */ 2853 ret = 0x03000002; /* USB 3.0 */ 2854 break; 2855 case 0x34: /* Supported Protocol:04 */ 2856 ret = 0x20425355; /* "USB " */ 2857 break; 2858 case 0x38: /* Supported Protocol:08 */ 2859 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2860 break; 2861 case 0x3c: /* Supported Protocol:0c */ 2862 ret = 0x00000000; /* reserved */ 2863 break; 2864 default: 2865 trace_usb_xhci_unimplemented("cap read", reg); 2866 ret = 0; 2867 } 2868 2869 trace_usb_xhci_cap_read(reg, ret); 2870 return ret; 2871 } 2872 2873 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2874 { 2875 XHCIPort *port = ptr; 2876 uint32_t ret; 2877 2878 switch (reg) { 2879 case 0x00: /* PORTSC */ 2880 ret = port->portsc; 2881 break; 2882 case 0x04: /* PORTPMSC */ 2883 case 0x08: /* PORTLI */ 2884 ret = 0; 2885 break; 2886 case 0x0c: /* reserved */ 2887 default: 2888 trace_usb_xhci_unimplemented("port read", reg); 2889 ret = 0; 2890 } 2891 2892 trace_usb_xhci_port_read(port->portnr, reg, ret); 2893 return ret; 2894 } 2895 2896 static void xhci_port_write(void *ptr, hwaddr reg, 2897 uint64_t val, unsigned size) 2898 { 2899 XHCIPort *port = ptr; 2900 uint32_t portsc, notify; 2901 2902 trace_usb_xhci_port_write(port->portnr, reg, val); 2903 2904 switch (reg) { 2905 case 0x00: /* PORTSC */ 2906 /* write-1-to-start bits */ 2907 if (val & PORTSC_WPR) { 2908 xhci_port_reset(port, true); 2909 break; 2910 } 2911 if (val & PORTSC_PR) { 2912 xhci_port_reset(port, false); 2913 break; 2914 } 2915 2916 portsc = port->portsc; 2917 notify = 0; 2918 /* write-1-to-clear bits*/ 2919 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2920 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2921 if (val & PORTSC_LWS) { 2922 /* overwrite PLS only when LWS=1 */ 2923 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2924 uint32_t new_pls = get_field(val, PORTSC_PLS); 2925 switch (new_pls) { 2926 case PLS_U0: 2927 if (old_pls != PLS_U0) { 2928 set_field(&portsc, new_pls, PORTSC_PLS); 2929 trace_usb_xhci_port_link(port->portnr, new_pls); 2930 notify = PORTSC_PLC; 2931 } 2932 break; 2933 case PLS_U3: 2934 if (old_pls < PLS_U3) { 2935 set_field(&portsc, new_pls, PORTSC_PLS); 2936 trace_usb_xhci_port_link(port->portnr, new_pls); 2937 } 2938 break; 2939 case PLS_RESUME: 2940 /* windows does this for some reason, don't spam stderr */ 2941 break; 2942 default: 2943 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2944 __func__, old_pls, new_pls); 2945 break; 2946 } 2947 } 2948 /* read/write bits */ 2949 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2950 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2951 port->portsc = portsc; 2952 if (notify) { 2953 xhci_port_notify(port, notify); 2954 } 2955 break; 2956 case 0x04: /* PORTPMSC */ 2957 case 0x08: /* PORTLI */ 2958 default: 2959 trace_usb_xhci_unimplemented("port write", reg); 2960 } 2961 } 2962 2963 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2964 { 2965 XHCIState *xhci = ptr; 2966 uint32_t ret; 2967 2968 switch (reg) { 2969 case 0x00: /* USBCMD */ 2970 ret = xhci->usbcmd; 2971 break; 2972 case 0x04: /* USBSTS */ 2973 ret = xhci->usbsts; 2974 break; 2975 case 0x08: /* PAGESIZE */ 2976 ret = 1; /* 4KiB */ 2977 break; 2978 case 0x14: /* DNCTRL */ 2979 ret = xhci->dnctrl; 2980 break; 2981 case 0x18: /* CRCR low */ 2982 ret = xhci->crcr_low & ~0xe; 2983 break; 2984 case 0x1c: /* CRCR high */ 2985 ret = xhci->crcr_high; 2986 break; 2987 case 0x30: /* DCBAAP low */ 2988 ret = xhci->dcbaap_low; 2989 break; 2990 case 0x34: /* DCBAAP high */ 2991 ret = xhci->dcbaap_high; 2992 break; 2993 case 0x38: /* CONFIG */ 2994 ret = xhci->config; 2995 break; 2996 default: 2997 trace_usb_xhci_unimplemented("oper read", reg); 2998 ret = 0; 2999 } 3000 3001 trace_usb_xhci_oper_read(reg, ret); 3002 return ret; 3003 } 3004 3005 static void xhci_oper_write(void *ptr, hwaddr reg, 3006 uint64_t val, unsigned size) 3007 { 3008 XHCIState *xhci = ptr; 3009 DeviceState *d = DEVICE(ptr); 3010 3011 trace_usb_xhci_oper_write(reg, val); 3012 3013 switch (reg) { 3014 case 0x00: /* USBCMD */ 3015 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3016 xhci_run(xhci); 3017 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3018 xhci_stop(xhci); 3019 } 3020 xhci->usbcmd = val & 0xc0f; 3021 xhci_mfwrap_update(xhci); 3022 if (val & USBCMD_HCRST) { 3023 xhci_reset(d); 3024 } 3025 xhci_intx_update(xhci); 3026 break; 3027 3028 case 0x04: /* USBSTS */ 3029 /* these bits are write-1-to-clear */ 3030 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3031 xhci_intx_update(xhci); 3032 break; 3033 3034 case 0x14: /* DNCTRL */ 3035 xhci->dnctrl = val & 0xffff; 3036 break; 3037 case 0x18: /* CRCR low */ 3038 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3039 break; 3040 case 0x1c: /* CRCR high */ 3041 xhci->crcr_high = val; 3042 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3043 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3044 xhci->crcr_low &= ~CRCR_CRR; 3045 xhci_event(xhci, &event, 0); 3046 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3047 } else { 3048 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3049 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3050 } 3051 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3052 break; 3053 case 0x30: /* DCBAAP low */ 3054 xhci->dcbaap_low = val & 0xffffffc0; 3055 break; 3056 case 0x34: /* DCBAAP high */ 3057 xhci->dcbaap_high = val; 3058 break; 3059 case 0x38: /* CONFIG */ 3060 xhci->config = val & 0xff; 3061 break; 3062 default: 3063 trace_usb_xhci_unimplemented("oper write", reg); 3064 } 3065 } 3066 3067 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3068 unsigned size) 3069 { 3070 XHCIState *xhci = ptr; 3071 uint32_t ret = 0; 3072 3073 if (reg < 0x20) { 3074 switch (reg) { 3075 case 0x00: /* MFINDEX */ 3076 ret = xhci_mfindex_get(xhci) & 0x3fff; 3077 break; 3078 default: 3079 trace_usb_xhci_unimplemented("runtime read", reg); 3080 break; 3081 } 3082 } else { 3083 int v = (reg - 0x20) / 0x20; 3084 XHCIInterrupter *intr = &xhci->intr[v]; 3085 switch (reg & 0x1f) { 3086 case 0x00: /* IMAN */ 3087 ret = intr->iman; 3088 break; 3089 case 0x04: /* IMOD */ 3090 ret = intr->imod; 3091 break; 3092 case 0x08: /* ERSTSZ */ 3093 ret = intr->erstsz; 3094 break; 3095 case 0x10: /* ERSTBA low */ 3096 ret = intr->erstba_low; 3097 break; 3098 case 0x14: /* ERSTBA high */ 3099 ret = intr->erstba_high; 3100 break; 3101 case 0x18: /* ERDP low */ 3102 ret = intr->erdp_low; 3103 break; 3104 case 0x1c: /* ERDP high */ 3105 ret = intr->erdp_high; 3106 break; 3107 } 3108 } 3109 3110 trace_usb_xhci_runtime_read(reg, ret); 3111 return ret; 3112 } 3113 3114 static void xhci_runtime_write(void *ptr, hwaddr reg, 3115 uint64_t val, unsigned size) 3116 { 3117 XHCIState *xhci = ptr; 3118 int v = (reg - 0x20) / 0x20; 3119 XHCIInterrupter *intr = &xhci->intr[v]; 3120 trace_usb_xhci_runtime_write(reg, val); 3121 3122 if (reg < 0x20) { 3123 trace_usb_xhci_unimplemented("runtime write", reg); 3124 return; 3125 } 3126 3127 switch (reg & 0x1f) { 3128 case 0x00: /* IMAN */ 3129 if (val & IMAN_IP) { 3130 intr->iman &= ~IMAN_IP; 3131 } 3132 intr->iman &= ~IMAN_IE; 3133 intr->iman |= val & IMAN_IE; 3134 if (v == 0) { 3135 xhci_intx_update(xhci); 3136 } 3137 xhci_msix_update(xhci, v); 3138 break; 3139 case 0x04: /* IMOD */ 3140 intr->imod = val; 3141 break; 3142 case 0x08: /* ERSTSZ */ 3143 intr->erstsz = val & 0xffff; 3144 break; 3145 case 0x10: /* ERSTBA low */ 3146 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3147 intr->erstba_low = val & 0xffffffc0; */ 3148 intr->erstba_low = val & 0xfffffff0; 3149 break; 3150 case 0x14: /* ERSTBA high */ 3151 intr->erstba_high = val; 3152 xhci_er_reset(xhci, v); 3153 break; 3154 case 0x18: /* ERDP low */ 3155 if (val & ERDP_EHB) { 3156 intr->erdp_low &= ~ERDP_EHB; 3157 } 3158 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3159 break; 3160 case 0x1c: /* ERDP high */ 3161 intr->erdp_high = val; 3162 xhci_events_update(xhci, v); 3163 break; 3164 default: 3165 trace_usb_xhci_unimplemented("oper write", reg); 3166 } 3167 } 3168 3169 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3170 unsigned size) 3171 { 3172 /* doorbells always read as 0 */ 3173 trace_usb_xhci_doorbell_read(reg, 0); 3174 return 0; 3175 } 3176 3177 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3178 uint64_t val, unsigned size) 3179 { 3180 XHCIState *xhci = ptr; 3181 unsigned int epid, streamid; 3182 3183 trace_usb_xhci_doorbell_write(reg, val); 3184 3185 if (!xhci_running(xhci)) { 3186 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3187 return; 3188 } 3189 3190 reg >>= 2; 3191 3192 if (reg == 0) { 3193 if (val == 0) { 3194 xhci_process_commands(xhci); 3195 } else { 3196 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3197 (uint32_t)val); 3198 } 3199 } else { 3200 epid = val & 0xff; 3201 streamid = (val >> 16) & 0xffff; 3202 if (reg > xhci->numslots) { 3203 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3204 } else if (epid > 31) { 3205 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3206 (int)reg, (uint32_t)val); 3207 } else { 3208 xhci_kick_ep(xhci, reg, epid, streamid); 3209 } 3210 } 3211 } 3212 3213 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3214 unsigned width) 3215 { 3216 /* nothing */ 3217 } 3218 3219 static const MemoryRegionOps xhci_cap_ops = { 3220 .read = xhci_cap_read, 3221 .write = xhci_cap_write, 3222 .valid.min_access_size = 1, 3223 .valid.max_access_size = 4, 3224 .impl.min_access_size = 4, 3225 .impl.max_access_size = 4, 3226 .endianness = DEVICE_LITTLE_ENDIAN, 3227 }; 3228 3229 static const MemoryRegionOps xhci_oper_ops = { 3230 .read = xhci_oper_read, 3231 .write = xhci_oper_write, 3232 .valid.min_access_size = 4, 3233 .valid.max_access_size = 4, 3234 .endianness = DEVICE_LITTLE_ENDIAN, 3235 }; 3236 3237 static const MemoryRegionOps xhci_port_ops = { 3238 .read = xhci_port_read, 3239 .write = xhci_port_write, 3240 .valid.min_access_size = 4, 3241 .valid.max_access_size = 4, 3242 .endianness = DEVICE_LITTLE_ENDIAN, 3243 }; 3244 3245 static const MemoryRegionOps xhci_runtime_ops = { 3246 .read = xhci_runtime_read, 3247 .write = xhci_runtime_write, 3248 .valid.min_access_size = 4, 3249 .valid.max_access_size = 4, 3250 .endianness = DEVICE_LITTLE_ENDIAN, 3251 }; 3252 3253 static const MemoryRegionOps xhci_doorbell_ops = { 3254 .read = xhci_doorbell_read, 3255 .write = xhci_doorbell_write, 3256 .valid.min_access_size = 4, 3257 .valid.max_access_size = 4, 3258 .endianness = DEVICE_LITTLE_ENDIAN, 3259 }; 3260 3261 static void xhci_attach(USBPort *usbport) 3262 { 3263 XHCIState *xhci = usbport->opaque; 3264 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3265 3266 xhci_port_update(port, 0); 3267 } 3268 3269 static void xhci_detach(USBPort *usbport) 3270 { 3271 XHCIState *xhci = usbport->opaque; 3272 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3273 3274 xhci_detach_slot(xhci, usbport); 3275 xhci_port_update(port, 1); 3276 } 3277 3278 static void xhci_wakeup(USBPort *usbport) 3279 { 3280 XHCIState *xhci = usbport->opaque; 3281 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3282 3283 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3284 return; 3285 } 3286 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3287 xhci_port_notify(port, PORTSC_PLC); 3288 } 3289 3290 static void xhci_complete(USBPort *port, USBPacket *packet) 3291 { 3292 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3293 3294 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3295 xhci_ep_nuke_one_xfer(xfer, 0); 3296 return; 3297 } 3298 xhci_complete_packet(xfer); 3299 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3300 } 3301 3302 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3303 { 3304 USBBus *bus = usb_bus_from_device(child); 3305 XHCIState *xhci = container_of(bus, XHCIState, bus); 3306 3307 xhci_detach_slot(xhci, uport); 3308 } 3309 3310 static USBPortOps xhci_uport_ops = { 3311 .attach = xhci_attach, 3312 .detach = xhci_detach, 3313 .wakeup = xhci_wakeup, 3314 .complete = xhci_complete, 3315 .child_detach = xhci_child_detach, 3316 }; 3317 3318 static int xhci_find_epid(USBEndpoint *ep) 3319 { 3320 if (ep->nr == 0) { 3321 return 1; 3322 } 3323 if (ep->pid == USB_TOKEN_IN) { 3324 return ep->nr * 2 + 1; 3325 } else { 3326 return ep->nr * 2; 3327 } 3328 } 3329 3330 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 3331 unsigned int slotid, unsigned int epid) 3332 { 3333 assert(slotid >= 1 && slotid <= xhci->numslots); 3334 3335 if (!xhci->slots[slotid - 1].uport) { 3336 return NULL; 3337 } 3338 3339 return usb_ep_get(xhci->slots[slotid - 1].uport->dev, 3340 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); 3341 } 3342 3343 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3344 unsigned int stream) 3345 { 3346 XHCIState *xhci = container_of(bus, XHCIState, bus); 3347 int slotid; 3348 3349 DPRINTF("%s\n", __func__); 3350 slotid = ep->dev->addr; 3351 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3352 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3353 return; 3354 } 3355 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3356 } 3357 3358 static USBBusOps xhci_bus_ops = { 3359 .wakeup_endpoint = xhci_wakeup_endpoint, 3360 }; 3361 3362 static void usb_xhci_init(XHCIState *xhci) 3363 { 3364 DeviceState *dev = DEVICE(xhci); 3365 XHCIPort *port; 3366 int i, usbports, speedmask; 3367 3368 xhci->usbsts = USBSTS_HCH; 3369 3370 if (xhci->numports_2 > MAXPORTS_2) { 3371 xhci->numports_2 = MAXPORTS_2; 3372 } 3373 if (xhci->numports_3 > MAXPORTS_3) { 3374 xhci->numports_3 = MAXPORTS_3; 3375 } 3376 usbports = MAX(xhci->numports_2, xhci->numports_3); 3377 xhci->numports = xhci->numports_2 + xhci->numports_3; 3378 3379 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3380 3381 for (i = 0; i < usbports; i++) { 3382 speedmask = 0; 3383 if (i < xhci->numports_2) { 3384 port = &xhci->ports[i]; 3385 port->portnr = i + 1; 3386 port->uport = &xhci->uports[i]; 3387 port->speedmask = 3388 USB_SPEED_MASK_LOW | 3389 USB_SPEED_MASK_FULL | 3390 USB_SPEED_MASK_HIGH; 3391 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3392 speedmask |= port->speedmask; 3393 } 3394 if (i < xhci->numports_3) { 3395 port = &xhci->ports[i + xhci->numports_2]; 3396 port->portnr = i + 1 + xhci->numports_2; 3397 port->uport = &xhci->uports[i]; 3398 port->speedmask = USB_SPEED_MASK_SUPER; 3399 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3400 speedmask |= port->speedmask; 3401 } 3402 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3403 &xhci_uport_ops, speedmask); 3404 } 3405 } 3406 3407 static int usb_xhci_initfn(struct PCIDevice *dev) 3408 { 3409 int i, ret; 3410 3411 XHCIState *xhci = XHCI(dev); 3412 3413 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3414 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3415 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3416 dev->config[0x60] = 0x30; /* release number */ 3417 3418 usb_xhci_init(xhci); 3419 3420 if (xhci->numintrs > MAXINTRS) { 3421 xhci->numintrs = MAXINTRS; 3422 } 3423 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3424 xhci->numintrs++; 3425 } 3426 if (xhci->numintrs < 1) { 3427 xhci->numintrs = 1; 3428 } 3429 if (xhci->numslots > MAXSLOTS) { 3430 xhci->numslots = MAXSLOTS; 3431 } 3432 if (xhci->numslots < 1) { 3433 xhci->numslots = 1; 3434 } 3435 3436 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3437 3438 xhci->irq = dev->irq[0]; 3439 3440 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3441 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3442 "capabilities", LEN_CAP); 3443 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3444 "operational", 0x400); 3445 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3446 "runtime", LEN_RUNTIME); 3447 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3448 "doorbell", LEN_DOORBELL); 3449 3450 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3451 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3452 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3453 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3454 3455 for (i = 0; i < xhci->numports; i++) { 3456 XHCIPort *port = &xhci->ports[i]; 3457 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3458 port->xhci = xhci; 3459 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3460 port->name, 0x10); 3461 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3462 } 3463 3464 pci_register_bar(dev, 0, 3465 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3466 &xhci->mem); 3467 3468 ret = pcie_endpoint_cap_init(dev, 0xa0); 3469 assert(ret >= 0); 3470 3471 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3472 msi_init(dev, 0x70, xhci->numintrs, true, false); 3473 } 3474 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3475 msix_init(dev, xhci->numintrs, 3476 &xhci->mem, 0, OFF_MSIX_TABLE, 3477 &xhci->mem, 0, OFF_MSIX_PBA, 3478 0x90); 3479 } 3480 3481 return 0; 3482 } 3483 3484 static int usb_xhci_post_load(void *opaque, int version_id) 3485 { 3486 XHCIState *xhci = opaque; 3487 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3488 XHCISlot *slot; 3489 XHCIEPContext *epctx; 3490 dma_addr_t dcbaap, pctx; 3491 uint32_t slot_ctx[4]; 3492 uint32_t ep_ctx[5]; 3493 int slotid, epid, state, intr; 3494 3495 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3496 3497 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3498 slot = &xhci->slots[slotid-1]; 3499 if (!slot->addressed) { 3500 continue; 3501 } 3502 slot->ctx = 3503 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3504 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3505 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3506 assert(slot->uport && slot->uport->dev); 3507 3508 for (epid = 1; epid <= 32; epid++) { 3509 pctx = slot->ctx + 32 * epid; 3510 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3511 state = ep_ctx[0] & EP_STATE_MASK; 3512 if (state == EP_DISABLED) { 3513 continue; 3514 } 3515 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3516 slot->eps[epid-1] = epctx; 3517 xhci_init_epctx(epctx, pctx, ep_ctx); 3518 epctx->state = state; 3519 if (state == EP_RUNNING) { 3520 /* kick endpoint after vmload is finished */ 3521 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3522 } 3523 } 3524 } 3525 3526 for (intr = 0; intr < xhci->numintrs; intr++) { 3527 if (xhci->intr[intr].msix_used) { 3528 msix_vector_use(pci_dev, intr); 3529 } else { 3530 msix_vector_unuse(pci_dev, intr); 3531 } 3532 } 3533 3534 return 0; 3535 } 3536 3537 static const VMStateDescription vmstate_xhci_ring = { 3538 .name = "xhci-ring", 3539 .version_id = 1, 3540 .fields = (VMStateField[]) { 3541 VMSTATE_UINT64(dequeue, XHCIRing), 3542 VMSTATE_BOOL(ccs, XHCIRing), 3543 VMSTATE_END_OF_LIST() 3544 } 3545 }; 3546 3547 static const VMStateDescription vmstate_xhci_port = { 3548 .name = "xhci-port", 3549 .version_id = 1, 3550 .fields = (VMStateField[]) { 3551 VMSTATE_UINT32(portsc, XHCIPort), 3552 VMSTATE_END_OF_LIST() 3553 } 3554 }; 3555 3556 static const VMStateDescription vmstate_xhci_slot = { 3557 .name = "xhci-slot", 3558 .version_id = 1, 3559 .fields = (VMStateField[]) { 3560 VMSTATE_BOOL(enabled, XHCISlot), 3561 VMSTATE_BOOL(addressed, XHCISlot), 3562 VMSTATE_END_OF_LIST() 3563 } 3564 }; 3565 3566 static const VMStateDescription vmstate_xhci_event = { 3567 .name = "xhci-event", 3568 .version_id = 1, 3569 .fields = (VMStateField[]) { 3570 VMSTATE_UINT32(type, XHCIEvent), 3571 VMSTATE_UINT32(ccode, XHCIEvent), 3572 VMSTATE_UINT64(ptr, XHCIEvent), 3573 VMSTATE_UINT32(length, XHCIEvent), 3574 VMSTATE_UINT32(flags, XHCIEvent), 3575 VMSTATE_UINT8(slotid, XHCIEvent), 3576 VMSTATE_UINT8(epid, XHCIEvent), 3577 } 3578 }; 3579 3580 static bool xhci_er_full(void *opaque, int version_id) 3581 { 3582 struct XHCIInterrupter *intr = opaque; 3583 return intr->er_full; 3584 } 3585 3586 static const VMStateDescription vmstate_xhci_intr = { 3587 .name = "xhci-intr", 3588 .version_id = 1, 3589 .fields = (VMStateField[]) { 3590 /* registers */ 3591 VMSTATE_UINT32(iman, XHCIInterrupter), 3592 VMSTATE_UINT32(imod, XHCIInterrupter), 3593 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3594 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3595 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3596 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3597 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3598 3599 /* state */ 3600 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3601 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3602 VMSTATE_UINT64(er_start, XHCIInterrupter), 3603 VMSTATE_UINT32(er_size, XHCIInterrupter), 3604 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3605 3606 /* event queue (used if ring is full) */ 3607 VMSTATE_BOOL(er_full, XHCIInterrupter), 3608 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3609 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3610 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3611 xhci_er_full, 1, 3612 vmstate_xhci_event, XHCIEvent), 3613 3614 VMSTATE_END_OF_LIST() 3615 } 3616 }; 3617 3618 static const VMStateDescription vmstate_xhci = { 3619 .name = "xhci", 3620 .version_id = 1, 3621 .post_load = usb_xhci_post_load, 3622 .fields = (VMStateField[]) { 3623 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3624 VMSTATE_MSIX(parent_obj, XHCIState), 3625 3626 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3627 vmstate_xhci_port, XHCIPort), 3628 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3629 vmstate_xhci_slot, XHCISlot), 3630 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3631 vmstate_xhci_intr, XHCIInterrupter), 3632 3633 /* Operational Registers */ 3634 VMSTATE_UINT32(usbcmd, XHCIState), 3635 VMSTATE_UINT32(usbsts, XHCIState), 3636 VMSTATE_UINT32(dnctrl, XHCIState), 3637 VMSTATE_UINT32(crcr_low, XHCIState), 3638 VMSTATE_UINT32(crcr_high, XHCIState), 3639 VMSTATE_UINT32(dcbaap_low, XHCIState), 3640 VMSTATE_UINT32(dcbaap_high, XHCIState), 3641 VMSTATE_UINT32(config, XHCIState), 3642 3643 /* Runtime Registers & state */ 3644 VMSTATE_INT64(mfindex_start, XHCIState), 3645 VMSTATE_TIMER(mfwrap_timer, XHCIState), 3646 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3647 3648 VMSTATE_END_OF_LIST() 3649 } 3650 }; 3651 3652 static Property xhci_properties[] = { 3653 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3654 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3655 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3656 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3657 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3658 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3659 DEFINE_PROP_END_OF_LIST(), 3660 }; 3661 3662 static void xhci_class_init(ObjectClass *klass, void *data) 3663 { 3664 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3665 DeviceClass *dc = DEVICE_CLASS(klass); 3666 3667 dc->vmsd = &vmstate_xhci; 3668 dc->props = xhci_properties; 3669 dc->reset = xhci_reset; 3670 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3671 k->init = usb_xhci_initfn; 3672 k->vendor_id = PCI_VENDOR_ID_NEC; 3673 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3674 k->class_id = PCI_CLASS_SERIAL_USB; 3675 k->revision = 0x03; 3676 k->is_express = 1; 3677 k->no_hotplug = 1; 3678 } 3679 3680 static const TypeInfo xhci_info = { 3681 .name = TYPE_XHCI, 3682 .parent = TYPE_PCI_DEVICE, 3683 .instance_size = sizeof(XHCIState), 3684 .class_init = xhci_class_init, 3685 }; 3686 3687 static void xhci_register_types(void) 3688 { 3689 type_register_static(&xhci_info); 3690 } 3691 3692 type_init(xhci_register_types) 3693