1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t base; 330 dma_addr_t dequeue; 331 bool ccs; 332 } XHCIRing; 333 334 typedef struct XHCIPort { 335 XHCIState *xhci; 336 uint32_t portsc; 337 uint32_t portnr; 338 USBPort *uport; 339 uint32_t speedmask; 340 char name[16]; 341 MemoryRegion mem; 342 } XHCIPort; 343 344 typedef struct XHCITransfer { 345 XHCIState *xhci; 346 USBPacket packet; 347 QEMUSGList sgl; 348 bool running_async; 349 bool running_retry; 350 bool cancelled; 351 bool complete; 352 bool int_req; 353 unsigned int iso_pkts; 354 unsigned int slotid; 355 unsigned int epid; 356 unsigned int streamid; 357 bool in_xfer; 358 bool iso_xfer; 359 360 unsigned int trb_count; 361 unsigned int trb_alloced; 362 XHCITRB *trbs; 363 364 TRBCCode status; 365 366 unsigned int pkts; 367 unsigned int pktsize; 368 unsigned int cur_pkt; 369 370 uint64_t mfindex_kick; 371 } XHCITransfer; 372 373 struct XHCIStreamContext { 374 dma_addr_t pctx; 375 unsigned int sct; 376 XHCIRing ring; 377 XHCIStreamContext *sstreams; 378 }; 379 380 struct XHCIEPContext { 381 XHCIState *xhci; 382 unsigned int slotid; 383 unsigned int epid; 384 385 XHCIRing ring; 386 unsigned int next_xfer; 387 unsigned int comp_xfer; 388 XHCITransfer transfers[TD_QUEUE]; 389 XHCITransfer *retry; 390 EPType type; 391 dma_addr_t pctx; 392 unsigned int max_psize; 393 uint32_t state; 394 395 /* streams */ 396 unsigned int max_pstreams; 397 bool lsa; 398 unsigned int nr_pstreams; 399 XHCIStreamContext *pstreams; 400 401 /* iso xfer scheduling */ 402 unsigned int interval; 403 int64_t mfindex_last; 404 QEMUTimer *kick_timer; 405 }; 406 407 typedef struct XHCISlot { 408 bool enabled; 409 dma_addr_t ctx; 410 USBPort *uport; 411 XHCIEPContext * eps[31]; 412 } XHCISlot; 413 414 typedef struct XHCIEvent { 415 TRBType type; 416 TRBCCode ccode; 417 uint64_t ptr; 418 uint32_t length; 419 uint32_t flags; 420 uint8_t slotid; 421 uint8_t epid; 422 } XHCIEvent; 423 424 typedef struct XHCIInterrupter { 425 uint32_t iman; 426 uint32_t imod; 427 uint32_t erstsz; 428 uint32_t erstba_low; 429 uint32_t erstba_high; 430 uint32_t erdp_low; 431 uint32_t erdp_high; 432 433 bool msix_used, er_pcs, er_full; 434 435 dma_addr_t er_start; 436 uint32_t er_size; 437 unsigned int er_ep_idx; 438 439 XHCIEvent ev_buffer[EV_QUEUE]; 440 unsigned int ev_buffer_put; 441 unsigned int ev_buffer_get; 442 443 } XHCIInterrupter; 444 445 struct XHCIState { 446 PCIDevice pci_dev; 447 USBBus bus; 448 qemu_irq irq; 449 MemoryRegion mem; 450 MemoryRegion mem_cap; 451 MemoryRegion mem_oper; 452 MemoryRegion mem_runtime; 453 MemoryRegion mem_doorbell; 454 455 /* properties */ 456 uint32_t numports_2; 457 uint32_t numports_3; 458 uint32_t numintrs; 459 uint32_t numslots; 460 uint32_t flags; 461 462 /* Operational Registers */ 463 uint32_t usbcmd; 464 uint32_t usbsts; 465 uint32_t dnctrl; 466 uint32_t crcr_low; 467 uint32_t crcr_high; 468 uint32_t dcbaap_low; 469 uint32_t dcbaap_high; 470 uint32_t config; 471 472 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 473 XHCIPort ports[MAXPORTS]; 474 XHCISlot slots[MAXSLOTS]; 475 uint32_t numports; 476 477 /* Runtime Registers */ 478 int64_t mfindex_start; 479 QEMUTimer *mfwrap_timer; 480 XHCIInterrupter intr[MAXINTRS]; 481 482 XHCIRing cmd_ring; 483 }; 484 485 typedef struct XHCIEvRingSeg { 486 uint32_t addr_low; 487 uint32_t addr_high; 488 uint32_t size; 489 uint32_t rsvd; 490 } XHCIEvRingSeg; 491 492 enum xhci_flags { 493 XHCI_FLAG_USE_MSI = 1, 494 XHCI_FLAG_USE_MSI_X, 495 }; 496 497 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 498 unsigned int epid, unsigned int streamid); 499 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 500 unsigned int epid); 501 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 502 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 503 504 static const char *TRBType_names[] = { 505 [TRB_RESERVED] = "TRB_RESERVED", 506 [TR_NORMAL] = "TR_NORMAL", 507 [TR_SETUP] = "TR_SETUP", 508 [TR_DATA] = "TR_DATA", 509 [TR_STATUS] = "TR_STATUS", 510 [TR_ISOCH] = "TR_ISOCH", 511 [TR_LINK] = "TR_LINK", 512 [TR_EVDATA] = "TR_EVDATA", 513 [TR_NOOP] = "TR_NOOP", 514 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 515 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 516 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 517 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 518 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 519 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 520 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 521 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 522 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 523 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 524 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 525 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 526 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 527 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 528 [CR_NOOP] = "CR_NOOP", 529 [ER_TRANSFER] = "ER_TRANSFER", 530 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 531 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 532 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 533 [ER_DOORBELL] = "ER_DOORBELL", 534 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 535 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 536 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 537 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 538 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 539 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 540 }; 541 542 static const char *TRBCCode_names[] = { 543 [CC_INVALID] = "CC_INVALID", 544 [CC_SUCCESS] = "CC_SUCCESS", 545 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 546 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 547 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 548 [CC_TRB_ERROR] = "CC_TRB_ERROR", 549 [CC_STALL_ERROR] = "CC_STALL_ERROR", 550 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 551 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 552 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 553 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 554 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 555 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 556 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 557 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 558 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 559 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 560 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 561 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 562 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 563 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 564 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 565 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 566 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 567 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 568 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 569 [CC_STOPPED] = "CC_STOPPED", 570 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 571 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 572 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 573 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 574 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 575 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 576 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 577 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 578 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 579 }; 580 581 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 582 { 583 if (index >= llen || list[index] == NULL) { 584 return "???"; 585 } 586 return list[index]; 587 } 588 589 static const char *trb_name(XHCITRB *trb) 590 { 591 return lookup_name(TRB_TYPE(*trb), TRBType_names, 592 ARRAY_SIZE(TRBType_names)); 593 } 594 595 static const char *event_name(XHCIEvent *event) 596 { 597 return lookup_name(event->ccode, TRBCCode_names, 598 ARRAY_SIZE(TRBCCode_names)); 599 } 600 601 static uint64_t xhci_mfindex_get(XHCIState *xhci) 602 { 603 int64_t now = qemu_get_clock_ns(vm_clock); 604 return (now - xhci->mfindex_start) / 125000; 605 } 606 607 static void xhci_mfwrap_update(XHCIState *xhci) 608 { 609 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 610 uint32_t mfindex, left; 611 int64_t now; 612 613 if ((xhci->usbcmd & bits) == bits) { 614 now = qemu_get_clock_ns(vm_clock); 615 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 616 left = 0x4000 - mfindex; 617 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 618 } else { 619 qemu_del_timer(xhci->mfwrap_timer); 620 } 621 } 622 623 static void xhci_mfwrap_timer(void *opaque) 624 { 625 XHCIState *xhci = opaque; 626 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 627 628 xhci_event(xhci, &wrap, 0); 629 xhci_mfwrap_update(xhci); 630 } 631 632 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 633 { 634 if (sizeof(dma_addr_t) == 4) { 635 return low; 636 } else { 637 return low | (((dma_addr_t)high << 16) << 16); 638 } 639 } 640 641 static inline dma_addr_t xhci_mask64(uint64_t addr) 642 { 643 if (sizeof(dma_addr_t) == 4) { 644 return addr & 0xffffffff; 645 } else { 646 return addr; 647 } 648 } 649 650 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 651 uint32_t *buf, size_t len) 652 { 653 int i; 654 655 assert((len % sizeof(uint32_t)) == 0); 656 657 pci_dma_read(&xhci->pci_dev, addr, buf, len); 658 659 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 660 buf[i] = le32_to_cpu(buf[i]); 661 } 662 } 663 664 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 665 uint32_t *buf, size_t len) 666 { 667 int i; 668 uint32_t tmp[len / sizeof(uint32_t)]; 669 670 assert((len % sizeof(uint32_t)) == 0); 671 672 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 673 tmp[i] = cpu_to_le32(buf[i]); 674 } 675 pci_dma_write(&xhci->pci_dev, addr, tmp, len); 676 } 677 678 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 679 { 680 int index; 681 682 if (!uport->dev) { 683 return NULL; 684 } 685 switch (uport->dev->speed) { 686 case USB_SPEED_LOW: 687 case USB_SPEED_FULL: 688 case USB_SPEED_HIGH: 689 index = uport->index; 690 break; 691 case USB_SPEED_SUPER: 692 index = uport->index + xhci->numports_2; 693 break; 694 default: 695 return NULL; 696 } 697 return &xhci->ports[index]; 698 } 699 700 static void xhci_intx_update(XHCIState *xhci) 701 { 702 int level = 0; 703 704 if (msix_enabled(&xhci->pci_dev) || 705 msi_enabled(&xhci->pci_dev)) { 706 return; 707 } 708 709 if (xhci->intr[0].iman & IMAN_IP && 710 xhci->intr[0].iman & IMAN_IE && 711 xhci->usbcmd & USBCMD_INTE) { 712 level = 1; 713 } 714 715 trace_usb_xhci_irq_intx(level); 716 qemu_set_irq(xhci->irq, level); 717 } 718 719 static void xhci_msix_update(XHCIState *xhci, int v) 720 { 721 bool enabled; 722 723 if (!msix_enabled(&xhci->pci_dev)) { 724 return; 725 } 726 727 enabled = xhci->intr[v].iman & IMAN_IE; 728 if (enabled == xhci->intr[v].msix_used) { 729 return; 730 } 731 732 if (enabled) { 733 trace_usb_xhci_irq_msix_use(v); 734 msix_vector_use(&xhci->pci_dev, v); 735 xhci->intr[v].msix_used = true; 736 } else { 737 trace_usb_xhci_irq_msix_unuse(v); 738 msix_vector_unuse(&xhci->pci_dev, v); 739 xhci->intr[v].msix_used = false; 740 } 741 } 742 743 static void xhci_intr_raise(XHCIState *xhci, int v) 744 { 745 xhci->intr[v].erdp_low |= ERDP_EHB; 746 xhci->intr[v].iman |= IMAN_IP; 747 xhci->usbsts |= USBSTS_EINT; 748 749 if (!(xhci->intr[v].iman & IMAN_IE)) { 750 return; 751 } 752 753 if (!(xhci->usbcmd & USBCMD_INTE)) { 754 return; 755 } 756 757 if (msix_enabled(&xhci->pci_dev)) { 758 trace_usb_xhci_irq_msix(v); 759 msix_notify(&xhci->pci_dev, v); 760 return; 761 } 762 763 if (msi_enabled(&xhci->pci_dev)) { 764 trace_usb_xhci_irq_msi(v); 765 msi_notify(&xhci->pci_dev, v); 766 return; 767 } 768 769 if (v == 0) { 770 trace_usb_xhci_irq_intx(1); 771 qemu_set_irq(xhci->irq, 1); 772 } 773 } 774 775 static inline int xhci_running(XHCIState *xhci) 776 { 777 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 778 } 779 780 static void xhci_die(XHCIState *xhci) 781 { 782 xhci->usbsts |= USBSTS_HCE; 783 fprintf(stderr, "xhci: asserted controller error\n"); 784 } 785 786 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 787 { 788 XHCIInterrupter *intr = &xhci->intr[v]; 789 XHCITRB ev_trb; 790 dma_addr_t addr; 791 792 ev_trb.parameter = cpu_to_le64(event->ptr); 793 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 794 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 795 event->flags | (event->type << TRB_TYPE_SHIFT); 796 if (intr->er_pcs) { 797 ev_trb.control |= TRB_C; 798 } 799 ev_trb.control = cpu_to_le32(ev_trb.control); 800 801 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 802 event_name(event), ev_trb.parameter, 803 ev_trb.status, ev_trb.control); 804 805 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 806 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 807 808 intr->er_ep_idx++; 809 if (intr->er_ep_idx >= intr->er_size) { 810 intr->er_ep_idx = 0; 811 intr->er_pcs = !intr->er_pcs; 812 } 813 } 814 815 static void xhci_events_update(XHCIState *xhci, int v) 816 { 817 XHCIInterrupter *intr = &xhci->intr[v]; 818 dma_addr_t erdp; 819 unsigned int dp_idx; 820 bool do_irq = 0; 821 822 if (xhci->usbsts & USBSTS_HCH) { 823 return; 824 } 825 826 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 827 if (erdp < intr->er_start || 828 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 829 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 830 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 831 v, intr->er_start, intr->er_size); 832 xhci_die(xhci); 833 return; 834 } 835 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 836 assert(dp_idx < intr->er_size); 837 838 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 839 * deadlocks when the ER is full. Hack it by holding off events until 840 * the driver decides to free at least half of the ring */ 841 if (intr->er_full) { 842 int er_free = dp_idx - intr->er_ep_idx; 843 if (er_free <= 0) { 844 er_free += intr->er_size; 845 } 846 if (er_free < (intr->er_size/2)) { 847 DPRINTF("xhci_events_update(): event ring still " 848 "more than half full (hack)\n"); 849 return; 850 } 851 } 852 853 while (intr->ev_buffer_put != intr->ev_buffer_get) { 854 assert(intr->er_full); 855 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 856 DPRINTF("xhci_events_update(): event ring full again\n"); 857 #ifndef ER_FULL_HACK 858 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 859 xhci_write_event(xhci, &full, v); 860 #endif 861 do_irq = 1; 862 break; 863 } 864 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 865 xhci_write_event(xhci, event, v); 866 intr->ev_buffer_get++; 867 do_irq = 1; 868 if (intr->ev_buffer_get == EV_QUEUE) { 869 intr->ev_buffer_get = 0; 870 } 871 } 872 873 if (do_irq) { 874 xhci_intr_raise(xhci, v); 875 } 876 877 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 878 DPRINTF("xhci_events_update(): event ring no longer full\n"); 879 intr->er_full = 0; 880 } 881 } 882 883 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 884 { 885 XHCIInterrupter *intr; 886 dma_addr_t erdp; 887 unsigned int dp_idx; 888 889 if (v >= xhci->numintrs) { 890 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 891 return; 892 } 893 intr = &xhci->intr[v]; 894 895 if (intr->er_full) { 896 DPRINTF("xhci_event(): ER full, queueing\n"); 897 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 898 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 899 return; 900 } 901 intr->ev_buffer[intr->ev_buffer_put++] = *event; 902 if (intr->ev_buffer_put == EV_QUEUE) { 903 intr->ev_buffer_put = 0; 904 } 905 return; 906 } 907 908 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 909 if (erdp < intr->er_start || 910 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 911 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 912 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 913 v, intr->er_start, intr->er_size); 914 xhci_die(xhci); 915 return; 916 } 917 918 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 919 assert(dp_idx < intr->er_size); 920 921 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 922 DPRINTF("xhci_event(): ER full, queueing\n"); 923 #ifndef ER_FULL_HACK 924 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 925 xhci_write_event(xhci, &full); 926 #endif 927 intr->er_full = 1; 928 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 929 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 930 return; 931 } 932 intr->ev_buffer[intr->ev_buffer_put++] = *event; 933 if (intr->ev_buffer_put == EV_QUEUE) { 934 intr->ev_buffer_put = 0; 935 } 936 } else { 937 xhci_write_event(xhci, event, v); 938 } 939 940 xhci_intr_raise(xhci, v); 941 } 942 943 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 944 dma_addr_t base) 945 { 946 ring->base = base; 947 ring->dequeue = base; 948 ring->ccs = 1; 949 } 950 951 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 952 dma_addr_t *addr) 953 { 954 while (1) { 955 TRBType type; 956 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 957 trb->addr = ring->dequeue; 958 trb->ccs = ring->ccs; 959 le64_to_cpus(&trb->parameter); 960 le32_to_cpus(&trb->status); 961 le32_to_cpus(&trb->control); 962 963 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 964 trb->parameter, trb->status, trb->control); 965 966 if ((trb->control & TRB_C) != ring->ccs) { 967 return 0; 968 } 969 970 type = TRB_TYPE(*trb); 971 972 if (type != TR_LINK) { 973 if (addr) { 974 *addr = ring->dequeue; 975 } 976 ring->dequeue += TRB_SIZE; 977 return type; 978 } else { 979 ring->dequeue = xhci_mask64(trb->parameter); 980 if (trb->control & TRB_LK_TC) { 981 ring->ccs = !ring->ccs; 982 } 983 } 984 } 985 } 986 987 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 988 { 989 XHCITRB trb; 990 int length = 0; 991 dma_addr_t dequeue = ring->dequeue; 992 bool ccs = ring->ccs; 993 /* hack to bundle together the two/three TDs that make a setup transfer */ 994 bool control_td_set = 0; 995 996 while (1) { 997 TRBType type; 998 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 999 le64_to_cpus(&trb.parameter); 1000 le32_to_cpus(&trb.status); 1001 le32_to_cpus(&trb.control); 1002 1003 if ((trb.control & TRB_C) != ccs) { 1004 return -length; 1005 } 1006 1007 type = TRB_TYPE(trb); 1008 1009 if (type == TR_LINK) { 1010 dequeue = xhci_mask64(trb.parameter); 1011 if (trb.control & TRB_LK_TC) { 1012 ccs = !ccs; 1013 } 1014 continue; 1015 } 1016 1017 length += 1; 1018 dequeue += TRB_SIZE; 1019 1020 if (type == TR_SETUP) { 1021 control_td_set = 1; 1022 } else if (type == TR_STATUS) { 1023 control_td_set = 0; 1024 } 1025 1026 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1027 return length; 1028 } 1029 } 1030 } 1031 1032 static void xhci_er_reset(XHCIState *xhci, int v) 1033 { 1034 XHCIInterrupter *intr = &xhci->intr[v]; 1035 XHCIEvRingSeg seg; 1036 1037 if (intr->erstsz == 0) { 1038 /* disabled */ 1039 intr->er_start = 0; 1040 intr->er_size = 0; 1041 return; 1042 } 1043 /* cache the (sole) event ring segment location */ 1044 if (intr->erstsz != 1) { 1045 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1046 xhci_die(xhci); 1047 return; 1048 } 1049 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1050 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 1051 le32_to_cpus(&seg.addr_low); 1052 le32_to_cpus(&seg.addr_high); 1053 le32_to_cpus(&seg.size); 1054 if (seg.size < 16 || seg.size > 4096) { 1055 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1056 xhci_die(xhci); 1057 return; 1058 } 1059 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1060 intr->er_size = seg.size; 1061 1062 intr->er_ep_idx = 0; 1063 intr->er_pcs = 1; 1064 intr->er_full = 0; 1065 1066 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1067 v, intr->er_start, intr->er_size); 1068 } 1069 1070 static void xhci_run(XHCIState *xhci) 1071 { 1072 trace_usb_xhci_run(); 1073 xhci->usbsts &= ~USBSTS_HCH; 1074 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1075 } 1076 1077 static void xhci_stop(XHCIState *xhci) 1078 { 1079 trace_usb_xhci_stop(); 1080 xhci->usbsts |= USBSTS_HCH; 1081 xhci->crcr_low &= ~CRCR_CRR; 1082 } 1083 1084 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1085 dma_addr_t base) 1086 { 1087 XHCIStreamContext *stctx; 1088 unsigned int i; 1089 1090 stctx = g_new0(XHCIStreamContext, count); 1091 for (i = 0; i < count; i++) { 1092 stctx[i].pctx = base + i * 16; 1093 stctx[i].sct = -1; 1094 } 1095 return stctx; 1096 } 1097 1098 static void xhci_reset_streams(XHCIEPContext *epctx) 1099 { 1100 unsigned int i; 1101 1102 for (i = 0; i < epctx->nr_pstreams; i++) { 1103 epctx->pstreams[i].sct = -1; 1104 g_free(epctx->pstreams[i].sstreams); 1105 } 1106 } 1107 1108 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1109 { 1110 assert(epctx->pstreams == NULL); 1111 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1112 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1113 } 1114 1115 static void xhci_free_streams(XHCIEPContext *epctx) 1116 { 1117 int i; 1118 1119 assert(epctx->pstreams != NULL); 1120 1121 if (!epctx->lsa) { 1122 for (i = 0; i < epctx->nr_pstreams; i++) { 1123 g_free(epctx->pstreams[i].sstreams); 1124 } 1125 } 1126 g_free(epctx->pstreams); 1127 epctx->pstreams = NULL; 1128 epctx->nr_pstreams = 0; 1129 } 1130 1131 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1132 unsigned int streamid, 1133 uint32_t *cc_error) 1134 { 1135 XHCIStreamContext *sctx; 1136 dma_addr_t base; 1137 uint32_t ctx[2], sct; 1138 1139 assert(streamid != 0); 1140 if (epctx->lsa) { 1141 if (streamid >= epctx->nr_pstreams) { 1142 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1143 return NULL; 1144 } 1145 sctx = epctx->pstreams + streamid; 1146 } else { 1147 FIXME("secondary streams not implemented yet"); 1148 } 1149 1150 if (sctx->sct == -1) { 1151 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1152 fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n", 1153 __func__, streamid, sctx->pctx, ctx[0], ctx[1]); 1154 sct = (ctx[0] >> 1) & 0x07; 1155 if (epctx->lsa && sct != 1) { 1156 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1157 return NULL; 1158 } 1159 sctx->sct = sct; 1160 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1161 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1162 } 1163 return sctx; 1164 } 1165 1166 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1167 XHCIStreamContext *sctx, uint32_t state) 1168 { 1169 uint32_t ctx[5]; 1170 uint32_t ctx2[2]; 1171 1172 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1173 ctx[0] &= ~EP_STATE_MASK; 1174 ctx[0] |= state; 1175 1176 /* update ring dequeue ptr */ 1177 if (epctx->nr_pstreams) { 1178 if (sctx != NULL) { 1179 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1180 ctx2[0] &= 0xe; 1181 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1182 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1183 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1184 } 1185 } else { 1186 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1187 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1188 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1189 epctx->pctx, state, ctx[3], ctx[2]); 1190 } 1191 1192 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1193 epctx->state = state; 1194 } 1195 1196 static void xhci_ep_kick_timer(void *opaque) 1197 { 1198 XHCIEPContext *epctx = opaque; 1199 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1200 } 1201 1202 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1203 unsigned int epid, dma_addr_t pctx, 1204 uint32_t *ctx) 1205 { 1206 XHCISlot *slot; 1207 XHCIEPContext *epctx; 1208 dma_addr_t dequeue; 1209 int i; 1210 1211 trace_usb_xhci_ep_enable(slotid, epid); 1212 assert(slotid >= 1 && slotid <= xhci->numslots); 1213 assert(epid >= 1 && epid <= 31); 1214 1215 slot = &xhci->slots[slotid-1]; 1216 if (slot->eps[epid-1]) { 1217 xhci_disable_ep(xhci, slotid, epid); 1218 } 1219 1220 epctx = g_malloc(sizeof(XHCIEPContext)); 1221 memset(epctx, 0, sizeof(XHCIEPContext)); 1222 epctx->xhci = xhci; 1223 epctx->slotid = slotid; 1224 epctx->epid = epid; 1225 1226 slot->eps[epid-1] = epctx; 1227 1228 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1229 1230 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1231 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1232 epctx->pctx = pctx; 1233 epctx->max_psize = ctx[1]>>16; 1234 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1235 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1236 epctx->lsa = (ctx[0] >> 15) & 1; 1237 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1238 epid/2, epid%2, epctx->max_psize); 1239 if (epctx->max_pstreams) { 1240 xhci_alloc_streams(epctx, dequeue); 1241 } else { 1242 xhci_ring_init(xhci, &epctx->ring, dequeue); 1243 epctx->ring.ccs = ctx[2] & 1; 1244 } 1245 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1246 usb_packet_init(&epctx->transfers[i].packet); 1247 } 1248 1249 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1250 epctx->mfindex_last = 0; 1251 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1252 1253 epctx->state = EP_RUNNING; 1254 ctx[0] &= ~EP_STATE_MASK; 1255 ctx[0] |= EP_RUNNING; 1256 1257 return CC_SUCCESS; 1258 } 1259 1260 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1261 { 1262 int killed = 0; 1263 1264 if (t->running_async) { 1265 usb_cancel_packet(&t->packet); 1266 t->running_async = 0; 1267 t->cancelled = 1; 1268 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1269 killed = 1; 1270 } 1271 if (t->running_retry) { 1272 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1273 if (epctx) { 1274 epctx->retry = NULL; 1275 qemu_del_timer(epctx->kick_timer); 1276 } 1277 t->running_retry = 0; 1278 } 1279 if (t->trbs) { 1280 g_free(t->trbs); 1281 } 1282 1283 t->trbs = NULL; 1284 t->trb_count = t->trb_alloced = 0; 1285 1286 return killed; 1287 } 1288 1289 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1290 unsigned int epid) 1291 { 1292 XHCISlot *slot; 1293 XHCIEPContext *epctx; 1294 int i, xferi, killed = 0; 1295 USBEndpoint *ep = NULL; 1296 assert(slotid >= 1 && slotid <= xhci->numslots); 1297 assert(epid >= 1 && epid <= 31); 1298 1299 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1300 1301 slot = &xhci->slots[slotid-1]; 1302 1303 if (!slot->eps[epid-1]) { 1304 return 0; 1305 } 1306 1307 epctx = slot->eps[epid-1]; 1308 1309 xferi = epctx->next_xfer; 1310 for (i = 0; i < TD_QUEUE; i++) { 1311 if (epctx->transfers[xferi].packet.ep) { 1312 ep = epctx->transfers[xferi].packet.ep; 1313 } 1314 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1315 epctx->transfers[xferi].packet.ep = NULL; 1316 xferi = (xferi + 1) % TD_QUEUE; 1317 } 1318 if (ep) { 1319 usb_device_ep_stopped(ep->dev, ep); 1320 } 1321 return killed; 1322 } 1323 1324 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1325 unsigned int epid) 1326 { 1327 XHCISlot *slot; 1328 XHCIEPContext *epctx; 1329 1330 trace_usb_xhci_ep_disable(slotid, epid); 1331 assert(slotid >= 1 && slotid <= xhci->numslots); 1332 assert(epid >= 1 && epid <= 31); 1333 1334 slot = &xhci->slots[slotid-1]; 1335 1336 if (!slot->eps[epid-1]) { 1337 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1338 return CC_SUCCESS; 1339 } 1340 1341 xhci_ep_nuke_xfers(xhci, slotid, epid); 1342 1343 epctx = slot->eps[epid-1]; 1344 1345 if (epctx->nr_pstreams) { 1346 xhci_free_streams(epctx); 1347 } 1348 1349 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1350 1351 qemu_free_timer(epctx->kick_timer); 1352 g_free(epctx); 1353 slot->eps[epid-1] = NULL; 1354 1355 return CC_SUCCESS; 1356 } 1357 1358 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1359 unsigned int epid) 1360 { 1361 XHCISlot *slot; 1362 XHCIEPContext *epctx; 1363 1364 trace_usb_xhci_ep_stop(slotid, epid); 1365 assert(slotid >= 1 && slotid <= xhci->numslots); 1366 1367 if (epid < 1 || epid > 31) { 1368 fprintf(stderr, "xhci: bad ep %d\n", epid); 1369 return CC_TRB_ERROR; 1370 } 1371 1372 slot = &xhci->slots[slotid-1]; 1373 1374 if (!slot->eps[epid-1]) { 1375 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1376 return CC_EP_NOT_ENABLED_ERROR; 1377 } 1378 1379 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1380 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1381 "data might be lost\n"); 1382 } 1383 1384 epctx = slot->eps[epid-1]; 1385 1386 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1387 1388 if (epctx->nr_pstreams) { 1389 xhci_reset_streams(epctx); 1390 } 1391 1392 return CC_SUCCESS; 1393 } 1394 1395 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1396 unsigned int epid) 1397 { 1398 XHCISlot *slot; 1399 XHCIEPContext *epctx; 1400 USBDevice *dev; 1401 1402 trace_usb_xhci_ep_reset(slotid, epid); 1403 assert(slotid >= 1 && slotid <= xhci->numslots); 1404 1405 if (epid < 1 || epid > 31) { 1406 fprintf(stderr, "xhci: bad ep %d\n", epid); 1407 return CC_TRB_ERROR; 1408 } 1409 1410 slot = &xhci->slots[slotid-1]; 1411 1412 if (!slot->eps[epid-1]) { 1413 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1414 return CC_EP_NOT_ENABLED_ERROR; 1415 } 1416 1417 epctx = slot->eps[epid-1]; 1418 1419 if (epctx->state != EP_HALTED) { 1420 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1421 epid, epctx->state); 1422 return CC_CONTEXT_STATE_ERROR; 1423 } 1424 1425 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1426 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1427 "data might be lost\n"); 1428 } 1429 1430 uint8_t ep = epid>>1; 1431 1432 if (epid & 1) { 1433 ep |= 0x80; 1434 } 1435 1436 dev = xhci->slots[slotid-1].uport->dev; 1437 if (!dev) { 1438 return CC_USB_TRANSACTION_ERROR; 1439 } 1440 1441 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1442 1443 if (epctx->nr_pstreams) { 1444 xhci_reset_streams(epctx); 1445 } 1446 1447 return CC_SUCCESS; 1448 } 1449 1450 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1451 unsigned int epid, unsigned int streamid, 1452 uint64_t pdequeue) 1453 { 1454 XHCISlot *slot; 1455 XHCIEPContext *epctx; 1456 XHCIStreamContext *sctx; 1457 dma_addr_t dequeue; 1458 1459 assert(slotid >= 1 && slotid <= xhci->numslots); 1460 1461 if (epid < 1 || epid > 31) { 1462 fprintf(stderr, "xhci: bad ep %d\n", epid); 1463 return CC_TRB_ERROR; 1464 } 1465 1466 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1467 dequeue = xhci_mask64(pdequeue); 1468 1469 slot = &xhci->slots[slotid-1]; 1470 1471 if (!slot->eps[epid-1]) { 1472 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1473 return CC_EP_NOT_ENABLED_ERROR; 1474 } 1475 1476 epctx = slot->eps[epid-1]; 1477 1478 if (epctx->state != EP_STOPPED) { 1479 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1480 return CC_CONTEXT_STATE_ERROR; 1481 } 1482 1483 if (epctx->nr_pstreams) { 1484 uint32_t err; 1485 sctx = xhci_find_stream(epctx, streamid, &err); 1486 if (sctx == NULL) { 1487 return err; 1488 } 1489 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1490 sctx->ring.ccs = dequeue & 1; 1491 } else { 1492 sctx = NULL; 1493 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1494 epctx->ring.ccs = dequeue & 1; 1495 } 1496 1497 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1498 1499 return CC_SUCCESS; 1500 } 1501 1502 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1503 { 1504 XHCIState *xhci = xfer->xhci; 1505 int i; 1506 1507 xfer->int_req = false; 1508 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1509 for (i = 0; i < xfer->trb_count; i++) { 1510 XHCITRB *trb = &xfer->trbs[i]; 1511 dma_addr_t addr; 1512 unsigned int chunk = 0; 1513 1514 if (trb->control & TRB_TR_IOC) { 1515 xfer->int_req = true; 1516 } 1517 1518 switch (TRB_TYPE(*trb)) { 1519 case TR_DATA: 1520 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1521 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1522 goto err; 1523 } 1524 /* fallthrough */ 1525 case TR_NORMAL: 1526 case TR_ISOCH: 1527 addr = xhci_mask64(trb->parameter); 1528 chunk = trb->status & 0x1ffff; 1529 if (trb->control & TRB_TR_IDT) { 1530 if (chunk > 8 || in_xfer) { 1531 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1532 goto err; 1533 } 1534 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1535 } else { 1536 qemu_sglist_add(&xfer->sgl, addr, chunk); 1537 } 1538 break; 1539 } 1540 } 1541 1542 return 0; 1543 1544 err: 1545 qemu_sglist_destroy(&xfer->sgl); 1546 xhci_die(xhci); 1547 return -1; 1548 } 1549 1550 static void xhci_xfer_unmap(XHCITransfer *xfer) 1551 { 1552 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1553 qemu_sglist_destroy(&xfer->sgl); 1554 } 1555 1556 static void xhci_xfer_report(XHCITransfer *xfer) 1557 { 1558 uint32_t edtla = 0; 1559 unsigned int left; 1560 bool reported = 0; 1561 bool shortpkt = 0; 1562 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1563 XHCIState *xhci = xfer->xhci; 1564 int i; 1565 1566 left = xfer->packet.actual_length; 1567 1568 for (i = 0; i < xfer->trb_count; i++) { 1569 XHCITRB *trb = &xfer->trbs[i]; 1570 unsigned int chunk = 0; 1571 1572 switch (TRB_TYPE(*trb)) { 1573 case TR_DATA: 1574 case TR_NORMAL: 1575 case TR_ISOCH: 1576 chunk = trb->status & 0x1ffff; 1577 if (chunk > left) { 1578 chunk = left; 1579 if (xfer->status == CC_SUCCESS) { 1580 shortpkt = 1; 1581 } 1582 } 1583 left -= chunk; 1584 edtla += chunk; 1585 break; 1586 case TR_STATUS: 1587 reported = 0; 1588 shortpkt = 0; 1589 break; 1590 } 1591 1592 if (!reported && ((trb->control & TRB_TR_IOC) || 1593 (shortpkt && (trb->control & TRB_TR_ISP)) || 1594 (xfer->status != CC_SUCCESS && left == 0))) { 1595 event.slotid = xfer->slotid; 1596 event.epid = xfer->epid; 1597 event.length = (trb->status & 0x1ffff) - chunk; 1598 event.flags = 0; 1599 event.ptr = trb->addr; 1600 if (xfer->status == CC_SUCCESS) { 1601 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1602 } else { 1603 event.ccode = xfer->status; 1604 } 1605 if (TRB_TYPE(*trb) == TR_EVDATA) { 1606 event.ptr = trb->parameter; 1607 event.flags |= TRB_EV_ED; 1608 event.length = edtla & 0xffffff; 1609 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1610 edtla = 0; 1611 } 1612 xhci_event(xhci, &event, TRB_INTR(*trb)); 1613 reported = 1; 1614 if (xfer->status != CC_SUCCESS) { 1615 return; 1616 } 1617 } 1618 } 1619 } 1620 1621 static void xhci_stall_ep(XHCITransfer *xfer) 1622 { 1623 XHCIState *xhci = xfer->xhci; 1624 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1625 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1626 uint32_t err; 1627 XHCIStreamContext *sctx; 1628 1629 if (epctx->nr_pstreams) { 1630 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1631 if (sctx == NULL) { 1632 return; 1633 } 1634 sctx->ring.dequeue = xfer->trbs[0].addr; 1635 sctx->ring.ccs = xfer->trbs[0].ccs; 1636 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1637 } else { 1638 epctx->ring.dequeue = xfer->trbs[0].addr; 1639 epctx->ring.ccs = xfer->trbs[0].ccs; 1640 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1641 } 1642 } 1643 1644 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1645 XHCIEPContext *epctx); 1646 1647 static int xhci_setup_packet(XHCITransfer *xfer) 1648 { 1649 XHCIState *xhci = xfer->xhci; 1650 USBDevice *dev; 1651 USBEndpoint *ep; 1652 int dir; 1653 1654 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1655 1656 if (xfer->packet.ep) { 1657 ep = xfer->packet.ep; 1658 dev = ep->dev; 1659 } else { 1660 if (!xhci->slots[xfer->slotid-1].uport) { 1661 fprintf(stderr, "xhci: slot %d has no device\n", 1662 xfer->slotid); 1663 return -1; 1664 } 1665 dev = xhci->slots[xfer->slotid-1].uport->dev; 1666 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1667 } 1668 1669 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1670 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1671 xfer->trbs[0].addr, false, xfer->int_req); 1672 usb_packet_map(&xfer->packet, &xfer->sgl); 1673 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1674 xfer->packet.pid, dev->addr, ep->nr); 1675 return 0; 1676 } 1677 1678 static int xhci_complete_packet(XHCITransfer *xfer) 1679 { 1680 if (xfer->packet.status == USB_RET_ASYNC) { 1681 trace_usb_xhci_xfer_async(xfer); 1682 xfer->running_async = 1; 1683 xfer->running_retry = 0; 1684 xfer->complete = 0; 1685 xfer->cancelled = 0; 1686 return 0; 1687 } else if (xfer->packet.status == USB_RET_NAK) { 1688 trace_usb_xhci_xfer_nak(xfer); 1689 xfer->running_async = 0; 1690 xfer->running_retry = 1; 1691 xfer->complete = 0; 1692 xfer->cancelled = 0; 1693 return 0; 1694 } else { 1695 xfer->running_async = 0; 1696 xfer->running_retry = 0; 1697 xfer->complete = 1; 1698 xhci_xfer_unmap(xfer); 1699 } 1700 1701 if (xfer->packet.status == USB_RET_SUCCESS) { 1702 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1703 xfer->status = CC_SUCCESS; 1704 xhci_xfer_report(xfer); 1705 return 0; 1706 } 1707 1708 /* error */ 1709 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1710 switch (xfer->packet.status) { 1711 case USB_RET_NODEV: 1712 xfer->status = CC_USB_TRANSACTION_ERROR; 1713 xhci_xfer_report(xfer); 1714 xhci_stall_ep(xfer); 1715 break; 1716 case USB_RET_STALL: 1717 xfer->status = CC_STALL_ERROR; 1718 xhci_xfer_report(xfer); 1719 xhci_stall_ep(xfer); 1720 break; 1721 default: 1722 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1723 xfer->packet.status); 1724 FIXME("unhandled USB_RET_*"); 1725 } 1726 return 0; 1727 } 1728 1729 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1730 { 1731 XHCITRB *trb_setup, *trb_status; 1732 uint8_t bmRequestType; 1733 1734 trb_setup = &xfer->trbs[0]; 1735 trb_status = &xfer->trbs[xfer->trb_count-1]; 1736 1737 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1738 1739 /* at most one Event Data TRB allowed after STATUS */ 1740 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1741 trb_status--; 1742 } 1743 1744 /* do some sanity checks */ 1745 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1746 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1747 TRB_TYPE(*trb_setup)); 1748 return -1; 1749 } 1750 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1751 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1752 TRB_TYPE(*trb_status)); 1753 return -1; 1754 } 1755 if (!(trb_setup->control & TRB_TR_IDT)) { 1756 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1757 return -1; 1758 } 1759 if ((trb_setup->status & 0x1ffff) != 8) { 1760 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1761 (trb_setup->status & 0x1ffff)); 1762 return -1; 1763 } 1764 1765 bmRequestType = trb_setup->parameter; 1766 1767 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1768 xfer->iso_xfer = false; 1769 1770 if (xhci_setup_packet(xfer) < 0) { 1771 return -1; 1772 } 1773 xfer->packet.parameter = trb_setup->parameter; 1774 1775 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1776 1777 xhci_complete_packet(xfer); 1778 if (!xfer->running_async && !xfer->running_retry) { 1779 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1780 } 1781 return 0; 1782 } 1783 1784 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1785 XHCIEPContext *epctx, uint64_t mfindex) 1786 { 1787 if (xfer->trbs[0].control & TRB_TR_SIA) { 1788 uint64_t asap = ((mfindex + epctx->interval - 1) & 1789 ~(epctx->interval-1)); 1790 if (asap >= epctx->mfindex_last && 1791 asap <= epctx->mfindex_last + epctx->interval * 4) { 1792 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1793 } else { 1794 xfer->mfindex_kick = asap; 1795 } 1796 } else { 1797 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1798 & TRB_TR_FRAMEID_MASK; 1799 xfer->mfindex_kick |= mfindex & ~0x3fff; 1800 if (xfer->mfindex_kick < mfindex) { 1801 xfer->mfindex_kick += 0x4000; 1802 } 1803 } 1804 } 1805 1806 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1807 XHCIEPContext *epctx, uint64_t mfindex) 1808 { 1809 if (xfer->mfindex_kick > mfindex) { 1810 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1811 (xfer->mfindex_kick - mfindex) * 125000); 1812 xfer->running_retry = 1; 1813 } else { 1814 epctx->mfindex_last = xfer->mfindex_kick; 1815 qemu_del_timer(epctx->kick_timer); 1816 xfer->running_retry = 0; 1817 } 1818 } 1819 1820 1821 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1822 { 1823 uint64_t mfindex; 1824 1825 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1826 1827 xfer->in_xfer = epctx->type>>2; 1828 1829 switch(epctx->type) { 1830 case ET_INTR_OUT: 1831 case ET_INTR_IN: 1832 case ET_BULK_OUT: 1833 case ET_BULK_IN: 1834 xfer->pkts = 0; 1835 xfer->iso_xfer = false; 1836 break; 1837 case ET_ISO_OUT: 1838 case ET_ISO_IN: 1839 xfer->pkts = 1; 1840 xfer->iso_xfer = true; 1841 mfindex = xhci_mfindex_get(xhci); 1842 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1843 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1844 if (xfer->running_retry) { 1845 return -1; 1846 } 1847 break; 1848 default: 1849 fprintf(stderr, "xhci: unknown or unhandled EP " 1850 "(type %d, in %d, ep %02x)\n", 1851 epctx->type, xfer->in_xfer, xfer->epid); 1852 return -1; 1853 } 1854 1855 if (xhci_setup_packet(xfer) < 0) { 1856 return -1; 1857 } 1858 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1859 1860 xhci_complete_packet(xfer); 1861 if (!xfer->running_async && !xfer->running_retry) { 1862 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1863 } 1864 return 0; 1865 } 1866 1867 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1868 { 1869 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1870 return xhci_submit(xhci, xfer, epctx); 1871 } 1872 1873 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1874 unsigned int epid, unsigned int streamid) 1875 { 1876 XHCIStreamContext *stctx; 1877 XHCIEPContext *epctx; 1878 XHCIRing *ring; 1879 USBEndpoint *ep = NULL; 1880 uint64_t mfindex; 1881 int length; 1882 int i; 1883 1884 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1885 assert(slotid >= 1 && slotid <= xhci->numslots); 1886 assert(epid >= 1 && epid <= 31); 1887 1888 if (!xhci->slots[slotid-1].enabled) { 1889 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1890 return; 1891 } 1892 epctx = xhci->slots[slotid-1].eps[epid-1]; 1893 if (!epctx) { 1894 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1895 epid, slotid); 1896 return; 1897 } 1898 1899 if (epctx->retry) { 1900 XHCITransfer *xfer = epctx->retry; 1901 1902 trace_usb_xhci_xfer_retry(xfer); 1903 assert(xfer->running_retry); 1904 if (xfer->iso_xfer) { 1905 /* retry delayed iso transfer */ 1906 mfindex = xhci_mfindex_get(xhci); 1907 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1908 if (xfer->running_retry) { 1909 return; 1910 } 1911 if (xhci_setup_packet(xfer) < 0) { 1912 return; 1913 } 1914 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1915 assert(xfer->packet.status != USB_RET_NAK); 1916 xhci_complete_packet(xfer); 1917 } else { 1918 /* retry nak'ed transfer */ 1919 if (xhci_setup_packet(xfer) < 0) { 1920 return; 1921 } 1922 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1923 if (xfer->packet.status == USB_RET_NAK) { 1924 return; 1925 } 1926 xhci_complete_packet(xfer); 1927 } 1928 assert(!xfer->running_retry); 1929 epctx->retry = NULL; 1930 } 1931 1932 if (epctx->state == EP_HALTED) { 1933 DPRINTF("xhci: ep halted, not running schedule\n"); 1934 return; 1935 } 1936 1937 1938 if (epctx->nr_pstreams) { 1939 uint32_t err; 1940 stctx = xhci_find_stream(epctx, streamid, &err); 1941 if (stctx == NULL) { 1942 return; 1943 } 1944 ring = &stctx->ring; 1945 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 1946 } else { 1947 ring = &epctx->ring; 1948 streamid = 0; 1949 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 1950 } 1951 assert(ring->base != 0); 1952 1953 while (1) { 1954 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1955 if (xfer->running_async || xfer->running_retry) { 1956 break; 1957 } 1958 length = xhci_ring_chain_length(xhci, ring); 1959 if (length < 0) { 1960 break; 1961 } else if (length == 0) { 1962 break; 1963 } 1964 if (xfer->trbs && xfer->trb_alloced < length) { 1965 xfer->trb_count = 0; 1966 xfer->trb_alloced = 0; 1967 g_free(xfer->trbs); 1968 xfer->trbs = NULL; 1969 } 1970 if (!xfer->trbs) { 1971 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1972 xfer->trb_alloced = length; 1973 } 1974 xfer->trb_count = length; 1975 1976 for (i = 0; i < length; i++) { 1977 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 1978 } 1979 xfer->xhci = xhci; 1980 xfer->epid = epid; 1981 xfer->slotid = slotid; 1982 xfer->streamid = streamid; 1983 1984 if (epid == 1) { 1985 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1986 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1987 ep = xfer->packet.ep; 1988 } else { 1989 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1990 } 1991 } else { 1992 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1993 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1994 ep = xfer->packet.ep; 1995 } else { 1996 if (!xfer->iso_xfer) { 1997 fprintf(stderr, "xhci: error firing data transfer\n"); 1998 } 1999 } 2000 } 2001 2002 if (epctx->state == EP_HALTED) { 2003 break; 2004 } 2005 if (xfer->running_retry) { 2006 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2007 epctx->retry = xfer; 2008 break; 2009 } 2010 } 2011 if (ep) { 2012 usb_device_flush_ep_queue(ep->dev, ep); 2013 } 2014 } 2015 2016 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2017 { 2018 trace_usb_xhci_slot_enable(slotid); 2019 assert(slotid >= 1 && slotid <= xhci->numslots); 2020 xhci->slots[slotid-1].enabled = 1; 2021 xhci->slots[slotid-1].uport = NULL; 2022 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2023 2024 return CC_SUCCESS; 2025 } 2026 2027 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2028 { 2029 int i; 2030 2031 trace_usb_xhci_slot_disable(slotid); 2032 assert(slotid >= 1 && slotid <= xhci->numslots); 2033 2034 for (i = 1; i <= 31; i++) { 2035 if (xhci->slots[slotid-1].eps[i-1]) { 2036 xhci_disable_ep(xhci, slotid, i); 2037 } 2038 } 2039 2040 xhci->slots[slotid-1].enabled = 0; 2041 return CC_SUCCESS; 2042 } 2043 2044 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2045 { 2046 USBPort *uport; 2047 char path[32]; 2048 int i, pos, port; 2049 2050 port = (slot_ctx[1]>>16) & 0xFF; 2051 port = xhci->ports[port-1].uport->index+1; 2052 pos = snprintf(path, sizeof(path), "%d", port); 2053 for (i = 0; i < 5; i++) { 2054 port = (slot_ctx[0] >> 4*i) & 0x0f; 2055 if (!port) { 2056 break; 2057 } 2058 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2059 } 2060 2061 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2062 if (strcmp(uport->path, path) == 0) { 2063 return uport; 2064 } 2065 } 2066 return NULL; 2067 } 2068 2069 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2070 uint64_t pictx, bool bsr) 2071 { 2072 XHCISlot *slot; 2073 USBPort *uport; 2074 USBDevice *dev; 2075 dma_addr_t ictx, octx, dcbaap; 2076 uint64_t poctx; 2077 uint32_t ictl_ctx[2]; 2078 uint32_t slot_ctx[4]; 2079 uint32_t ep0_ctx[5]; 2080 int i; 2081 TRBCCode res; 2082 2083 trace_usb_xhci_slot_address(slotid); 2084 assert(slotid >= 1 && slotid <= xhci->numslots); 2085 2086 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2087 poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid); 2088 ictx = xhci_mask64(pictx); 2089 octx = xhci_mask64(poctx); 2090 2091 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2092 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2093 2094 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2095 2096 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2097 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2098 ictl_ctx[0], ictl_ctx[1]); 2099 return CC_TRB_ERROR; 2100 } 2101 2102 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2103 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2104 2105 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2106 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2107 2108 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2109 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2110 2111 uport = xhci_lookup_uport(xhci, slot_ctx); 2112 if (uport == NULL) { 2113 fprintf(stderr, "xhci: port not found\n"); 2114 return CC_TRB_ERROR; 2115 } 2116 2117 dev = uport->dev; 2118 if (!dev) { 2119 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2120 return CC_USB_TRANSACTION_ERROR; 2121 } 2122 2123 for (i = 0; i < xhci->numslots; i++) { 2124 if (i == slotid-1) { 2125 continue; 2126 } 2127 if (xhci->slots[i].uport == uport) { 2128 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2129 uport->path, i+1); 2130 return CC_TRB_ERROR; 2131 } 2132 } 2133 2134 slot = &xhci->slots[slotid-1]; 2135 slot->uport = uport; 2136 slot->ctx = octx; 2137 2138 if (bsr) { 2139 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2140 } else { 2141 USBPacket p; 2142 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2143 usb_device_reset(dev); 2144 usb_packet_setup(&p, USB_TOKEN_OUT, 2145 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2146 0, false, false); 2147 usb_device_handle_control(dev, &p, 2148 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2149 slotid, 0, 0, NULL); 2150 assert(p.status != USB_RET_ASYNC); 2151 } 2152 2153 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2154 2155 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2156 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2157 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2158 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2159 2160 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2161 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2162 2163 return res; 2164 } 2165 2166 2167 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2168 uint64_t pictx, bool dc) 2169 { 2170 dma_addr_t ictx, octx; 2171 uint32_t ictl_ctx[2]; 2172 uint32_t slot_ctx[4]; 2173 uint32_t islot_ctx[4]; 2174 uint32_t ep_ctx[5]; 2175 int i; 2176 TRBCCode res; 2177 2178 trace_usb_xhci_slot_configure(slotid); 2179 assert(slotid >= 1 && slotid <= xhci->numslots); 2180 2181 ictx = xhci_mask64(pictx); 2182 octx = xhci->slots[slotid-1].ctx; 2183 2184 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2185 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2186 2187 if (dc) { 2188 for (i = 2; i <= 31; i++) { 2189 if (xhci->slots[slotid-1].eps[i-1]) { 2190 xhci_disable_ep(xhci, slotid, i); 2191 } 2192 } 2193 2194 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2195 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2196 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2197 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2198 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2199 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2200 2201 return CC_SUCCESS; 2202 } 2203 2204 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2205 2206 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2207 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2208 ictl_ctx[0], ictl_ctx[1]); 2209 return CC_TRB_ERROR; 2210 } 2211 2212 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2213 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2214 2215 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2216 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2217 return CC_CONTEXT_STATE_ERROR; 2218 } 2219 2220 for (i = 2; i <= 31; i++) { 2221 if (ictl_ctx[0] & (1<<i)) { 2222 xhci_disable_ep(xhci, slotid, i); 2223 } 2224 if (ictl_ctx[1] & (1<<i)) { 2225 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2226 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2227 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2228 ep_ctx[3], ep_ctx[4]); 2229 xhci_disable_ep(xhci, slotid, i); 2230 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2231 if (res != CC_SUCCESS) { 2232 return res; 2233 } 2234 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2235 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2236 ep_ctx[3], ep_ctx[4]); 2237 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2238 } 2239 } 2240 2241 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2242 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2243 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2244 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2245 SLOT_CONTEXT_ENTRIES_SHIFT); 2246 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2247 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2248 2249 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2250 2251 return CC_SUCCESS; 2252 } 2253 2254 2255 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2256 uint64_t pictx) 2257 { 2258 dma_addr_t ictx, octx; 2259 uint32_t ictl_ctx[2]; 2260 uint32_t iep0_ctx[5]; 2261 uint32_t ep0_ctx[5]; 2262 uint32_t islot_ctx[4]; 2263 uint32_t slot_ctx[4]; 2264 2265 trace_usb_xhci_slot_evaluate(slotid); 2266 assert(slotid >= 1 && slotid <= xhci->numslots); 2267 2268 ictx = xhci_mask64(pictx); 2269 octx = xhci->slots[slotid-1].ctx; 2270 2271 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2272 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2273 2274 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2275 2276 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2277 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2278 ictl_ctx[0], ictl_ctx[1]); 2279 return CC_TRB_ERROR; 2280 } 2281 2282 if (ictl_ctx[1] & 0x1) { 2283 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2284 2285 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2286 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2287 2288 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2289 2290 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2291 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2292 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2293 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2294 2295 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2296 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2297 2298 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2299 } 2300 2301 if (ictl_ctx[1] & 0x2) { 2302 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2303 2304 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2305 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2306 iep0_ctx[3], iep0_ctx[4]); 2307 2308 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2309 2310 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2311 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2312 2313 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2314 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2315 2316 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2317 } 2318 2319 return CC_SUCCESS; 2320 } 2321 2322 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2323 { 2324 uint32_t slot_ctx[4]; 2325 dma_addr_t octx; 2326 int i; 2327 2328 trace_usb_xhci_slot_reset(slotid); 2329 assert(slotid >= 1 && slotid <= xhci->numslots); 2330 2331 octx = xhci->slots[slotid-1].ctx; 2332 2333 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2334 2335 for (i = 2; i <= 31; i++) { 2336 if (xhci->slots[slotid-1].eps[i-1]) { 2337 xhci_disable_ep(xhci, slotid, i); 2338 } 2339 } 2340 2341 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2342 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2343 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2344 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2345 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2346 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2347 2348 return CC_SUCCESS; 2349 } 2350 2351 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2352 { 2353 unsigned int slotid; 2354 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2355 if (slotid < 1 || slotid > xhci->numslots) { 2356 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2357 event->ccode = CC_TRB_ERROR; 2358 return 0; 2359 } else if (!xhci->slots[slotid-1].enabled) { 2360 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2361 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2362 return 0; 2363 } 2364 return slotid; 2365 } 2366 2367 /* cleanup slot state on usb device detach */ 2368 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2369 { 2370 int slot, ep; 2371 2372 for (slot = 0; slot < xhci->numslots; slot++) { 2373 if (xhci->slots[slot].uport == uport) { 2374 break; 2375 } 2376 } 2377 if (slot == xhci->numslots) { 2378 return; 2379 } 2380 2381 for (ep = 0; ep < 31; ep++) { 2382 if (xhci->slots[slot].eps[ep]) { 2383 xhci_ep_nuke_xfers(xhci, slot+1, ep+1); 2384 } 2385 } 2386 xhci->slots[slot].uport = NULL; 2387 } 2388 2389 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2390 { 2391 dma_addr_t ctx; 2392 uint8_t bw_ctx[xhci->numports+1]; 2393 2394 DPRINTF("xhci_get_port_bandwidth()\n"); 2395 2396 ctx = xhci_mask64(pctx); 2397 2398 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2399 2400 /* TODO: actually implement real values here */ 2401 bw_ctx[0] = 0; 2402 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2403 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2404 2405 return CC_SUCCESS; 2406 } 2407 2408 static uint32_t rotl(uint32_t v, unsigned count) 2409 { 2410 count &= 31; 2411 return (v << count) | (v >> (32 - count)); 2412 } 2413 2414 2415 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2416 { 2417 uint32_t val; 2418 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2419 val += rotl(lo + 0x49434878, hi & 0x1F); 2420 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2421 return ~val; 2422 } 2423 2424 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2425 { 2426 uint32_t buf[8]; 2427 uint32_t obuf[8]; 2428 dma_addr_t paddr = xhci_mask64(addr); 2429 2430 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2431 2432 memcpy(obuf, buf, sizeof(obuf)); 2433 2434 if ((buf[0] & 0xff) == 2) { 2435 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2436 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2437 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2438 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2439 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2440 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2441 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2442 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2443 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2444 } 2445 2446 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2447 } 2448 2449 static void xhci_process_commands(XHCIState *xhci) 2450 { 2451 XHCITRB trb; 2452 TRBType type; 2453 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2454 dma_addr_t addr; 2455 unsigned int i, slotid = 0; 2456 2457 DPRINTF("xhci_process_commands()\n"); 2458 if (!xhci_running(xhci)) { 2459 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2460 return; 2461 } 2462 2463 xhci->crcr_low |= CRCR_CRR; 2464 2465 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2466 event.ptr = addr; 2467 switch (type) { 2468 case CR_ENABLE_SLOT: 2469 for (i = 0; i < xhci->numslots; i++) { 2470 if (!xhci->slots[i].enabled) { 2471 break; 2472 } 2473 } 2474 if (i >= xhci->numslots) { 2475 fprintf(stderr, "xhci: no device slots available\n"); 2476 event.ccode = CC_NO_SLOTS_ERROR; 2477 } else { 2478 slotid = i+1; 2479 event.ccode = xhci_enable_slot(xhci, slotid); 2480 } 2481 break; 2482 case CR_DISABLE_SLOT: 2483 slotid = xhci_get_slot(xhci, &event, &trb); 2484 if (slotid) { 2485 event.ccode = xhci_disable_slot(xhci, slotid); 2486 } 2487 break; 2488 case CR_ADDRESS_DEVICE: 2489 slotid = xhci_get_slot(xhci, &event, &trb); 2490 if (slotid) { 2491 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2492 trb.control & TRB_CR_BSR); 2493 } 2494 break; 2495 case CR_CONFIGURE_ENDPOINT: 2496 slotid = xhci_get_slot(xhci, &event, &trb); 2497 if (slotid) { 2498 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2499 trb.control & TRB_CR_DC); 2500 } 2501 break; 2502 case CR_EVALUATE_CONTEXT: 2503 slotid = xhci_get_slot(xhci, &event, &trb); 2504 if (slotid) { 2505 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2506 } 2507 break; 2508 case CR_STOP_ENDPOINT: 2509 slotid = xhci_get_slot(xhci, &event, &trb); 2510 if (slotid) { 2511 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2512 & TRB_CR_EPID_MASK; 2513 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2514 } 2515 break; 2516 case CR_RESET_ENDPOINT: 2517 slotid = xhci_get_slot(xhci, &event, &trb); 2518 if (slotid) { 2519 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2520 & TRB_CR_EPID_MASK; 2521 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2522 } 2523 break; 2524 case CR_SET_TR_DEQUEUE: 2525 slotid = xhci_get_slot(xhci, &event, &trb); 2526 if (slotid) { 2527 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2528 & TRB_CR_EPID_MASK; 2529 unsigned int streamid = (trb.status >> 16) & 0xffff; 2530 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2531 epid, streamid, 2532 trb.parameter); 2533 } 2534 break; 2535 case CR_RESET_DEVICE: 2536 slotid = xhci_get_slot(xhci, &event, &trb); 2537 if (slotid) { 2538 event.ccode = xhci_reset_slot(xhci, slotid); 2539 } 2540 break; 2541 case CR_GET_PORT_BANDWIDTH: 2542 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2543 break; 2544 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2545 xhci_via_challenge(xhci, trb.parameter); 2546 break; 2547 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2548 event.type = 48; /* NEC reply */ 2549 event.length = 0x3025; 2550 break; 2551 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2552 { 2553 uint32_t chi = trb.parameter >> 32; 2554 uint32_t clo = trb.parameter; 2555 uint32_t val = xhci_nec_challenge(chi, clo); 2556 event.length = val & 0xFFFF; 2557 event.epid = val >> 16; 2558 slotid = val >> 24; 2559 event.type = 48; /* NEC reply */ 2560 } 2561 break; 2562 default: 2563 trace_usb_xhci_unimplemented("command", type); 2564 event.ccode = CC_TRB_ERROR; 2565 break; 2566 } 2567 event.slotid = slotid; 2568 xhci_event(xhci, &event, 0); 2569 } 2570 } 2571 2572 static bool xhci_port_have_device(XHCIPort *port) 2573 { 2574 if (!port->uport->dev || !port->uport->dev->attached) { 2575 return false; /* no device present */ 2576 } 2577 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2578 return false; /* speed mismatch */ 2579 } 2580 return true; 2581 } 2582 2583 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2584 { 2585 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2586 port->portnr << 24 }; 2587 2588 if ((port->portsc & bits) == bits) { 2589 return; 2590 } 2591 trace_usb_xhci_port_notify(port->portnr, bits); 2592 port->portsc |= bits; 2593 if (!xhci_running(port->xhci)) { 2594 return; 2595 } 2596 xhci_event(port->xhci, &ev, 0); 2597 } 2598 2599 static void xhci_port_update(XHCIPort *port, int is_detach) 2600 { 2601 uint32_t pls = PLS_RX_DETECT; 2602 2603 port->portsc = PORTSC_PP; 2604 if (!is_detach && xhci_port_have_device(port)) { 2605 port->portsc |= PORTSC_CCS; 2606 switch (port->uport->dev->speed) { 2607 case USB_SPEED_LOW: 2608 port->portsc |= PORTSC_SPEED_LOW; 2609 pls = PLS_POLLING; 2610 break; 2611 case USB_SPEED_FULL: 2612 port->portsc |= PORTSC_SPEED_FULL; 2613 pls = PLS_POLLING; 2614 break; 2615 case USB_SPEED_HIGH: 2616 port->portsc |= PORTSC_SPEED_HIGH; 2617 pls = PLS_POLLING; 2618 break; 2619 case USB_SPEED_SUPER: 2620 port->portsc |= PORTSC_SPEED_SUPER; 2621 port->portsc |= PORTSC_PED; 2622 pls = PLS_U0; 2623 break; 2624 } 2625 } 2626 set_field(&port->portsc, pls, PORTSC_PLS); 2627 trace_usb_xhci_port_link(port->portnr, pls); 2628 xhci_port_notify(port, PORTSC_CSC); 2629 } 2630 2631 static void xhci_port_reset(XHCIPort *port) 2632 { 2633 trace_usb_xhci_port_reset(port->portnr); 2634 2635 if (!xhci_port_have_device(port)) { 2636 return; 2637 } 2638 2639 usb_device_reset(port->uport->dev); 2640 2641 switch (port->uport->dev->speed) { 2642 case USB_SPEED_LOW: 2643 case USB_SPEED_FULL: 2644 case USB_SPEED_HIGH: 2645 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2646 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2647 port->portsc |= PORTSC_PED; 2648 break; 2649 } 2650 2651 port->portsc &= ~PORTSC_PR; 2652 xhci_port_notify(port, PORTSC_PRC); 2653 } 2654 2655 static void xhci_reset(DeviceState *dev) 2656 { 2657 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2658 int i; 2659 2660 trace_usb_xhci_reset(); 2661 if (!(xhci->usbsts & USBSTS_HCH)) { 2662 fprintf(stderr, "xhci: reset while running!\n"); 2663 } 2664 2665 xhci->usbcmd = 0; 2666 xhci->usbsts = USBSTS_HCH; 2667 xhci->dnctrl = 0; 2668 xhci->crcr_low = 0; 2669 xhci->crcr_high = 0; 2670 xhci->dcbaap_low = 0; 2671 xhci->dcbaap_high = 0; 2672 xhci->config = 0; 2673 2674 for (i = 0; i < xhci->numslots; i++) { 2675 xhci_disable_slot(xhci, i+1); 2676 } 2677 2678 for (i = 0; i < xhci->numports; i++) { 2679 xhci_port_update(xhci->ports + i, 0); 2680 } 2681 2682 for (i = 0; i < xhci->numintrs; i++) { 2683 xhci->intr[i].iman = 0; 2684 xhci->intr[i].imod = 0; 2685 xhci->intr[i].erstsz = 0; 2686 xhci->intr[i].erstba_low = 0; 2687 xhci->intr[i].erstba_high = 0; 2688 xhci->intr[i].erdp_low = 0; 2689 xhci->intr[i].erdp_high = 0; 2690 xhci->intr[i].msix_used = 0; 2691 2692 xhci->intr[i].er_ep_idx = 0; 2693 xhci->intr[i].er_pcs = 1; 2694 xhci->intr[i].er_full = 0; 2695 xhci->intr[i].ev_buffer_put = 0; 2696 xhci->intr[i].ev_buffer_get = 0; 2697 } 2698 2699 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2700 xhci_mfwrap_update(xhci); 2701 } 2702 2703 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2704 { 2705 XHCIState *xhci = ptr; 2706 uint32_t ret; 2707 2708 switch (reg) { 2709 case 0x00: /* HCIVERSION, CAPLENGTH */ 2710 ret = 0x01000000 | LEN_CAP; 2711 break; 2712 case 0x04: /* HCSPARAMS 1 */ 2713 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2714 | (xhci->numintrs<<8) | xhci->numslots; 2715 break; 2716 case 0x08: /* HCSPARAMS 2 */ 2717 ret = 0x0000000f; 2718 break; 2719 case 0x0c: /* HCSPARAMS 3 */ 2720 ret = 0x00000000; 2721 break; 2722 case 0x10: /* HCCPARAMS */ 2723 if (sizeof(dma_addr_t) == 4) { 2724 ret = 0x00087000; 2725 } else { 2726 ret = 0x00087001; 2727 } 2728 break; 2729 case 0x14: /* DBOFF */ 2730 ret = OFF_DOORBELL; 2731 break; 2732 case 0x18: /* RTSOFF */ 2733 ret = OFF_RUNTIME; 2734 break; 2735 2736 /* extended capabilities */ 2737 case 0x20: /* Supported Protocol:00 */ 2738 ret = 0x02000402; /* USB 2.0 */ 2739 break; 2740 case 0x24: /* Supported Protocol:04 */ 2741 ret = 0x20425355; /* "USB " */ 2742 break; 2743 case 0x28: /* Supported Protocol:08 */ 2744 ret = 0x00000001 | (xhci->numports_2<<8); 2745 break; 2746 case 0x2c: /* Supported Protocol:0c */ 2747 ret = 0x00000000; /* reserved */ 2748 break; 2749 case 0x30: /* Supported Protocol:00 */ 2750 ret = 0x03000002; /* USB 3.0 */ 2751 break; 2752 case 0x34: /* Supported Protocol:04 */ 2753 ret = 0x20425355; /* "USB " */ 2754 break; 2755 case 0x38: /* Supported Protocol:08 */ 2756 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2757 break; 2758 case 0x3c: /* Supported Protocol:0c */ 2759 ret = 0x00000000; /* reserved */ 2760 break; 2761 default: 2762 trace_usb_xhci_unimplemented("cap read", reg); 2763 ret = 0; 2764 } 2765 2766 trace_usb_xhci_cap_read(reg, ret); 2767 return ret; 2768 } 2769 2770 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2771 { 2772 XHCIPort *port = ptr; 2773 uint32_t ret; 2774 2775 switch (reg) { 2776 case 0x00: /* PORTSC */ 2777 ret = port->portsc; 2778 break; 2779 case 0x04: /* PORTPMSC */ 2780 case 0x08: /* PORTLI */ 2781 ret = 0; 2782 break; 2783 case 0x0c: /* reserved */ 2784 default: 2785 trace_usb_xhci_unimplemented("port read", reg); 2786 ret = 0; 2787 } 2788 2789 trace_usb_xhci_port_read(port->portnr, reg, ret); 2790 return ret; 2791 } 2792 2793 static void xhci_port_write(void *ptr, hwaddr reg, 2794 uint64_t val, unsigned size) 2795 { 2796 XHCIPort *port = ptr; 2797 uint32_t portsc, notify; 2798 2799 trace_usb_xhci_port_write(port->portnr, reg, val); 2800 2801 switch (reg) { 2802 case 0x00: /* PORTSC */ 2803 /* write-1-to-start bits */ 2804 if (val & PORTSC_PR) { 2805 xhci_port_reset(port); 2806 break; 2807 } 2808 2809 portsc = port->portsc; 2810 notify = 0; 2811 /* write-1-to-clear bits*/ 2812 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2813 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2814 if (val & PORTSC_LWS) { 2815 /* overwrite PLS only when LWS=1 */ 2816 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2817 uint32_t new_pls = get_field(val, PORTSC_PLS); 2818 switch (new_pls) { 2819 case PLS_U0: 2820 if (old_pls != PLS_U0) { 2821 set_field(&portsc, new_pls, PORTSC_PLS); 2822 trace_usb_xhci_port_link(port->portnr, new_pls); 2823 notify = PORTSC_PLC; 2824 } 2825 break; 2826 case PLS_U3: 2827 if (old_pls < PLS_U3) { 2828 set_field(&portsc, new_pls, PORTSC_PLS); 2829 trace_usb_xhci_port_link(port->portnr, new_pls); 2830 } 2831 break; 2832 case PLS_RESUME: 2833 /* windows does this for some reason, don't spam stderr */ 2834 break; 2835 default: 2836 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2837 __func__, old_pls, new_pls); 2838 break; 2839 } 2840 } 2841 /* read/write bits */ 2842 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2843 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2844 port->portsc = portsc; 2845 if (notify) { 2846 xhci_port_notify(port, notify); 2847 } 2848 break; 2849 case 0x04: /* PORTPMSC */ 2850 case 0x08: /* PORTLI */ 2851 default: 2852 trace_usb_xhci_unimplemented("port write", reg); 2853 } 2854 } 2855 2856 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2857 { 2858 XHCIState *xhci = ptr; 2859 uint32_t ret; 2860 2861 switch (reg) { 2862 case 0x00: /* USBCMD */ 2863 ret = xhci->usbcmd; 2864 break; 2865 case 0x04: /* USBSTS */ 2866 ret = xhci->usbsts; 2867 break; 2868 case 0x08: /* PAGESIZE */ 2869 ret = 1; /* 4KiB */ 2870 break; 2871 case 0x14: /* DNCTRL */ 2872 ret = xhci->dnctrl; 2873 break; 2874 case 0x18: /* CRCR low */ 2875 ret = xhci->crcr_low & ~0xe; 2876 break; 2877 case 0x1c: /* CRCR high */ 2878 ret = xhci->crcr_high; 2879 break; 2880 case 0x30: /* DCBAAP low */ 2881 ret = xhci->dcbaap_low; 2882 break; 2883 case 0x34: /* DCBAAP high */ 2884 ret = xhci->dcbaap_high; 2885 break; 2886 case 0x38: /* CONFIG */ 2887 ret = xhci->config; 2888 break; 2889 default: 2890 trace_usb_xhci_unimplemented("oper read", reg); 2891 ret = 0; 2892 } 2893 2894 trace_usb_xhci_oper_read(reg, ret); 2895 return ret; 2896 } 2897 2898 static void xhci_oper_write(void *ptr, hwaddr reg, 2899 uint64_t val, unsigned size) 2900 { 2901 XHCIState *xhci = ptr; 2902 2903 trace_usb_xhci_oper_write(reg, val); 2904 2905 switch (reg) { 2906 case 0x00: /* USBCMD */ 2907 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2908 xhci_run(xhci); 2909 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2910 xhci_stop(xhci); 2911 } 2912 xhci->usbcmd = val & 0xc0f; 2913 xhci_mfwrap_update(xhci); 2914 if (val & USBCMD_HCRST) { 2915 xhci_reset(&xhci->pci_dev.qdev); 2916 } 2917 xhci_intx_update(xhci); 2918 break; 2919 2920 case 0x04: /* USBSTS */ 2921 /* these bits are write-1-to-clear */ 2922 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2923 xhci_intx_update(xhci); 2924 break; 2925 2926 case 0x14: /* DNCTRL */ 2927 xhci->dnctrl = val & 0xffff; 2928 break; 2929 case 0x18: /* CRCR low */ 2930 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2931 break; 2932 case 0x1c: /* CRCR high */ 2933 xhci->crcr_high = val; 2934 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2935 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2936 xhci->crcr_low &= ~CRCR_CRR; 2937 xhci_event(xhci, &event, 0); 2938 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2939 } else { 2940 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2941 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2942 } 2943 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2944 break; 2945 case 0x30: /* DCBAAP low */ 2946 xhci->dcbaap_low = val & 0xffffffc0; 2947 break; 2948 case 0x34: /* DCBAAP high */ 2949 xhci->dcbaap_high = val; 2950 break; 2951 case 0x38: /* CONFIG */ 2952 xhci->config = val & 0xff; 2953 break; 2954 default: 2955 trace_usb_xhci_unimplemented("oper write", reg); 2956 } 2957 } 2958 2959 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2960 unsigned size) 2961 { 2962 XHCIState *xhci = ptr; 2963 uint32_t ret = 0; 2964 2965 if (reg < 0x20) { 2966 switch (reg) { 2967 case 0x00: /* MFINDEX */ 2968 ret = xhci_mfindex_get(xhci) & 0x3fff; 2969 break; 2970 default: 2971 trace_usb_xhci_unimplemented("runtime read", reg); 2972 break; 2973 } 2974 } else { 2975 int v = (reg - 0x20) / 0x20; 2976 XHCIInterrupter *intr = &xhci->intr[v]; 2977 switch (reg & 0x1f) { 2978 case 0x00: /* IMAN */ 2979 ret = intr->iman; 2980 break; 2981 case 0x04: /* IMOD */ 2982 ret = intr->imod; 2983 break; 2984 case 0x08: /* ERSTSZ */ 2985 ret = intr->erstsz; 2986 break; 2987 case 0x10: /* ERSTBA low */ 2988 ret = intr->erstba_low; 2989 break; 2990 case 0x14: /* ERSTBA high */ 2991 ret = intr->erstba_high; 2992 break; 2993 case 0x18: /* ERDP low */ 2994 ret = intr->erdp_low; 2995 break; 2996 case 0x1c: /* ERDP high */ 2997 ret = intr->erdp_high; 2998 break; 2999 } 3000 } 3001 3002 trace_usb_xhci_runtime_read(reg, ret); 3003 return ret; 3004 } 3005 3006 static void xhci_runtime_write(void *ptr, hwaddr reg, 3007 uint64_t val, unsigned size) 3008 { 3009 XHCIState *xhci = ptr; 3010 int v = (reg - 0x20) / 0x20; 3011 XHCIInterrupter *intr = &xhci->intr[v]; 3012 trace_usb_xhci_runtime_write(reg, val); 3013 3014 if (reg < 0x20) { 3015 trace_usb_xhci_unimplemented("runtime write", reg); 3016 return; 3017 } 3018 3019 switch (reg & 0x1f) { 3020 case 0x00: /* IMAN */ 3021 if (val & IMAN_IP) { 3022 intr->iman &= ~IMAN_IP; 3023 } 3024 intr->iman &= ~IMAN_IE; 3025 intr->iman |= val & IMAN_IE; 3026 if (v == 0) { 3027 xhci_intx_update(xhci); 3028 } 3029 xhci_msix_update(xhci, v); 3030 break; 3031 case 0x04: /* IMOD */ 3032 intr->imod = val; 3033 break; 3034 case 0x08: /* ERSTSZ */ 3035 intr->erstsz = val & 0xffff; 3036 break; 3037 case 0x10: /* ERSTBA low */ 3038 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3039 intr->erstba_low = val & 0xffffffc0; */ 3040 intr->erstba_low = val & 0xfffffff0; 3041 break; 3042 case 0x14: /* ERSTBA high */ 3043 intr->erstba_high = val; 3044 xhci_er_reset(xhci, v); 3045 break; 3046 case 0x18: /* ERDP low */ 3047 if (val & ERDP_EHB) { 3048 intr->erdp_low &= ~ERDP_EHB; 3049 } 3050 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3051 break; 3052 case 0x1c: /* ERDP high */ 3053 intr->erdp_high = val; 3054 xhci_events_update(xhci, v); 3055 break; 3056 default: 3057 trace_usb_xhci_unimplemented("oper write", reg); 3058 } 3059 } 3060 3061 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3062 unsigned size) 3063 { 3064 /* doorbells always read as 0 */ 3065 trace_usb_xhci_doorbell_read(reg, 0); 3066 return 0; 3067 } 3068 3069 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3070 uint64_t val, unsigned size) 3071 { 3072 XHCIState *xhci = ptr; 3073 unsigned int epid, streamid; 3074 3075 trace_usb_xhci_doorbell_write(reg, val); 3076 3077 if (!xhci_running(xhci)) { 3078 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3079 return; 3080 } 3081 3082 reg >>= 2; 3083 3084 if (reg == 0) { 3085 if (val == 0) { 3086 xhci_process_commands(xhci); 3087 } else { 3088 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3089 (uint32_t)val); 3090 } 3091 } else { 3092 epid = val & 0xff; 3093 streamid = (val >> 16) & 0xffff; 3094 if (reg > xhci->numslots) { 3095 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3096 } else if (epid > 31) { 3097 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3098 (int)reg, (uint32_t)val); 3099 } else { 3100 xhci_kick_ep(xhci, reg, epid, streamid); 3101 } 3102 } 3103 } 3104 3105 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3106 unsigned width) 3107 { 3108 /* nothing */ 3109 } 3110 3111 static const MemoryRegionOps xhci_cap_ops = { 3112 .read = xhci_cap_read, 3113 .write = xhci_cap_write, 3114 .valid.min_access_size = 1, 3115 .valid.max_access_size = 4, 3116 .impl.min_access_size = 4, 3117 .impl.max_access_size = 4, 3118 .endianness = DEVICE_LITTLE_ENDIAN, 3119 }; 3120 3121 static const MemoryRegionOps xhci_oper_ops = { 3122 .read = xhci_oper_read, 3123 .write = xhci_oper_write, 3124 .valid.min_access_size = 4, 3125 .valid.max_access_size = 4, 3126 .endianness = DEVICE_LITTLE_ENDIAN, 3127 }; 3128 3129 static const MemoryRegionOps xhci_port_ops = { 3130 .read = xhci_port_read, 3131 .write = xhci_port_write, 3132 .valid.min_access_size = 4, 3133 .valid.max_access_size = 4, 3134 .endianness = DEVICE_LITTLE_ENDIAN, 3135 }; 3136 3137 static const MemoryRegionOps xhci_runtime_ops = { 3138 .read = xhci_runtime_read, 3139 .write = xhci_runtime_write, 3140 .valid.min_access_size = 4, 3141 .valid.max_access_size = 4, 3142 .endianness = DEVICE_LITTLE_ENDIAN, 3143 }; 3144 3145 static const MemoryRegionOps xhci_doorbell_ops = { 3146 .read = xhci_doorbell_read, 3147 .write = xhci_doorbell_write, 3148 .valid.min_access_size = 4, 3149 .valid.max_access_size = 4, 3150 .endianness = DEVICE_LITTLE_ENDIAN, 3151 }; 3152 3153 static void xhci_attach(USBPort *usbport) 3154 { 3155 XHCIState *xhci = usbport->opaque; 3156 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3157 3158 xhci_port_update(port, 0); 3159 } 3160 3161 static void xhci_detach(USBPort *usbport) 3162 { 3163 XHCIState *xhci = usbport->opaque; 3164 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3165 3166 xhci_detach_slot(xhci, usbport); 3167 xhci_port_update(port, 1); 3168 } 3169 3170 static void xhci_wakeup(USBPort *usbport) 3171 { 3172 XHCIState *xhci = usbport->opaque; 3173 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3174 3175 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3176 return; 3177 } 3178 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3179 xhci_port_notify(port, PORTSC_PLC); 3180 } 3181 3182 static void xhci_complete(USBPort *port, USBPacket *packet) 3183 { 3184 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3185 3186 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3187 xhci_ep_nuke_one_xfer(xfer); 3188 return; 3189 } 3190 xhci_complete_packet(xfer); 3191 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3192 } 3193 3194 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3195 { 3196 USBBus *bus = usb_bus_from_device(child); 3197 XHCIState *xhci = container_of(bus, XHCIState, bus); 3198 3199 xhci_detach_slot(xhci, uport); 3200 } 3201 3202 static USBPortOps xhci_uport_ops = { 3203 .attach = xhci_attach, 3204 .detach = xhci_detach, 3205 .wakeup = xhci_wakeup, 3206 .complete = xhci_complete, 3207 .child_detach = xhci_child_detach, 3208 }; 3209 3210 static int xhci_find_epid(USBEndpoint *ep) 3211 { 3212 if (ep->nr == 0) { 3213 return 1; 3214 } 3215 if (ep->pid == USB_TOKEN_IN) { 3216 return ep->nr * 2 + 1; 3217 } else { 3218 return ep->nr * 2; 3219 } 3220 } 3221 3222 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3223 unsigned int stream) 3224 { 3225 XHCIState *xhci = container_of(bus, XHCIState, bus); 3226 int slotid; 3227 3228 DPRINTF("%s\n", __func__); 3229 slotid = ep->dev->addr; 3230 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3231 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3232 return; 3233 } 3234 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3235 } 3236 3237 static USBBusOps xhci_bus_ops = { 3238 .wakeup_endpoint = xhci_wakeup_endpoint, 3239 }; 3240 3241 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 3242 { 3243 XHCIPort *port; 3244 int i, usbports, speedmask; 3245 3246 xhci->usbsts = USBSTS_HCH; 3247 3248 if (xhci->numports_2 > MAXPORTS_2) { 3249 xhci->numports_2 = MAXPORTS_2; 3250 } 3251 if (xhci->numports_3 > MAXPORTS_3) { 3252 xhci->numports_3 = MAXPORTS_3; 3253 } 3254 usbports = MAX(xhci->numports_2, xhci->numports_3); 3255 xhci->numports = xhci->numports_2 + xhci->numports_3; 3256 3257 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 3258 3259 for (i = 0; i < usbports; i++) { 3260 speedmask = 0; 3261 if (i < xhci->numports_2) { 3262 port = &xhci->ports[i]; 3263 port->portnr = i + 1; 3264 port->uport = &xhci->uports[i]; 3265 port->speedmask = 3266 USB_SPEED_MASK_LOW | 3267 USB_SPEED_MASK_FULL | 3268 USB_SPEED_MASK_HIGH; 3269 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3270 speedmask |= port->speedmask; 3271 } 3272 if (i < xhci->numports_3) { 3273 port = &xhci->ports[i + xhci->numports_2]; 3274 port->portnr = i + 1 + xhci->numports_2; 3275 port->uport = &xhci->uports[i]; 3276 port->speedmask = USB_SPEED_MASK_SUPER; 3277 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3278 speedmask |= port->speedmask; 3279 } 3280 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3281 &xhci_uport_ops, speedmask); 3282 } 3283 } 3284 3285 static int usb_xhci_initfn(struct PCIDevice *dev) 3286 { 3287 int i, ret; 3288 3289 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 3290 3291 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3292 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3293 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 3294 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 3295 3296 usb_xhci_init(xhci, &dev->qdev); 3297 3298 if (xhci->numintrs > MAXINTRS) { 3299 xhci->numintrs = MAXINTRS; 3300 } 3301 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3302 xhci->numintrs++; 3303 } 3304 if (xhci->numintrs < 1) { 3305 xhci->numintrs = 1; 3306 } 3307 if (xhci->numslots > MAXSLOTS) { 3308 xhci->numslots = MAXSLOTS; 3309 } 3310 if (xhci->numslots < 1) { 3311 xhci->numslots = 1; 3312 } 3313 3314 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 3315 3316 xhci->irq = xhci->pci_dev.irq[0]; 3317 3318 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 3319 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 3320 "capabilities", LEN_CAP); 3321 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 3322 "operational", 0x400); 3323 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 3324 "runtime", LEN_RUNTIME); 3325 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 3326 "doorbell", LEN_DOORBELL); 3327 3328 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3329 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3330 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3331 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3332 3333 for (i = 0; i < xhci->numports; i++) { 3334 XHCIPort *port = &xhci->ports[i]; 3335 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3336 port->xhci = xhci; 3337 memory_region_init_io(&port->mem, &xhci_port_ops, port, 3338 port->name, 0x10); 3339 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3340 } 3341 3342 pci_register_bar(&xhci->pci_dev, 0, 3343 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3344 &xhci->mem); 3345 3346 ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0); 3347 assert(ret >= 0); 3348 3349 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3350 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); 3351 } 3352 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3353 msix_init(&xhci->pci_dev, xhci->numintrs, 3354 &xhci->mem, 0, OFF_MSIX_TABLE, 3355 &xhci->mem, 0, OFF_MSIX_PBA, 3356 0x90); 3357 } 3358 3359 return 0; 3360 } 3361 3362 static const VMStateDescription vmstate_xhci = { 3363 .name = "xhci", 3364 .unmigratable = 1, 3365 }; 3366 3367 static Property xhci_properties[] = { 3368 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3369 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3370 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3371 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3372 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3373 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3374 DEFINE_PROP_END_OF_LIST(), 3375 }; 3376 3377 static void xhci_class_init(ObjectClass *klass, void *data) 3378 { 3379 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3380 DeviceClass *dc = DEVICE_CLASS(klass); 3381 3382 dc->vmsd = &vmstate_xhci; 3383 dc->props = xhci_properties; 3384 dc->reset = xhci_reset; 3385 k->init = usb_xhci_initfn; 3386 k->vendor_id = PCI_VENDOR_ID_NEC; 3387 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3388 k->class_id = PCI_CLASS_SERIAL_USB; 3389 k->revision = 0x03; 3390 k->is_express = 1; 3391 k->no_hotplug = 1; 3392 } 3393 3394 static const TypeInfo xhci_info = { 3395 .name = "nec-usb-xhci", 3396 .parent = TYPE_PCI_DEVICE, 3397 .instance_size = sizeof(XHCIState), 3398 .class_init = xhci_class_init, 3399 }; 3400 3401 static void xhci_register_types(void) 3402 { 3403 type_register_static(&xhci_info); 3404 } 3405 3406 type_init(xhci_register_types) 3407