1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 unsigned int streamid; 355 bool in_xfer; 356 bool iso_xfer; 357 bool timed_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 unsigned int next_xfer; 385 unsigned int comp_xfer; 386 XHCITransfer transfers[TD_QUEUE]; 387 XHCITransfer *retry; 388 EPType type; 389 dma_addr_t pctx; 390 unsigned int max_psize; 391 uint32_t state; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs, er_full; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 XHCIEvent ev_buffer[EV_QUEUE]; 439 unsigned int ev_buffer_put; 440 unsigned int ev_buffer_get; 441 442 } XHCIInterrupter; 443 444 struct XHCIState { 445 /*< private >*/ 446 PCIDevice parent_obj; 447 /*< public >*/ 448 449 USBBus bus; 450 qemu_irq irq; 451 MemoryRegion mem; 452 MemoryRegion mem_cap; 453 MemoryRegion mem_oper; 454 MemoryRegion mem_runtime; 455 MemoryRegion mem_doorbell; 456 457 /* properties */ 458 uint32_t numports_2; 459 uint32_t numports_3; 460 uint32_t numintrs; 461 uint32_t numslots; 462 uint32_t flags; 463 464 /* Operational Registers */ 465 uint32_t usbcmd; 466 uint32_t usbsts; 467 uint32_t dnctrl; 468 uint32_t crcr_low; 469 uint32_t crcr_high; 470 uint32_t dcbaap_low; 471 uint32_t dcbaap_high; 472 uint32_t config; 473 474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 475 XHCIPort ports[MAXPORTS]; 476 XHCISlot slots[MAXSLOTS]; 477 uint32_t numports; 478 479 /* Runtime Registers */ 480 int64_t mfindex_start; 481 QEMUTimer *mfwrap_timer; 482 XHCIInterrupter intr[MAXINTRS]; 483 484 XHCIRing cmd_ring; 485 }; 486 487 #define TYPE_XHCI "nec-usb-xhci" 488 489 #define XHCI(obj) \ 490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 491 492 typedef struct XHCIEvRingSeg { 493 uint32_t addr_low; 494 uint32_t addr_high; 495 uint32_t size; 496 uint32_t rsvd; 497 } XHCIEvRingSeg; 498 499 enum xhci_flags { 500 XHCI_FLAG_USE_MSI = 1, 501 XHCI_FLAG_USE_MSI_X, 502 }; 503 504 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 505 unsigned int epid, unsigned int streamid); 506 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 507 unsigned int epid); 508 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 509 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 510 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 511 unsigned int slotid, unsigned int epid); 512 513 static const char *TRBType_names[] = { 514 [TRB_RESERVED] = "TRB_RESERVED", 515 [TR_NORMAL] = "TR_NORMAL", 516 [TR_SETUP] = "TR_SETUP", 517 [TR_DATA] = "TR_DATA", 518 [TR_STATUS] = "TR_STATUS", 519 [TR_ISOCH] = "TR_ISOCH", 520 [TR_LINK] = "TR_LINK", 521 [TR_EVDATA] = "TR_EVDATA", 522 [TR_NOOP] = "TR_NOOP", 523 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 524 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 525 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 526 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 527 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 528 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 529 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 530 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 531 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 532 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 533 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 534 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 535 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 536 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 537 [CR_NOOP] = "CR_NOOP", 538 [ER_TRANSFER] = "ER_TRANSFER", 539 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 540 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 541 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 542 [ER_DOORBELL] = "ER_DOORBELL", 543 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 544 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 545 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 546 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 547 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 548 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 549 }; 550 551 static const char *TRBCCode_names[] = { 552 [CC_INVALID] = "CC_INVALID", 553 [CC_SUCCESS] = "CC_SUCCESS", 554 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 555 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 556 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 557 [CC_TRB_ERROR] = "CC_TRB_ERROR", 558 [CC_STALL_ERROR] = "CC_STALL_ERROR", 559 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 560 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 561 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 562 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 563 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 564 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 565 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 566 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 567 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 568 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 569 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 570 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 571 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 572 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 573 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 574 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 575 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 576 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 577 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 578 [CC_STOPPED] = "CC_STOPPED", 579 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 580 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 581 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 582 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 583 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 584 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 585 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 586 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 587 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 588 }; 589 590 static const char *ep_state_names[] = { 591 [EP_DISABLED] = "disabled", 592 [EP_RUNNING] = "running", 593 [EP_HALTED] = "halted", 594 [EP_STOPPED] = "stopped", 595 [EP_ERROR] = "error", 596 }; 597 598 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 599 { 600 if (index >= llen || list[index] == NULL) { 601 return "???"; 602 } 603 return list[index]; 604 } 605 606 static const char *trb_name(XHCITRB *trb) 607 { 608 return lookup_name(TRB_TYPE(*trb), TRBType_names, 609 ARRAY_SIZE(TRBType_names)); 610 } 611 612 static const char *event_name(XHCIEvent *event) 613 { 614 return lookup_name(event->ccode, TRBCCode_names, 615 ARRAY_SIZE(TRBCCode_names)); 616 } 617 618 static const char *ep_state_name(uint32_t state) 619 { 620 return lookup_name(state, ep_state_names, 621 ARRAY_SIZE(ep_state_names)); 622 } 623 624 static uint64_t xhci_mfindex_get(XHCIState *xhci) 625 { 626 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 627 return (now - xhci->mfindex_start) / 125000; 628 } 629 630 static void xhci_mfwrap_update(XHCIState *xhci) 631 { 632 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 633 uint32_t mfindex, left; 634 int64_t now; 635 636 if ((xhci->usbcmd & bits) == bits) { 637 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 638 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 639 left = 0x4000 - mfindex; 640 timer_mod(xhci->mfwrap_timer, now + left * 125000); 641 } else { 642 timer_del(xhci->mfwrap_timer); 643 } 644 } 645 646 static void xhci_mfwrap_timer(void *opaque) 647 { 648 XHCIState *xhci = opaque; 649 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 650 651 xhci_event(xhci, &wrap, 0); 652 xhci_mfwrap_update(xhci); 653 } 654 655 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 656 { 657 if (sizeof(dma_addr_t) == 4) { 658 return low; 659 } else { 660 return low | (((dma_addr_t)high << 16) << 16); 661 } 662 } 663 664 static inline dma_addr_t xhci_mask64(uint64_t addr) 665 { 666 if (sizeof(dma_addr_t) == 4) { 667 return addr & 0xffffffff; 668 } else { 669 return addr; 670 } 671 } 672 673 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 674 uint32_t *buf, size_t len) 675 { 676 int i; 677 678 assert((len % sizeof(uint32_t)) == 0); 679 680 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 681 682 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 683 buf[i] = le32_to_cpu(buf[i]); 684 } 685 } 686 687 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 688 uint32_t *buf, size_t len) 689 { 690 int i; 691 uint32_t tmp[len / sizeof(uint32_t)]; 692 693 assert((len % sizeof(uint32_t)) == 0); 694 695 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 696 tmp[i] = cpu_to_le32(buf[i]); 697 } 698 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 699 } 700 701 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 702 { 703 int index; 704 705 if (!uport->dev) { 706 return NULL; 707 } 708 switch (uport->dev->speed) { 709 case USB_SPEED_LOW: 710 case USB_SPEED_FULL: 711 case USB_SPEED_HIGH: 712 index = uport->index; 713 break; 714 case USB_SPEED_SUPER: 715 index = uport->index + xhci->numports_2; 716 break; 717 default: 718 return NULL; 719 } 720 return &xhci->ports[index]; 721 } 722 723 static void xhci_intx_update(XHCIState *xhci) 724 { 725 PCIDevice *pci_dev = PCI_DEVICE(xhci); 726 int level = 0; 727 728 if (msix_enabled(pci_dev) || 729 msi_enabled(pci_dev)) { 730 return; 731 } 732 733 if (xhci->intr[0].iman & IMAN_IP && 734 xhci->intr[0].iman & IMAN_IE && 735 xhci->usbcmd & USBCMD_INTE) { 736 level = 1; 737 } 738 739 trace_usb_xhci_irq_intx(level); 740 qemu_set_irq(xhci->irq, level); 741 } 742 743 static void xhci_msix_update(XHCIState *xhci, int v) 744 { 745 PCIDevice *pci_dev = PCI_DEVICE(xhci); 746 bool enabled; 747 748 if (!msix_enabled(pci_dev)) { 749 return; 750 } 751 752 enabled = xhci->intr[v].iman & IMAN_IE; 753 if (enabled == xhci->intr[v].msix_used) { 754 return; 755 } 756 757 if (enabled) { 758 trace_usb_xhci_irq_msix_use(v); 759 msix_vector_use(pci_dev, v); 760 xhci->intr[v].msix_used = true; 761 } else { 762 trace_usb_xhci_irq_msix_unuse(v); 763 msix_vector_unuse(pci_dev, v); 764 xhci->intr[v].msix_used = false; 765 } 766 } 767 768 static void xhci_intr_raise(XHCIState *xhci, int v) 769 { 770 PCIDevice *pci_dev = PCI_DEVICE(xhci); 771 772 xhci->intr[v].erdp_low |= ERDP_EHB; 773 xhci->intr[v].iman |= IMAN_IP; 774 xhci->usbsts |= USBSTS_EINT; 775 776 if (!(xhci->intr[v].iman & IMAN_IE)) { 777 return; 778 } 779 780 if (!(xhci->usbcmd & USBCMD_INTE)) { 781 return; 782 } 783 784 if (msix_enabled(pci_dev)) { 785 trace_usb_xhci_irq_msix(v); 786 msix_notify(pci_dev, v); 787 return; 788 } 789 790 if (msi_enabled(pci_dev)) { 791 trace_usb_xhci_irq_msi(v); 792 msi_notify(pci_dev, v); 793 return; 794 } 795 796 if (v == 0) { 797 trace_usb_xhci_irq_intx(1); 798 qemu_set_irq(xhci->irq, 1); 799 } 800 } 801 802 static inline int xhci_running(XHCIState *xhci) 803 { 804 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 805 } 806 807 static void xhci_die(XHCIState *xhci) 808 { 809 xhci->usbsts |= USBSTS_HCE; 810 fprintf(stderr, "xhci: asserted controller error\n"); 811 } 812 813 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 814 { 815 PCIDevice *pci_dev = PCI_DEVICE(xhci); 816 XHCIInterrupter *intr = &xhci->intr[v]; 817 XHCITRB ev_trb; 818 dma_addr_t addr; 819 820 ev_trb.parameter = cpu_to_le64(event->ptr); 821 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 822 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 823 event->flags | (event->type << TRB_TYPE_SHIFT); 824 if (intr->er_pcs) { 825 ev_trb.control |= TRB_C; 826 } 827 ev_trb.control = cpu_to_le32(ev_trb.control); 828 829 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 830 event_name(event), ev_trb.parameter, 831 ev_trb.status, ev_trb.control); 832 833 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 834 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 835 836 intr->er_ep_idx++; 837 if (intr->er_ep_idx >= intr->er_size) { 838 intr->er_ep_idx = 0; 839 intr->er_pcs = !intr->er_pcs; 840 } 841 } 842 843 static void xhci_events_update(XHCIState *xhci, int v) 844 { 845 XHCIInterrupter *intr = &xhci->intr[v]; 846 dma_addr_t erdp; 847 unsigned int dp_idx; 848 bool do_irq = 0; 849 850 if (xhci->usbsts & USBSTS_HCH) { 851 return; 852 } 853 854 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 855 if (erdp < intr->er_start || 856 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 857 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 858 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 859 v, intr->er_start, intr->er_size); 860 xhci_die(xhci); 861 return; 862 } 863 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 864 assert(dp_idx < intr->er_size); 865 866 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 867 * deadlocks when the ER is full. Hack it by holding off events until 868 * the driver decides to free at least half of the ring */ 869 if (intr->er_full) { 870 int er_free = dp_idx - intr->er_ep_idx; 871 if (er_free <= 0) { 872 er_free += intr->er_size; 873 } 874 if (er_free < (intr->er_size/2)) { 875 DPRINTF("xhci_events_update(): event ring still " 876 "more than half full (hack)\n"); 877 return; 878 } 879 } 880 881 while (intr->ev_buffer_put != intr->ev_buffer_get) { 882 assert(intr->er_full); 883 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 884 DPRINTF("xhci_events_update(): event ring full again\n"); 885 #ifndef ER_FULL_HACK 886 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 887 xhci_write_event(xhci, &full, v); 888 #endif 889 do_irq = 1; 890 break; 891 } 892 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 893 xhci_write_event(xhci, event, v); 894 intr->ev_buffer_get++; 895 do_irq = 1; 896 if (intr->ev_buffer_get == EV_QUEUE) { 897 intr->ev_buffer_get = 0; 898 } 899 } 900 901 if (do_irq) { 902 xhci_intr_raise(xhci, v); 903 } 904 905 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 906 DPRINTF("xhci_events_update(): event ring no longer full\n"); 907 intr->er_full = 0; 908 } 909 } 910 911 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 912 { 913 XHCIInterrupter *intr; 914 dma_addr_t erdp; 915 unsigned int dp_idx; 916 917 if (v >= xhci->numintrs) { 918 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 919 return; 920 } 921 intr = &xhci->intr[v]; 922 923 if (intr->er_full) { 924 DPRINTF("xhci_event(): ER full, queueing\n"); 925 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 926 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 927 return; 928 } 929 intr->ev_buffer[intr->ev_buffer_put++] = *event; 930 if (intr->ev_buffer_put == EV_QUEUE) { 931 intr->ev_buffer_put = 0; 932 } 933 return; 934 } 935 936 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 937 if (erdp < intr->er_start || 938 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 939 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 940 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 941 v, intr->er_start, intr->er_size); 942 xhci_die(xhci); 943 return; 944 } 945 946 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 947 assert(dp_idx < intr->er_size); 948 949 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 950 DPRINTF("xhci_event(): ER full, queueing\n"); 951 #ifndef ER_FULL_HACK 952 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 953 xhci_write_event(xhci, &full); 954 #endif 955 intr->er_full = 1; 956 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 957 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 958 return; 959 } 960 intr->ev_buffer[intr->ev_buffer_put++] = *event; 961 if (intr->ev_buffer_put == EV_QUEUE) { 962 intr->ev_buffer_put = 0; 963 } 964 } else { 965 xhci_write_event(xhci, event, v); 966 } 967 968 xhci_intr_raise(xhci, v); 969 } 970 971 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 972 dma_addr_t base) 973 { 974 ring->dequeue = base; 975 ring->ccs = 1; 976 } 977 978 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 979 dma_addr_t *addr) 980 { 981 PCIDevice *pci_dev = PCI_DEVICE(xhci); 982 983 while (1) { 984 TRBType type; 985 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 986 trb->addr = ring->dequeue; 987 trb->ccs = ring->ccs; 988 le64_to_cpus(&trb->parameter); 989 le32_to_cpus(&trb->status); 990 le32_to_cpus(&trb->control); 991 992 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 993 trb->parameter, trb->status, trb->control); 994 995 if ((trb->control & TRB_C) != ring->ccs) { 996 return 0; 997 } 998 999 type = TRB_TYPE(*trb); 1000 1001 if (type != TR_LINK) { 1002 if (addr) { 1003 *addr = ring->dequeue; 1004 } 1005 ring->dequeue += TRB_SIZE; 1006 return type; 1007 } else { 1008 ring->dequeue = xhci_mask64(trb->parameter); 1009 if (trb->control & TRB_LK_TC) { 1010 ring->ccs = !ring->ccs; 1011 } 1012 } 1013 } 1014 } 1015 1016 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1017 { 1018 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1019 XHCITRB trb; 1020 int length = 0; 1021 dma_addr_t dequeue = ring->dequeue; 1022 bool ccs = ring->ccs; 1023 /* hack to bundle together the two/three TDs that make a setup transfer */ 1024 bool control_td_set = 0; 1025 1026 while (1) { 1027 TRBType type; 1028 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1029 le64_to_cpus(&trb.parameter); 1030 le32_to_cpus(&trb.status); 1031 le32_to_cpus(&trb.control); 1032 1033 if ((trb.control & TRB_C) != ccs) { 1034 return -length; 1035 } 1036 1037 type = TRB_TYPE(trb); 1038 1039 if (type == TR_LINK) { 1040 dequeue = xhci_mask64(trb.parameter); 1041 if (trb.control & TRB_LK_TC) { 1042 ccs = !ccs; 1043 } 1044 continue; 1045 } 1046 1047 length += 1; 1048 dequeue += TRB_SIZE; 1049 1050 if (type == TR_SETUP) { 1051 control_td_set = 1; 1052 } else if (type == TR_STATUS) { 1053 control_td_set = 0; 1054 } 1055 1056 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1057 return length; 1058 } 1059 } 1060 } 1061 1062 static void xhci_er_reset(XHCIState *xhci, int v) 1063 { 1064 XHCIInterrupter *intr = &xhci->intr[v]; 1065 XHCIEvRingSeg seg; 1066 1067 if (intr->erstsz == 0) { 1068 /* disabled */ 1069 intr->er_start = 0; 1070 intr->er_size = 0; 1071 return; 1072 } 1073 /* cache the (sole) event ring segment location */ 1074 if (intr->erstsz != 1) { 1075 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1076 xhci_die(xhci); 1077 return; 1078 } 1079 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1080 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1081 le32_to_cpus(&seg.addr_low); 1082 le32_to_cpus(&seg.addr_high); 1083 le32_to_cpus(&seg.size); 1084 if (seg.size < 16 || seg.size > 4096) { 1085 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1086 xhci_die(xhci); 1087 return; 1088 } 1089 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1090 intr->er_size = seg.size; 1091 1092 intr->er_ep_idx = 0; 1093 intr->er_pcs = 1; 1094 intr->er_full = 0; 1095 1096 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1097 v, intr->er_start, intr->er_size); 1098 } 1099 1100 static void xhci_run(XHCIState *xhci) 1101 { 1102 trace_usb_xhci_run(); 1103 xhci->usbsts &= ~USBSTS_HCH; 1104 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1105 } 1106 1107 static void xhci_stop(XHCIState *xhci) 1108 { 1109 trace_usb_xhci_stop(); 1110 xhci->usbsts |= USBSTS_HCH; 1111 xhci->crcr_low &= ~CRCR_CRR; 1112 } 1113 1114 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1115 dma_addr_t base) 1116 { 1117 XHCIStreamContext *stctx; 1118 unsigned int i; 1119 1120 stctx = g_new0(XHCIStreamContext, count); 1121 for (i = 0; i < count; i++) { 1122 stctx[i].pctx = base + i * 16; 1123 stctx[i].sct = -1; 1124 } 1125 return stctx; 1126 } 1127 1128 static void xhci_reset_streams(XHCIEPContext *epctx) 1129 { 1130 unsigned int i; 1131 1132 for (i = 0; i < epctx->nr_pstreams; i++) { 1133 epctx->pstreams[i].sct = -1; 1134 } 1135 } 1136 1137 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1138 { 1139 assert(epctx->pstreams == NULL); 1140 epctx->nr_pstreams = 2 << (epctx->max_pstreams + 1); 1141 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1142 } 1143 1144 static void xhci_free_streams(XHCIEPContext *epctx) 1145 { 1146 assert(epctx->pstreams != NULL); 1147 1148 g_free(epctx->pstreams); 1149 epctx->pstreams = NULL; 1150 epctx->nr_pstreams = 0; 1151 } 1152 1153 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1154 unsigned int streamid, 1155 uint32_t *cc_error) 1156 { 1157 XHCIStreamContext *sctx; 1158 dma_addr_t base; 1159 uint32_t ctx[2], sct; 1160 1161 assert(streamid != 0); 1162 if (epctx->lsa) { 1163 if (streamid >= epctx->nr_pstreams) { 1164 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1165 return NULL; 1166 } 1167 sctx = epctx->pstreams + streamid; 1168 } else { 1169 FIXME("secondary streams not implemented yet"); 1170 } 1171 1172 if (sctx->sct == -1) { 1173 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1174 sct = (ctx[0] >> 1) & 0x07; 1175 if (epctx->lsa && sct != 1) { 1176 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1177 return NULL; 1178 } 1179 sctx->sct = sct; 1180 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1181 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1182 } 1183 return sctx; 1184 } 1185 1186 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1187 XHCIStreamContext *sctx, uint32_t state) 1188 { 1189 uint32_t ctx[5]; 1190 uint32_t ctx2[2]; 1191 1192 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1193 ctx[0] &= ~EP_STATE_MASK; 1194 ctx[0] |= state; 1195 1196 /* update ring dequeue ptr */ 1197 if (epctx->nr_pstreams) { 1198 if (sctx != NULL) { 1199 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1200 ctx2[0] &= 0xe; 1201 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1202 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1203 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1204 } 1205 } else { 1206 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1207 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1208 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1209 epctx->pctx, state, ctx[3], ctx[2]); 1210 } 1211 1212 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1213 if (epctx->state != state) { 1214 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1215 ep_state_name(epctx->state), 1216 ep_state_name(state)); 1217 } 1218 epctx->state = state; 1219 } 1220 1221 static void xhci_ep_kick_timer(void *opaque) 1222 { 1223 XHCIEPContext *epctx = opaque; 1224 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1225 } 1226 1227 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1228 unsigned int slotid, 1229 unsigned int epid) 1230 { 1231 XHCIEPContext *epctx; 1232 int i; 1233 1234 epctx = g_new0(XHCIEPContext, 1); 1235 epctx->xhci = xhci; 1236 epctx->slotid = slotid; 1237 epctx->epid = epid; 1238 1239 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1240 epctx->transfers[i].xhci = xhci; 1241 epctx->transfers[i].slotid = slotid; 1242 epctx->transfers[i].epid = epid; 1243 usb_packet_init(&epctx->transfers[i].packet); 1244 } 1245 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1246 1247 return epctx; 1248 } 1249 1250 static void xhci_init_epctx(XHCIEPContext *epctx, 1251 dma_addr_t pctx, uint32_t *ctx) 1252 { 1253 dma_addr_t dequeue; 1254 1255 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1256 1257 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1258 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1259 epctx->pctx = pctx; 1260 epctx->max_psize = ctx[1]>>16; 1261 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1262 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1263 epctx->lsa = (ctx[0] >> 15) & 1; 1264 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1265 epid/2, epid%2, epctx->max_psize); 1266 if (epctx->max_pstreams) { 1267 xhci_alloc_streams(epctx, dequeue); 1268 } else { 1269 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1270 epctx->ring.ccs = ctx[2] & 1; 1271 } 1272 1273 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1274 } 1275 1276 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1277 unsigned int epid, dma_addr_t pctx, 1278 uint32_t *ctx) 1279 { 1280 XHCISlot *slot; 1281 XHCIEPContext *epctx; 1282 1283 trace_usb_xhci_ep_enable(slotid, epid); 1284 assert(slotid >= 1 && slotid <= xhci->numslots); 1285 assert(epid >= 1 && epid <= 31); 1286 1287 slot = &xhci->slots[slotid-1]; 1288 if (slot->eps[epid-1]) { 1289 xhci_disable_ep(xhci, slotid, epid); 1290 } 1291 1292 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1293 slot->eps[epid-1] = epctx; 1294 xhci_init_epctx(epctx, pctx, ctx); 1295 1296 epctx->mfindex_last = 0; 1297 1298 epctx->state = EP_RUNNING; 1299 ctx[0] &= ~EP_STATE_MASK; 1300 ctx[0] |= EP_RUNNING; 1301 1302 return CC_SUCCESS; 1303 } 1304 1305 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1306 { 1307 int killed = 0; 1308 1309 if (t->running_async) { 1310 usb_cancel_packet(&t->packet); 1311 t->running_async = 0; 1312 killed = 1; 1313 } 1314 if (t->running_retry) { 1315 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1316 if (epctx) { 1317 epctx->retry = NULL; 1318 timer_del(epctx->kick_timer); 1319 } 1320 t->running_retry = 0; 1321 } 1322 if (t->trbs) { 1323 g_free(t->trbs); 1324 } 1325 1326 t->trbs = NULL; 1327 t->trb_count = t->trb_alloced = 0; 1328 1329 return killed; 1330 } 1331 1332 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1333 unsigned int epid) 1334 { 1335 XHCISlot *slot; 1336 XHCIEPContext *epctx; 1337 int i, xferi, killed = 0; 1338 USBEndpoint *ep = NULL; 1339 assert(slotid >= 1 && slotid <= xhci->numslots); 1340 assert(epid >= 1 && epid <= 31); 1341 1342 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1343 1344 slot = &xhci->slots[slotid-1]; 1345 1346 if (!slot->eps[epid-1]) { 1347 return 0; 1348 } 1349 1350 epctx = slot->eps[epid-1]; 1351 1352 xferi = epctx->next_xfer; 1353 for (i = 0; i < TD_QUEUE; i++) { 1354 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1355 epctx->transfers[xferi].packet.ep = NULL; 1356 xferi = (xferi + 1) % TD_QUEUE; 1357 } 1358 1359 ep = xhci_epid_to_usbep(xhci, slotid, epid); 1360 if (ep) { 1361 usb_device_ep_stopped(ep->dev, ep); 1362 } 1363 return killed; 1364 } 1365 1366 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1367 unsigned int epid) 1368 { 1369 XHCISlot *slot; 1370 XHCIEPContext *epctx; 1371 int i; 1372 1373 trace_usb_xhci_ep_disable(slotid, epid); 1374 assert(slotid >= 1 && slotid <= xhci->numslots); 1375 assert(epid >= 1 && epid <= 31); 1376 1377 slot = &xhci->slots[slotid-1]; 1378 1379 if (!slot->eps[epid-1]) { 1380 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1381 return CC_SUCCESS; 1382 } 1383 1384 xhci_ep_nuke_xfers(xhci, slotid, epid); 1385 1386 epctx = slot->eps[epid-1]; 1387 1388 if (epctx->nr_pstreams) { 1389 xhci_free_streams(epctx); 1390 } 1391 1392 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1393 usb_packet_cleanup(&epctx->transfers[i].packet); 1394 } 1395 1396 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1397 1398 timer_free(epctx->kick_timer); 1399 g_free(epctx); 1400 slot->eps[epid-1] = NULL; 1401 1402 return CC_SUCCESS; 1403 } 1404 1405 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1406 unsigned int epid) 1407 { 1408 XHCISlot *slot; 1409 XHCIEPContext *epctx; 1410 1411 trace_usb_xhci_ep_stop(slotid, epid); 1412 assert(slotid >= 1 && slotid <= xhci->numslots); 1413 1414 if (epid < 1 || epid > 31) { 1415 fprintf(stderr, "xhci: bad ep %d\n", epid); 1416 return CC_TRB_ERROR; 1417 } 1418 1419 slot = &xhci->slots[slotid-1]; 1420 1421 if (!slot->eps[epid-1]) { 1422 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1423 return CC_EP_NOT_ENABLED_ERROR; 1424 } 1425 1426 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1427 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1428 "data might be lost\n"); 1429 } 1430 1431 epctx = slot->eps[epid-1]; 1432 1433 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1434 1435 if (epctx->nr_pstreams) { 1436 xhci_reset_streams(epctx); 1437 } 1438 1439 return CC_SUCCESS; 1440 } 1441 1442 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1443 unsigned int epid) 1444 { 1445 XHCISlot *slot; 1446 XHCIEPContext *epctx; 1447 1448 trace_usb_xhci_ep_reset(slotid, epid); 1449 assert(slotid >= 1 && slotid <= xhci->numslots); 1450 1451 if (epid < 1 || epid > 31) { 1452 fprintf(stderr, "xhci: bad ep %d\n", epid); 1453 return CC_TRB_ERROR; 1454 } 1455 1456 slot = &xhci->slots[slotid-1]; 1457 1458 if (!slot->eps[epid-1]) { 1459 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1460 return CC_EP_NOT_ENABLED_ERROR; 1461 } 1462 1463 epctx = slot->eps[epid-1]; 1464 1465 if (epctx->state != EP_HALTED) { 1466 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1467 epid, epctx->state); 1468 return CC_CONTEXT_STATE_ERROR; 1469 } 1470 1471 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1472 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1473 "data might be lost\n"); 1474 } 1475 1476 uint8_t ep = epid>>1; 1477 1478 if (epid & 1) { 1479 ep |= 0x80; 1480 } 1481 1482 if (!xhci->slots[slotid-1].uport || 1483 !xhci->slots[slotid-1].uport->dev) { 1484 return CC_USB_TRANSACTION_ERROR; 1485 } 1486 1487 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1488 1489 if (epctx->nr_pstreams) { 1490 xhci_reset_streams(epctx); 1491 } 1492 1493 return CC_SUCCESS; 1494 } 1495 1496 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1497 unsigned int epid, unsigned int streamid, 1498 uint64_t pdequeue) 1499 { 1500 XHCISlot *slot; 1501 XHCIEPContext *epctx; 1502 XHCIStreamContext *sctx; 1503 dma_addr_t dequeue; 1504 1505 assert(slotid >= 1 && slotid <= xhci->numslots); 1506 1507 if (epid < 1 || epid > 31) { 1508 fprintf(stderr, "xhci: bad ep %d\n", epid); 1509 return CC_TRB_ERROR; 1510 } 1511 1512 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1513 dequeue = xhci_mask64(pdequeue); 1514 1515 slot = &xhci->slots[slotid-1]; 1516 1517 if (!slot->eps[epid-1]) { 1518 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1519 return CC_EP_NOT_ENABLED_ERROR; 1520 } 1521 1522 epctx = slot->eps[epid-1]; 1523 1524 if (epctx->state != EP_STOPPED) { 1525 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1526 return CC_CONTEXT_STATE_ERROR; 1527 } 1528 1529 if (epctx->nr_pstreams) { 1530 uint32_t err; 1531 sctx = xhci_find_stream(epctx, streamid, &err); 1532 if (sctx == NULL) { 1533 return err; 1534 } 1535 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1536 sctx->ring.ccs = dequeue & 1; 1537 } else { 1538 sctx = NULL; 1539 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1540 epctx->ring.ccs = dequeue & 1; 1541 } 1542 1543 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1544 1545 return CC_SUCCESS; 1546 } 1547 1548 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1549 { 1550 XHCIState *xhci = xfer->xhci; 1551 int i; 1552 1553 xfer->int_req = false; 1554 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1555 for (i = 0; i < xfer->trb_count; i++) { 1556 XHCITRB *trb = &xfer->trbs[i]; 1557 dma_addr_t addr; 1558 unsigned int chunk = 0; 1559 1560 if (trb->control & TRB_TR_IOC) { 1561 xfer->int_req = true; 1562 } 1563 1564 switch (TRB_TYPE(*trb)) { 1565 case TR_DATA: 1566 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1567 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1568 goto err; 1569 } 1570 /* fallthrough */ 1571 case TR_NORMAL: 1572 case TR_ISOCH: 1573 addr = xhci_mask64(trb->parameter); 1574 chunk = trb->status & 0x1ffff; 1575 if (trb->control & TRB_TR_IDT) { 1576 if (chunk > 8 || in_xfer) { 1577 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1578 goto err; 1579 } 1580 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1581 } else { 1582 qemu_sglist_add(&xfer->sgl, addr, chunk); 1583 } 1584 break; 1585 } 1586 } 1587 1588 return 0; 1589 1590 err: 1591 qemu_sglist_destroy(&xfer->sgl); 1592 xhci_die(xhci); 1593 return -1; 1594 } 1595 1596 static void xhci_xfer_unmap(XHCITransfer *xfer) 1597 { 1598 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1599 qemu_sglist_destroy(&xfer->sgl); 1600 } 1601 1602 static void xhci_xfer_report(XHCITransfer *xfer) 1603 { 1604 uint32_t edtla = 0; 1605 unsigned int left; 1606 bool reported = 0; 1607 bool shortpkt = 0; 1608 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1609 XHCIState *xhci = xfer->xhci; 1610 int i; 1611 1612 left = xfer->packet.actual_length; 1613 1614 for (i = 0; i < xfer->trb_count; i++) { 1615 XHCITRB *trb = &xfer->trbs[i]; 1616 unsigned int chunk = 0; 1617 1618 switch (TRB_TYPE(*trb)) { 1619 case TR_DATA: 1620 case TR_NORMAL: 1621 case TR_ISOCH: 1622 chunk = trb->status & 0x1ffff; 1623 if (chunk > left) { 1624 chunk = left; 1625 if (xfer->status == CC_SUCCESS) { 1626 shortpkt = 1; 1627 } 1628 } 1629 left -= chunk; 1630 edtla += chunk; 1631 break; 1632 case TR_STATUS: 1633 reported = 0; 1634 shortpkt = 0; 1635 break; 1636 } 1637 1638 if (!reported && ((trb->control & TRB_TR_IOC) || 1639 (shortpkt && (trb->control & TRB_TR_ISP)) || 1640 (xfer->status != CC_SUCCESS && left == 0))) { 1641 event.slotid = xfer->slotid; 1642 event.epid = xfer->epid; 1643 event.length = (trb->status & 0x1ffff) - chunk; 1644 event.flags = 0; 1645 event.ptr = trb->addr; 1646 if (xfer->status == CC_SUCCESS) { 1647 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1648 } else { 1649 event.ccode = xfer->status; 1650 } 1651 if (TRB_TYPE(*trb) == TR_EVDATA) { 1652 event.ptr = trb->parameter; 1653 event.flags |= TRB_EV_ED; 1654 event.length = edtla & 0xffffff; 1655 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1656 edtla = 0; 1657 } 1658 xhci_event(xhci, &event, TRB_INTR(*trb)); 1659 reported = 1; 1660 if (xfer->status != CC_SUCCESS) { 1661 return; 1662 } 1663 } 1664 } 1665 } 1666 1667 static void xhci_stall_ep(XHCITransfer *xfer) 1668 { 1669 XHCIState *xhci = xfer->xhci; 1670 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1671 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1672 uint32_t err; 1673 XHCIStreamContext *sctx; 1674 1675 if (epctx->nr_pstreams) { 1676 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1677 if (sctx == NULL) { 1678 return; 1679 } 1680 sctx->ring.dequeue = xfer->trbs[0].addr; 1681 sctx->ring.ccs = xfer->trbs[0].ccs; 1682 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1683 } else { 1684 epctx->ring.dequeue = xfer->trbs[0].addr; 1685 epctx->ring.ccs = xfer->trbs[0].ccs; 1686 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1687 } 1688 } 1689 1690 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1691 XHCIEPContext *epctx); 1692 1693 static int xhci_setup_packet(XHCITransfer *xfer) 1694 { 1695 XHCIState *xhci = xfer->xhci; 1696 USBEndpoint *ep; 1697 int dir; 1698 1699 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1700 1701 if (xfer->packet.ep) { 1702 ep = xfer->packet.ep; 1703 } else { 1704 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); 1705 if (!ep) { 1706 fprintf(stderr, "xhci: slot %d has no device\n", 1707 xfer->slotid); 1708 return -1; 1709 } 1710 } 1711 1712 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1713 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1714 xfer->trbs[0].addr, false, xfer->int_req); 1715 usb_packet_map(&xfer->packet, &xfer->sgl); 1716 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1717 xfer->packet.pid, ep->dev->addr, ep->nr); 1718 return 0; 1719 } 1720 1721 static int xhci_complete_packet(XHCITransfer *xfer) 1722 { 1723 if (xfer->packet.status == USB_RET_ASYNC) { 1724 trace_usb_xhci_xfer_async(xfer); 1725 xfer->running_async = 1; 1726 xfer->running_retry = 0; 1727 xfer->complete = 0; 1728 return 0; 1729 } else if (xfer->packet.status == USB_RET_NAK) { 1730 trace_usb_xhci_xfer_nak(xfer); 1731 xfer->running_async = 0; 1732 xfer->running_retry = 1; 1733 xfer->complete = 0; 1734 return 0; 1735 } else { 1736 xfer->running_async = 0; 1737 xfer->running_retry = 0; 1738 xfer->complete = 1; 1739 xhci_xfer_unmap(xfer); 1740 } 1741 1742 if (xfer->packet.status == USB_RET_SUCCESS) { 1743 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1744 xfer->status = CC_SUCCESS; 1745 xhci_xfer_report(xfer); 1746 return 0; 1747 } 1748 1749 /* error */ 1750 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1751 switch (xfer->packet.status) { 1752 case USB_RET_NODEV: 1753 case USB_RET_IOERROR: 1754 xfer->status = CC_USB_TRANSACTION_ERROR; 1755 xhci_xfer_report(xfer); 1756 xhci_stall_ep(xfer); 1757 break; 1758 case USB_RET_STALL: 1759 xfer->status = CC_STALL_ERROR; 1760 xhci_xfer_report(xfer); 1761 xhci_stall_ep(xfer); 1762 break; 1763 case USB_RET_BABBLE: 1764 xfer->status = CC_BABBLE_DETECTED; 1765 xhci_xfer_report(xfer); 1766 xhci_stall_ep(xfer); 1767 break; 1768 default: 1769 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1770 xfer->packet.status); 1771 FIXME("unhandled USB_RET_*"); 1772 } 1773 return 0; 1774 } 1775 1776 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1777 { 1778 XHCITRB *trb_setup, *trb_status; 1779 uint8_t bmRequestType; 1780 1781 trb_setup = &xfer->trbs[0]; 1782 trb_status = &xfer->trbs[xfer->trb_count-1]; 1783 1784 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1785 1786 /* at most one Event Data TRB allowed after STATUS */ 1787 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1788 trb_status--; 1789 } 1790 1791 /* do some sanity checks */ 1792 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1793 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1794 TRB_TYPE(*trb_setup)); 1795 return -1; 1796 } 1797 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1798 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1799 TRB_TYPE(*trb_status)); 1800 return -1; 1801 } 1802 if (!(trb_setup->control & TRB_TR_IDT)) { 1803 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1804 return -1; 1805 } 1806 if ((trb_setup->status & 0x1ffff) != 8) { 1807 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1808 (trb_setup->status & 0x1ffff)); 1809 return -1; 1810 } 1811 1812 bmRequestType = trb_setup->parameter; 1813 1814 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1815 xfer->iso_xfer = false; 1816 xfer->timed_xfer = false; 1817 1818 if (xhci_setup_packet(xfer) < 0) { 1819 return -1; 1820 } 1821 xfer->packet.parameter = trb_setup->parameter; 1822 1823 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1824 1825 xhci_complete_packet(xfer); 1826 if (!xfer->running_async && !xfer->running_retry) { 1827 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1828 } 1829 return 0; 1830 } 1831 1832 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1833 XHCIEPContext *epctx, uint64_t mfindex) 1834 { 1835 uint64_t asap = ((mfindex + epctx->interval - 1) & 1836 ~(epctx->interval-1)); 1837 uint64_t kick = epctx->mfindex_last + epctx->interval; 1838 1839 assert(epctx->interval != 0); 1840 xfer->mfindex_kick = MAX(asap, kick); 1841 } 1842 1843 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1844 XHCIEPContext *epctx, uint64_t mfindex) 1845 { 1846 if (xfer->trbs[0].control & TRB_TR_SIA) { 1847 uint64_t asap = ((mfindex + epctx->interval - 1) & 1848 ~(epctx->interval-1)); 1849 if (asap >= epctx->mfindex_last && 1850 asap <= epctx->mfindex_last + epctx->interval * 4) { 1851 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1852 } else { 1853 xfer->mfindex_kick = asap; 1854 } 1855 } else { 1856 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1857 & TRB_TR_FRAMEID_MASK; 1858 xfer->mfindex_kick |= mfindex & ~0x3fff; 1859 if (xfer->mfindex_kick < mfindex) { 1860 xfer->mfindex_kick += 0x4000; 1861 } 1862 } 1863 } 1864 1865 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1866 XHCIEPContext *epctx, uint64_t mfindex) 1867 { 1868 if (xfer->mfindex_kick > mfindex) { 1869 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1870 (xfer->mfindex_kick - mfindex) * 125000); 1871 xfer->running_retry = 1; 1872 } else { 1873 epctx->mfindex_last = xfer->mfindex_kick; 1874 timer_del(epctx->kick_timer); 1875 xfer->running_retry = 0; 1876 } 1877 } 1878 1879 1880 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1881 { 1882 uint64_t mfindex; 1883 1884 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1885 1886 xfer->in_xfer = epctx->type>>2; 1887 1888 switch(epctx->type) { 1889 case ET_INTR_OUT: 1890 case ET_INTR_IN: 1891 xfer->pkts = 0; 1892 xfer->iso_xfer = false; 1893 xfer->timed_xfer = true; 1894 mfindex = xhci_mfindex_get(xhci); 1895 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1896 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1897 if (xfer->running_retry) { 1898 return -1; 1899 } 1900 break; 1901 case ET_BULK_OUT: 1902 case ET_BULK_IN: 1903 xfer->pkts = 0; 1904 xfer->iso_xfer = false; 1905 xfer->timed_xfer = false; 1906 break; 1907 case ET_ISO_OUT: 1908 case ET_ISO_IN: 1909 xfer->pkts = 1; 1910 xfer->iso_xfer = true; 1911 xfer->timed_xfer = true; 1912 mfindex = xhci_mfindex_get(xhci); 1913 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1914 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1915 if (xfer->running_retry) { 1916 return -1; 1917 } 1918 break; 1919 default: 1920 fprintf(stderr, "xhci: unknown or unhandled EP " 1921 "(type %d, in %d, ep %02x)\n", 1922 epctx->type, xfer->in_xfer, xfer->epid); 1923 return -1; 1924 } 1925 1926 if (xhci_setup_packet(xfer) < 0) { 1927 return -1; 1928 } 1929 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1930 1931 xhci_complete_packet(xfer); 1932 if (!xfer->running_async && !xfer->running_retry) { 1933 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1934 } 1935 return 0; 1936 } 1937 1938 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1939 { 1940 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1941 return xhci_submit(xhci, xfer, epctx); 1942 } 1943 1944 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1945 unsigned int epid, unsigned int streamid) 1946 { 1947 XHCIStreamContext *stctx; 1948 XHCIEPContext *epctx; 1949 XHCIRing *ring; 1950 USBEndpoint *ep = NULL; 1951 uint64_t mfindex; 1952 int length; 1953 int i; 1954 1955 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1956 assert(slotid >= 1 && slotid <= xhci->numslots); 1957 assert(epid >= 1 && epid <= 31); 1958 1959 if (!xhci->slots[slotid-1].enabled) { 1960 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1961 return; 1962 } 1963 epctx = xhci->slots[slotid-1].eps[epid-1]; 1964 if (!epctx) { 1965 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1966 epid, slotid); 1967 return; 1968 } 1969 1970 if (epctx->retry) { 1971 XHCITransfer *xfer = epctx->retry; 1972 1973 trace_usb_xhci_xfer_retry(xfer); 1974 assert(xfer->running_retry); 1975 if (xfer->timed_xfer) { 1976 /* time to kick the transfer? */ 1977 mfindex = xhci_mfindex_get(xhci); 1978 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1979 if (xfer->running_retry) { 1980 return; 1981 } 1982 xfer->timed_xfer = 0; 1983 xfer->running_retry = 1; 1984 } 1985 if (xfer->iso_xfer) { 1986 /* retry iso transfer */ 1987 if (xhci_setup_packet(xfer) < 0) { 1988 return; 1989 } 1990 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1991 assert(xfer->packet.status != USB_RET_NAK); 1992 xhci_complete_packet(xfer); 1993 } else { 1994 /* retry nak'ed transfer */ 1995 if (xhci_setup_packet(xfer) < 0) { 1996 return; 1997 } 1998 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1999 if (xfer->packet.status == USB_RET_NAK) { 2000 return; 2001 } 2002 xhci_complete_packet(xfer); 2003 } 2004 assert(!xfer->running_retry); 2005 epctx->retry = NULL; 2006 } 2007 2008 if (epctx->state == EP_HALTED) { 2009 DPRINTF("xhci: ep halted, not running schedule\n"); 2010 return; 2011 } 2012 2013 2014 if (epctx->nr_pstreams) { 2015 uint32_t err; 2016 stctx = xhci_find_stream(epctx, streamid, &err); 2017 if (stctx == NULL) { 2018 return; 2019 } 2020 ring = &stctx->ring; 2021 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2022 } else { 2023 ring = &epctx->ring; 2024 streamid = 0; 2025 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2026 } 2027 assert(ring->dequeue != 0); 2028 2029 while (1) { 2030 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 2031 if (xfer->running_async || xfer->running_retry) { 2032 break; 2033 } 2034 length = xhci_ring_chain_length(xhci, ring); 2035 if (length < 0) { 2036 break; 2037 } else if (length == 0) { 2038 break; 2039 } 2040 if (xfer->trbs && xfer->trb_alloced < length) { 2041 xfer->trb_count = 0; 2042 xfer->trb_alloced = 0; 2043 g_free(xfer->trbs); 2044 xfer->trbs = NULL; 2045 } 2046 if (!xfer->trbs) { 2047 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 2048 xfer->trb_alloced = length; 2049 } 2050 xfer->trb_count = length; 2051 2052 for (i = 0; i < length; i++) { 2053 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2054 } 2055 xfer->streamid = streamid; 2056 2057 if (epid == 1) { 2058 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2059 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2060 ep = xfer->packet.ep; 2061 } else { 2062 fprintf(stderr, "xhci: error firing CTL transfer\n"); 2063 } 2064 } else { 2065 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2066 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2067 } else { 2068 if (!xfer->timed_xfer) { 2069 fprintf(stderr, "xhci: error firing data transfer\n"); 2070 } 2071 } 2072 } 2073 2074 if (epctx->state == EP_HALTED) { 2075 break; 2076 } 2077 if (xfer->running_retry) { 2078 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2079 epctx->retry = xfer; 2080 break; 2081 } 2082 } 2083 2084 ep = xhci_epid_to_usbep(xhci, slotid, epid); 2085 if (ep) { 2086 usb_device_flush_ep_queue(ep->dev, ep); 2087 } 2088 } 2089 2090 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2091 { 2092 trace_usb_xhci_slot_enable(slotid); 2093 assert(slotid >= 1 && slotid <= xhci->numslots); 2094 xhci->slots[slotid-1].enabled = 1; 2095 xhci->slots[slotid-1].uport = NULL; 2096 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2097 2098 return CC_SUCCESS; 2099 } 2100 2101 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2102 { 2103 int i; 2104 2105 trace_usb_xhci_slot_disable(slotid); 2106 assert(slotid >= 1 && slotid <= xhci->numslots); 2107 2108 for (i = 1; i <= 31; i++) { 2109 if (xhci->slots[slotid-1].eps[i-1]) { 2110 xhci_disable_ep(xhci, slotid, i); 2111 } 2112 } 2113 2114 xhci->slots[slotid-1].enabled = 0; 2115 xhci->slots[slotid-1].addressed = 0; 2116 xhci->slots[slotid-1].uport = NULL; 2117 return CC_SUCCESS; 2118 } 2119 2120 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2121 { 2122 USBPort *uport; 2123 char path[32]; 2124 int i, pos, port; 2125 2126 port = (slot_ctx[1]>>16) & 0xFF; 2127 port = xhci->ports[port-1].uport->index+1; 2128 pos = snprintf(path, sizeof(path), "%d", port); 2129 for (i = 0; i < 5; i++) { 2130 port = (slot_ctx[0] >> 4*i) & 0x0f; 2131 if (!port) { 2132 break; 2133 } 2134 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2135 } 2136 2137 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2138 if (strcmp(uport->path, path) == 0) { 2139 return uport; 2140 } 2141 } 2142 return NULL; 2143 } 2144 2145 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2146 uint64_t pictx, bool bsr) 2147 { 2148 XHCISlot *slot; 2149 USBPort *uport; 2150 USBDevice *dev; 2151 dma_addr_t ictx, octx, dcbaap; 2152 uint64_t poctx; 2153 uint32_t ictl_ctx[2]; 2154 uint32_t slot_ctx[4]; 2155 uint32_t ep0_ctx[5]; 2156 int i; 2157 TRBCCode res; 2158 2159 assert(slotid >= 1 && slotid <= xhci->numslots); 2160 2161 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2162 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2163 ictx = xhci_mask64(pictx); 2164 octx = xhci_mask64(poctx); 2165 2166 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2167 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2168 2169 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2170 2171 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2172 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2173 ictl_ctx[0], ictl_ctx[1]); 2174 return CC_TRB_ERROR; 2175 } 2176 2177 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2178 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2179 2180 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2181 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2182 2183 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2184 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2185 2186 uport = xhci_lookup_uport(xhci, slot_ctx); 2187 if (uport == NULL) { 2188 fprintf(stderr, "xhci: port not found\n"); 2189 return CC_TRB_ERROR; 2190 } 2191 trace_usb_xhci_slot_address(slotid, uport->path); 2192 2193 dev = uport->dev; 2194 if (!dev) { 2195 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2196 return CC_USB_TRANSACTION_ERROR; 2197 } 2198 2199 for (i = 0; i < xhci->numslots; i++) { 2200 if (i == slotid-1) { 2201 continue; 2202 } 2203 if (xhci->slots[i].uport == uport) { 2204 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2205 uport->path, i+1); 2206 return CC_TRB_ERROR; 2207 } 2208 } 2209 2210 slot = &xhci->slots[slotid-1]; 2211 slot->uport = uport; 2212 slot->ctx = octx; 2213 2214 if (bsr) { 2215 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2216 } else { 2217 USBPacket p; 2218 uint8_t buf[1]; 2219 2220 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2221 usb_device_reset(dev); 2222 memset(&p, 0, sizeof(p)); 2223 usb_packet_addbuf(&p, buf, sizeof(buf)); 2224 usb_packet_setup(&p, USB_TOKEN_OUT, 2225 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2226 0, false, false); 2227 usb_device_handle_control(dev, &p, 2228 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2229 slotid, 0, 0, NULL); 2230 assert(p.status != USB_RET_ASYNC); 2231 } 2232 2233 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2234 2235 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2236 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2237 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2238 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2239 2240 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2241 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2242 2243 xhci->slots[slotid-1].addressed = 1; 2244 return res; 2245 } 2246 2247 2248 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2249 uint64_t pictx, bool dc) 2250 { 2251 dma_addr_t ictx, octx; 2252 uint32_t ictl_ctx[2]; 2253 uint32_t slot_ctx[4]; 2254 uint32_t islot_ctx[4]; 2255 uint32_t ep_ctx[5]; 2256 int i; 2257 TRBCCode res; 2258 2259 trace_usb_xhci_slot_configure(slotid); 2260 assert(slotid >= 1 && slotid <= xhci->numslots); 2261 2262 ictx = xhci_mask64(pictx); 2263 octx = xhci->slots[slotid-1].ctx; 2264 2265 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2266 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2267 2268 if (dc) { 2269 for (i = 2; i <= 31; i++) { 2270 if (xhci->slots[slotid-1].eps[i-1]) { 2271 xhci_disable_ep(xhci, slotid, i); 2272 } 2273 } 2274 2275 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2276 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2277 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2278 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2279 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2280 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2281 2282 return CC_SUCCESS; 2283 } 2284 2285 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2286 2287 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2288 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2289 ictl_ctx[0], ictl_ctx[1]); 2290 return CC_TRB_ERROR; 2291 } 2292 2293 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2294 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2295 2296 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2297 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2298 return CC_CONTEXT_STATE_ERROR; 2299 } 2300 2301 for (i = 2; i <= 31; i++) { 2302 if (ictl_ctx[0] & (1<<i)) { 2303 xhci_disable_ep(xhci, slotid, i); 2304 } 2305 if (ictl_ctx[1] & (1<<i)) { 2306 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2307 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2308 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2309 ep_ctx[3], ep_ctx[4]); 2310 xhci_disable_ep(xhci, slotid, i); 2311 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2312 if (res != CC_SUCCESS) { 2313 return res; 2314 } 2315 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2316 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2317 ep_ctx[3], ep_ctx[4]); 2318 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2319 } 2320 } 2321 2322 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2323 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2324 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2325 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2326 SLOT_CONTEXT_ENTRIES_SHIFT); 2327 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2328 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2329 2330 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2331 2332 return CC_SUCCESS; 2333 } 2334 2335 2336 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2337 uint64_t pictx) 2338 { 2339 dma_addr_t ictx, octx; 2340 uint32_t ictl_ctx[2]; 2341 uint32_t iep0_ctx[5]; 2342 uint32_t ep0_ctx[5]; 2343 uint32_t islot_ctx[4]; 2344 uint32_t slot_ctx[4]; 2345 2346 trace_usb_xhci_slot_evaluate(slotid); 2347 assert(slotid >= 1 && slotid <= xhci->numslots); 2348 2349 ictx = xhci_mask64(pictx); 2350 octx = xhci->slots[slotid-1].ctx; 2351 2352 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2353 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2354 2355 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2356 2357 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2358 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2359 ictl_ctx[0], ictl_ctx[1]); 2360 return CC_TRB_ERROR; 2361 } 2362 2363 if (ictl_ctx[1] & 0x1) { 2364 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2365 2366 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2367 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2368 2369 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2370 2371 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2372 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2373 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2374 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2375 2376 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2377 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2378 2379 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2380 } 2381 2382 if (ictl_ctx[1] & 0x2) { 2383 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2384 2385 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2386 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2387 iep0_ctx[3], iep0_ctx[4]); 2388 2389 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2390 2391 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2392 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2393 2394 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2395 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2396 2397 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2398 } 2399 2400 return CC_SUCCESS; 2401 } 2402 2403 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2404 { 2405 uint32_t slot_ctx[4]; 2406 dma_addr_t octx; 2407 int i; 2408 2409 trace_usb_xhci_slot_reset(slotid); 2410 assert(slotid >= 1 && slotid <= xhci->numslots); 2411 2412 octx = xhci->slots[slotid-1].ctx; 2413 2414 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2415 2416 for (i = 2; i <= 31; i++) { 2417 if (xhci->slots[slotid-1].eps[i-1]) { 2418 xhci_disable_ep(xhci, slotid, i); 2419 } 2420 } 2421 2422 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2423 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2424 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2425 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2426 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2427 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2428 2429 return CC_SUCCESS; 2430 } 2431 2432 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2433 { 2434 unsigned int slotid; 2435 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2436 if (slotid < 1 || slotid > xhci->numslots) { 2437 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2438 event->ccode = CC_TRB_ERROR; 2439 return 0; 2440 } else if (!xhci->slots[slotid-1].enabled) { 2441 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2442 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2443 return 0; 2444 } 2445 return slotid; 2446 } 2447 2448 /* cleanup slot state on usb device detach */ 2449 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2450 { 2451 int slot, ep; 2452 2453 for (slot = 0; slot < xhci->numslots; slot++) { 2454 if (xhci->slots[slot].uport == uport) { 2455 break; 2456 } 2457 } 2458 if (slot == xhci->numslots) { 2459 return; 2460 } 2461 2462 for (ep = 0; ep < 31; ep++) { 2463 if (xhci->slots[slot].eps[ep]) { 2464 xhci_ep_nuke_xfers(xhci, slot+1, ep+1); 2465 } 2466 } 2467 xhci->slots[slot].uport = NULL; 2468 } 2469 2470 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2471 { 2472 dma_addr_t ctx; 2473 uint8_t bw_ctx[xhci->numports+1]; 2474 2475 DPRINTF("xhci_get_port_bandwidth()\n"); 2476 2477 ctx = xhci_mask64(pctx); 2478 2479 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2480 2481 /* TODO: actually implement real values here */ 2482 bw_ctx[0] = 0; 2483 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2484 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2485 2486 return CC_SUCCESS; 2487 } 2488 2489 static uint32_t rotl(uint32_t v, unsigned count) 2490 { 2491 count &= 31; 2492 return (v << count) | (v >> (32 - count)); 2493 } 2494 2495 2496 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2497 { 2498 uint32_t val; 2499 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2500 val += rotl(lo + 0x49434878, hi & 0x1F); 2501 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2502 return ~val; 2503 } 2504 2505 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2506 { 2507 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2508 uint32_t buf[8]; 2509 uint32_t obuf[8]; 2510 dma_addr_t paddr = xhci_mask64(addr); 2511 2512 pci_dma_read(pci_dev, paddr, &buf, 32); 2513 2514 memcpy(obuf, buf, sizeof(obuf)); 2515 2516 if ((buf[0] & 0xff) == 2) { 2517 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2518 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2519 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2520 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2521 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2522 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2523 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2524 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2525 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2526 } 2527 2528 pci_dma_write(pci_dev, paddr, &obuf, 32); 2529 } 2530 2531 static void xhci_process_commands(XHCIState *xhci) 2532 { 2533 XHCITRB trb; 2534 TRBType type; 2535 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2536 dma_addr_t addr; 2537 unsigned int i, slotid = 0; 2538 2539 DPRINTF("xhci_process_commands()\n"); 2540 if (!xhci_running(xhci)) { 2541 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2542 return; 2543 } 2544 2545 xhci->crcr_low |= CRCR_CRR; 2546 2547 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2548 event.ptr = addr; 2549 switch (type) { 2550 case CR_ENABLE_SLOT: 2551 for (i = 0; i < xhci->numslots; i++) { 2552 if (!xhci->slots[i].enabled) { 2553 break; 2554 } 2555 } 2556 if (i >= xhci->numslots) { 2557 fprintf(stderr, "xhci: no device slots available\n"); 2558 event.ccode = CC_NO_SLOTS_ERROR; 2559 } else { 2560 slotid = i+1; 2561 event.ccode = xhci_enable_slot(xhci, slotid); 2562 } 2563 break; 2564 case CR_DISABLE_SLOT: 2565 slotid = xhci_get_slot(xhci, &event, &trb); 2566 if (slotid) { 2567 event.ccode = xhci_disable_slot(xhci, slotid); 2568 } 2569 break; 2570 case CR_ADDRESS_DEVICE: 2571 slotid = xhci_get_slot(xhci, &event, &trb); 2572 if (slotid) { 2573 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2574 trb.control & TRB_CR_BSR); 2575 } 2576 break; 2577 case CR_CONFIGURE_ENDPOINT: 2578 slotid = xhci_get_slot(xhci, &event, &trb); 2579 if (slotid) { 2580 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2581 trb.control & TRB_CR_DC); 2582 } 2583 break; 2584 case CR_EVALUATE_CONTEXT: 2585 slotid = xhci_get_slot(xhci, &event, &trb); 2586 if (slotid) { 2587 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2588 } 2589 break; 2590 case CR_STOP_ENDPOINT: 2591 slotid = xhci_get_slot(xhci, &event, &trb); 2592 if (slotid) { 2593 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2594 & TRB_CR_EPID_MASK; 2595 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2596 } 2597 break; 2598 case CR_RESET_ENDPOINT: 2599 slotid = xhci_get_slot(xhci, &event, &trb); 2600 if (slotid) { 2601 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2602 & TRB_CR_EPID_MASK; 2603 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2604 } 2605 break; 2606 case CR_SET_TR_DEQUEUE: 2607 slotid = xhci_get_slot(xhci, &event, &trb); 2608 if (slotid) { 2609 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2610 & TRB_CR_EPID_MASK; 2611 unsigned int streamid = (trb.status >> 16) & 0xffff; 2612 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2613 epid, streamid, 2614 trb.parameter); 2615 } 2616 break; 2617 case CR_RESET_DEVICE: 2618 slotid = xhci_get_slot(xhci, &event, &trb); 2619 if (slotid) { 2620 event.ccode = xhci_reset_slot(xhci, slotid); 2621 } 2622 break; 2623 case CR_GET_PORT_BANDWIDTH: 2624 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2625 break; 2626 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2627 xhci_via_challenge(xhci, trb.parameter); 2628 break; 2629 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2630 event.type = 48; /* NEC reply */ 2631 event.length = 0x3025; 2632 break; 2633 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2634 { 2635 uint32_t chi = trb.parameter >> 32; 2636 uint32_t clo = trb.parameter; 2637 uint32_t val = xhci_nec_challenge(chi, clo); 2638 event.length = val & 0xFFFF; 2639 event.epid = val >> 16; 2640 slotid = val >> 24; 2641 event.type = 48; /* NEC reply */ 2642 } 2643 break; 2644 default: 2645 trace_usb_xhci_unimplemented("command", type); 2646 event.ccode = CC_TRB_ERROR; 2647 break; 2648 } 2649 event.slotid = slotid; 2650 xhci_event(xhci, &event, 0); 2651 } 2652 } 2653 2654 static bool xhci_port_have_device(XHCIPort *port) 2655 { 2656 if (!port->uport->dev || !port->uport->dev->attached) { 2657 return false; /* no device present */ 2658 } 2659 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2660 return false; /* speed mismatch */ 2661 } 2662 return true; 2663 } 2664 2665 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2666 { 2667 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2668 port->portnr << 24 }; 2669 2670 if ((port->portsc & bits) == bits) { 2671 return; 2672 } 2673 trace_usb_xhci_port_notify(port->portnr, bits); 2674 port->portsc |= bits; 2675 if (!xhci_running(port->xhci)) { 2676 return; 2677 } 2678 xhci_event(port->xhci, &ev, 0); 2679 } 2680 2681 static void xhci_port_update(XHCIPort *port, int is_detach) 2682 { 2683 uint32_t pls = PLS_RX_DETECT; 2684 2685 port->portsc = PORTSC_PP; 2686 if (!is_detach && xhci_port_have_device(port)) { 2687 port->portsc |= PORTSC_CCS; 2688 switch (port->uport->dev->speed) { 2689 case USB_SPEED_LOW: 2690 port->portsc |= PORTSC_SPEED_LOW; 2691 pls = PLS_POLLING; 2692 break; 2693 case USB_SPEED_FULL: 2694 port->portsc |= PORTSC_SPEED_FULL; 2695 pls = PLS_POLLING; 2696 break; 2697 case USB_SPEED_HIGH: 2698 port->portsc |= PORTSC_SPEED_HIGH; 2699 pls = PLS_POLLING; 2700 break; 2701 case USB_SPEED_SUPER: 2702 port->portsc |= PORTSC_SPEED_SUPER; 2703 port->portsc |= PORTSC_PED; 2704 pls = PLS_U0; 2705 break; 2706 } 2707 } 2708 set_field(&port->portsc, pls, PORTSC_PLS); 2709 trace_usb_xhci_port_link(port->portnr, pls); 2710 xhci_port_notify(port, PORTSC_CSC); 2711 } 2712 2713 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2714 { 2715 trace_usb_xhci_port_reset(port->portnr); 2716 2717 if (!xhci_port_have_device(port)) { 2718 return; 2719 } 2720 2721 usb_device_reset(port->uport->dev); 2722 2723 switch (port->uport->dev->speed) { 2724 case USB_SPEED_SUPER: 2725 if (warm_reset) { 2726 port->portsc |= PORTSC_WRC; 2727 } 2728 /* fall through */ 2729 case USB_SPEED_LOW: 2730 case USB_SPEED_FULL: 2731 case USB_SPEED_HIGH: 2732 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2733 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2734 port->portsc |= PORTSC_PED; 2735 break; 2736 } 2737 2738 port->portsc &= ~PORTSC_PR; 2739 xhci_port_notify(port, PORTSC_PRC); 2740 } 2741 2742 static void xhci_reset(DeviceState *dev) 2743 { 2744 XHCIState *xhci = XHCI(dev); 2745 int i; 2746 2747 trace_usb_xhci_reset(); 2748 if (!(xhci->usbsts & USBSTS_HCH)) { 2749 fprintf(stderr, "xhci: reset while running!\n"); 2750 } 2751 2752 xhci->usbcmd = 0; 2753 xhci->usbsts = USBSTS_HCH; 2754 xhci->dnctrl = 0; 2755 xhci->crcr_low = 0; 2756 xhci->crcr_high = 0; 2757 xhci->dcbaap_low = 0; 2758 xhci->dcbaap_high = 0; 2759 xhci->config = 0; 2760 2761 for (i = 0; i < xhci->numslots; i++) { 2762 xhci_disable_slot(xhci, i+1); 2763 } 2764 2765 for (i = 0; i < xhci->numports; i++) { 2766 xhci_port_update(xhci->ports + i, 0); 2767 } 2768 2769 for (i = 0; i < xhci->numintrs; i++) { 2770 xhci->intr[i].iman = 0; 2771 xhci->intr[i].imod = 0; 2772 xhci->intr[i].erstsz = 0; 2773 xhci->intr[i].erstba_low = 0; 2774 xhci->intr[i].erstba_high = 0; 2775 xhci->intr[i].erdp_low = 0; 2776 xhci->intr[i].erdp_high = 0; 2777 xhci->intr[i].msix_used = 0; 2778 2779 xhci->intr[i].er_ep_idx = 0; 2780 xhci->intr[i].er_pcs = 1; 2781 xhci->intr[i].er_full = 0; 2782 xhci->intr[i].ev_buffer_put = 0; 2783 xhci->intr[i].ev_buffer_get = 0; 2784 } 2785 2786 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2787 xhci_mfwrap_update(xhci); 2788 } 2789 2790 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2791 { 2792 XHCIState *xhci = ptr; 2793 uint32_t ret; 2794 2795 switch (reg) { 2796 case 0x00: /* HCIVERSION, CAPLENGTH */ 2797 ret = 0x01000000 | LEN_CAP; 2798 break; 2799 case 0x04: /* HCSPARAMS 1 */ 2800 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2801 | (xhci->numintrs<<8) | xhci->numslots; 2802 break; 2803 case 0x08: /* HCSPARAMS 2 */ 2804 ret = 0x0000000f; 2805 break; 2806 case 0x0c: /* HCSPARAMS 3 */ 2807 ret = 0x00000000; 2808 break; 2809 case 0x10: /* HCCPARAMS */ 2810 if (sizeof(dma_addr_t) == 4) { 2811 ret = 0x00087000; 2812 } else { 2813 ret = 0x00087001; 2814 } 2815 break; 2816 case 0x14: /* DBOFF */ 2817 ret = OFF_DOORBELL; 2818 break; 2819 case 0x18: /* RTSOFF */ 2820 ret = OFF_RUNTIME; 2821 break; 2822 2823 /* extended capabilities */ 2824 case 0x20: /* Supported Protocol:00 */ 2825 ret = 0x02000402; /* USB 2.0 */ 2826 break; 2827 case 0x24: /* Supported Protocol:04 */ 2828 ret = 0x20425355; /* "USB " */ 2829 break; 2830 case 0x28: /* Supported Protocol:08 */ 2831 ret = 0x00000001 | (xhci->numports_2<<8); 2832 break; 2833 case 0x2c: /* Supported Protocol:0c */ 2834 ret = 0x00000000; /* reserved */ 2835 break; 2836 case 0x30: /* Supported Protocol:00 */ 2837 ret = 0x03000002; /* USB 3.0 */ 2838 break; 2839 case 0x34: /* Supported Protocol:04 */ 2840 ret = 0x20425355; /* "USB " */ 2841 break; 2842 case 0x38: /* Supported Protocol:08 */ 2843 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2844 break; 2845 case 0x3c: /* Supported Protocol:0c */ 2846 ret = 0x00000000; /* reserved */ 2847 break; 2848 default: 2849 trace_usb_xhci_unimplemented("cap read", reg); 2850 ret = 0; 2851 } 2852 2853 trace_usb_xhci_cap_read(reg, ret); 2854 return ret; 2855 } 2856 2857 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2858 { 2859 XHCIPort *port = ptr; 2860 uint32_t ret; 2861 2862 switch (reg) { 2863 case 0x00: /* PORTSC */ 2864 ret = port->portsc; 2865 break; 2866 case 0x04: /* PORTPMSC */ 2867 case 0x08: /* PORTLI */ 2868 ret = 0; 2869 break; 2870 case 0x0c: /* reserved */ 2871 default: 2872 trace_usb_xhci_unimplemented("port read", reg); 2873 ret = 0; 2874 } 2875 2876 trace_usb_xhci_port_read(port->portnr, reg, ret); 2877 return ret; 2878 } 2879 2880 static void xhci_port_write(void *ptr, hwaddr reg, 2881 uint64_t val, unsigned size) 2882 { 2883 XHCIPort *port = ptr; 2884 uint32_t portsc, notify; 2885 2886 trace_usb_xhci_port_write(port->portnr, reg, val); 2887 2888 switch (reg) { 2889 case 0x00: /* PORTSC */ 2890 /* write-1-to-start bits */ 2891 if (val & PORTSC_WPR) { 2892 xhci_port_reset(port, true); 2893 break; 2894 } 2895 if (val & PORTSC_PR) { 2896 xhci_port_reset(port, false); 2897 break; 2898 } 2899 2900 portsc = port->portsc; 2901 notify = 0; 2902 /* write-1-to-clear bits*/ 2903 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2904 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2905 if (val & PORTSC_LWS) { 2906 /* overwrite PLS only when LWS=1 */ 2907 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2908 uint32_t new_pls = get_field(val, PORTSC_PLS); 2909 switch (new_pls) { 2910 case PLS_U0: 2911 if (old_pls != PLS_U0) { 2912 set_field(&portsc, new_pls, PORTSC_PLS); 2913 trace_usb_xhci_port_link(port->portnr, new_pls); 2914 notify = PORTSC_PLC; 2915 } 2916 break; 2917 case PLS_U3: 2918 if (old_pls < PLS_U3) { 2919 set_field(&portsc, new_pls, PORTSC_PLS); 2920 trace_usb_xhci_port_link(port->portnr, new_pls); 2921 } 2922 break; 2923 case PLS_RESUME: 2924 /* windows does this for some reason, don't spam stderr */ 2925 break; 2926 default: 2927 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2928 __func__, old_pls, new_pls); 2929 break; 2930 } 2931 } 2932 /* read/write bits */ 2933 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2934 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2935 port->portsc = portsc; 2936 if (notify) { 2937 xhci_port_notify(port, notify); 2938 } 2939 break; 2940 case 0x04: /* PORTPMSC */ 2941 case 0x08: /* PORTLI */ 2942 default: 2943 trace_usb_xhci_unimplemented("port write", reg); 2944 } 2945 } 2946 2947 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2948 { 2949 XHCIState *xhci = ptr; 2950 uint32_t ret; 2951 2952 switch (reg) { 2953 case 0x00: /* USBCMD */ 2954 ret = xhci->usbcmd; 2955 break; 2956 case 0x04: /* USBSTS */ 2957 ret = xhci->usbsts; 2958 break; 2959 case 0x08: /* PAGESIZE */ 2960 ret = 1; /* 4KiB */ 2961 break; 2962 case 0x14: /* DNCTRL */ 2963 ret = xhci->dnctrl; 2964 break; 2965 case 0x18: /* CRCR low */ 2966 ret = xhci->crcr_low & ~0xe; 2967 break; 2968 case 0x1c: /* CRCR high */ 2969 ret = xhci->crcr_high; 2970 break; 2971 case 0x30: /* DCBAAP low */ 2972 ret = xhci->dcbaap_low; 2973 break; 2974 case 0x34: /* DCBAAP high */ 2975 ret = xhci->dcbaap_high; 2976 break; 2977 case 0x38: /* CONFIG */ 2978 ret = xhci->config; 2979 break; 2980 default: 2981 trace_usb_xhci_unimplemented("oper read", reg); 2982 ret = 0; 2983 } 2984 2985 trace_usb_xhci_oper_read(reg, ret); 2986 return ret; 2987 } 2988 2989 static void xhci_oper_write(void *ptr, hwaddr reg, 2990 uint64_t val, unsigned size) 2991 { 2992 XHCIState *xhci = ptr; 2993 DeviceState *d = DEVICE(ptr); 2994 2995 trace_usb_xhci_oper_write(reg, val); 2996 2997 switch (reg) { 2998 case 0x00: /* USBCMD */ 2999 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3000 xhci_run(xhci); 3001 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3002 xhci_stop(xhci); 3003 } 3004 xhci->usbcmd = val & 0xc0f; 3005 xhci_mfwrap_update(xhci); 3006 if (val & USBCMD_HCRST) { 3007 xhci_reset(d); 3008 } 3009 xhci_intx_update(xhci); 3010 break; 3011 3012 case 0x04: /* USBSTS */ 3013 /* these bits are write-1-to-clear */ 3014 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3015 xhci_intx_update(xhci); 3016 break; 3017 3018 case 0x14: /* DNCTRL */ 3019 xhci->dnctrl = val & 0xffff; 3020 break; 3021 case 0x18: /* CRCR low */ 3022 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3023 break; 3024 case 0x1c: /* CRCR high */ 3025 xhci->crcr_high = val; 3026 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3027 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3028 xhci->crcr_low &= ~CRCR_CRR; 3029 xhci_event(xhci, &event, 0); 3030 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3031 } else { 3032 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3033 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3034 } 3035 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3036 break; 3037 case 0x30: /* DCBAAP low */ 3038 xhci->dcbaap_low = val & 0xffffffc0; 3039 break; 3040 case 0x34: /* DCBAAP high */ 3041 xhci->dcbaap_high = val; 3042 break; 3043 case 0x38: /* CONFIG */ 3044 xhci->config = val & 0xff; 3045 break; 3046 default: 3047 trace_usb_xhci_unimplemented("oper write", reg); 3048 } 3049 } 3050 3051 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3052 unsigned size) 3053 { 3054 XHCIState *xhci = ptr; 3055 uint32_t ret = 0; 3056 3057 if (reg < 0x20) { 3058 switch (reg) { 3059 case 0x00: /* MFINDEX */ 3060 ret = xhci_mfindex_get(xhci) & 0x3fff; 3061 break; 3062 default: 3063 trace_usb_xhci_unimplemented("runtime read", reg); 3064 break; 3065 } 3066 } else { 3067 int v = (reg - 0x20) / 0x20; 3068 XHCIInterrupter *intr = &xhci->intr[v]; 3069 switch (reg & 0x1f) { 3070 case 0x00: /* IMAN */ 3071 ret = intr->iman; 3072 break; 3073 case 0x04: /* IMOD */ 3074 ret = intr->imod; 3075 break; 3076 case 0x08: /* ERSTSZ */ 3077 ret = intr->erstsz; 3078 break; 3079 case 0x10: /* ERSTBA low */ 3080 ret = intr->erstba_low; 3081 break; 3082 case 0x14: /* ERSTBA high */ 3083 ret = intr->erstba_high; 3084 break; 3085 case 0x18: /* ERDP low */ 3086 ret = intr->erdp_low; 3087 break; 3088 case 0x1c: /* ERDP high */ 3089 ret = intr->erdp_high; 3090 break; 3091 } 3092 } 3093 3094 trace_usb_xhci_runtime_read(reg, ret); 3095 return ret; 3096 } 3097 3098 static void xhci_runtime_write(void *ptr, hwaddr reg, 3099 uint64_t val, unsigned size) 3100 { 3101 XHCIState *xhci = ptr; 3102 int v = (reg - 0x20) / 0x20; 3103 XHCIInterrupter *intr = &xhci->intr[v]; 3104 trace_usb_xhci_runtime_write(reg, val); 3105 3106 if (reg < 0x20) { 3107 trace_usb_xhci_unimplemented("runtime write", reg); 3108 return; 3109 } 3110 3111 switch (reg & 0x1f) { 3112 case 0x00: /* IMAN */ 3113 if (val & IMAN_IP) { 3114 intr->iman &= ~IMAN_IP; 3115 } 3116 intr->iman &= ~IMAN_IE; 3117 intr->iman |= val & IMAN_IE; 3118 if (v == 0) { 3119 xhci_intx_update(xhci); 3120 } 3121 xhci_msix_update(xhci, v); 3122 break; 3123 case 0x04: /* IMOD */ 3124 intr->imod = val; 3125 break; 3126 case 0x08: /* ERSTSZ */ 3127 intr->erstsz = val & 0xffff; 3128 break; 3129 case 0x10: /* ERSTBA low */ 3130 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3131 intr->erstba_low = val & 0xffffffc0; */ 3132 intr->erstba_low = val & 0xfffffff0; 3133 break; 3134 case 0x14: /* ERSTBA high */ 3135 intr->erstba_high = val; 3136 xhci_er_reset(xhci, v); 3137 break; 3138 case 0x18: /* ERDP low */ 3139 if (val & ERDP_EHB) { 3140 intr->erdp_low &= ~ERDP_EHB; 3141 } 3142 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3143 break; 3144 case 0x1c: /* ERDP high */ 3145 intr->erdp_high = val; 3146 xhci_events_update(xhci, v); 3147 break; 3148 default: 3149 trace_usb_xhci_unimplemented("oper write", reg); 3150 } 3151 } 3152 3153 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3154 unsigned size) 3155 { 3156 /* doorbells always read as 0 */ 3157 trace_usb_xhci_doorbell_read(reg, 0); 3158 return 0; 3159 } 3160 3161 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3162 uint64_t val, unsigned size) 3163 { 3164 XHCIState *xhci = ptr; 3165 unsigned int epid, streamid; 3166 3167 trace_usb_xhci_doorbell_write(reg, val); 3168 3169 if (!xhci_running(xhci)) { 3170 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3171 return; 3172 } 3173 3174 reg >>= 2; 3175 3176 if (reg == 0) { 3177 if (val == 0) { 3178 xhci_process_commands(xhci); 3179 } else { 3180 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3181 (uint32_t)val); 3182 } 3183 } else { 3184 epid = val & 0xff; 3185 streamid = (val >> 16) & 0xffff; 3186 if (reg > xhci->numslots) { 3187 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3188 } else if (epid > 31) { 3189 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3190 (int)reg, (uint32_t)val); 3191 } else { 3192 xhci_kick_ep(xhci, reg, epid, streamid); 3193 } 3194 } 3195 } 3196 3197 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3198 unsigned width) 3199 { 3200 /* nothing */ 3201 } 3202 3203 static const MemoryRegionOps xhci_cap_ops = { 3204 .read = xhci_cap_read, 3205 .write = xhci_cap_write, 3206 .valid.min_access_size = 1, 3207 .valid.max_access_size = 4, 3208 .impl.min_access_size = 4, 3209 .impl.max_access_size = 4, 3210 .endianness = DEVICE_LITTLE_ENDIAN, 3211 }; 3212 3213 static const MemoryRegionOps xhci_oper_ops = { 3214 .read = xhci_oper_read, 3215 .write = xhci_oper_write, 3216 .valid.min_access_size = 4, 3217 .valid.max_access_size = 4, 3218 .endianness = DEVICE_LITTLE_ENDIAN, 3219 }; 3220 3221 static const MemoryRegionOps xhci_port_ops = { 3222 .read = xhci_port_read, 3223 .write = xhci_port_write, 3224 .valid.min_access_size = 4, 3225 .valid.max_access_size = 4, 3226 .endianness = DEVICE_LITTLE_ENDIAN, 3227 }; 3228 3229 static const MemoryRegionOps xhci_runtime_ops = { 3230 .read = xhci_runtime_read, 3231 .write = xhci_runtime_write, 3232 .valid.min_access_size = 4, 3233 .valid.max_access_size = 4, 3234 .endianness = DEVICE_LITTLE_ENDIAN, 3235 }; 3236 3237 static const MemoryRegionOps xhci_doorbell_ops = { 3238 .read = xhci_doorbell_read, 3239 .write = xhci_doorbell_write, 3240 .valid.min_access_size = 4, 3241 .valid.max_access_size = 4, 3242 .endianness = DEVICE_LITTLE_ENDIAN, 3243 }; 3244 3245 static void xhci_attach(USBPort *usbport) 3246 { 3247 XHCIState *xhci = usbport->opaque; 3248 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3249 3250 xhci_port_update(port, 0); 3251 } 3252 3253 static void xhci_detach(USBPort *usbport) 3254 { 3255 XHCIState *xhci = usbport->opaque; 3256 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3257 3258 xhci_detach_slot(xhci, usbport); 3259 xhci_port_update(port, 1); 3260 } 3261 3262 static void xhci_wakeup(USBPort *usbport) 3263 { 3264 XHCIState *xhci = usbport->opaque; 3265 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3266 3267 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3268 return; 3269 } 3270 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3271 xhci_port_notify(port, PORTSC_PLC); 3272 } 3273 3274 static void xhci_complete(USBPort *port, USBPacket *packet) 3275 { 3276 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3277 3278 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3279 xhci_ep_nuke_one_xfer(xfer); 3280 return; 3281 } 3282 xhci_complete_packet(xfer); 3283 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3284 } 3285 3286 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3287 { 3288 USBBus *bus = usb_bus_from_device(child); 3289 XHCIState *xhci = container_of(bus, XHCIState, bus); 3290 3291 xhci_detach_slot(xhci, uport); 3292 } 3293 3294 static USBPortOps xhci_uport_ops = { 3295 .attach = xhci_attach, 3296 .detach = xhci_detach, 3297 .wakeup = xhci_wakeup, 3298 .complete = xhci_complete, 3299 .child_detach = xhci_child_detach, 3300 }; 3301 3302 static int xhci_find_epid(USBEndpoint *ep) 3303 { 3304 if (ep->nr == 0) { 3305 return 1; 3306 } 3307 if (ep->pid == USB_TOKEN_IN) { 3308 return ep->nr * 2 + 1; 3309 } else { 3310 return ep->nr * 2; 3311 } 3312 } 3313 3314 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 3315 unsigned int slotid, unsigned int epid) 3316 { 3317 assert(slotid >= 1 && slotid <= xhci->numslots); 3318 3319 if (!xhci->slots[slotid - 1].uport) { 3320 return NULL; 3321 } 3322 3323 return usb_ep_get(xhci->slots[slotid - 1].uport->dev, 3324 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); 3325 } 3326 3327 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3328 unsigned int stream) 3329 { 3330 XHCIState *xhci = container_of(bus, XHCIState, bus); 3331 int slotid; 3332 3333 DPRINTF("%s\n", __func__); 3334 slotid = ep->dev->addr; 3335 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3336 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3337 return; 3338 } 3339 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3340 } 3341 3342 static USBBusOps xhci_bus_ops = { 3343 .wakeup_endpoint = xhci_wakeup_endpoint, 3344 }; 3345 3346 static void usb_xhci_init(XHCIState *xhci) 3347 { 3348 DeviceState *dev = DEVICE(xhci); 3349 XHCIPort *port; 3350 int i, usbports, speedmask; 3351 3352 xhci->usbsts = USBSTS_HCH; 3353 3354 if (xhci->numports_2 > MAXPORTS_2) { 3355 xhci->numports_2 = MAXPORTS_2; 3356 } 3357 if (xhci->numports_3 > MAXPORTS_3) { 3358 xhci->numports_3 = MAXPORTS_3; 3359 } 3360 usbports = MAX(xhci->numports_2, xhci->numports_3); 3361 xhci->numports = xhci->numports_2 + xhci->numports_3; 3362 3363 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3364 3365 for (i = 0; i < usbports; i++) { 3366 speedmask = 0; 3367 if (i < xhci->numports_2) { 3368 port = &xhci->ports[i]; 3369 port->portnr = i + 1; 3370 port->uport = &xhci->uports[i]; 3371 port->speedmask = 3372 USB_SPEED_MASK_LOW | 3373 USB_SPEED_MASK_FULL | 3374 USB_SPEED_MASK_HIGH; 3375 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3376 speedmask |= port->speedmask; 3377 } 3378 if (i < xhci->numports_3) { 3379 port = &xhci->ports[i + xhci->numports_2]; 3380 port->portnr = i + 1 + xhci->numports_2; 3381 port->uport = &xhci->uports[i]; 3382 port->speedmask = USB_SPEED_MASK_SUPER; 3383 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3384 speedmask |= port->speedmask; 3385 } 3386 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3387 &xhci_uport_ops, speedmask); 3388 } 3389 } 3390 3391 static int usb_xhci_initfn(struct PCIDevice *dev) 3392 { 3393 int i, ret; 3394 3395 XHCIState *xhci = XHCI(dev); 3396 3397 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3398 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3399 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3400 dev->config[0x60] = 0x30; /* release number */ 3401 3402 usb_xhci_init(xhci); 3403 3404 if (xhci->numintrs > MAXINTRS) { 3405 xhci->numintrs = MAXINTRS; 3406 } 3407 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3408 xhci->numintrs++; 3409 } 3410 if (xhci->numintrs < 1) { 3411 xhci->numintrs = 1; 3412 } 3413 if (xhci->numslots > MAXSLOTS) { 3414 xhci->numslots = MAXSLOTS; 3415 } 3416 if (xhci->numslots < 1) { 3417 xhci->numslots = 1; 3418 } 3419 3420 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3421 3422 xhci->irq = dev->irq[0]; 3423 3424 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3425 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3426 "capabilities", LEN_CAP); 3427 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3428 "operational", 0x400); 3429 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3430 "runtime", LEN_RUNTIME); 3431 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3432 "doorbell", LEN_DOORBELL); 3433 3434 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3435 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3436 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3437 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3438 3439 for (i = 0; i < xhci->numports; i++) { 3440 XHCIPort *port = &xhci->ports[i]; 3441 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3442 port->xhci = xhci; 3443 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3444 port->name, 0x10); 3445 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3446 } 3447 3448 pci_register_bar(dev, 0, 3449 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3450 &xhci->mem); 3451 3452 ret = pcie_endpoint_cap_init(dev, 0xa0); 3453 assert(ret >= 0); 3454 3455 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3456 msi_init(dev, 0x70, xhci->numintrs, true, false); 3457 } 3458 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3459 msix_init(dev, xhci->numintrs, 3460 &xhci->mem, 0, OFF_MSIX_TABLE, 3461 &xhci->mem, 0, OFF_MSIX_PBA, 3462 0x90); 3463 } 3464 3465 return 0; 3466 } 3467 3468 static int usb_xhci_post_load(void *opaque, int version_id) 3469 { 3470 XHCIState *xhci = opaque; 3471 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3472 XHCISlot *slot; 3473 XHCIEPContext *epctx; 3474 dma_addr_t dcbaap, pctx; 3475 uint32_t slot_ctx[4]; 3476 uint32_t ep_ctx[5]; 3477 int slotid, epid, state, intr; 3478 3479 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3480 3481 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3482 slot = &xhci->slots[slotid-1]; 3483 if (!slot->addressed) { 3484 continue; 3485 } 3486 slot->ctx = 3487 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3488 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3489 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3490 assert(slot->uport && slot->uport->dev); 3491 3492 for (epid = 1; epid <= 32; epid++) { 3493 pctx = slot->ctx + 32 * epid; 3494 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3495 state = ep_ctx[0] & EP_STATE_MASK; 3496 if (state == EP_DISABLED) { 3497 continue; 3498 } 3499 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3500 slot->eps[epid-1] = epctx; 3501 xhci_init_epctx(epctx, pctx, ep_ctx); 3502 epctx->state = state; 3503 if (state == EP_RUNNING) { 3504 /* kick endpoint after vmload is finished */ 3505 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3506 } 3507 } 3508 } 3509 3510 for (intr = 0; intr < xhci->numintrs; intr++) { 3511 if (xhci->intr[intr].msix_used) { 3512 msix_vector_use(pci_dev, intr); 3513 } else { 3514 msix_vector_unuse(pci_dev, intr); 3515 } 3516 } 3517 3518 return 0; 3519 } 3520 3521 static const VMStateDescription vmstate_xhci_ring = { 3522 .name = "xhci-ring", 3523 .version_id = 1, 3524 .fields = (VMStateField[]) { 3525 VMSTATE_UINT64(dequeue, XHCIRing), 3526 VMSTATE_BOOL(ccs, XHCIRing), 3527 VMSTATE_END_OF_LIST() 3528 } 3529 }; 3530 3531 static const VMStateDescription vmstate_xhci_port = { 3532 .name = "xhci-port", 3533 .version_id = 1, 3534 .fields = (VMStateField[]) { 3535 VMSTATE_UINT32(portsc, XHCIPort), 3536 VMSTATE_END_OF_LIST() 3537 } 3538 }; 3539 3540 static const VMStateDescription vmstate_xhci_slot = { 3541 .name = "xhci-slot", 3542 .version_id = 1, 3543 .fields = (VMStateField[]) { 3544 VMSTATE_BOOL(enabled, XHCISlot), 3545 VMSTATE_BOOL(addressed, XHCISlot), 3546 VMSTATE_END_OF_LIST() 3547 } 3548 }; 3549 3550 static const VMStateDescription vmstate_xhci_event = { 3551 .name = "xhci-event", 3552 .version_id = 1, 3553 .fields = (VMStateField[]) { 3554 VMSTATE_UINT32(type, XHCIEvent), 3555 VMSTATE_UINT32(ccode, XHCIEvent), 3556 VMSTATE_UINT64(ptr, XHCIEvent), 3557 VMSTATE_UINT32(length, XHCIEvent), 3558 VMSTATE_UINT32(flags, XHCIEvent), 3559 VMSTATE_UINT8(slotid, XHCIEvent), 3560 VMSTATE_UINT8(epid, XHCIEvent), 3561 } 3562 }; 3563 3564 static bool xhci_er_full(void *opaque, int version_id) 3565 { 3566 struct XHCIInterrupter *intr = opaque; 3567 return intr->er_full; 3568 } 3569 3570 static const VMStateDescription vmstate_xhci_intr = { 3571 .name = "xhci-intr", 3572 .version_id = 1, 3573 .fields = (VMStateField[]) { 3574 /* registers */ 3575 VMSTATE_UINT32(iman, XHCIInterrupter), 3576 VMSTATE_UINT32(imod, XHCIInterrupter), 3577 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3578 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3579 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3580 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3581 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3582 3583 /* state */ 3584 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3585 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3586 VMSTATE_UINT64(er_start, XHCIInterrupter), 3587 VMSTATE_UINT32(er_size, XHCIInterrupter), 3588 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3589 3590 /* event queue (used if ring is full) */ 3591 VMSTATE_BOOL(er_full, XHCIInterrupter), 3592 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3593 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3594 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3595 xhci_er_full, 1, 3596 vmstate_xhci_event, XHCIEvent), 3597 3598 VMSTATE_END_OF_LIST() 3599 } 3600 }; 3601 3602 static const VMStateDescription vmstate_xhci = { 3603 .name = "xhci", 3604 .version_id = 1, 3605 .post_load = usb_xhci_post_load, 3606 .fields = (VMStateField[]) { 3607 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3608 VMSTATE_MSIX(parent_obj, XHCIState), 3609 3610 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3611 vmstate_xhci_port, XHCIPort), 3612 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3613 vmstate_xhci_slot, XHCISlot), 3614 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3615 vmstate_xhci_intr, XHCIInterrupter), 3616 3617 /* Operational Registers */ 3618 VMSTATE_UINT32(usbcmd, XHCIState), 3619 VMSTATE_UINT32(usbsts, XHCIState), 3620 VMSTATE_UINT32(dnctrl, XHCIState), 3621 VMSTATE_UINT32(crcr_low, XHCIState), 3622 VMSTATE_UINT32(crcr_high, XHCIState), 3623 VMSTATE_UINT32(dcbaap_low, XHCIState), 3624 VMSTATE_UINT32(dcbaap_high, XHCIState), 3625 VMSTATE_UINT32(config, XHCIState), 3626 3627 /* Runtime Registers & state */ 3628 VMSTATE_INT64(mfindex_start, XHCIState), 3629 VMSTATE_TIMER(mfwrap_timer, XHCIState), 3630 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3631 3632 VMSTATE_END_OF_LIST() 3633 } 3634 }; 3635 3636 static Property xhci_properties[] = { 3637 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3638 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3639 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3640 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3641 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3642 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3643 DEFINE_PROP_END_OF_LIST(), 3644 }; 3645 3646 static void xhci_class_init(ObjectClass *klass, void *data) 3647 { 3648 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3649 DeviceClass *dc = DEVICE_CLASS(klass); 3650 3651 dc->vmsd = &vmstate_xhci; 3652 dc->props = xhci_properties; 3653 dc->reset = xhci_reset; 3654 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3655 k->init = usb_xhci_initfn; 3656 k->vendor_id = PCI_VENDOR_ID_NEC; 3657 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3658 k->class_id = PCI_CLASS_SERIAL_USB; 3659 k->revision = 0x03; 3660 k->is_express = 1; 3661 k->no_hotplug = 1; 3662 } 3663 3664 static const TypeInfo xhci_info = { 3665 .name = TYPE_XHCI, 3666 .parent = TYPE_PCI_DEVICE, 3667 .instance_size = sizeof(XHCIState), 3668 .class_init = xhci_class_init, 3669 }; 3670 3671 static void xhci_register_types(void) 3672 { 3673 type_register_static(&xhci_info); 3674 } 3675 3676 type_init(xhci_register_types) 3677