1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 unsigned int streamid; 355 bool in_xfer; 356 bool iso_xfer; 357 bool timed_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 unsigned int next_xfer; 385 unsigned int comp_xfer; 386 XHCITransfer transfers[TD_QUEUE]; 387 XHCITransfer *retry; 388 EPType type; 389 dma_addr_t pctx; 390 unsigned int max_psize; 391 uint32_t state; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs, er_full; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 XHCIEvent ev_buffer[EV_QUEUE]; 439 unsigned int ev_buffer_put; 440 unsigned int ev_buffer_get; 441 442 } XHCIInterrupter; 443 444 struct XHCIState { 445 /*< private >*/ 446 PCIDevice parent_obj; 447 /*< public >*/ 448 449 USBBus bus; 450 MemoryRegion mem; 451 MemoryRegion mem_cap; 452 MemoryRegion mem_oper; 453 MemoryRegion mem_runtime; 454 MemoryRegion mem_doorbell; 455 456 /* properties */ 457 uint32_t numports_2; 458 uint32_t numports_3; 459 uint32_t numintrs; 460 uint32_t numslots; 461 uint32_t flags; 462 uint32_t max_pstreams_mask; 463 464 /* Operational Registers */ 465 uint32_t usbcmd; 466 uint32_t usbsts; 467 uint32_t dnctrl; 468 uint32_t crcr_low; 469 uint32_t crcr_high; 470 uint32_t dcbaap_low; 471 uint32_t dcbaap_high; 472 uint32_t config; 473 474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 475 XHCIPort ports[MAXPORTS]; 476 XHCISlot slots[MAXSLOTS]; 477 uint32_t numports; 478 479 /* Runtime Registers */ 480 int64_t mfindex_start; 481 QEMUTimer *mfwrap_timer; 482 XHCIInterrupter intr[MAXINTRS]; 483 484 XHCIRing cmd_ring; 485 }; 486 487 #define TYPE_XHCI "nec-usb-xhci" 488 489 #define XHCI(obj) \ 490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 491 492 typedef struct XHCIEvRingSeg { 493 uint32_t addr_low; 494 uint32_t addr_high; 495 uint32_t size; 496 uint32_t rsvd; 497 } XHCIEvRingSeg; 498 499 enum xhci_flags { 500 XHCI_FLAG_USE_MSI = 1, 501 XHCI_FLAG_USE_MSI_X, 502 XHCI_FLAG_SS_FIRST, 503 XHCI_FLAG_FORCE_PCIE_ENDCAP, 504 XHCI_FLAG_ENABLE_STREAMS, 505 }; 506 507 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 508 unsigned int epid, unsigned int streamid); 509 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 510 unsigned int epid); 511 static void xhci_xfer_report(XHCITransfer *xfer); 512 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 513 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 514 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 515 unsigned int slotid, unsigned int epid); 516 517 static const char *TRBType_names[] = { 518 [TRB_RESERVED] = "TRB_RESERVED", 519 [TR_NORMAL] = "TR_NORMAL", 520 [TR_SETUP] = "TR_SETUP", 521 [TR_DATA] = "TR_DATA", 522 [TR_STATUS] = "TR_STATUS", 523 [TR_ISOCH] = "TR_ISOCH", 524 [TR_LINK] = "TR_LINK", 525 [TR_EVDATA] = "TR_EVDATA", 526 [TR_NOOP] = "TR_NOOP", 527 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 528 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 529 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 530 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 531 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 532 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 533 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 534 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 535 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 536 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 537 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 538 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 539 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 540 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 541 [CR_NOOP] = "CR_NOOP", 542 [ER_TRANSFER] = "ER_TRANSFER", 543 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 544 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 545 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 546 [ER_DOORBELL] = "ER_DOORBELL", 547 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 548 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 549 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 550 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 551 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 552 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 553 }; 554 555 static const char *TRBCCode_names[] = { 556 [CC_INVALID] = "CC_INVALID", 557 [CC_SUCCESS] = "CC_SUCCESS", 558 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 559 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 560 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 561 [CC_TRB_ERROR] = "CC_TRB_ERROR", 562 [CC_STALL_ERROR] = "CC_STALL_ERROR", 563 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 564 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 565 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 566 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 567 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 568 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 569 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 570 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 571 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 572 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 573 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 574 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 575 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 576 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 577 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 578 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 579 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 580 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 581 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 582 [CC_STOPPED] = "CC_STOPPED", 583 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 584 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 585 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 586 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 587 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 588 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 589 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 590 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 591 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 592 }; 593 594 static const char *ep_state_names[] = { 595 [EP_DISABLED] = "disabled", 596 [EP_RUNNING] = "running", 597 [EP_HALTED] = "halted", 598 [EP_STOPPED] = "stopped", 599 [EP_ERROR] = "error", 600 }; 601 602 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 603 { 604 if (index >= llen || list[index] == NULL) { 605 return "???"; 606 } 607 return list[index]; 608 } 609 610 static const char *trb_name(XHCITRB *trb) 611 { 612 return lookup_name(TRB_TYPE(*trb), TRBType_names, 613 ARRAY_SIZE(TRBType_names)); 614 } 615 616 static const char *event_name(XHCIEvent *event) 617 { 618 return lookup_name(event->ccode, TRBCCode_names, 619 ARRAY_SIZE(TRBCCode_names)); 620 } 621 622 static const char *ep_state_name(uint32_t state) 623 { 624 return lookup_name(state, ep_state_names, 625 ARRAY_SIZE(ep_state_names)); 626 } 627 628 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 629 { 630 return xhci->flags & (1 << bit); 631 } 632 633 static uint64_t xhci_mfindex_get(XHCIState *xhci) 634 { 635 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 636 return (now - xhci->mfindex_start) / 125000; 637 } 638 639 static void xhci_mfwrap_update(XHCIState *xhci) 640 { 641 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 642 uint32_t mfindex, left; 643 int64_t now; 644 645 if ((xhci->usbcmd & bits) == bits) { 646 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 647 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 648 left = 0x4000 - mfindex; 649 timer_mod(xhci->mfwrap_timer, now + left * 125000); 650 } else { 651 timer_del(xhci->mfwrap_timer); 652 } 653 } 654 655 static void xhci_mfwrap_timer(void *opaque) 656 { 657 XHCIState *xhci = opaque; 658 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 659 660 xhci_event(xhci, &wrap, 0); 661 xhci_mfwrap_update(xhci); 662 } 663 664 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 665 { 666 if (sizeof(dma_addr_t) == 4) { 667 return low; 668 } else { 669 return low | (((dma_addr_t)high << 16) << 16); 670 } 671 } 672 673 static inline dma_addr_t xhci_mask64(uint64_t addr) 674 { 675 if (sizeof(dma_addr_t) == 4) { 676 return addr & 0xffffffff; 677 } else { 678 return addr; 679 } 680 } 681 682 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 683 uint32_t *buf, size_t len) 684 { 685 int i; 686 687 assert((len % sizeof(uint32_t)) == 0); 688 689 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 690 691 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 692 buf[i] = le32_to_cpu(buf[i]); 693 } 694 } 695 696 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 697 uint32_t *buf, size_t len) 698 { 699 int i; 700 uint32_t tmp[len / sizeof(uint32_t)]; 701 702 assert((len % sizeof(uint32_t)) == 0); 703 704 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 705 tmp[i] = cpu_to_le32(buf[i]); 706 } 707 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 708 } 709 710 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 711 { 712 int index; 713 714 if (!uport->dev) { 715 return NULL; 716 } 717 switch (uport->dev->speed) { 718 case USB_SPEED_LOW: 719 case USB_SPEED_FULL: 720 case USB_SPEED_HIGH: 721 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 722 index = uport->index + xhci->numports_3; 723 } else { 724 index = uport->index; 725 } 726 break; 727 case USB_SPEED_SUPER: 728 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 729 index = uport->index; 730 } else { 731 index = uport->index + xhci->numports_2; 732 } 733 break; 734 default: 735 return NULL; 736 } 737 return &xhci->ports[index]; 738 } 739 740 static void xhci_intx_update(XHCIState *xhci) 741 { 742 PCIDevice *pci_dev = PCI_DEVICE(xhci); 743 int level = 0; 744 745 if (msix_enabled(pci_dev) || 746 msi_enabled(pci_dev)) { 747 return; 748 } 749 750 if (xhci->intr[0].iman & IMAN_IP && 751 xhci->intr[0].iman & IMAN_IE && 752 xhci->usbcmd & USBCMD_INTE) { 753 level = 1; 754 } 755 756 trace_usb_xhci_irq_intx(level); 757 pci_set_irq(pci_dev, level); 758 } 759 760 static void xhci_msix_update(XHCIState *xhci, int v) 761 { 762 PCIDevice *pci_dev = PCI_DEVICE(xhci); 763 bool enabled; 764 765 if (!msix_enabled(pci_dev)) { 766 return; 767 } 768 769 enabled = xhci->intr[v].iman & IMAN_IE; 770 if (enabled == xhci->intr[v].msix_used) { 771 return; 772 } 773 774 if (enabled) { 775 trace_usb_xhci_irq_msix_use(v); 776 msix_vector_use(pci_dev, v); 777 xhci->intr[v].msix_used = true; 778 } else { 779 trace_usb_xhci_irq_msix_unuse(v); 780 msix_vector_unuse(pci_dev, v); 781 xhci->intr[v].msix_used = false; 782 } 783 } 784 785 static void xhci_intr_raise(XHCIState *xhci, int v) 786 { 787 PCIDevice *pci_dev = PCI_DEVICE(xhci); 788 789 xhci->intr[v].erdp_low |= ERDP_EHB; 790 xhci->intr[v].iman |= IMAN_IP; 791 xhci->usbsts |= USBSTS_EINT; 792 793 if (!(xhci->intr[v].iman & IMAN_IE)) { 794 return; 795 } 796 797 if (!(xhci->usbcmd & USBCMD_INTE)) { 798 return; 799 } 800 801 if (msix_enabled(pci_dev)) { 802 trace_usb_xhci_irq_msix(v); 803 msix_notify(pci_dev, v); 804 return; 805 } 806 807 if (msi_enabled(pci_dev)) { 808 trace_usb_xhci_irq_msi(v); 809 msi_notify(pci_dev, v); 810 return; 811 } 812 813 if (v == 0) { 814 trace_usb_xhci_irq_intx(1); 815 pci_irq_assert(pci_dev); 816 } 817 } 818 819 static inline int xhci_running(XHCIState *xhci) 820 { 821 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 822 } 823 824 static void xhci_die(XHCIState *xhci) 825 { 826 xhci->usbsts |= USBSTS_HCE; 827 DPRINTF("xhci: asserted controller error\n"); 828 } 829 830 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 831 { 832 PCIDevice *pci_dev = PCI_DEVICE(xhci); 833 XHCIInterrupter *intr = &xhci->intr[v]; 834 XHCITRB ev_trb; 835 dma_addr_t addr; 836 837 ev_trb.parameter = cpu_to_le64(event->ptr); 838 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 839 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 840 event->flags | (event->type << TRB_TYPE_SHIFT); 841 if (intr->er_pcs) { 842 ev_trb.control |= TRB_C; 843 } 844 ev_trb.control = cpu_to_le32(ev_trb.control); 845 846 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 847 event_name(event), ev_trb.parameter, 848 ev_trb.status, ev_trb.control); 849 850 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 851 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 852 853 intr->er_ep_idx++; 854 if (intr->er_ep_idx >= intr->er_size) { 855 intr->er_ep_idx = 0; 856 intr->er_pcs = !intr->er_pcs; 857 } 858 } 859 860 static void xhci_events_update(XHCIState *xhci, int v) 861 { 862 XHCIInterrupter *intr = &xhci->intr[v]; 863 dma_addr_t erdp; 864 unsigned int dp_idx; 865 bool do_irq = 0; 866 867 if (xhci->usbsts & USBSTS_HCH) { 868 return; 869 } 870 871 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 872 if (erdp < intr->er_start || 873 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 874 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 875 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 876 v, intr->er_start, intr->er_size); 877 xhci_die(xhci); 878 return; 879 } 880 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 881 assert(dp_idx < intr->er_size); 882 883 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 884 * deadlocks when the ER is full. Hack it by holding off events until 885 * the driver decides to free at least half of the ring */ 886 if (intr->er_full) { 887 int er_free = dp_idx - intr->er_ep_idx; 888 if (er_free <= 0) { 889 er_free += intr->er_size; 890 } 891 if (er_free < (intr->er_size/2)) { 892 DPRINTF("xhci_events_update(): event ring still " 893 "more than half full (hack)\n"); 894 return; 895 } 896 } 897 898 while (intr->ev_buffer_put != intr->ev_buffer_get) { 899 assert(intr->er_full); 900 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 901 DPRINTF("xhci_events_update(): event ring full again\n"); 902 #ifndef ER_FULL_HACK 903 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 904 xhci_write_event(xhci, &full, v); 905 #endif 906 do_irq = 1; 907 break; 908 } 909 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 910 xhci_write_event(xhci, event, v); 911 intr->ev_buffer_get++; 912 do_irq = 1; 913 if (intr->ev_buffer_get == EV_QUEUE) { 914 intr->ev_buffer_get = 0; 915 } 916 } 917 918 if (do_irq) { 919 xhci_intr_raise(xhci, v); 920 } 921 922 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 923 DPRINTF("xhci_events_update(): event ring no longer full\n"); 924 intr->er_full = 0; 925 } 926 } 927 928 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 929 { 930 XHCIInterrupter *intr; 931 dma_addr_t erdp; 932 unsigned int dp_idx; 933 934 if (v >= xhci->numintrs) { 935 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 936 return; 937 } 938 intr = &xhci->intr[v]; 939 940 if (intr->er_full) { 941 DPRINTF("xhci_event(): ER full, queueing\n"); 942 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 943 DPRINTF("xhci: event queue full, dropping event!\n"); 944 return; 945 } 946 intr->ev_buffer[intr->ev_buffer_put++] = *event; 947 if (intr->ev_buffer_put == EV_QUEUE) { 948 intr->ev_buffer_put = 0; 949 } 950 return; 951 } 952 953 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 954 if (erdp < intr->er_start || 955 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 956 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 957 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 958 v, intr->er_start, intr->er_size); 959 xhci_die(xhci); 960 return; 961 } 962 963 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 964 assert(dp_idx < intr->er_size); 965 966 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 967 DPRINTF("xhci_event(): ER full, queueing\n"); 968 #ifndef ER_FULL_HACK 969 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 970 xhci_write_event(xhci, &full); 971 #endif 972 intr->er_full = 1; 973 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 974 DPRINTF("xhci: event queue full, dropping event!\n"); 975 return; 976 } 977 intr->ev_buffer[intr->ev_buffer_put++] = *event; 978 if (intr->ev_buffer_put == EV_QUEUE) { 979 intr->ev_buffer_put = 0; 980 } 981 } else { 982 xhci_write_event(xhci, event, v); 983 } 984 985 xhci_intr_raise(xhci, v); 986 } 987 988 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 989 dma_addr_t base) 990 { 991 ring->dequeue = base; 992 ring->ccs = 1; 993 } 994 995 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 996 dma_addr_t *addr) 997 { 998 PCIDevice *pci_dev = PCI_DEVICE(xhci); 999 1000 while (1) { 1001 TRBType type; 1002 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 1003 trb->addr = ring->dequeue; 1004 trb->ccs = ring->ccs; 1005 le64_to_cpus(&trb->parameter); 1006 le32_to_cpus(&trb->status); 1007 le32_to_cpus(&trb->control); 1008 1009 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 1010 trb->parameter, trb->status, trb->control); 1011 1012 if ((trb->control & TRB_C) != ring->ccs) { 1013 return 0; 1014 } 1015 1016 type = TRB_TYPE(*trb); 1017 1018 if (type != TR_LINK) { 1019 if (addr) { 1020 *addr = ring->dequeue; 1021 } 1022 ring->dequeue += TRB_SIZE; 1023 return type; 1024 } else { 1025 ring->dequeue = xhci_mask64(trb->parameter); 1026 if (trb->control & TRB_LK_TC) { 1027 ring->ccs = !ring->ccs; 1028 } 1029 } 1030 } 1031 } 1032 1033 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1034 { 1035 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1036 XHCITRB trb; 1037 int length = 0; 1038 dma_addr_t dequeue = ring->dequeue; 1039 bool ccs = ring->ccs; 1040 /* hack to bundle together the two/three TDs that make a setup transfer */ 1041 bool control_td_set = 0; 1042 1043 while (1) { 1044 TRBType type; 1045 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1046 le64_to_cpus(&trb.parameter); 1047 le32_to_cpus(&trb.status); 1048 le32_to_cpus(&trb.control); 1049 1050 if ((trb.control & TRB_C) != ccs) { 1051 return -length; 1052 } 1053 1054 type = TRB_TYPE(trb); 1055 1056 if (type == TR_LINK) { 1057 dequeue = xhci_mask64(trb.parameter); 1058 if (trb.control & TRB_LK_TC) { 1059 ccs = !ccs; 1060 } 1061 continue; 1062 } 1063 1064 length += 1; 1065 dequeue += TRB_SIZE; 1066 1067 if (type == TR_SETUP) { 1068 control_td_set = 1; 1069 } else if (type == TR_STATUS) { 1070 control_td_set = 0; 1071 } 1072 1073 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1074 return length; 1075 } 1076 } 1077 } 1078 1079 static void xhci_er_reset(XHCIState *xhci, int v) 1080 { 1081 XHCIInterrupter *intr = &xhci->intr[v]; 1082 XHCIEvRingSeg seg; 1083 1084 if (intr->erstsz == 0) { 1085 /* disabled */ 1086 intr->er_start = 0; 1087 intr->er_size = 0; 1088 return; 1089 } 1090 /* cache the (sole) event ring segment location */ 1091 if (intr->erstsz != 1) { 1092 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1093 xhci_die(xhci); 1094 return; 1095 } 1096 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1097 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1098 le32_to_cpus(&seg.addr_low); 1099 le32_to_cpus(&seg.addr_high); 1100 le32_to_cpus(&seg.size); 1101 if (seg.size < 16 || seg.size > 4096) { 1102 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 1103 xhci_die(xhci); 1104 return; 1105 } 1106 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1107 intr->er_size = seg.size; 1108 1109 intr->er_ep_idx = 0; 1110 intr->er_pcs = 1; 1111 intr->er_full = 0; 1112 1113 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1114 v, intr->er_start, intr->er_size); 1115 } 1116 1117 static void xhci_run(XHCIState *xhci) 1118 { 1119 trace_usb_xhci_run(); 1120 xhci->usbsts &= ~USBSTS_HCH; 1121 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1122 } 1123 1124 static void xhci_stop(XHCIState *xhci) 1125 { 1126 trace_usb_xhci_stop(); 1127 xhci->usbsts |= USBSTS_HCH; 1128 xhci->crcr_low &= ~CRCR_CRR; 1129 } 1130 1131 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1132 dma_addr_t base) 1133 { 1134 XHCIStreamContext *stctx; 1135 unsigned int i; 1136 1137 stctx = g_new0(XHCIStreamContext, count); 1138 for (i = 0; i < count; i++) { 1139 stctx[i].pctx = base + i * 16; 1140 stctx[i].sct = -1; 1141 } 1142 return stctx; 1143 } 1144 1145 static void xhci_reset_streams(XHCIEPContext *epctx) 1146 { 1147 unsigned int i; 1148 1149 for (i = 0; i < epctx->nr_pstreams; i++) { 1150 epctx->pstreams[i].sct = -1; 1151 } 1152 } 1153 1154 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1155 { 1156 assert(epctx->pstreams == NULL); 1157 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1158 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1159 } 1160 1161 static void xhci_free_streams(XHCIEPContext *epctx) 1162 { 1163 assert(epctx->pstreams != NULL); 1164 1165 g_free(epctx->pstreams); 1166 epctx->pstreams = NULL; 1167 epctx->nr_pstreams = 0; 1168 } 1169 1170 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 1171 unsigned int slotid, 1172 uint32_t epmask, 1173 XHCIEPContext **epctxs, 1174 USBEndpoint **eps) 1175 { 1176 XHCISlot *slot; 1177 XHCIEPContext *epctx; 1178 USBEndpoint *ep; 1179 int i, j; 1180 1181 assert(slotid >= 1 && slotid <= xhci->numslots); 1182 1183 slot = &xhci->slots[slotid - 1]; 1184 1185 for (i = 2, j = 0; i <= 31; i++) { 1186 if (!(epmask & (1u << i))) { 1187 continue; 1188 } 1189 1190 epctx = slot->eps[i - 1]; 1191 ep = xhci_epid_to_usbep(xhci, slotid, i); 1192 if (!epctx || !epctx->nr_pstreams || !ep) { 1193 continue; 1194 } 1195 1196 if (epctxs) { 1197 epctxs[j] = epctx; 1198 } 1199 eps[j++] = ep; 1200 } 1201 return j; 1202 } 1203 1204 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 1205 uint32_t epmask) 1206 { 1207 USBEndpoint *eps[30]; 1208 int nr_eps; 1209 1210 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 1211 if (nr_eps) { 1212 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 1213 } 1214 } 1215 1216 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 1217 uint32_t epmask) 1218 { 1219 XHCIEPContext *epctxs[30]; 1220 USBEndpoint *eps[30]; 1221 int i, r, nr_eps, req_nr_streams, dev_max_streams; 1222 1223 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 1224 eps); 1225 if (nr_eps == 0) { 1226 return CC_SUCCESS; 1227 } 1228 1229 req_nr_streams = epctxs[0]->nr_pstreams; 1230 dev_max_streams = eps[0]->max_streams; 1231 1232 for (i = 1; i < nr_eps; i++) { 1233 /* 1234 * HdG: I don't expect these to ever trigger, but if they do we need 1235 * to come up with another solution, ie group identical endpoints 1236 * together and make an usb_device_alloc_streams call per group. 1237 */ 1238 if (epctxs[i]->nr_pstreams != req_nr_streams) { 1239 FIXME("guest streams config not identical for all eps"); 1240 return CC_RESOURCE_ERROR; 1241 } 1242 if (eps[i]->max_streams != dev_max_streams) { 1243 FIXME("device streams config not identical for all eps"); 1244 return CC_RESOURCE_ERROR; 1245 } 1246 } 1247 1248 /* 1249 * max-streams in both the device descriptor and in the controller is a 1250 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 1251 * streams the guest will ask for 5 rounded up to the next power of 2 which 1252 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 1253 * 1254 * For redirected devices however this is an issue, as there we must ask 1255 * the real xhci controller to alloc streams, and the host driver for the 1256 * real xhci controller will likely disallow allocating more streams then 1257 * the device can handle. 1258 * 1259 * So we limit the requested nr_streams to the maximum number the device 1260 * can handle. 1261 */ 1262 if (req_nr_streams > dev_max_streams) { 1263 req_nr_streams = dev_max_streams; 1264 } 1265 1266 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 1267 if (r != 0) { 1268 DPRINTF("xhci: alloc streams failed\n"); 1269 return CC_RESOURCE_ERROR; 1270 } 1271 1272 return CC_SUCCESS; 1273 } 1274 1275 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1276 unsigned int streamid, 1277 uint32_t *cc_error) 1278 { 1279 XHCIStreamContext *sctx; 1280 dma_addr_t base; 1281 uint32_t ctx[2], sct; 1282 1283 assert(streamid != 0); 1284 if (epctx->lsa) { 1285 if (streamid >= epctx->nr_pstreams) { 1286 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1287 return NULL; 1288 } 1289 sctx = epctx->pstreams + streamid; 1290 } else { 1291 FIXME("secondary streams not implemented yet"); 1292 } 1293 1294 if (sctx->sct == -1) { 1295 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1296 sct = (ctx[0] >> 1) & 0x07; 1297 if (epctx->lsa && sct != 1) { 1298 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1299 return NULL; 1300 } 1301 sctx->sct = sct; 1302 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1303 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1304 } 1305 return sctx; 1306 } 1307 1308 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1309 XHCIStreamContext *sctx, uint32_t state) 1310 { 1311 XHCIRing *ring = NULL; 1312 uint32_t ctx[5]; 1313 uint32_t ctx2[2]; 1314 1315 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1316 ctx[0] &= ~EP_STATE_MASK; 1317 ctx[0] |= state; 1318 1319 /* update ring dequeue ptr */ 1320 if (epctx->nr_pstreams) { 1321 if (sctx != NULL) { 1322 ring = &sctx->ring; 1323 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1324 ctx2[0] &= 0xe; 1325 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1326 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1327 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1328 } 1329 } else { 1330 ring = &epctx->ring; 1331 } 1332 if (ring) { 1333 ctx[2] = ring->dequeue | ring->ccs; 1334 ctx[3] = (ring->dequeue >> 16) >> 16; 1335 1336 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1337 epctx->pctx, state, ctx[3], ctx[2]); 1338 } 1339 1340 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1341 if (epctx->state != state) { 1342 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1343 ep_state_name(epctx->state), 1344 ep_state_name(state)); 1345 } 1346 epctx->state = state; 1347 } 1348 1349 static void xhci_ep_kick_timer(void *opaque) 1350 { 1351 XHCIEPContext *epctx = opaque; 1352 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1353 } 1354 1355 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1356 unsigned int slotid, 1357 unsigned int epid) 1358 { 1359 XHCIEPContext *epctx; 1360 int i; 1361 1362 epctx = g_new0(XHCIEPContext, 1); 1363 epctx->xhci = xhci; 1364 epctx->slotid = slotid; 1365 epctx->epid = epid; 1366 1367 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1368 epctx->transfers[i].xhci = xhci; 1369 epctx->transfers[i].slotid = slotid; 1370 epctx->transfers[i].epid = epid; 1371 usb_packet_init(&epctx->transfers[i].packet); 1372 } 1373 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1374 1375 return epctx; 1376 } 1377 1378 static void xhci_init_epctx(XHCIEPContext *epctx, 1379 dma_addr_t pctx, uint32_t *ctx) 1380 { 1381 dma_addr_t dequeue; 1382 1383 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1384 1385 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1386 epctx->pctx = pctx; 1387 epctx->max_psize = ctx[1]>>16; 1388 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1389 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1390 epctx->lsa = (ctx[0] >> 15) & 1; 1391 if (epctx->max_pstreams) { 1392 xhci_alloc_streams(epctx, dequeue); 1393 } else { 1394 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1395 epctx->ring.ccs = ctx[2] & 1; 1396 } 1397 1398 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1399 } 1400 1401 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1402 unsigned int epid, dma_addr_t pctx, 1403 uint32_t *ctx) 1404 { 1405 XHCISlot *slot; 1406 XHCIEPContext *epctx; 1407 1408 trace_usb_xhci_ep_enable(slotid, epid); 1409 assert(slotid >= 1 && slotid <= xhci->numslots); 1410 assert(epid >= 1 && epid <= 31); 1411 1412 slot = &xhci->slots[slotid-1]; 1413 if (slot->eps[epid-1]) { 1414 xhci_disable_ep(xhci, slotid, epid); 1415 } 1416 1417 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1418 slot->eps[epid-1] = epctx; 1419 xhci_init_epctx(epctx, pctx, ctx); 1420 1421 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1422 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1423 1424 epctx->mfindex_last = 0; 1425 1426 epctx->state = EP_RUNNING; 1427 ctx[0] &= ~EP_STATE_MASK; 1428 ctx[0] |= EP_RUNNING; 1429 1430 return CC_SUCCESS; 1431 } 1432 1433 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1434 { 1435 int killed = 0; 1436 1437 if (report && (t->running_async || t->running_retry)) { 1438 t->status = report; 1439 xhci_xfer_report(t); 1440 } 1441 1442 if (t->running_async) { 1443 usb_cancel_packet(&t->packet); 1444 t->running_async = 0; 1445 killed = 1; 1446 } 1447 if (t->running_retry) { 1448 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1449 if (epctx) { 1450 epctx->retry = NULL; 1451 timer_del(epctx->kick_timer); 1452 } 1453 t->running_retry = 0; 1454 killed = 1; 1455 } 1456 if (t->trbs) { 1457 g_free(t->trbs); 1458 } 1459 1460 t->trbs = NULL; 1461 t->trb_count = t->trb_alloced = 0; 1462 1463 return killed; 1464 } 1465 1466 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1467 unsigned int epid, TRBCCode report) 1468 { 1469 XHCISlot *slot; 1470 XHCIEPContext *epctx; 1471 int i, xferi, killed = 0; 1472 USBEndpoint *ep = NULL; 1473 assert(slotid >= 1 && slotid <= xhci->numslots); 1474 assert(epid >= 1 && epid <= 31); 1475 1476 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1477 1478 slot = &xhci->slots[slotid-1]; 1479 1480 if (!slot->eps[epid-1]) { 1481 return 0; 1482 } 1483 1484 epctx = slot->eps[epid-1]; 1485 1486 xferi = epctx->next_xfer; 1487 for (i = 0; i < TD_QUEUE; i++) { 1488 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report); 1489 if (killed) { 1490 report = 0; /* Only report once */ 1491 } 1492 epctx->transfers[xferi].packet.ep = NULL; 1493 xferi = (xferi + 1) % TD_QUEUE; 1494 } 1495 1496 ep = xhci_epid_to_usbep(xhci, slotid, epid); 1497 if (ep) { 1498 usb_device_ep_stopped(ep->dev, ep); 1499 } 1500 return killed; 1501 } 1502 1503 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1504 unsigned int epid) 1505 { 1506 XHCISlot *slot; 1507 XHCIEPContext *epctx; 1508 int i; 1509 1510 trace_usb_xhci_ep_disable(slotid, epid); 1511 assert(slotid >= 1 && slotid <= xhci->numslots); 1512 assert(epid >= 1 && epid <= 31); 1513 1514 slot = &xhci->slots[slotid-1]; 1515 1516 if (!slot->eps[epid-1]) { 1517 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1518 return CC_SUCCESS; 1519 } 1520 1521 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1522 1523 epctx = slot->eps[epid-1]; 1524 1525 if (epctx->nr_pstreams) { 1526 xhci_free_streams(epctx); 1527 } 1528 1529 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1530 usb_packet_cleanup(&epctx->transfers[i].packet); 1531 } 1532 1533 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1534 1535 timer_free(epctx->kick_timer); 1536 g_free(epctx); 1537 slot->eps[epid-1] = NULL; 1538 1539 return CC_SUCCESS; 1540 } 1541 1542 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1543 unsigned int epid) 1544 { 1545 XHCISlot *slot; 1546 XHCIEPContext *epctx; 1547 1548 trace_usb_xhci_ep_stop(slotid, epid); 1549 assert(slotid >= 1 && slotid <= xhci->numslots); 1550 1551 if (epid < 1 || epid > 31) { 1552 DPRINTF("xhci: bad ep %d\n", epid); 1553 return CC_TRB_ERROR; 1554 } 1555 1556 slot = &xhci->slots[slotid-1]; 1557 1558 if (!slot->eps[epid-1]) { 1559 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1560 return CC_EP_NOT_ENABLED_ERROR; 1561 } 1562 1563 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1564 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1565 "data might be lost\n"); 1566 } 1567 1568 epctx = slot->eps[epid-1]; 1569 1570 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1571 1572 if (epctx->nr_pstreams) { 1573 xhci_reset_streams(epctx); 1574 } 1575 1576 return CC_SUCCESS; 1577 } 1578 1579 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1580 unsigned int epid) 1581 { 1582 XHCISlot *slot; 1583 XHCIEPContext *epctx; 1584 1585 trace_usb_xhci_ep_reset(slotid, epid); 1586 assert(slotid >= 1 && slotid <= xhci->numslots); 1587 1588 if (epid < 1 || epid > 31) { 1589 DPRINTF("xhci: bad ep %d\n", epid); 1590 return CC_TRB_ERROR; 1591 } 1592 1593 slot = &xhci->slots[slotid-1]; 1594 1595 if (!slot->eps[epid-1]) { 1596 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1597 return CC_EP_NOT_ENABLED_ERROR; 1598 } 1599 1600 epctx = slot->eps[epid-1]; 1601 1602 if (epctx->state != EP_HALTED) { 1603 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1604 epid, epctx->state); 1605 return CC_CONTEXT_STATE_ERROR; 1606 } 1607 1608 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1609 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1610 "data might be lost\n"); 1611 } 1612 1613 if (!xhci->slots[slotid-1].uport || 1614 !xhci->slots[slotid-1].uport->dev || 1615 !xhci->slots[slotid-1].uport->dev->attached) { 1616 return CC_USB_TRANSACTION_ERROR; 1617 } 1618 1619 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1620 1621 if (epctx->nr_pstreams) { 1622 xhci_reset_streams(epctx); 1623 } 1624 1625 return CC_SUCCESS; 1626 } 1627 1628 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1629 unsigned int epid, unsigned int streamid, 1630 uint64_t pdequeue) 1631 { 1632 XHCISlot *slot; 1633 XHCIEPContext *epctx; 1634 XHCIStreamContext *sctx; 1635 dma_addr_t dequeue; 1636 1637 assert(slotid >= 1 && slotid <= xhci->numslots); 1638 1639 if (epid < 1 || epid > 31) { 1640 DPRINTF("xhci: bad ep %d\n", epid); 1641 return CC_TRB_ERROR; 1642 } 1643 1644 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1645 dequeue = xhci_mask64(pdequeue); 1646 1647 slot = &xhci->slots[slotid-1]; 1648 1649 if (!slot->eps[epid-1]) { 1650 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1651 return CC_EP_NOT_ENABLED_ERROR; 1652 } 1653 1654 epctx = slot->eps[epid-1]; 1655 1656 if (epctx->state != EP_STOPPED) { 1657 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1658 return CC_CONTEXT_STATE_ERROR; 1659 } 1660 1661 if (epctx->nr_pstreams) { 1662 uint32_t err; 1663 sctx = xhci_find_stream(epctx, streamid, &err); 1664 if (sctx == NULL) { 1665 return err; 1666 } 1667 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1668 sctx->ring.ccs = dequeue & 1; 1669 } else { 1670 sctx = NULL; 1671 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1672 epctx->ring.ccs = dequeue & 1; 1673 } 1674 1675 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1676 1677 return CC_SUCCESS; 1678 } 1679 1680 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1681 { 1682 XHCIState *xhci = xfer->xhci; 1683 int i; 1684 1685 xfer->int_req = false; 1686 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1687 for (i = 0; i < xfer->trb_count; i++) { 1688 XHCITRB *trb = &xfer->trbs[i]; 1689 dma_addr_t addr; 1690 unsigned int chunk = 0; 1691 1692 if (trb->control & TRB_TR_IOC) { 1693 xfer->int_req = true; 1694 } 1695 1696 switch (TRB_TYPE(*trb)) { 1697 case TR_DATA: 1698 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1699 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1700 goto err; 1701 } 1702 /* fallthrough */ 1703 case TR_NORMAL: 1704 case TR_ISOCH: 1705 addr = xhci_mask64(trb->parameter); 1706 chunk = trb->status & 0x1ffff; 1707 if (trb->control & TRB_TR_IDT) { 1708 if (chunk > 8 || in_xfer) { 1709 DPRINTF("xhci: invalid immediate data TRB\n"); 1710 goto err; 1711 } 1712 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1713 } else { 1714 qemu_sglist_add(&xfer->sgl, addr, chunk); 1715 } 1716 break; 1717 } 1718 } 1719 1720 return 0; 1721 1722 err: 1723 qemu_sglist_destroy(&xfer->sgl); 1724 xhci_die(xhci); 1725 return -1; 1726 } 1727 1728 static void xhci_xfer_unmap(XHCITransfer *xfer) 1729 { 1730 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1731 qemu_sglist_destroy(&xfer->sgl); 1732 } 1733 1734 static void xhci_xfer_report(XHCITransfer *xfer) 1735 { 1736 uint32_t edtla = 0; 1737 unsigned int left; 1738 bool reported = 0; 1739 bool shortpkt = 0; 1740 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1741 XHCIState *xhci = xfer->xhci; 1742 int i; 1743 1744 left = xfer->packet.actual_length; 1745 1746 for (i = 0; i < xfer->trb_count; i++) { 1747 XHCITRB *trb = &xfer->trbs[i]; 1748 unsigned int chunk = 0; 1749 1750 switch (TRB_TYPE(*trb)) { 1751 case TR_DATA: 1752 case TR_NORMAL: 1753 case TR_ISOCH: 1754 chunk = trb->status & 0x1ffff; 1755 if (chunk > left) { 1756 chunk = left; 1757 if (xfer->status == CC_SUCCESS) { 1758 shortpkt = 1; 1759 } 1760 } 1761 left -= chunk; 1762 edtla += chunk; 1763 break; 1764 case TR_STATUS: 1765 reported = 0; 1766 shortpkt = 0; 1767 break; 1768 } 1769 1770 if (!reported && ((trb->control & TRB_TR_IOC) || 1771 (shortpkt && (trb->control & TRB_TR_ISP)) || 1772 (xfer->status != CC_SUCCESS && left == 0))) { 1773 event.slotid = xfer->slotid; 1774 event.epid = xfer->epid; 1775 event.length = (trb->status & 0x1ffff) - chunk; 1776 event.flags = 0; 1777 event.ptr = trb->addr; 1778 if (xfer->status == CC_SUCCESS) { 1779 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1780 } else { 1781 event.ccode = xfer->status; 1782 } 1783 if (TRB_TYPE(*trb) == TR_EVDATA) { 1784 event.ptr = trb->parameter; 1785 event.flags |= TRB_EV_ED; 1786 event.length = edtla & 0xffffff; 1787 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1788 edtla = 0; 1789 } 1790 xhci_event(xhci, &event, TRB_INTR(*trb)); 1791 reported = 1; 1792 if (xfer->status != CC_SUCCESS) { 1793 return; 1794 } 1795 } 1796 } 1797 } 1798 1799 static void xhci_stall_ep(XHCITransfer *xfer) 1800 { 1801 XHCIState *xhci = xfer->xhci; 1802 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1803 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1804 uint32_t err; 1805 XHCIStreamContext *sctx; 1806 1807 if (epctx->nr_pstreams) { 1808 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1809 if (sctx == NULL) { 1810 return; 1811 } 1812 sctx->ring.dequeue = xfer->trbs[0].addr; 1813 sctx->ring.ccs = xfer->trbs[0].ccs; 1814 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1815 } else { 1816 epctx->ring.dequeue = xfer->trbs[0].addr; 1817 epctx->ring.ccs = xfer->trbs[0].ccs; 1818 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1819 } 1820 } 1821 1822 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1823 XHCIEPContext *epctx); 1824 1825 static int xhci_setup_packet(XHCITransfer *xfer) 1826 { 1827 XHCIState *xhci = xfer->xhci; 1828 USBEndpoint *ep; 1829 int dir; 1830 1831 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1832 1833 if (xfer->packet.ep) { 1834 ep = xfer->packet.ep; 1835 } else { 1836 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); 1837 if (!ep) { 1838 DPRINTF("xhci: slot %d has no device\n", 1839 xfer->slotid); 1840 return -1; 1841 } 1842 } 1843 1844 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1845 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1846 xfer->trbs[0].addr, false, xfer->int_req); 1847 usb_packet_map(&xfer->packet, &xfer->sgl); 1848 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1849 xfer->packet.pid, ep->dev->addr, ep->nr); 1850 return 0; 1851 } 1852 1853 static int xhci_complete_packet(XHCITransfer *xfer) 1854 { 1855 if (xfer->packet.status == USB_RET_ASYNC) { 1856 trace_usb_xhci_xfer_async(xfer); 1857 xfer->running_async = 1; 1858 xfer->running_retry = 0; 1859 xfer->complete = 0; 1860 return 0; 1861 } else if (xfer->packet.status == USB_RET_NAK) { 1862 trace_usb_xhci_xfer_nak(xfer); 1863 xfer->running_async = 0; 1864 xfer->running_retry = 1; 1865 xfer->complete = 0; 1866 return 0; 1867 } else { 1868 xfer->running_async = 0; 1869 xfer->running_retry = 0; 1870 xfer->complete = 1; 1871 xhci_xfer_unmap(xfer); 1872 } 1873 1874 if (xfer->packet.status == USB_RET_SUCCESS) { 1875 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1876 xfer->status = CC_SUCCESS; 1877 xhci_xfer_report(xfer); 1878 return 0; 1879 } 1880 1881 /* error */ 1882 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1883 switch (xfer->packet.status) { 1884 case USB_RET_NODEV: 1885 case USB_RET_IOERROR: 1886 xfer->status = CC_USB_TRANSACTION_ERROR; 1887 xhci_xfer_report(xfer); 1888 xhci_stall_ep(xfer); 1889 break; 1890 case USB_RET_STALL: 1891 xfer->status = CC_STALL_ERROR; 1892 xhci_xfer_report(xfer); 1893 xhci_stall_ep(xfer); 1894 break; 1895 case USB_RET_BABBLE: 1896 xfer->status = CC_BABBLE_DETECTED; 1897 xhci_xfer_report(xfer); 1898 xhci_stall_ep(xfer); 1899 break; 1900 default: 1901 DPRINTF("%s: FIXME: status = %d\n", __func__, 1902 xfer->packet.status); 1903 FIXME("unhandled USB_RET_*"); 1904 } 1905 return 0; 1906 } 1907 1908 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1909 { 1910 XHCITRB *trb_setup, *trb_status; 1911 uint8_t bmRequestType; 1912 1913 trb_setup = &xfer->trbs[0]; 1914 trb_status = &xfer->trbs[xfer->trb_count-1]; 1915 1916 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1917 1918 /* at most one Event Data TRB allowed after STATUS */ 1919 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1920 trb_status--; 1921 } 1922 1923 /* do some sanity checks */ 1924 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1925 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1926 TRB_TYPE(*trb_setup)); 1927 return -1; 1928 } 1929 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1930 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1931 TRB_TYPE(*trb_status)); 1932 return -1; 1933 } 1934 if (!(trb_setup->control & TRB_TR_IDT)) { 1935 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1936 return -1; 1937 } 1938 if ((trb_setup->status & 0x1ffff) != 8) { 1939 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1940 (trb_setup->status & 0x1ffff)); 1941 return -1; 1942 } 1943 1944 bmRequestType = trb_setup->parameter; 1945 1946 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1947 xfer->iso_xfer = false; 1948 xfer->timed_xfer = false; 1949 1950 if (xhci_setup_packet(xfer) < 0) { 1951 return -1; 1952 } 1953 xfer->packet.parameter = trb_setup->parameter; 1954 1955 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1956 1957 xhci_complete_packet(xfer); 1958 if (!xfer->running_async && !xfer->running_retry) { 1959 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1960 } 1961 return 0; 1962 } 1963 1964 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1965 XHCIEPContext *epctx, uint64_t mfindex) 1966 { 1967 uint64_t asap = ((mfindex + epctx->interval - 1) & 1968 ~(epctx->interval-1)); 1969 uint64_t kick = epctx->mfindex_last + epctx->interval; 1970 1971 assert(epctx->interval != 0); 1972 xfer->mfindex_kick = MAX(asap, kick); 1973 } 1974 1975 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1976 XHCIEPContext *epctx, uint64_t mfindex) 1977 { 1978 if (xfer->trbs[0].control & TRB_TR_SIA) { 1979 uint64_t asap = ((mfindex + epctx->interval - 1) & 1980 ~(epctx->interval-1)); 1981 if (asap >= epctx->mfindex_last && 1982 asap <= epctx->mfindex_last + epctx->interval * 4) { 1983 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1984 } else { 1985 xfer->mfindex_kick = asap; 1986 } 1987 } else { 1988 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1989 & TRB_TR_FRAMEID_MASK) << 3; 1990 xfer->mfindex_kick |= mfindex & ~0x3fff; 1991 if (xfer->mfindex_kick + 0x100 < mfindex) { 1992 xfer->mfindex_kick += 0x4000; 1993 } 1994 } 1995 } 1996 1997 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1998 XHCIEPContext *epctx, uint64_t mfindex) 1999 { 2000 if (xfer->mfindex_kick > mfindex) { 2001 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2002 (xfer->mfindex_kick - mfindex) * 125000); 2003 xfer->running_retry = 1; 2004 } else { 2005 epctx->mfindex_last = xfer->mfindex_kick; 2006 timer_del(epctx->kick_timer); 2007 xfer->running_retry = 0; 2008 } 2009 } 2010 2011 2012 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2013 { 2014 uint64_t mfindex; 2015 2016 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 2017 2018 xfer->in_xfer = epctx->type>>2; 2019 2020 switch(epctx->type) { 2021 case ET_INTR_OUT: 2022 case ET_INTR_IN: 2023 xfer->pkts = 0; 2024 xfer->iso_xfer = false; 2025 xfer->timed_xfer = true; 2026 mfindex = xhci_mfindex_get(xhci); 2027 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 2028 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2029 if (xfer->running_retry) { 2030 return -1; 2031 } 2032 break; 2033 case ET_BULK_OUT: 2034 case ET_BULK_IN: 2035 xfer->pkts = 0; 2036 xfer->iso_xfer = false; 2037 xfer->timed_xfer = false; 2038 break; 2039 case ET_ISO_OUT: 2040 case ET_ISO_IN: 2041 xfer->pkts = 1; 2042 xfer->iso_xfer = true; 2043 xfer->timed_xfer = true; 2044 mfindex = xhci_mfindex_get(xhci); 2045 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 2046 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2047 if (xfer->running_retry) { 2048 return -1; 2049 } 2050 break; 2051 default: 2052 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 2053 return -1; 2054 } 2055 2056 if (xhci_setup_packet(xfer) < 0) { 2057 return -1; 2058 } 2059 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2060 2061 xhci_complete_packet(xfer); 2062 if (!xfer->running_async && !xfer->running_retry) { 2063 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 2064 } 2065 return 0; 2066 } 2067 2068 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2069 { 2070 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 2071 return xhci_submit(xhci, xfer, epctx); 2072 } 2073 2074 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 2075 unsigned int epid, unsigned int streamid) 2076 { 2077 XHCIStreamContext *stctx; 2078 XHCIEPContext *epctx; 2079 XHCIRing *ring; 2080 USBEndpoint *ep = NULL; 2081 uint64_t mfindex; 2082 int length; 2083 int i; 2084 2085 trace_usb_xhci_ep_kick(slotid, epid, streamid); 2086 assert(slotid >= 1 && slotid <= xhci->numslots); 2087 assert(epid >= 1 && epid <= 31); 2088 2089 if (!xhci->slots[slotid-1].enabled) { 2090 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 2091 return; 2092 } 2093 epctx = xhci->slots[slotid-1].eps[epid-1]; 2094 if (!epctx) { 2095 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 2096 epid, slotid); 2097 return; 2098 } 2099 2100 /* If the device has been detached, but the guest has not noticed this 2101 yet the 2 above checks will succeed, but we must NOT continue */ 2102 if (!xhci->slots[slotid - 1].uport || 2103 !xhci->slots[slotid - 1].uport->dev || 2104 !xhci->slots[slotid - 1].uport->dev->attached) { 2105 return; 2106 } 2107 2108 if (epctx->retry) { 2109 XHCITransfer *xfer = epctx->retry; 2110 2111 trace_usb_xhci_xfer_retry(xfer); 2112 assert(xfer->running_retry); 2113 if (xfer->timed_xfer) { 2114 /* time to kick the transfer? */ 2115 mfindex = xhci_mfindex_get(xhci); 2116 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2117 if (xfer->running_retry) { 2118 return; 2119 } 2120 xfer->timed_xfer = 0; 2121 xfer->running_retry = 1; 2122 } 2123 if (xfer->iso_xfer) { 2124 /* retry iso transfer */ 2125 if (xhci_setup_packet(xfer) < 0) { 2126 return; 2127 } 2128 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2129 assert(xfer->packet.status != USB_RET_NAK); 2130 xhci_complete_packet(xfer); 2131 } else { 2132 /* retry nak'ed transfer */ 2133 if (xhci_setup_packet(xfer) < 0) { 2134 return; 2135 } 2136 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2137 if (xfer->packet.status == USB_RET_NAK) { 2138 return; 2139 } 2140 xhci_complete_packet(xfer); 2141 } 2142 assert(!xfer->running_retry); 2143 epctx->retry = NULL; 2144 } 2145 2146 if (epctx->state == EP_HALTED) { 2147 DPRINTF("xhci: ep halted, not running schedule\n"); 2148 return; 2149 } 2150 2151 2152 if (epctx->nr_pstreams) { 2153 uint32_t err; 2154 stctx = xhci_find_stream(epctx, streamid, &err); 2155 if (stctx == NULL) { 2156 return; 2157 } 2158 ring = &stctx->ring; 2159 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2160 } else { 2161 ring = &epctx->ring; 2162 streamid = 0; 2163 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2164 } 2165 assert(ring->dequeue != 0); 2166 2167 while (1) { 2168 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 2169 if (xfer->running_async || xfer->running_retry) { 2170 break; 2171 } 2172 length = xhci_ring_chain_length(xhci, ring); 2173 if (length < 0) { 2174 break; 2175 } else if (length == 0) { 2176 break; 2177 } 2178 if (xfer->trbs && xfer->trb_alloced < length) { 2179 xfer->trb_count = 0; 2180 xfer->trb_alloced = 0; 2181 g_free(xfer->trbs); 2182 xfer->trbs = NULL; 2183 } 2184 if (!xfer->trbs) { 2185 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 2186 xfer->trb_alloced = length; 2187 } 2188 xfer->trb_count = length; 2189 2190 for (i = 0; i < length; i++) { 2191 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2192 } 2193 xfer->streamid = streamid; 2194 2195 if (epid == 1) { 2196 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2197 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2198 ep = xfer->packet.ep; 2199 } else { 2200 DPRINTF("xhci: error firing CTL transfer\n"); 2201 } 2202 } else { 2203 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2204 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2205 } else { 2206 if (!xfer->timed_xfer) { 2207 DPRINTF("xhci: error firing data transfer\n"); 2208 } 2209 } 2210 } 2211 2212 if (epctx->state == EP_HALTED) { 2213 break; 2214 } 2215 if (xfer->running_retry) { 2216 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2217 epctx->retry = xfer; 2218 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2219 epctx->interval * 125000); 2220 break; 2221 } 2222 } 2223 2224 ep = xhci_epid_to_usbep(xhci, slotid, epid); 2225 if (ep) { 2226 usb_device_flush_ep_queue(ep->dev, ep); 2227 } 2228 } 2229 2230 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2231 { 2232 trace_usb_xhci_slot_enable(slotid); 2233 assert(slotid >= 1 && slotid <= xhci->numslots); 2234 xhci->slots[slotid-1].enabled = 1; 2235 xhci->slots[slotid-1].uport = NULL; 2236 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2237 2238 return CC_SUCCESS; 2239 } 2240 2241 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2242 { 2243 int i; 2244 2245 trace_usb_xhci_slot_disable(slotid); 2246 assert(slotid >= 1 && slotid <= xhci->numslots); 2247 2248 for (i = 1; i <= 31; i++) { 2249 if (xhci->slots[slotid-1].eps[i-1]) { 2250 xhci_disable_ep(xhci, slotid, i); 2251 } 2252 } 2253 2254 xhci->slots[slotid-1].enabled = 0; 2255 xhci->slots[slotid-1].addressed = 0; 2256 xhci->slots[slotid-1].uport = NULL; 2257 return CC_SUCCESS; 2258 } 2259 2260 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2261 { 2262 USBPort *uport; 2263 char path[32]; 2264 int i, pos, port; 2265 2266 port = (slot_ctx[1]>>16) & 0xFF; 2267 if (port < 1 || port > xhci->numports) { 2268 return NULL; 2269 } 2270 port = xhci->ports[port-1].uport->index+1; 2271 pos = snprintf(path, sizeof(path), "%d", port); 2272 for (i = 0; i < 5; i++) { 2273 port = (slot_ctx[0] >> 4*i) & 0x0f; 2274 if (!port) { 2275 break; 2276 } 2277 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2278 } 2279 2280 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2281 if (strcmp(uport->path, path) == 0) { 2282 return uport; 2283 } 2284 } 2285 return NULL; 2286 } 2287 2288 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2289 uint64_t pictx, bool bsr) 2290 { 2291 XHCISlot *slot; 2292 USBPort *uport; 2293 USBDevice *dev; 2294 dma_addr_t ictx, octx, dcbaap; 2295 uint64_t poctx; 2296 uint32_t ictl_ctx[2]; 2297 uint32_t slot_ctx[4]; 2298 uint32_t ep0_ctx[5]; 2299 int i; 2300 TRBCCode res; 2301 2302 assert(slotid >= 1 && slotid <= xhci->numslots); 2303 2304 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2305 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2306 ictx = xhci_mask64(pictx); 2307 octx = xhci_mask64(poctx); 2308 2309 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2310 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2311 2312 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2313 2314 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2315 DPRINTF("xhci: invalid input context control %08x %08x\n", 2316 ictl_ctx[0], ictl_ctx[1]); 2317 return CC_TRB_ERROR; 2318 } 2319 2320 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2321 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2322 2323 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2324 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2325 2326 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2327 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2328 2329 uport = xhci_lookup_uport(xhci, slot_ctx); 2330 if (uport == NULL) { 2331 DPRINTF("xhci: port not found\n"); 2332 return CC_TRB_ERROR; 2333 } 2334 trace_usb_xhci_slot_address(slotid, uport->path); 2335 2336 dev = uport->dev; 2337 if (!dev || !dev->attached) { 2338 DPRINTF("xhci: port %s not connected\n", uport->path); 2339 return CC_USB_TRANSACTION_ERROR; 2340 } 2341 2342 for (i = 0; i < xhci->numslots; i++) { 2343 if (i == slotid-1) { 2344 continue; 2345 } 2346 if (xhci->slots[i].uport == uport) { 2347 DPRINTF("xhci: port %s already assigned to slot %d\n", 2348 uport->path, i+1); 2349 return CC_TRB_ERROR; 2350 } 2351 } 2352 2353 slot = &xhci->slots[slotid-1]; 2354 slot->uport = uport; 2355 slot->ctx = octx; 2356 2357 if (bsr) { 2358 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2359 } else { 2360 USBPacket p; 2361 uint8_t buf[1]; 2362 2363 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2364 usb_device_reset(dev); 2365 memset(&p, 0, sizeof(p)); 2366 usb_packet_addbuf(&p, buf, sizeof(buf)); 2367 usb_packet_setup(&p, USB_TOKEN_OUT, 2368 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2369 0, false, false); 2370 usb_device_handle_control(dev, &p, 2371 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2372 slotid, 0, 0, NULL); 2373 assert(p.status != USB_RET_ASYNC); 2374 } 2375 2376 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2377 2378 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2379 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2380 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2381 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2382 2383 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2384 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2385 2386 xhci->slots[slotid-1].addressed = 1; 2387 return res; 2388 } 2389 2390 2391 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2392 uint64_t pictx, bool dc) 2393 { 2394 dma_addr_t ictx, octx; 2395 uint32_t ictl_ctx[2]; 2396 uint32_t slot_ctx[4]; 2397 uint32_t islot_ctx[4]; 2398 uint32_t ep_ctx[5]; 2399 int i; 2400 TRBCCode res; 2401 2402 trace_usb_xhci_slot_configure(slotid); 2403 assert(slotid >= 1 && slotid <= xhci->numslots); 2404 2405 ictx = xhci_mask64(pictx); 2406 octx = xhci->slots[slotid-1].ctx; 2407 2408 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2409 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2410 2411 if (dc) { 2412 for (i = 2; i <= 31; i++) { 2413 if (xhci->slots[slotid-1].eps[i-1]) { 2414 xhci_disable_ep(xhci, slotid, i); 2415 } 2416 } 2417 2418 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2419 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2420 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2421 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2422 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2423 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2424 2425 return CC_SUCCESS; 2426 } 2427 2428 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2429 2430 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2431 DPRINTF("xhci: invalid input context control %08x %08x\n", 2432 ictl_ctx[0], ictl_ctx[1]); 2433 return CC_TRB_ERROR; 2434 } 2435 2436 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2437 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2438 2439 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2440 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2441 return CC_CONTEXT_STATE_ERROR; 2442 } 2443 2444 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2445 2446 for (i = 2; i <= 31; i++) { 2447 if (ictl_ctx[0] & (1<<i)) { 2448 xhci_disable_ep(xhci, slotid, i); 2449 } 2450 if (ictl_ctx[1] & (1<<i)) { 2451 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2452 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2453 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2454 ep_ctx[3], ep_ctx[4]); 2455 xhci_disable_ep(xhci, slotid, i); 2456 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2457 if (res != CC_SUCCESS) { 2458 return res; 2459 } 2460 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2461 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2462 ep_ctx[3], ep_ctx[4]); 2463 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2464 } 2465 } 2466 2467 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2468 if (res != CC_SUCCESS) { 2469 for (i = 2; i <= 31; i++) { 2470 if (ictl_ctx[1] & (1u << i)) { 2471 xhci_disable_ep(xhci, slotid, i); 2472 } 2473 } 2474 return res; 2475 } 2476 2477 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2478 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2479 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2480 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2481 SLOT_CONTEXT_ENTRIES_SHIFT); 2482 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2483 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2484 2485 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2486 2487 return CC_SUCCESS; 2488 } 2489 2490 2491 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2492 uint64_t pictx) 2493 { 2494 dma_addr_t ictx, octx; 2495 uint32_t ictl_ctx[2]; 2496 uint32_t iep0_ctx[5]; 2497 uint32_t ep0_ctx[5]; 2498 uint32_t islot_ctx[4]; 2499 uint32_t slot_ctx[4]; 2500 2501 trace_usb_xhci_slot_evaluate(slotid); 2502 assert(slotid >= 1 && slotid <= xhci->numslots); 2503 2504 ictx = xhci_mask64(pictx); 2505 octx = xhci->slots[slotid-1].ctx; 2506 2507 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2508 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2509 2510 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2511 2512 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2513 DPRINTF("xhci: invalid input context control %08x %08x\n", 2514 ictl_ctx[0], ictl_ctx[1]); 2515 return CC_TRB_ERROR; 2516 } 2517 2518 if (ictl_ctx[1] & 0x1) { 2519 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2520 2521 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2522 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2523 2524 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2525 2526 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2527 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2528 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2529 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2530 2531 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2532 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2533 2534 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2535 } 2536 2537 if (ictl_ctx[1] & 0x2) { 2538 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2539 2540 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2541 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2542 iep0_ctx[3], iep0_ctx[4]); 2543 2544 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2545 2546 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2547 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2548 2549 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2550 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2551 2552 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2553 } 2554 2555 return CC_SUCCESS; 2556 } 2557 2558 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2559 { 2560 uint32_t slot_ctx[4]; 2561 dma_addr_t octx; 2562 int i; 2563 2564 trace_usb_xhci_slot_reset(slotid); 2565 assert(slotid >= 1 && slotid <= xhci->numslots); 2566 2567 octx = xhci->slots[slotid-1].ctx; 2568 2569 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2570 2571 for (i = 2; i <= 31; i++) { 2572 if (xhci->slots[slotid-1].eps[i-1]) { 2573 xhci_disable_ep(xhci, slotid, i); 2574 } 2575 } 2576 2577 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2578 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2579 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2580 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2581 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2582 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2583 2584 return CC_SUCCESS; 2585 } 2586 2587 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2588 { 2589 unsigned int slotid; 2590 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2591 if (slotid < 1 || slotid > xhci->numslots) { 2592 DPRINTF("xhci: bad slot id %d\n", slotid); 2593 event->ccode = CC_TRB_ERROR; 2594 return 0; 2595 } else if (!xhci->slots[slotid-1].enabled) { 2596 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2597 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2598 return 0; 2599 } 2600 return slotid; 2601 } 2602 2603 /* cleanup slot state on usb device detach */ 2604 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2605 { 2606 int slot, ep; 2607 2608 for (slot = 0; slot < xhci->numslots; slot++) { 2609 if (xhci->slots[slot].uport == uport) { 2610 break; 2611 } 2612 } 2613 if (slot == xhci->numslots) { 2614 return; 2615 } 2616 2617 for (ep = 0; ep < 31; ep++) { 2618 if (xhci->slots[slot].eps[ep]) { 2619 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2620 } 2621 } 2622 xhci->slots[slot].uport = NULL; 2623 } 2624 2625 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2626 { 2627 dma_addr_t ctx; 2628 uint8_t bw_ctx[xhci->numports+1]; 2629 2630 DPRINTF("xhci_get_port_bandwidth()\n"); 2631 2632 ctx = xhci_mask64(pctx); 2633 2634 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2635 2636 /* TODO: actually implement real values here */ 2637 bw_ctx[0] = 0; 2638 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2639 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2640 2641 return CC_SUCCESS; 2642 } 2643 2644 static uint32_t rotl(uint32_t v, unsigned count) 2645 { 2646 count &= 31; 2647 return (v << count) | (v >> (32 - count)); 2648 } 2649 2650 2651 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2652 { 2653 uint32_t val; 2654 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2655 val += rotl(lo + 0x49434878, hi & 0x1F); 2656 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2657 return ~val; 2658 } 2659 2660 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2661 { 2662 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2663 uint32_t buf[8]; 2664 uint32_t obuf[8]; 2665 dma_addr_t paddr = xhci_mask64(addr); 2666 2667 pci_dma_read(pci_dev, paddr, &buf, 32); 2668 2669 memcpy(obuf, buf, sizeof(obuf)); 2670 2671 if ((buf[0] & 0xff) == 2) { 2672 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2673 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2674 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2675 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2676 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2677 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2678 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2679 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2680 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2681 } 2682 2683 pci_dma_write(pci_dev, paddr, &obuf, 32); 2684 } 2685 2686 static void xhci_process_commands(XHCIState *xhci) 2687 { 2688 XHCITRB trb; 2689 TRBType type; 2690 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2691 dma_addr_t addr; 2692 unsigned int i, slotid = 0; 2693 2694 DPRINTF("xhci_process_commands()\n"); 2695 if (!xhci_running(xhci)) { 2696 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2697 return; 2698 } 2699 2700 xhci->crcr_low |= CRCR_CRR; 2701 2702 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2703 event.ptr = addr; 2704 switch (type) { 2705 case CR_ENABLE_SLOT: 2706 for (i = 0; i < xhci->numslots; i++) { 2707 if (!xhci->slots[i].enabled) { 2708 break; 2709 } 2710 } 2711 if (i >= xhci->numslots) { 2712 DPRINTF("xhci: no device slots available\n"); 2713 event.ccode = CC_NO_SLOTS_ERROR; 2714 } else { 2715 slotid = i+1; 2716 event.ccode = xhci_enable_slot(xhci, slotid); 2717 } 2718 break; 2719 case CR_DISABLE_SLOT: 2720 slotid = xhci_get_slot(xhci, &event, &trb); 2721 if (slotid) { 2722 event.ccode = xhci_disable_slot(xhci, slotid); 2723 } 2724 break; 2725 case CR_ADDRESS_DEVICE: 2726 slotid = xhci_get_slot(xhci, &event, &trb); 2727 if (slotid) { 2728 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2729 trb.control & TRB_CR_BSR); 2730 } 2731 break; 2732 case CR_CONFIGURE_ENDPOINT: 2733 slotid = xhci_get_slot(xhci, &event, &trb); 2734 if (slotid) { 2735 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2736 trb.control & TRB_CR_DC); 2737 } 2738 break; 2739 case CR_EVALUATE_CONTEXT: 2740 slotid = xhci_get_slot(xhci, &event, &trb); 2741 if (slotid) { 2742 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2743 } 2744 break; 2745 case CR_STOP_ENDPOINT: 2746 slotid = xhci_get_slot(xhci, &event, &trb); 2747 if (slotid) { 2748 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2749 & TRB_CR_EPID_MASK; 2750 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2751 } 2752 break; 2753 case CR_RESET_ENDPOINT: 2754 slotid = xhci_get_slot(xhci, &event, &trb); 2755 if (slotid) { 2756 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2757 & TRB_CR_EPID_MASK; 2758 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2759 } 2760 break; 2761 case CR_SET_TR_DEQUEUE: 2762 slotid = xhci_get_slot(xhci, &event, &trb); 2763 if (slotid) { 2764 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2765 & TRB_CR_EPID_MASK; 2766 unsigned int streamid = (trb.status >> 16) & 0xffff; 2767 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2768 epid, streamid, 2769 trb.parameter); 2770 } 2771 break; 2772 case CR_RESET_DEVICE: 2773 slotid = xhci_get_slot(xhci, &event, &trb); 2774 if (slotid) { 2775 event.ccode = xhci_reset_slot(xhci, slotid); 2776 } 2777 break; 2778 case CR_GET_PORT_BANDWIDTH: 2779 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2780 break; 2781 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2782 xhci_via_challenge(xhci, trb.parameter); 2783 break; 2784 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2785 event.type = 48; /* NEC reply */ 2786 event.length = 0x3025; 2787 break; 2788 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2789 { 2790 uint32_t chi = trb.parameter >> 32; 2791 uint32_t clo = trb.parameter; 2792 uint32_t val = xhci_nec_challenge(chi, clo); 2793 event.length = val & 0xFFFF; 2794 event.epid = val >> 16; 2795 slotid = val >> 24; 2796 event.type = 48; /* NEC reply */ 2797 } 2798 break; 2799 default: 2800 trace_usb_xhci_unimplemented("command", type); 2801 event.ccode = CC_TRB_ERROR; 2802 break; 2803 } 2804 event.slotid = slotid; 2805 xhci_event(xhci, &event, 0); 2806 } 2807 } 2808 2809 static bool xhci_port_have_device(XHCIPort *port) 2810 { 2811 if (!port->uport->dev || !port->uport->dev->attached) { 2812 return false; /* no device present */ 2813 } 2814 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2815 return false; /* speed mismatch */ 2816 } 2817 return true; 2818 } 2819 2820 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2821 { 2822 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2823 port->portnr << 24 }; 2824 2825 if ((port->portsc & bits) == bits) { 2826 return; 2827 } 2828 trace_usb_xhci_port_notify(port->portnr, bits); 2829 port->portsc |= bits; 2830 if (!xhci_running(port->xhci)) { 2831 return; 2832 } 2833 xhci_event(port->xhci, &ev, 0); 2834 } 2835 2836 static void xhci_port_update(XHCIPort *port, int is_detach) 2837 { 2838 uint32_t pls = PLS_RX_DETECT; 2839 2840 port->portsc = PORTSC_PP; 2841 if (!is_detach && xhci_port_have_device(port)) { 2842 port->portsc |= PORTSC_CCS; 2843 switch (port->uport->dev->speed) { 2844 case USB_SPEED_LOW: 2845 port->portsc |= PORTSC_SPEED_LOW; 2846 pls = PLS_POLLING; 2847 break; 2848 case USB_SPEED_FULL: 2849 port->portsc |= PORTSC_SPEED_FULL; 2850 pls = PLS_POLLING; 2851 break; 2852 case USB_SPEED_HIGH: 2853 port->portsc |= PORTSC_SPEED_HIGH; 2854 pls = PLS_POLLING; 2855 break; 2856 case USB_SPEED_SUPER: 2857 port->portsc |= PORTSC_SPEED_SUPER; 2858 port->portsc |= PORTSC_PED; 2859 pls = PLS_U0; 2860 break; 2861 } 2862 } 2863 set_field(&port->portsc, pls, PORTSC_PLS); 2864 trace_usb_xhci_port_link(port->portnr, pls); 2865 xhci_port_notify(port, PORTSC_CSC); 2866 } 2867 2868 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2869 { 2870 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2871 2872 if (!xhci_port_have_device(port)) { 2873 return; 2874 } 2875 2876 usb_device_reset(port->uport->dev); 2877 2878 switch (port->uport->dev->speed) { 2879 case USB_SPEED_SUPER: 2880 if (warm_reset) { 2881 port->portsc |= PORTSC_WRC; 2882 } 2883 /* fall through */ 2884 case USB_SPEED_LOW: 2885 case USB_SPEED_FULL: 2886 case USB_SPEED_HIGH: 2887 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2888 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2889 port->portsc |= PORTSC_PED; 2890 break; 2891 } 2892 2893 port->portsc &= ~PORTSC_PR; 2894 xhci_port_notify(port, PORTSC_PRC); 2895 } 2896 2897 static void xhci_reset(DeviceState *dev) 2898 { 2899 XHCIState *xhci = XHCI(dev); 2900 int i; 2901 2902 trace_usb_xhci_reset(); 2903 if (!(xhci->usbsts & USBSTS_HCH)) { 2904 DPRINTF("xhci: reset while running!\n"); 2905 } 2906 2907 xhci->usbcmd = 0; 2908 xhci->usbsts = USBSTS_HCH; 2909 xhci->dnctrl = 0; 2910 xhci->crcr_low = 0; 2911 xhci->crcr_high = 0; 2912 xhci->dcbaap_low = 0; 2913 xhci->dcbaap_high = 0; 2914 xhci->config = 0; 2915 2916 for (i = 0; i < xhci->numslots; i++) { 2917 xhci_disable_slot(xhci, i+1); 2918 } 2919 2920 for (i = 0; i < xhci->numports; i++) { 2921 xhci_port_update(xhci->ports + i, 0); 2922 } 2923 2924 for (i = 0; i < xhci->numintrs; i++) { 2925 xhci->intr[i].iman = 0; 2926 xhci->intr[i].imod = 0; 2927 xhci->intr[i].erstsz = 0; 2928 xhci->intr[i].erstba_low = 0; 2929 xhci->intr[i].erstba_high = 0; 2930 xhci->intr[i].erdp_low = 0; 2931 xhci->intr[i].erdp_high = 0; 2932 xhci->intr[i].msix_used = 0; 2933 2934 xhci->intr[i].er_ep_idx = 0; 2935 xhci->intr[i].er_pcs = 1; 2936 xhci->intr[i].er_full = 0; 2937 xhci->intr[i].ev_buffer_put = 0; 2938 xhci->intr[i].ev_buffer_get = 0; 2939 } 2940 2941 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2942 xhci_mfwrap_update(xhci); 2943 } 2944 2945 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2946 { 2947 XHCIState *xhci = ptr; 2948 uint32_t ret; 2949 2950 switch (reg) { 2951 case 0x00: /* HCIVERSION, CAPLENGTH */ 2952 ret = 0x01000000 | LEN_CAP; 2953 break; 2954 case 0x04: /* HCSPARAMS 1 */ 2955 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2956 | (xhci->numintrs<<8) | xhci->numslots; 2957 break; 2958 case 0x08: /* HCSPARAMS 2 */ 2959 ret = 0x0000000f; 2960 break; 2961 case 0x0c: /* HCSPARAMS 3 */ 2962 ret = 0x00000000; 2963 break; 2964 case 0x10: /* HCCPARAMS */ 2965 if (sizeof(dma_addr_t) == 4) { 2966 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 2967 } else { 2968 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 2969 } 2970 break; 2971 case 0x14: /* DBOFF */ 2972 ret = OFF_DOORBELL; 2973 break; 2974 case 0x18: /* RTSOFF */ 2975 ret = OFF_RUNTIME; 2976 break; 2977 2978 /* extended capabilities */ 2979 case 0x20: /* Supported Protocol:00 */ 2980 ret = 0x02000402; /* USB 2.0 */ 2981 break; 2982 case 0x24: /* Supported Protocol:04 */ 2983 ret = 0x20425355; /* "USB " */ 2984 break; 2985 case 0x28: /* Supported Protocol:08 */ 2986 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2987 ret = (xhci->numports_2<<8) | (xhci->numports_3+1); 2988 } else { 2989 ret = (xhci->numports_2<<8) | 1; 2990 } 2991 break; 2992 case 0x2c: /* Supported Protocol:0c */ 2993 ret = 0x00000000; /* reserved */ 2994 break; 2995 case 0x30: /* Supported Protocol:00 */ 2996 ret = 0x03000002; /* USB 3.0 */ 2997 break; 2998 case 0x34: /* Supported Protocol:04 */ 2999 ret = 0x20425355; /* "USB " */ 3000 break; 3001 case 0x38: /* Supported Protocol:08 */ 3002 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3003 ret = (xhci->numports_3<<8) | 1; 3004 } else { 3005 ret = (xhci->numports_3<<8) | (xhci->numports_2+1); 3006 } 3007 break; 3008 case 0x3c: /* Supported Protocol:0c */ 3009 ret = 0x00000000; /* reserved */ 3010 break; 3011 default: 3012 trace_usb_xhci_unimplemented("cap read", reg); 3013 ret = 0; 3014 } 3015 3016 trace_usb_xhci_cap_read(reg, ret); 3017 return ret; 3018 } 3019 3020 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 3021 { 3022 XHCIPort *port = ptr; 3023 uint32_t ret; 3024 3025 switch (reg) { 3026 case 0x00: /* PORTSC */ 3027 ret = port->portsc; 3028 break; 3029 case 0x04: /* PORTPMSC */ 3030 case 0x08: /* PORTLI */ 3031 ret = 0; 3032 break; 3033 case 0x0c: /* reserved */ 3034 default: 3035 trace_usb_xhci_unimplemented("port read", reg); 3036 ret = 0; 3037 } 3038 3039 trace_usb_xhci_port_read(port->portnr, reg, ret); 3040 return ret; 3041 } 3042 3043 static void xhci_port_write(void *ptr, hwaddr reg, 3044 uint64_t val, unsigned size) 3045 { 3046 XHCIPort *port = ptr; 3047 uint32_t portsc, notify; 3048 3049 trace_usb_xhci_port_write(port->portnr, reg, val); 3050 3051 switch (reg) { 3052 case 0x00: /* PORTSC */ 3053 /* write-1-to-start bits */ 3054 if (val & PORTSC_WPR) { 3055 xhci_port_reset(port, true); 3056 break; 3057 } 3058 if (val & PORTSC_PR) { 3059 xhci_port_reset(port, false); 3060 break; 3061 } 3062 3063 portsc = port->portsc; 3064 notify = 0; 3065 /* write-1-to-clear bits*/ 3066 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 3067 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 3068 if (val & PORTSC_LWS) { 3069 /* overwrite PLS only when LWS=1 */ 3070 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 3071 uint32_t new_pls = get_field(val, PORTSC_PLS); 3072 switch (new_pls) { 3073 case PLS_U0: 3074 if (old_pls != PLS_U0) { 3075 set_field(&portsc, new_pls, PORTSC_PLS); 3076 trace_usb_xhci_port_link(port->portnr, new_pls); 3077 notify = PORTSC_PLC; 3078 } 3079 break; 3080 case PLS_U3: 3081 if (old_pls < PLS_U3) { 3082 set_field(&portsc, new_pls, PORTSC_PLS); 3083 trace_usb_xhci_port_link(port->portnr, new_pls); 3084 } 3085 break; 3086 case PLS_RESUME: 3087 /* windows does this for some reason, don't spam stderr */ 3088 break; 3089 default: 3090 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 3091 __func__, old_pls, new_pls); 3092 break; 3093 } 3094 } 3095 /* read/write bits */ 3096 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 3097 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 3098 port->portsc = portsc; 3099 if (notify) { 3100 xhci_port_notify(port, notify); 3101 } 3102 break; 3103 case 0x04: /* PORTPMSC */ 3104 case 0x08: /* PORTLI */ 3105 default: 3106 trace_usb_xhci_unimplemented("port write", reg); 3107 } 3108 } 3109 3110 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 3111 { 3112 XHCIState *xhci = ptr; 3113 uint32_t ret; 3114 3115 switch (reg) { 3116 case 0x00: /* USBCMD */ 3117 ret = xhci->usbcmd; 3118 break; 3119 case 0x04: /* USBSTS */ 3120 ret = xhci->usbsts; 3121 break; 3122 case 0x08: /* PAGESIZE */ 3123 ret = 1; /* 4KiB */ 3124 break; 3125 case 0x14: /* DNCTRL */ 3126 ret = xhci->dnctrl; 3127 break; 3128 case 0x18: /* CRCR low */ 3129 ret = xhci->crcr_low & ~0xe; 3130 break; 3131 case 0x1c: /* CRCR high */ 3132 ret = xhci->crcr_high; 3133 break; 3134 case 0x30: /* DCBAAP low */ 3135 ret = xhci->dcbaap_low; 3136 break; 3137 case 0x34: /* DCBAAP high */ 3138 ret = xhci->dcbaap_high; 3139 break; 3140 case 0x38: /* CONFIG */ 3141 ret = xhci->config; 3142 break; 3143 default: 3144 trace_usb_xhci_unimplemented("oper read", reg); 3145 ret = 0; 3146 } 3147 3148 trace_usb_xhci_oper_read(reg, ret); 3149 return ret; 3150 } 3151 3152 static void xhci_oper_write(void *ptr, hwaddr reg, 3153 uint64_t val, unsigned size) 3154 { 3155 XHCIState *xhci = ptr; 3156 DeviceState *d = DEVICE(ptr); 3157 3158 trace_usb_xhci_oper_write(reg, val); 3159 3160 switch (reg) { 3161 case 0x00: /* USBCMD */ 3162 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3163 xhci_run(xhci); 3164 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3165 xhci_stop(xhci); 3166 } 3167 if (val & USBCMD_CSS) { 3168 /* save state */ 3169 xhci->usbsts &= ~USBSTS_SRE; 3170 } 3171 if (val & USBCMD_CRS) { 3172 /* restore state */ 3173 xhci->usbsts |= USBSTS_SRE; 3174 } 3175 xhci->usbcmd = val & 0xc0f; 3176 xhci_mfwrap_update(xhci); 3177 if (val & USBCMD_HCRST) { 3178 xhci_reset(d); 3179 } 3180 xhci_intx_update(xhci); 3181 break; 3182 3183 case 0x04: /* USBSTS */ 3184 /* these bits are write-1-to-clear */ 3185 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3186 xhci_intx_update(xhci); 3187 break; 3188 3189 case 0x14: /* DNCTRL */ 3190 xhci->dnctrl = val & 0xffff; 3191 break; 3192 case 0x18: /* CRCR low */ 3193 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3194 break; 3195 case 0x1c: /* CRCR high */ 3196 xhci->crcr_high = val; 3197 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3198 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3199 xhci->crcr_low &= ~CRCR_CRR; 3200 xhci_event(xhci, &event, 0); 3201 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3202 } else { 3203 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3204 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3205 } 3206 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3207 break; 3208 case 0x30: /* DCBAAP low */ 3209 xhci->dcbaap_low = val & 0xffffffc0; 3210 break; 3211 case 0x34: /* DCBAAP high */ 3212 xhci->dcbaap_high = val; 3213 break; 3214 case 0x38: /* CONFIG */ 3215 xhci->config = val & 0xff; 3216 break; 3217 default: 3218 trace_usb_xhci_unimplemented("oper write", reg); 3219 } 3220 } 3221 3222 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3223 unsigned size) 3224 { 3225 XHCIState *xhci = ptr; 3226 uint32_t ret = 0; 3227 3228 if (reg < 0x20) { 3229 switch (reg) { 3230 case 0x00: /* MFINDEX */ 3231 ret = xhci_mfindex_get(xhci) & 0x3fff; 3232 break; 3233 default: 3234 trace_usb_xhci_unimplemented("runtime read", reg); 3235 break; 3236 } 3237 } else { 3238 int v = (reg - 0x20) / 0x20; 3239 XHCIInterrupter *intr = &xhci->intr[v]; 3240 switch (reg & 0x1f) { 3241 case 0x00: /* IMAN */ 3242 ret = intr->iman; 3243 break; 3244 case 0x04: /* IMOD */ 3245 ret = intr->imod; 3246 break; 3247 case 0x08: /* ERSTSZ */ 3248 ret = intr->erstsz; 3249 break; 3250 case 0x10: /* ERSTBA low */ 3251 ret = intr->erstba_low; 3252 break; 3253 case 0x14: /* ERSTBA high */ 3254 ret = intr->erstba_high; 3255 break; 3256 case 0x18: /* ERDP low */ 3257 ret = intr->erdp_low; 3258 break; 3259 case 0x1c: /* ERDP high */ 3260 ret = intr->erdp_high; 3261 break; 3262 } 3263 } 3264 3265 trace_usb_xhci_runtime_read(reg, ret); 3266 return ret; 3267 } 3268 3269 static void xhci_runtime_write(void *ptr, hwaddr reg, 3270 uint64_t val, unsigned size) 3271 { 3272 XHCIState *xhci = ptr; 3273 int v = (reg - 0x20) / 0x20; 3274 XHCIInterrupter *intr = &xhci->intr[v]; 3275 trace_usb_xhci_runtime_write(reg, val); 3276 3277 if (reg < 0x20) { 3278 trace_usb_xhci_unimplemented("runtime write", reg); 3279 return; 3280 } 3281 3282 switch (reg & 0x1f) { 3283 case 0x00: /* IMAN */ 3284 if (val & IMAN_IP) { 3285 intr->iman &= ~IMAN_IP; 3286 } 3287 intr->iman &= ~IMAN_IE; 3288 intr->iman |= val & IMAN_IE; 3289 if (v == 0) { 3290 xhci_intx_update(xhci); 3291 } 3292 xhci_msix_update(xhci, v); 3293 break; 3294 case 0x04: /* IMOD */ 3295 intr->imod = val; 3296 break; 3297 case 0x08: /* ERSTSZ */ 3298 intr->erstsz = val & 0xffff; 3299 break; 3300 case 0x10: /* ERSTBA low */ 3301 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3302 intr->erstba_low = val & 0xffffffc0; */ 3303 intr->erstba_low = val & 0xfffffff0; 3304 break; 3305 case 0x14: /* ERSTBA high */ 3306 intr->erstba_high = val; 3307 xhci_er_reset(xhci, v); 3308 break; 3309 case 0x18: /* ERDP low */ 3310 if (val & ERDP_EHB) { 3311 intr->erdp_low &= ~ERDP_EHB; 3312 } 3313 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3314 break; 3315 case 0x1c: /* ERDP high */ 3316 intr->erdp_high = val; 3317 xhci_events_update(xhci, v); 3318 break; 3319 default: 3320 trace_usb_xhci_unimplemented("oper write", reg); 3321 } 3322 } 3323 3324 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3325 unsigned size) 3326 { 3327 /* doorbells always read as 0 */ 3328 trace_usb_xhci_doorbell_read(reg, 0); 3329 return 0; 3330 } 3331 3332 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3333 uint64_t val, unsigned size) 3334 { 3335 XHCIState *xhci = ptr; 3336 unsigned int epid, streamid; 3337 3338 trace_usb_xhci_doorbell_write(reg, val); 3339 3340 if (!xhci_running(xhci)) { 3341 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3342 return; 3343 } 3344 3345 reg >>= 2; 3346 3347 if (reg == 0) { 3348 if (val == 0) { 3349 xhci_process_commands(xhci); 3350 } else { 3351 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3352 (uint32_t)val); 3353 } 3354 } else { 3355 epid = val & 0xff; 3356 streamid = (val >> 16) & 0xffff; 3357 if (reg > xhci->numslots) { 3358 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3359 } else if (epid > 31) { 3360 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3361 (int)reg, (uint32_t)val); 3362 } else { 3363 xhci_kick_ep(xhci, reg, epid, streamid); 3364 } 3365 } 3366 } 3367 3368 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3369 unsigned width) 3370 { 3371 /* nothing */ 3372 } 3373 3374 static const MemoryRegionOps xhci_cap_ops = { 3375 .read = xhci_cap_read, 3376 .write = xhci_cap_write, 3377 .valid.min_access_size = 1, 3378 .valid.max_access_size = 4, 3379 .impl.min_access_size = 4, 3380 .impl.max_access_size = 4, 3381 .endianness = DEVICE_LITTLE_ENDIAN, 3382 }; 3383 3384 static const MemoryRegionOps xhci_oper_ops = { 3385 .read = xhci_oper_read, 3386 .write = xhci_oper_write, 3387 .valid.min_access_size = 4, 3388 .valid.max_access_size = 4, 3389 .endianness = DEVICE_LITTLE_ENDIAN, 3390 }; 3391 3392 static const MemoryRegionOps xhci_port_ops = { 3393 .read = xhci_port_read, 3394 .write = xhci_port_write, 3395 .valid.min_access_size = 4, 3396 .valid.max_access_size = 4, 3397 .endianness = DEVICE_LITTLE_ENDIAN, 3398 }; 3399 3400 static const MemoryRegionOps xhci_runtime_ops = { 3401 .read = xhci_runtime_read, 3402 .write = xhci_runtime_write, 3403 .valid.min_access_size = 4, 3404 .valid.max_access_size = 4, 3405 .endianness = DEVICE_LITTLE_ENDIAN, 3406 }; 3407 3408 static const MemoryRegionOps xhci_doorbell_ops = { 3409 .read = xhci_doorbell_read, 3410 .write = xhci_doorbell_write, 3411 .valid.min_access_size = 4, 3412 .valid.max_access_size = 4, 3413 .endianness = DEVICE_LITTLE_ENDIAN, 3414 }; 3415 3416 static void xhci_attach(USBPort *usbport) 3417 { 3418 XHCIState *xhci = usbport->opaque; 3419 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3420 3421 xhci_port_update(port, 0); 3422 } 3423 3424 static void xhci_detach(USBPort *usbport) 3425 { 3426 XHCIState *xhci = usbport->opaque; 3427 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3428 3429 xhci_detach_slot(xhci, usbport); 3430 xhci_port_update(port, 1); 3431 } 3432 3433 static void xhci_wakeup(USBPort *usbport) 3434 { 3435 XHCIState *xhci = usbport->opaque; 3436 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3437 3438 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3439 return; 3440 } 3441 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3442 xhci_port_notify(port, PORTSC_PLC); 3443 } 3444 3445 static void xhci_complete(USBPort *port, USBPacket *packet) 3446 { 3447 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3448 3449 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3450 xhci_ep_nuke_one_xfer(xfer, 0); 3451 return; 3452 } 3453 xhci_complete_packet(xfer); 3454 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3455 } 3456 3457 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3458 { 3459 USBBus *bus = usb_bus_from_device(child); 3460 XHCIState *xhci = container_of(bus, XHCIState, bus); 3461 3462 xhci_detach_slot(xhci, child->port); 3463 } 3464 3465 static USBPortOps xhci_uport_ops = { 3466 .attach = xhci_attach, 3467 .detach = xhci_detach, 3468 .wakeup = xhci_wakeup, 3469 .complete = xhci_complete, 3470 .child_detach = xhci_child_detach, 3471 }; 3472 3473 static int xhci_find_epid(USBEndpoint *ep) 3474 { 3475 if (ep->nr == 0) { 3476 return 1; 3477 } 3478 if (ep->pid == USB_TOKEN_IN) { 3479 return ep->nr * 2 + 1; 3480 } else { 3481 return ep->nr * 2; 3482 } 3483 } 3484 3485 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 3486 unsigned int slotid, unsigned int epid) 3487 { 3488 assert(slotid >= 1 && slotid <= xhci->numslots); 3489 3490 if (!xhci->slots[slotid - 1].uport) { 3491 return NULL; 3492 } 3493 3494 return usb_ep_get(xhci->slots[slotid - 1].uport->dev, 3495 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); 3496 } 3497 3498 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3499 unsigned int stream) 3500 { 3501 XHCIState *xhci = container_of(bus, XHCIState, bus); 3502 int slotid; 3503 3504 DPRINTF("%s\n", __func__); 3505 slotid = ep->dev->addr; 3506 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3507 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3508 return; 3509 } 3510 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3511 } 3512 3513 static USBBusOps xhci_bus_ops = { 3514 .wakeup_endpoint = xhci_wakeup_endpoint, 3515 }; 3516 3517 static void usb_xhci_init(XHCIState *xhci) 3518 { 3519 DeviceState *dev = DEVICE(xhci); 3520 XHCIPort *port; 3521 int i, usbports, speedmask; 3522 3523 xhci->usbsts = USBSTS_HCH; 3524 3525 if (xhci->numports_2 > MAXPORTS_2) { 3526 xhci->numports_2 = MAXPORTS_2; 3527 } 3528 if (xhci->numports_3 > MAXPORTS_3) { 3529 xhci->numports_3 = MAXPORTS_3; 3530 } 3531 usbports = MAX(xhci->numports_2, xhci->numports_3); 3532 xhci->numports = xhci->numports_2 + xhci->numports_3; 3533 3534 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3535 3536 for (i = 0; i < usbports; i++) { 3537 speedmask = 0; 3538 if (i < xhci->numports_2) { 3539 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3540 port = &xhci->ports[i + xhci->numports_3]; 3541 port->portnr = i + 1 + xhci->numports_3; 3542 } else { 3543 port = &xhci->ports[i]; 3544 port->portnr = i + 1; 3545 } 3546 port->uport = &xhci->uports[i]; 3547 port->speedmask = 3548 USB_SPEED_MASK_LOW | 3549 USB_SPEED_MASK_FULL | 3550 USB_SPEED_MASK_HIGH; 3551 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3552 speedmask |= port->speedmask; 3553 } 3554 if (i < xhci->numports_3) { 3555 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3556 port = &xhci->ports[i]; 3557 port->portnr = i + 1; 3558 } else { 3559 port = &xhci->ports[i + xhci->numports_2]; 3560 port->portnr = i + 1 + xhci->numports_2; 3561 } 3562 port->uport = &xhci->uports[i]; 3563 port->speedmask = USB_SPEED_MASK_SUPER; 3564 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3565 speedmask |= port->speedmask; 3566 } 3567 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3568 &xhci_uport_ops, speedmask); 3569 } 3570 } 3571 3572 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) 3573 { 3574 int i, ret; 3575 3576 XHCIState *xhci = XHCI(dev); 3577 3578 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3579 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3580 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3581 dev->config[0x60] = 0x30; /* release number */ 3582 3583 usb_xhci_init(xhci); 3584 3585 if (xhci->numintrs > MAXINTRS) { 3586 xhci->numintrs = MAXINTRS; 3587 } 3588 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3589 xhci->numintrs++; 3590 } 3591 if (xhci->numintrs < 1) { 3592 xhci->numintrs = 1; 3593 } 3594 if (xhci->numslots > MAXSLOTS) { 3595 xhci->numslots = MAXSLOTS; 3596 } 3597 if (xhci->numslots < 1) { 3598 xhci->numslots = 1; 3599 } 3600 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3601 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3602 } else { 3603 xhci->max_pstreams_mask = 0; 3604 } 3605 3606 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3607 3608 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3609 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3610 "capabilities", LEN_CAP); 3611 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3612 "operational", 0x400); 3613 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3614 "runtime", LEN_RUNTIME); 3615 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3616 "doorbell", LEN_DOORBELL); 3617 3618 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3619 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3620 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3621 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3622 3623 for (i = 0; i < xhci->numports; i++) { 3624 XHCIPort *port = &xhci->ports[i]; 3625 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3626 port->xhci = xhci; 3627 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3628 port->name, 0x10); 3629 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3630 } 3631 3632 pci_register_bar(dev, 0, 3633 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3634 &xhci->mem); 3635 3636 if (pci_bus_is_express(dev->bus) || 3637 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 3638 ret = pcie_endpoint_cap_init(dev, 0xa0); 3639 assert(ret >= 0); 3640 } 3641 3642 if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI)) { 3643 msi_init(dev, 0x70, xhci->numintrs, true, false); 3644 } 3645 if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI_X)) { 3646 msix_init(dev, xhci->numintrs, 3647 &xhci->mem, 0, OFF_MSIX_TABLE, 3648 &xhci->mem, 0, OFF_MSIX_PBA, 3649 0x90); 3650 } 3651 } 3652 3653 static void usb_xhci_exit(PCIDevice *dev) 3654 { 3655 int i; 3656 XHCIState *xhci = XHCI(dev); 3657 3658 trace_usb_xhci_exit(); 3659 3660 for (i = 0; i < xhci->numslots; i++) { 3661 xhci_disable_slot(xhci, i + 1); 3662 } 3663 3664 if (xhci->mfwrap_timer) { 3665 timer_del(xhci->mfwrap_timer); 3666 timer_free(xhci->mfwrap_timer); 3667 xhci->mfwrap_timer = NULL; 3668 } 3669 3670 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3671 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3672 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3673 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3674 3675 for (i = 0; i < xhci->numports; i++) { 3676 XHCIPort *port = &xhci->ports[i]; 3677 memory_region_del_subregion(&xhci->mem, &port->mem); 3678 } 3679 3680 /* destroy msix memory region */ 3681 if (dev->msix_table && dev->msix_pba 3682 && dev->msix_entry_used) { 3683 memory_region_del_subregion(&xhci->mem, &dev->msix_table_mmio); 3684 memory_region_del_subregion(&xhci->mem, &dev->msix_pba_mmio); 3685 } 3686 3687 usb_bus_release(&xhci->bus); 3688 } 3689 3690 static int usb_xhci_post_load(void *opaque, int version_id) 3691 { 3692 XHCIState *xhci = opaque; 3693 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3694 XHCISlot *slot; 3695 XHCIEPContext *epctx; 3696 dma_addr_t dcbaap, pctx; 3697 uint32_t slot_ctx[4]; 3698 uint32_t ep_ctx[5]; 3699 int slotid, epid, state, intr; 3700 3701 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3702 3703 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3704 slot = &xhci->slots[slotid-1]; 3705 if (!slot->addressed) { 3706 continue; 3707 } 3708 slot->ctx = 3709 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3710 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3711 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3712 if (!slot->uport) { 3713 /* should not happen, but may trigger on guest bugs */ 3714 slot->enabled = 0; 3715 slot->addressed = 0; 3716 continue; 3717 } 3718 assert(slot->uport && slot->uport->dev); 3719 3720 for (epid = 1; epid <= 31; epid++) { 3721 pctx = slot->ctx + 32 * epid; 3722 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3723 state = ep_ctx[0] & EP_STATE_MASK; 3724 if (state == EP_DISABLED) { 3725 continue; 3726 } 3727 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3728 slot->eps[epid-1] = epctx; 3729 xhci_init_epctx(epctx, pctx, ep_ctx); 3730 epctx->state = state; 3731 if (state == EP_RUNNING) { 3732 /* kick endpoint after vmload is finished */ 3733 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3734 } 3735 } 3736 } 3737 3738 for (intr = 0; intr < xhci->numintrs; intr++) { 3739 if (xhci->intr[intr].msix_used) { 3740 msix_vector_use(pci_dev, intr); 3741 } else { 3742 msix_vector_unuse(pci_dev, intr); 3743 } 3744 } 3745 3746 return 0; 3747 } 3748 3749 static const VMStateDescription vmstate_xhci_ring = { 3750 .name = "xhci-ring", 3751 .version_id = 1, 3752 .fields = (VMStateField[]) { 3753 VMSTATE_UINT64(dequeue, XHCIRing), 3754 VMSTATE_BOOL(ccs, XHCIRing), 3755 VMSTATE_END_OF_LIST() 3756 } 3757 }; 3758 3759 static const VMStateDescription vmstate_xhci_port = { 3760 .name = "xhci-port", 3761 .version_id = 1, 3762 .fields = (VMStateField[]) { 3763 VMSTATE_UINT32(portsc, XHCIPort), 3764 VMSTATE_END_OF_LIST() 3765 } 3766 }; 3767 3768 static const VMStateDescription vmstate_xhci_slot = { 3769 .name = "xhci-slot", 3770 .version_id = 1, 3771 .fields = (VMStateField[]) { 3772 VMSTATE_BOOL(enabled, XHCISlot), 3773 VMSTATE_BOOL(addressed, XHCISlot), 3774 VMSTATE_END_OF_LIST() 3775 } 3776 }; 3777 3778 static const VMStateDescription vmstate_xhci_event = { 3779 .name = "xhci-event", 3780 .version_id = 1, 3781 .fields = (VMStateField[]) { 3782 VMSTATE_UINT32(type, XHCIEvent), 3783 VMSTATE_UINT32(ccode, XHCIEvent), 3784 VMSTATE_UINT64(ptr, XHCIEvent), 3785 VMSTATE_UINT32(length, XHCIEvent), 3786 VMSTATE_UINT32(flags, XHCIEvent), 3787 VMSTATE_UINT8(slotid, XHCIEvent), 3788 VMSTATE_UINT8(epid, XHCIEvent), 3789 VMSTATE_END_OF_LIST() 3790 } 3791 }; 3792 3793 static bool xhci_er_full(void *opaque, int version_id) 3794 { 3795 struct XHCIInterrupter *intr = opaque; 3796 return intr->er_full; 3797 } 3798 3799 static const VMStateDescription vmstate_xhci_intr = { 3800 .name = "xhci-intr", 3801 .version_id = 1, 3802 .fields = (VMStateField[]) { 3803 /* registers */ 3804 VMSTATE_UINT32(iman, XHCIInterrupter), 3805 VMSTATE_UINT32(imod, XHCIInterrupter), 3806 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3807 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3808 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3809 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3810 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3811 3812 /* state */ 3813 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3814 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3815 VMSTATE_UINT64(er_start, XHCIInterrupter), 3816 VMSTATE_UINT32(er_size, XHCIInterrupter), 3817 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3818 3819 /* event queue (used if ring is full) */ 3820 VMSTATE_BOOL(er_full, XHCIInterrupter), 3821 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3822 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3823 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3824 xhci_er_full, 1, 3825 vmstate_xhci_event, XHCIEvent), 3826 3827 VMSTATE_END_OF_LIST() 3828 } 3829 }; 3830 3831 static const VMStateDescription vmstate_xhci = { 3832 .name = "xhci", 3833 .version_id = 1, 3834 .post_load = usb_xhci_post_load, 3835 .fields = (VMStateField[]) { 3836 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3837 VMSTATE_MSIX(parent_obj, XHCIState), 3838 3839 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3840 vmstate_xhci_port, XHCIPort), 3841 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3842 vmstate_xhci_slot, XHCISlot), 3843 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3844 vmstate_xhci_intr, XHCIInterrupter), 3845 3846 /* Operational Registers */ 3847 VMSTATE_UINT32(usbcmd, XHCIState), 3848 VMSTATE_UINT32(usbsts, XHCIState), 3849 VMSTATE_UINT32(dnctrl, XHCIState), 3850 VMSTATE_UINT32(crcr_low, XHCIState), 3851 VMSTATE_UINT32(crcr_high, XHCIState), 3852 VMSTATE_UINT32(dcbaap_low, XHCIState), 3853 VMSTATE_UINT32(dcbaap_high, XHCIState), 3854 VMSTATE_UINT32(config, XHCIState), 3855 3856 /* Runtime Registers & state */ 3857 VMSTATE_INT64(mfindex_start, XHCIState), 3858 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3859 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3860 3861 VMSTATE_END_OF_LIST() 3862 } 3863 }; 3864 3865 static Property xhci_properties[] = { 3866 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3867 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3868 DEFINE_PROP_BIT("superspeed-ports-first", 3869 XHCIState, flags, XHCI_FLAG_SS_FIRST, true), 3870 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, 3871 XHCI_FLAG_FORCE_PCIE_ENDCAP, false), 3872 DEFINE_PROP_BIT("streams", XHCIState, flags, 3873 XHCI_FLAG_ENABLE_STREAMS, true), 3874 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3875 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3876 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3877 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3878 DEFINE_PROP_END_OF_LIST(), 3879 }; 3880 3881 static void xhci_class_init(ObjectClass *klass, void *data) 3882 { 3883 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3884 DeviceClass *dc = DEVICE_CLASS(klass); 3885 3886 dc->vmsd = &vmstate_xhci; 3887 dc->props = xhci_properties; 3888 dc->reset = xhci_reset; 3889 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3890 k->realize = usb_xhci_realize; 3891 k->exit = usb_xhci_exit; 3892 k->vendor_id = PCI_VENDOR_ID_NEC; 3893 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3894 k->class_id = PCI_CLASS_SERIAL_USB; 3895 k->revision = 0x03; 3896 k->is_express = 1; 3897 } 3898 3899 static const TypeInfo xhci_info = { 3900 .name = TYPE_XHCI, 3901 .parent = TYPE_PCI_DEVICE, 3902 .instance_size = sizeof(XHCIState), 3903 .class_init = xhci_class_init, 3904 }; 3905 3906 static void xhci_register_types(void) 3907 { 3908 type_register_static(&xhci_info); 3909 } 3910 3911 type_init(xhci_register_types) 3912