1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 305 #define get_field(data, field) \ 306 (((data) >> field##_SHIFT) & field##_MASK) 307 308 #define set_field(data, newval, field) do { \ 309 uint32_t val = *data; \ 310 val &= ~(field##_MASK << field##_SHIFT); \ 311 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 312 *data = val; \ 313 } while (0) 314 315 typedef enum EPType { 316 ET_INVALID = 0, 317 ET_ISO_OUT, 318 ET_BULK_OUT, 319 ET_INTR_OUT, 320 ET_CONTROL, 321 ET_ISO_IN, 322 ET_BULK_IN, 323 ET_INTR_IN, 324 } EPType; 325 326 typedef struct XHCIRing { 327 dma_addr_t base; 328 dma_addr_t dequeue; 329 bool ccs; 330 } XHCIRing; 331 332 typedef struct XHCIPort { 333 XHCIState *xhci; 334 uint32_t portsc; 335 uint32_t portnr; 336 USBPort *uport; 337 uint32_t speedmask; 338 char name[16]; 339 MemoryRegion mem; 340 } XHCIPort; 341 342 typedef struct XHCITransfer { 343 XHCIState *xhci; 344 USBPacket packet; 345 QEMUSGList sgl; 346 bool running_async; 347 bool running_retry; 348 bool cancelled; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 bool in_xfer; 355 bool iso_xfer; 356 357 unsigned int trb_count; 358 unsigned int trb_alloced; 359 XHCITRB *trbs; 360 361 TRBCCode status; 362 363 unsigned int pkts; 364 unsigned int pktsize; 365 unsigned int cur_pkt; 366 367 uint64_t mfindex_kick; 368 } XHCITransfer; 369 370 typedef struct XHCIEPContext { 371 XHCIState *xhci; 372 unsigned int slotid; 373 unsigned int epid; 374 375 XHCIRing ring; 376 unsigned int next_xfer; 377 unsigned int comp_xfer; 378 XHCITransfer transfers[TD_QUEUE]; 379 XHCITransfer *retry; 380 EPType type; 381 dma_addr_t pctx; 382 unsigned int max_psize; 383 uint32_t state; 384 385 /* iso xfer scheduling */ 386 unsigned int interval; 387 int64_t mfindex_last; 388 QEMUTimer *kick_timer; 389 } XHCIEPContext; 390 391 typedef struct XHCISlot { 392 bool enabled; 393 dma_addr_t ctx; 394 USBPort *uport; 395 unsigned int devaddr; 396 XHCIEPContext * eps[31]; 397 } XHCISlot; 398 399 typedef struct XHCIEvent { 400 TRBType type; 401 TRBCCode ccode; 402 uint64_t ptr; 403 uint32_t length; 404 uint32_t flags; 405 uint8_t slotid; 406 uint8_t epid; 407 } XHCIEvent; 408 409 typedef struct XHCIInterrupter { 410 uint32_t iman; 411 uint32_t imod; 412 uint32_t erstsz; 413 uint32_t erstba_low; 414 uint32_t erstba_high; 415 uint32_t erdp_low; 416 uint32_t erdp_high; 417 418 bool msix_used, er_pcs, er_full; 419 420 dma_addr_t er_start; 421 uint32_t er_size; 422 unsigned int er_ep_idx; 423 424 XHCIEvent ev_buffer[EV_QUEUE]; 425 unsigned int ev_buffer_put; 426 unsigned int ev_buffer_get; 427 428 } XHCIInterrupter; 429 430 struct XHCIState { 431 PCIDevice pci_dev; 432 USBBus bus; 433 qemu_irq irq; 434 MemoryRegion mem; 435 MemoryRegion mem_cap; 436 MemoryRegion mem_oper; 437 MemoryRegion mem_runtime; 438 MemoryRegion mem_doorbell; 439 const char *name; 440 unsigned int devaddr; 441 442 /* properties */ 443 uint32_t numports_2; 444 uint32_t numports_3; 445 uint32_t numintrs; 446 uint32_t numslots; 447 uint32_t flags; 448 449 /* Operational Registers */ 450 uint32_t usbcmd; 451 uint32_t usbsts; 452 uint32_t dnctrl; 453 uint32_t crcr_low; 454 uint32_t crcr_high; 455 uint32_t dcbaap_low; 456 uint32_t dcbaap_high; 457 uint32_t config; 458 459 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 460 XHCIPort ports[MAXPORTS]; 461 XHCISlot slots[MAXSLOTS]; 462 uint32_t numports; 463 464 /* Runtime Registers */ 465 int64_t mfindex_start; 466 QEMUTimer *mfwrap_timer; 467 XHCIInterrupter intr[MAXINTRS]; 468 469 XHCIRing cmd_ring; 470 }; 471 472 typedef struct XHCIEvRingSeg { 473 uint32_t addr_low; 474 uint32_t addr_high; 475 uint32_t size; 476 uint32_t rsvd; 477 } XHCIEvRingSeg; 478 479 enum xhci_flags { 480 XHCI_FLAG_USE_MSI = 1, 481 XHCI_FLAG_USE_MSI_X, 482 }; 483 484 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 485 unsigned int epid); 486 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 487 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 488 489 static const char *TRBType_names[] = { 490 [TRB_RESERVED] = "TRB_RESERVED", 491 [TR_NORMAL] = "TR_NORMAL", 492 [TR_SETUP] = "TR_SETUP", 493 [TR_DATA] = "TR_DATA", 494 [TR_STATUS] = "TR_STATUS", 495 [TR_ISOCH] = "TR_ISOCH", 496 [TR_LINK] = "TR_LINK", 497 [TR_EVDATA] = "TR_EVDATA", 498 [TR_NOOP] = "TR_NOOP", 499 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 500 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 501 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 502 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 503 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 504 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 505 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 506 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 507 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 508 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 509 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 510 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 511 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 512 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 513 [CR_NOOP] = "CR_NOOP", 514 [ER_TRANSFER] = "ER_TRANSFER", 515 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 516 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 517 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 518 [ER_DOORBELL] = "ER_DOORBELL", 519 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 520 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 521 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 522 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 523 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 524 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 525 }; 526 527 static const char *TRBCCode_names[] = { 528 [CC_INVALID] = "CC_INVALID", 529 [CC_SUCCESS] = "CC_SUCCESS", 530 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 531 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 532 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 533 [CC_TRB_ERROR] = "CC_TRB_ERROR", 534 [CC_STALL_ERROR] = "CC_STALL_ERROR", 535 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 536 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 537 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 538 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 539 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 540 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 541 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 542 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 543 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 544 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 545 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 546 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 547 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 548 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 549 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 550 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 551 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 552 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 553 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 554 [CC_STOPPED] = "CC_STOPPED", 555 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 556 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 557 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 558 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 559 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 560 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 561 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 562 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 563 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 564 }; 565 566 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 567 { 568 if (index >= llen || list[index] == NULL) { 569 return "???"; 570 } 571 return list[index]; 572 } 573 574 static const char *trb_name(XHCITRB *trb) 575 { 576 return lookup_name(TRB_TYPE(*trb), TRBType_names, 577 ARRAY_SIZE(TRBType_names)); 578 } 579 580 static const char *event_name(XHCIEvent *event) 581 { 582 return lookup_name(event->ccode, TRBCCode_names, 583 ARRAY_SIZE(TRBCCode_names)); 584 } 585 586 static uint64_t xhci_mfindex_get(XHCIState *xhci) 587 { 588 int64_t now = qemu_get_clock_ns(vm_clock); 589 return (now - xhci->mfindex_start) / 125000; 590 } 591 592 static void xhci_mfwrap_update(XHCIState *xhci) 593 { 594 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 595 uint32_t mfindex, left; 596 int64_t now; 597 598 if ((xhci->usbcmd & bits) == bits) { 599 now = qemu_get_clock_ns(vm_clock); 600 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 601 left = 0x4000 - mfindex; 602 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 603 } else { 604 qemu_del_timer(xhci->mfwrap_timer); 605 } 606 } 607 608 static void xhci_mfwrap_timer(void *opaque) 609 { 610 XHCIState *xhci = opaque; 611 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 612 613 xhci_event(xhci, &wrap, 0); 614 xhci_mfwrap_update(xhci); 615 } 616 617 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 618 { 619 if (sizeof(dma_addr_t) == 4) { 620 return low; 621 } else { 622 return low | (((dma_addr_t)high << 16) << 16); 623 } 624 } 625 626 static inline dma_addr_t xhci_mask64(uint64_t addr) 627 { 628 if (sizeof(dma_addr_t) == 4) { 629 return addr & 0xffffffff; 630 } else { 631 return addr; 632 } 633 } 634 635 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 636 { 637 int index; 638 639 if (!uport->dev) { 640 return NULL; 641 } 642 switch (uport->dev->speed) { 643 case USB_SPEED_LOW: 644 case USB_SPEED_FULL: 645 case USB_SPEED_HIGH: 646 index = uport->index; 647 break; 648 case USB_SPEED_SUPER: 649 index = uport->index + xhci->numports_2; 650 break; 651 default: 652 return NULL; 653 } 654 return &xhci->ports[index]; 655 } 656 657 static void xhci_intx_update(XHCIState *xhci) 658 { 659 int level = 0; 660 661 if (msix_enabled(&xhci->pci_dev) || 662 msi_enabled(&xhci->pci_dev)) { 663 return; 664 } 665 666 if (xhci->intr[0].iman & IMAN_IP && 667 xhci->intr[0].iman & IMAN_IE && 668 xhci->usbcmd & USBCMD_INTE) { 669 level = 1; 670 } 671 672 trace_usb_xhci_irq_intx(level); 673 qemu_set_irq(xhci->irq, level); 674 } 675 676 static void xhci_msix_update(XHCIState *xhci, int v) 677 { 678 bool enabled; 679 680 if (!msix_enabled(&xhci->pci_dev)) { 681 return; 682 } 683 684 enabled = xhci->intr[v].iman & IMAN_IE; 685 if (enabled == xhci->intr[v].msix_used) { 686 return; 687 } 688 689 if (enabled) { 690 trace_usb_xhci_irq_msix_use(v); 691 msix_vector_use(&xhci->pci_dev, v); 692 xhci->intr[v].msix_used = true; 693 } else { 694 trace_usb_xhci_irq_msix_unuse(v); 695 msix_vector_unuse(&xhci->pci_dev, v); 696 xhci->intr[v].msix_used = false; 697 } 698 } 699 700 static void xhci_intr_raise(XHCIState *xhci, int v) 701 { 702 xhci->intr[v].erdp_low |= ERDP_EHB; 703 xhci->intr[v].iman |= IMAN_IP; 704 xhci->usbsts |= USBSTS_EINT; 705 706 if (!(xhci->intr[v].iman & IMAN_IE)) { 707 return; 708 } 709 710 if (!(xhci->usbcmd & USBCMD_INTE)) { 711 return; 712 } 713 714 if (msix_enabled(&xhci->pci_dev)) { 715 trace_usb_xhci_irq_msix(v); 716 msix_notify(&xhci->pci_dev, v); 717 return; 718 } 719 720 if (msi_enabled(&xhci->pci_dev)) { 721 trace_usb_xhci_irq_msi(v); 722 msi_notify(&xhci->pci_dev, v); 723 return; 724 } 725 726 if (v == 0) { 727 trace_usb_xhci_irq_intx(1); 728 qemu_set_irq(xhci->irq, 1); 729 } 730 } 731 732 static inline int xhci_running(XHCIState *xhci) 733 { 734 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 735 } 736 737 static void xhci_die(XHCIState *xhci) 738 { 739 xhci->usbsts |= USBSTS_HCE; 740 fprintf(stderr, "xhci: asserted controller error\n"); 741 } 742 743 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 744 { 745 XHCIInterrupter *intr = &xhci->intr[v]; 746 XHCITRB ev_trb; 747 dma_addr_t addr; 748 749 ev_trb.parameter = cpu_to_le64(event->ptr); 750 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 751 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 752 event->flags | (event->type << TRB_TYPE_SHIFT); 753 if (intr->er_pcs) { 754 ev_trb.control |= TRB_C; 755 } 756 ev_trb.control = cpu_to_le32(ev_trb.control); 757 758 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 759 event_name(event), ev_trb.parameter, 760 ev_trb.status, ev_trb.control); 761 762 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 763 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 764 765 intr->er_ep_idx++; 766 if (intr->er_ep_idx >= intr->er_size) { 767 intr->er_ep_idx = 0; 768 intr->er_pcs = !intr->er_pcs; 769 } 770 } 771 772 static void xhci_events_update(XHCIState *xhci, int v) 773 { 774 XHCIInterrupter *intr = &xhci->intr[v]; 775 dma_addr_t erdp; 776 unsigned int dp_idx; 777 bool do_irq = 0; 778 779 if (xhci->usbsts & USBSTS_HCH) { 780 return; 781 } 782 783 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 784 if (erdp < intr->er_start || 785 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 786 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 787 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 788 v, intr->er_start, intr->er_size); 789 xhci_die(xhci); 790 return; 791 } 792 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 793 assert(dp_idx < intr->er_size); 794 795 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 796 * deadlocks when the ER is full. Hack it by holding off events until 797 * the driver decides to free at least half of the ring */ 798 if (intr->er_full) { 799 int er_free = dp_idx - intr->er_ep_idx; 800 if (er_free <= 0) { 801 er_free += intr->er_size; 802 } 803 if (er_free < (intr->er_size/2)) { 804 DPRINTF("xhci_events_update(): event ring still " 805 "more than half full (hack)\n"); 806 return; 807 } 808 } 809 810 while (intr->ev_buffer_put != intr->ev_buffer_get) { 811 assert(intr->er_full); 812 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 813 DPRINTF("xhci_events_update(): event ring full again\n"); 814 #ifndef ER_FULL_HACK 815 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 816 xhci_write_event(xhci, &full, v); 817 #endif 818 do_irq = 1; 819 break; 820 } 821 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 822 xhci_write_event(xhci, event, v); 823 intr->ev_buffer_get++; 824 do_irq = 1; 825 if (intr->ev_buffer_get == EV_QUEUE) { 826 intr->ev_buffer_get = 0; 827 } 828 } 829 830 if (do_irq) { 831 xhci_intr_raise(xhci, v); 832 } 833 834 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 835 DPRINTF("xhci_events_update(): event ring no longer full\n"); 836 intr->er_full = 0; 837 } 838 } 839 840 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 841 { 842 XHCIInterrupter *intr; 843 dma_addr_t erdp; 844 unsigned int dp_idx; 845 846 if (v >= xhci->numintrs) { 847 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 848 return; 849 } 850 intr = &xhci->intr[v]; 851 852 if (intr->er_full) { 853 DPRINTF("xhci_event(): ER full, queueing\n"); 854 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 855 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 856 return; 857 } 858 intr->ev_buffer[intr->ev_buffer_put++] = *event; 859 if (intr->ev_buffer_put == EV_QUEUE) { 860 intr->ev_buffer_put = 0; 861 } 862 return; 863 } 864 865 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 866 if (erdp < intr->er_start || 867 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 868 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 869 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 870 v, intr->er_start, intr->er_size); 871 xhci_die(xhci); 872 return; 873 } 874 875 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 876 assert(dp_idx < intr->er_size); 877 878 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 879 DPRINTF("xhci_event(): ER full, queueing\n"); 880 #ifndef ER_FULL_HACK 881 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 882 xhci_write_event(xhci, &full); 883 #endif 884 intr->er_full = 1; 885 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 886 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 887 return; 888 } 889 intr->ev_buffer[intr->ev_buffer_put++] = *event; 890 if (intr->ev_buffer_put == EV_QUEUE) { 891 intr->ev_buffer_put = 0; 892 } 893 } else { 894 xhci_write_event(xhci, event, v); 895 } 896 897 xhci_intr_raise(xhci, v); 898 } 899 900 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 901 dma_addr_t base) 902 { 903 ring->base = base; 904 ring->dequeue = base; 905 ring->ccs = 1; 906 } 907 908 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 909 dma_addr_t *addr) 910 { 911 while (1) { 912 TRBType type; 913 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 914 trb->addr = ring->dequeue; 915 trb->ccs = ring->ccs; 916 le64_to_cpus(&trb->parameter); 917 le32_to_cpus(&trb->status); 918 le32_to_cpus(&trb->control); 919 920 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 921 trb->parameter, trb->status, trb->control); 922 923 if ((trb->control & TRB_C) != ring->ccs) { 924 return 0; 925 } 926 927 type = TRB_TYPE(*trb); 928 929 if (type != TR_LINK) { 930 if (addr) { 931 *addr = ring->dequeue; 932 } 933 ring->dequeue += TRB_SIZE; 934 return type; 935 } else { 936 ring->dequeue = xhci_mask64(trb->parameter); 937 if (trb->control & TRB_LK_TC) { 938 ring->ccs = !ring->ccs; 939 } 940 } 941 } 942 } 943 944 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 945 { 946 XHCITRB trb; 947 int length = 0; 948 dma_addr_t dequeue = ring->dequeue; 949 bool ccs = ring->ccs; 950 /* hack to bundle together the two/three TDs that make a setup transfer */ 951 bool control_td_set = 0; 952 953 while (1) { 954 TRBType type; 955 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 956 le64_to_cpus(&trb.parameter); 957 le32_to_cpus(&trb.status); 958 le32_to_cpus(&trb.control); 959 960 if ((trb.control & TRB_C) != ccs) { 961 return -length; 962 } 963 964 type = TRB_TYPE(trb); 965 966 if (type == TR_LINK) { 967 dequeue = xhci_mask64(trb.parameter); 968 if (trb.control & TRB_LK_TC) { 969 ccs = !ccs; 970 } 971 continue; 972 } 973 974 length += 1; 975 dequeue += TRB_SIZE; 976 977 if (type == TR_SETUP) { 978 control_td_set = 1; 979 } else if (type == TR_STATUS) { 980 control_td_set = 0; 981 } 982 983 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 984 return length; 985 } 986 } 987 } 988 989 static void xhci_er_reset(XHCIState *xhci, int v) 990 { 991 XHCIInterrupter *intr = &xhci->intr[v]; 992 XHCIEvRingSeg seg; 993 994 if (intr->erstsz == 0) { 995 /* disabled */ 996 intr->er_start = 0; 997 intr->er_size = 0; 998 return; 999 } 1000 /* cache the (sole) event ring segment location */ 1001 if (intr->erstsz != 1) { 1002 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1003 xhci_die(xhci); 1004 return; 1005 } 1006 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1007 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 1008 le32_to_cpus(&seg.addr_low); 1009 le32_to_cpus(&seg.addr_high); 1010 le32_to_cpus(&seg.size); 1011 if (seg.size < 16 || seg.size > 4096) { 1012 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1013 xhci_die(xhci); 1014 return; 1015 } 1016 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1017 intr->er_size = seg.size; 1018 1019 intr->er_ep_idx = 0; 1020 intr->er_pcs = 1; 1021 intr->er_full = 0; 1022 1023 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1024 v, intr->er_start, intr->er_size); 1025 } 1026 1027 static void xhci_run(XHCIState *xhci) 1028 { 1029 trace_usb_xhci_run(); 1030 xhci->usbsts &= ~USBSTS_HCH; 1031 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1032 } 1033 1034 static void xhci_stop(XHCIState *xhci) 1035 { 1036 trace_usb_xhci_stop(); 1037 xhci->usbsts |= USBSTS_HCH; 1038 xhci->crcr_low &= ~CRCR_CRR; 1039 } 1040 1041 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1042 uint32_t state) 1043 { 1044 uint32_t ctx[5]; 1045 1046 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1047 ctx[0] &= ~EP_STATE_MASK; 1048 ctx[0] |= state; 1049 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1050 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1051 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1052 epctx->pctx, state, ctx[3], ctx[2]); 1053 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1054 epctx->state = state; 1055 } 1056 1057 static void xhci_ep_kick_timer(void *opaque) 1058 { 1059 XHCIEPContext *epctx = opaque; 1060 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1061 } 1062 1063 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1064 unsigned int epid, dma_addr_t pctx, 1065 uint32_t *ctx) 1066 { 1067 XHCISlot *slot; 1068 XHCIEPContext *epctx; 1069 dma_addr_t dequeue; 1070 int i; 1071 1072 trace_usb_xhci_ep_enable(slotid, epid); 1073 assert(slotid >= 1 && slotid <= xhci->numslots); 1074 assert(epid >= 1 && epid <= 31); 1075 1076 slot = &xhci->slots[slotid-1]; 1077 if (slot->eps[epid-1]) { 1078 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1079 return CC_TRB_ERROR; 1080 } 1081 1082 epctx = g_malloc(sizeof(XHCIEPContext)); 1083 memset(epctx, 0, sizeof(XHCIEPContext)); 1084 epctx->xhci = xhci; 1085 epctx->slotid = slotid; 1086 epctx->epid = epid; 1087 1088 slot->eps[epid-1] = epctx; 1089 1090 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1091 xhci_ring_init(xhci, &epctx->ring, dequeue); 1092 epctx->ring.ccs = ctx[2] & 1; 1093 1094 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1095 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1096 epctx->pctx = pctx; 1097 epctx->max_psize = ctx[1]>>16; 1098 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1099 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1100 epid/2, epid%2, epctx->max_psize); 1101 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1102 usb_packet_init(&epctx->transfers[i].packet); 1103 } 1104 1105 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1106 epctx->mfindex_last = 0; 1107 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1108 1109 epctx->state = EP_RUNNING; 1110 ctx[0] &= ~EP_STATE_MASK; 1111 ctx[0] |= EP_RUNNING; 1112 1113 return CC_SUCCESS; 1114 } 1115 1116 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1117 { 1118 int killed = 0; 1119 1120 if (t->running_async) { 1121 usb_cancel_packet(&t->packet); 1122 t->running_async = 0; 1123 t->cancelled = 1; 1124 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1125 killed = 1; 1126 } 1127 if (t->running_retry) { 1128 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1129 if (epctx) { 1130 epctx->retry = NULL; 1131 qemu_del_timer(epctx->kick_timer); 1132 } 1133 t->running_retry = 0; 1134 } 1135 if (t->trbs) { 1136 g_free(t->trbs); 1137 } 1138 1139 t->trbs = NULL; 1140 t->trb_count = t->trb_alloced = 0; 1141 1142 return killed; 1143 } 1144 1145 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1146 unsigned int epid) 1147 { 1148 XHCISlot *slot; 1149 XHCIEPContext *epctx; 1150 int i, xferi, killed = 0; 1151 assert(slotid >= 1 && slotid <= xhci->numslots); 1152 assert(epid >= 1 && epid <= 31); 1153 1154 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1155 1156 slot = &xhci->slots[slotid-1]; 1157 1158 if (!slot->eps[epid-1]) { 1159 return 0; 1160 } 1161 1162 epctx = slot->eps[epid-1]; 1163 1164 xferi = epctx->next_xfer; 1165 for (i = 0; i < TD_QUEUE; i++) { 1166 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1167 xferi = (xferi + 1) % TD_QUEUE; 1168 } 1169 return killed; 1170 } 1171 1172 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1173 unsigned int epid) 1174 { 1175 XHCISlot *slot; 1176 XHCIEPContext *epctx; 1177 1178 trace_usb_xhci_ep_disable(slotid, epid); 1179 assert(slotid >= 1 && slotid <= xhci->numslots); 1180 assert(epid >= 1 && epid <= 31); 1181 1182 slot = &xhci->slots[slotid-1]; 1183 1184 if (!slot->eps[epid-1]) { 1185 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1186 return CC_SUCCESS; 1187 } 1188 1189 xhci_ep_nuke_xfers(xhci, slotid, epid); 1190 1191 epctx = slot->eps[epid-1]; 1192 1193 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1194 1195 qemu_free_timer(epctx->kick_timer); 1196 g_free(epctx); 1197 slot->eps[epid-1] = NULL; 1198 1199 return CC_SUCCESS; 1200 } 1201 1202 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1203 unsigned int epid) 1204 { 1205 XHCISlot *slot; 1206 XHCIEPContext *epctx; 1207 1208 trace_usb_xhci_ep_stop(slotid, epid); 1209 assert(slotid >= 1 && slotid <= xhci->numslots); 1210 1211 if (epid < 1 || epid > 31) { 1212 fprintf(stderr, "xhci: bad ep %d\n", epid); 1213 return CC_TRB_ERROR; 1214 } 1215 1216 slot = &xhci->slots[slotid-1]; 1217 1218 if (!slot->eps[epid-1]) { 1219 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1220 return CC_EP_NOT_ENABLED_ERROR; 1221 } 1222 1223 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1224 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1225 "data might be lost\n"); 1226 } 1227 1228 epctx = slot->eps[epid-1]; 1229 1230 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1231 1232 return CC_SUCCESS; 1233 } 1234 1235 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1236 unsigned int epid) 1237 { 1238 XHCISlot *slot; 1239 XHCIEPContext *epctx; 1240 USBDevice *dev; 1241 1242 trace_usb_xhci_ep_reset(slotid, epid); 1243 assert(slotid >= 1 && slotid <= xhci->numslots); 1244 1245 if (epid < 1 || epid > 31) { 1246 fprintf(stderr, "xhci: bad ep %d\n", epid); 1247 return CC_TRB_ERROR; 1248 } 1249 1250 slot = &xhci->slots[slotid-1]; 1251 1252 if (!slot->eps[epid-1]) { 1253 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1254 return CC_EP_NOT_ENABLED_ERROR; 1255 } 1256 1257 epctx = slot->eps[epid-1]; 1258 1259 if (epctx->state != EP_HALTED) { 1260 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1261 epid, epctx->state); 1262 return CC_CONTEXT_STATE_ERROR; 1263 } 1264 1265 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1266 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1267 "data might be lost\n"); 1268 } 1269 1270 uint8_t ep = epid>>1; 1271 1272 if (epid & 1) { 1273 ep |= 0x80; 1274 } 1275 1276 dev = xhci->slots[slotid-1].uport->dev; 1277 if (!dev) { 1278 return CC_USB_TRANSACTION_ERROR; 1279 } 1280 1281 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1282 1283 return CC_SUCCESS; 1284 } 1285 1286 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1287 unsigned int epid, uint64_t pdequeue) 1288 { 1289 XHCISlot *slot; 1290 XHCIEPContext *epctx; 1291 dma_addr_t dequeue; 1292 1293 assert(slotid >= 1 && slotid <= xhci->numslots); 1294 1295 if (epid < 1 || epid > 31) { 1296 fprintf(stderr, "xhci: bad ep %d\n", epid); 1297 return CC_TRB_ERROR; 1298 } 1299 1300 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1301 dequeue = xhci_mask64(pdequeue); 1302 1303 slot = &xhci->slots[slotid-1]; 1304 1305 if (!slot->eps[epid-1]) { 1306 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1307 return CC_EP_NOT_ENABLED_ERROR; 1308 } 1309 1310 epctx = slot->eps[epid-1]; 1311 1312 1313 if (epctx->state != EP_STOPPED) { 1314 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1315 return CC_CONTEXT_STATE_ERROR; 1316 } 1317 1318 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1319 epctx->ring.ccs = dequeue & 1; 1320 1321 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1322 1323 return CC_SUCCESS; 1324 } 1325 1326 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1327 { 1328 XHCIState *xhci = xfer->xhci; 1329 int i; 1330 1331 xfer->int_req = false; 1332 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1333 for (i = 0; i < xfer->trb_count; i++) { 1334 XHCITRB *trb = &xfer->trbs[i]; 1335 dma_addr_t addr; 1336 unsigned int chunk = 0; 1337 1338 if (trb->control & TRB_TR_IOC) { 1339 xfer->int_req = true; 1340 } 1341 1342 switch (TRB_TYPE(*trb)) { 1343 case TR_DATA: 1344 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1345 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1346 goto err; 1347 } 1348 /* fallthrough */ 1349 case TR_NORMAL: 1350 case TR_ISOCH: 1351 addr = xhci_mask64(trb->parameter); 1352 chunk = trb->status & 0x1ffff; 1353 if (trb->control & TRB_TR_IDT) { 1354 if (chunk > 8 || in_xfer) { 1355 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1356 goto err; 1357 } 1358 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1359 } else { 1360 qemu_sglist_add(&xfer->sgl, addr, chunk); 1361 } 1362 break; 1363 } 1364 } 1365 1366 return 0; 1367 1368 err: 1369 qemu_sglist_destroy(&xfer->sgl); 1370 xhci_die(xhci); 1371 return -1; 1372 } 1373 1374 static void xhci_xfer_unmap(XHCITransfer *xfer) 1375 { 1376 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1377 qemu_sglist_destroy(&xfer->sgl); 1378 } 1379 1380 static void xhci_xfer_report(XHCITransfer *xfer) 1381 { 1382 uint32_t edtla = 0; 1383 unsigned int left; 1384 bool reported = 0; 1385 bool shortpkt = 0; 1386 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1387 XHCIState *xhci = xfer->xhci; 1388 int i; 1389 1390 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1391 1392 for (i = 0; i < xfer->trb_count; i++) { 1393 XHCITRB *trb = &xfer->trbs[i]; 1394 unsigned int chunk = 0; 1395 1396 switch (TRB_TYPE(*trb)) { 1397 case TR_DATA: 1398 case TR_NORMAL: 1399 case TR_ISOCH: 1400 chunk = trb->status & 0x1ffff; 1401 if (chunk > left) { 1402 chunk = left; 1403 if (xfer->status == CC_SUCCESS) { 1404 shortpkt = 1; 1405 } 1406 } 1407 left -= chunk; 1408 edtla += chunk; 1409 break; 1410 case TR_STATUS: 1411 reported = 0; 1412 shortpkt = 0; 1413 break; 1414 } 1415 1416 if (!reported && ((trb->control & TRB_TR_IOC) || 1417 (shortpkt && (trb->control & TRB_TR_ISP)) || 1418 (xfer->status != CC_SUCCESS))) { 1419 event.slotid = xfer->slotid; 1420 event.epid = xfer->epid; 1421 event.length = (trb->status & 0x1ffff) - chunk; 1422 event.flags = 0; 1423 event.ptr = trb->addr; 1424 if (xfer->status == CC_SUCCESS) { 1425 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1426 } else { 1427 event.ccode = xfer->status; 1428 } 1429 if (TRB_TYPE(*trb) == TR_EVDATA) { 1430 event.ptr = trb->parameter; 1431 event.flags |= TRB_EV_ED; 1432 event.length = edtla & 0xffffff; 1433 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1434 edtla = 0; 1435 } 1436 xhci_event(xhci, &event, TRB_INTR(*trb)); 1437 reported = 1; 1438 if (xfer->status != CC_SUCCESS) { 1439 return; 1440 } 1441 } 1442 } 1443 } 1444 1445 static void xhci_stall_ep(XHCITransfer *xfer) 1446 { 1447 XHCIState *xhci = xfer->xhci; 1448 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1449 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1450 1451 epctx->ring.dequeue = xfer->trbs[0].addr; 1452 epctx->ring.ccs = xfer->trbs[0].ccs; 1453 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1454 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1455 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1456 } 1457 1458 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1459 XHCIEPContext *epctx); 1460 1461 static int xhci_setup_packet(XHCITransfer *xfer) 1462 { 1463 XHCIState *xhci = xfer->xhci; 1464 USBDevice *dev; 1465 USBEndpoint *ep; 1466 int dir; 1467 1468 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1469 1470 if (xfer->packet.ep) { 1471 ep = xfer->packet.ep; 1472 dev = ep->dev; 1473 } else { 1474 if (!xhci->slots[xfer->slotid-1].uport) { 1475 fprintf(stderr, "xhci: slot %d has no device\n", 1476 xfer->slotid); 1477 return -1; 1478 } 1479 dev = xhci->slots[xfer->slotid-1].uport->dev; 1480 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1481 } 1482 1483 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1484 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr, false, 1485 xfer->int_req); 1486 usb_packet_map(&xfer->packet, &xfer->sgl); 1487 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1488 xfer->packet.pid, dev->addr, ep->nr); 1489 return 0; 1490 } 1491 1492 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1493 { 1494 if (ret == USB_RET_ASYNC) { 1495 trace_usb_xhci_xfer_async(xfer); 1496 xfer->running_async = 1; 1497 xfer->running_retry = 0; 1498 xfer->complete = 0; 1499 xfer->cancelled = 0; 1500 return 0; 1501 } else if (ret == USB_RET_NAK) { 1502 trace_usb_xhci_xfer_nak(xfer); 1503 xfer->running_async = 0; 1504 xfer->running_retry = 1; 1505 xfer->complete = 0; 1506 xfer->cancelled = 0; 1507 return 0; 1508 } else { 1509 xfer->running_async = 0; 1510 xfer->running_retry = 0; 1511 xfer->complete = 1; 1512 xhci_xfer_unmap(xfer); 1513 } 1514 1515 if (ret >= 0) { 1516 trace_usb_xhci_xfer_success(xfer, ret); 1517 xfer->status = CC_SUCCESS; 1518 xhci_xfer_report(xfer); 1519 return 0; 1520 } 1521 1522 /* error */ 1523 trace_usb_xhci_xfer_error(xfer, ret); 1524 switch (ret) { 1525 case USB_RET_NODEV: 1526 xfer->status = CC_USB_TRANSACTION_ERROR; 1527 xhci_xfer_report(xfer); 1528 xhci_stall_ep(xfer); 1529 break; 1530 case USB_RET_STALL: 1531 xfer->status = CC_STALL_ERROR; 1532 xhci_xfer_report(xfer); 1533 xhci_stall_ep(xfer); 1534 break; 1535 default: 1536 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1537 FIXME(); 1538 } 1539 return 0; 1540 } 1541 1542 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1543 { 1544 XHCITRB *trb_setup, *trb_status; 1545 uint8_t bmRequestType; 1546 int ret; 1547 1548 trb_setup = &xfer->trbs[0]; 1549 trb_status = &xfer->trbs[xfer->trb_count-1]; 1550 1551 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1552 1553 /* at most one Event Data TRB allowed after STATUS */ 1554 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1555 trb_status--; 1556 } 1557 1558 /* do some sanity checks */ 1559 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1560 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1561 TRB_TYPE(*trb_setup)); 1562 return -1; 1563 } 1564 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1565 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1566 TRB_TYPE(*trb_status)); 1567 return -1; 1568 } 1569 if (!(trb_setup->control & TRB_TR_IDT)) { 1570 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1571 return -1; 1572 } 1573 if ((trb_setup->status & 0x1ffff) != 8) { 1574 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1575 (trb_setup->status & 0x1ffff)); 1576 return -1; 1577 } 1578 1579 bmRequestType = trb_setup->parameter; 1580 1581 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1582 xfer->iso_xfer = false; 1583 1584 if (xhci_setup_packet(xfer) < 0) { 1585 return -1; 1586 } 1587 xfer->packet.parameter = trb_setup->parameter; 1588 1589 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1590 1591 xhci_complete_packet(xfer, ret); 1592 if (!xfer->running_async && !xfer->running_retry) { 1593 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1594 } 1595 return 0; 1596 } 1597 1598 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1599 XHCIEPContext *epctx, uint64_t mfindex) 1600 { 1601 if (xfer->trbs[0].control & TRB_TR_SIA) { 1602 uint64_t asap = ((mfindex + epctx->interval - 1) & 1603 ~(epctx->interval-1)); 1604 if (asap >= epctx->mfindex_last && 1605 asap <= epctx->mfindex_last + epctx->interval * 4) { 1606 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1607 } else { 1608 xfer->mfindex_kick = asap; 1609 } 1610 } else { 1611 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1612 & TRB_TR_FRAMEID_MASK; 1613 xfer->mfindex_kick |= mfindex & ~0x3fff; 1614 if (xfer->mfindex_kick < mfindex) { 1615 xfer->mfindex_kick += 0x4000; 1616 } 1617 } 1618 } 1619 1620 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1621 XHCIEPContext *epctx, uint64_t mfindex) 1622 { 1623 if (xfer->mfindex_kick > mfindex) { 1624 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1625 (xfer->mfindex_kick - mfindex) * 125000); 1626 xfer->running_retry = 1; 1627 } else { 1628 epctx->mfindex_last = xfer->mfindex_kick; 1629 qemu_del_timer(epctx->kick_timer); 1630 xfer->running_retry = 0; 1631 } 1632 } 1633 1634 1635 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1636 { 1637 uint64_t mfindex; 1638 int ret; 1639 1640 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1641 1642 xfer->in_xfer = epctx->type>>2; 1643 1644 switch(epctx->type) { 1645 case ET_INTR_OUT: 1646 case ET_INTR_IN: 1647 case ET_BULK_OUT: 1648 case ET_BULK_IN: 1649 xfer->pkts = 0; 1650 xfer->iso_xfer = false; 1651 break; 1652 case ET_ISO_OUT: 1653 case ET_ISO_IN: 1654 xfer->pkts = 1; 1655 xfer->iso_xfer = true; 1656 mfindex = xhci_mfindex_get(xhci); 1657 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1658 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1659 if (xfer->running_retry) { 1660 return -1; 1661 } 1662 break; 1663 default: 1664 fprintf(stderr, "xhci: unknown or unhandled EP " 1665 "(type %d, in %d, ep %02x)\n", 1666 epctx->type, xfer->in_xfer, xfer->epid); 1667 return -1; 1668 } 1669 1670 if (xhci_setup_packet(xfer) < 0) { 1671 return -1; 1672 } 1673 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1674 1675 xhci_complete_packet(xfer, ret); 1676 if (!xfer->running_async && !xfer->running_retry) { 1677 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1678 } 1679 return 0; 1680 } 1681 1682 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1683 { 1684 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1685 return xhci_submit(xhci, xfer, epctx); 1686 } 1687 1688 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1689 { 1690 XHCIEPContext *epctx; 1691 USBEndpoint *ep = NULL; 1692 uint64_t mfindex; 1693 int length; 1694 int i; 1695 1696 trace_usb_xhci_ep_kick(slotid, epid); 1697 assert(slotid >= 1 && slotid <= xhci->numslots); 1698 assert(epid >= 1 && epid <= 31); 1699 1700 if (!xhci->slots[slotid-1].enabled) { 1701 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1702 return; 1703 } 1704 epctx = xhci->slots[slotid-1].eps[epid-1]; 1705 if (!epctx) { 1706 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1707 epid, slotid); 1708 return; 1709 } 1710 1711 if (epctx->retry) { 1712 XHCITransfer *xfer = epctx->retry; 1713 int result; 1714 1715 trace_usb_xhci_xfer_retry(xfer); 1716 assert(xfer->running_retry); 1717 if (xfer->iso_xfer) { 1718 /* retry delayed iso transfer */ 1719 mfindex = xhci_mfindex_get(xhci); 1720 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1721 if (xfer->running_retry) { 1722 return; 1723 } 1724 if (xhci_setup_packet(xfer) < 0) { 1725 return; 1726 } 1727 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1728 assert(result != USB_RET_NAK); 1729 xhci_complete_packet(xfer, result); 1730 } else { 1731 /* retry nak'ed transfer */ 1732 if (xhci_setup_packet(xfer) < 0) { 1733 return; 1734 } 1735 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1736 if (result == USB_RET_NAK) { 1737 return; 1738 } 1739 xhci_complete_packet(xfer, result); 1740 } 1741 assert(!xfer->running_retry); 1742 epctx->retry = NULL; 1743 } 1744 1745 if (epctx->state == EP_HALTED) { 1746 DPRINTF("xhci: ep halted, not running schedule\n"); 1747 return; 1748 } 1749 1750 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1751 1752 while (1) { 1753 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1754 if (xfer->running_async || xfer->running_retry) { 1755 break; 1756 } 1757 length = xhci_ring_chain_length(xhci, &epctx->ring); 1758 if (length < 0) { 1759 break; 1760 } else if (length == 0) { 1761 break; 1762 } 1763 if (xfer->trbs && xfer->trb_alloced < length) { 1764 xfer->trb_count = 0; 1765 xfer->trb_alloced = 0; 1766 g_free(xfer->trbs); 1767 xfer->trbs = NULL; 1768 } 1769 if (!xfer->trbs) { 1770 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1771 xfer->trb_alloced = length; 1772 } 1773 xfer->trb_count = length; 1774 1775 for (i = 0; i < length; i++) { 1776 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1777 } 1778 xfer->xhci = xhci; 1779 xfer->epid = epid; 1780 xfer->slotid = slotid; 1781 1782 if (epid == 1) { 1783 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1784 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1785 ep = xfer->packet.ep; 1786 } else { 1787 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1788 } 1789 } else { 1790 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1791 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1792 ep = xfer->packet.ep; 1793 } else { 1794 if (!xfer->iso_xfer) { 1795 fprintf(stderr, "xhci: error firing data transfer\n"); 1796 } 1797 } 1798 } 1799 1800 if (epctx->state == EP_HALTED) { 1801 break; 1802 } 1803 if (xfer->running_retry) { 1804 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1805 epctx->retry = xfer; 1806 break; 1807 } 1808 } 1809 if (ep) { 1810 usb_device_flush_ep_queue(ep->dev, ep); 1811 } 1812 } 1813 1814 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1815 { 1816 trace_usb_xhci_slot_enable(slotid); 1817 assert(slotid >= 1 && slotid <= xhci->numslots); 1818 xhci->slots[slotid-1].enabled = 1; 1819 xhci->slots[slotid-1].uport = NULL; 1820 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1821 1822 return CC_SUCCESS; 1823 } 1824 1825 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1826 { 1827 int i; 1828 1829 trace_usb_xhci_slot_disable(slotid); 1830 assert(slotid >= 1 && slotid <= xhci->numslots); 1831 1832 for (i = 1; i <= 31; i++) { 1833 if (xhci->slots[slotid-1].eps[i-1]) { 1834 xhci_disable_ep(xhci, slotid, i); 1835 } 1836 } 1837 1838 xhci->slots[slotid-1].enabled = 0; 1839 return CC_SUCCESS; 1840 } 1841 1842 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1843 { 1844 USBPort *uport; 1845 char path[32]; 1846 int i, pos, port; 1847 1848 port = (slot_ctx[1]>>16) & 0xFF; 1849 port = xhci->ports[port-1].uport->index+1; 1850 pos = snprintf(path, sizeof(path), "%d", port); 1851 for (i = 0; i < 5; i++) { 1852 port = (slot_ctx[0] >> 4*i) & 0x0f; 1853 if (!port) { 1854 break; 1855 } 1856 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1857 } 1858 1859 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1860 if (strcmp(uport->path, path) == 0) { 1861 return uport; 1862 } 1863 } 1864 return NULL; 1865 } 1866 1867 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1868 uint64_t pictx, bool bsr) 1869 { 1870 XHCISlot *slot; 1871 USBPort *uport; 1872 USBDevice *dev; 1873 dma_addr_t ictx, octx, dcbaap; 1874 uint64_t poctx; 1875 uint32_t ictl_ctx[2]; 1876 uint32_t slot_ctx[4]; 1877 uint32_t ep0_ctx[5]; 1878 int i; 1879 TRBCCode res; 1880 1881 trace_usb_xhci_slot_address(slotid); 1882 assert(slotid >= 1 && slotid <= xhci->numslots); 1883 1884 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1885 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1886 ictx = xhci_mask64(pictx); 1887 octx = xhci_mask64(le64_to_cpu(poctx)); 1888 1889 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1890 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1891 1892 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1893 1894 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1895 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1896 ictl_ctx[0], ictl_ctx[1]); 1897 return CC_TRB_ERROR; 1898 } 1899 1900 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1901 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1902 1903 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1904 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1905 1906 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1907 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1908 1909 uport = xhci_lookup_uport(xhci, slot_ctx); 1910 if (uport == NULL) { 1911 fprintf(stderr, "xhci: port not found\n"); 1912 return CC_TRB_ERROR; 1913 } 1914 1915 dev = uport->dev; 1916 if (!dev) { 1917 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1918 return CC_USB_TRANSACTION_ERROR; 1919 } 1920 1921 for (i = 0; i < xhci->numslots; i++) { 1922 if (xhci->slots[i].uport == uport) { 1923 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1924 uport->path, i+1); 1925 return CC_TRB_ERROR; 1926 } 1927 } 1928 1929 slot = &xhci->slots[slotid-1]; 1930 slot->uport = uport; 1931 slot->ctx = octx; 1932 1933 if (bsr) { 1934 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1935 } else { 1936 slot->devaddr = xhci->devaddr++; 1937 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1938 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1939 usb_device_handle_control(dev, NULL, 1940 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1941 slot->devaddr, 0, 0, NULL); 1942 } 1943 1944 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1945 1946 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1947 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1948 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1949 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1950 1951 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1952 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1953 1954 return res; 1955 } 1956 1957 1958 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1959 uint64_t pictx, bool dc) 1960 { 1961 dma_addr_t ictx, octx; 1962 uint32_t ictl_ctx[2]; 1963 uint32_t slot_ctx[4]; 1964 uint32_t islot_ctx[4]; 1965 uint32_t ep_ctx[5]; 1966 int i; 1967 TRBCCode res; 1968 1969 trace_usb_xhci_slot_configure(slotid); 1970 assert(slotid >= 1 && slotid <= xhci->numslots); 1971 1972 ictx = xhci_mask64(pictx); 1973 octx = xhci->slots[slotid-1].ctx; 1974 1975 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1976 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1977 1978 if (dc) { 1979 for (i = 2; i <= 31; i++) { 1980 if (xhci->slots[slotid-1].eps[i-1]) { 1981 xhci_disable_ep(xhci, slotid, i); 1982 } 1983 } 1984 1985 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1986 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1987 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1988 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1989 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1990 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1991 1992 return CC_SUCCESS; 1993 } 1994 1995 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1996 1997 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1998 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1999 ictl_ctx[0], ictl_ctx[1]); 2000 return CC_TRB_ERROR; 2001 } 2002 2003 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2004 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2005 2006 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2007 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2008 return CC_CONTEXT_STATE_ERROR; 2009 } 2010 2011 for (i = 2; i <= 31; i++) { 2012 if (ictl_ctx[0] & (1<<i)) { 2013 xhci_disable_ep(xhci, slotid, i); 2014 } 2015 if (ictl_ctx[1] & (1<<i)) { 2016 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 2017 sizeof(ep_ctx)); 2018 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2019 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2020 ep_ctx[3], ep_ctx[4]); 2021 xhci_disable_ep(xhci, slotid, i); 2022 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2023 if (res != CC_SUCCESS) { 2024 return res; 2025 } 2026 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2027 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2028 ep_ctx[3], ep_ctx[4]); 2029 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2030 } 2031 } 2032 2033 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2034 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2035 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2036 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2037 SLOT_CONTEXT_ENTRIES_SHIFT); 2038 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2039 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2040 2041 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2042 2043 return CC_SUCCESS; 2044 } 2045 2046 2047 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2048 uint64_t pictx) 2049 { 2050 dma_addr_t ictx, octx; 2051 uint32_t ictl_ctx[2]; 2052 uint32_t iep0_ctx[5]; 2053 uint32_t ep0_ctx[5]; 2054 uint32_t islot_ctx[4]; 2055 uint32_t slot_ctx[4]; 2056 2057 trace_usb_xhci_slot_evaluate(slotid); 2058 assert(slotid >= 1 && slotid <= xhci->numslots); 2059 2060 ictx = xhci_mask64(pictx); 2061 octx = xhci->slots[slotid-1].ctx; 2062 2063 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2064 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2065 2066 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 2067 2068 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2069 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2070 ictl_ctx[0], ictl_ctx[1]); 2071 return CC_TRB_ERROR; 2072 } 2073 2074 if (ictl_ctx[1] & 0x1) { 2075 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2076 2077 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2078 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2079 2080 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2081 2082 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2083 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2084 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2085 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2086 2087 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2088 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2089 2090 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2091 } 2092 2093 if (ictl_ctx[1] & 0x2) { 2094 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2095 2096 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2097 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2098 iep0_ctx[3], iep0_ctx[4]); 2099 2100 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2101 2102 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2103 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2104 2105 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2106 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2107 2108 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2109 } 2110 2111 return CC_SUCCESS; 2112 } 2113 2114 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2115 { 2116 uint32_t slot_ctx[4]; 2117 dma_addr_t octx; 2118 int i; 2119 2120 trace_usb_xhci_slot_reset(slotid); 2121 assert(slotid >= 1 && slotid <= xhci->numslots); 2122 2123 octx = xhci->slots[slotid-1].ctx; 2124 2125 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2126 2127 for (i = 2; i <= 31; i++) { 2128 if (xhci->slots[slotid-1].eps[i-1]) { 2129 xhci_disable_ep(xhci, slotid, i); 2130 } 2131 } 2132 2133 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2134 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2135 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2136 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2137 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2138 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2139 2140 return CC_SUCCESS; 2141 } 2142 2143 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2144 { 2145 unsigned int slotid; 2146 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2147 if (slotid < 1 || slotid > xhci->numslots) { 2148 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2149 event->ccode = CC_TRB_ERROR; 2150 return 0; 2151 } else if (!xhci->slots[slotid-1].enabled) { 2152 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2153 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2154 return 0; 2155 } 2156 return slotid; 2157 } 2158 2159 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2160 { 2161 dma_addr_t ctx; 2162 uint8_t bw_ctx[xhci->numports+1]; 2163 2164 DPRINTF("xhci_get_port_bandwidth()\n"); 2165 2166 ctx = xhci_mask64(pctx); 2167 2168 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2169 2170 /* TODO: actually implement real values here */ 2171 bw_ctx[0] = 0; 2172 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2173 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2174 2175 return CC_SUCCESS; 2176 } 2177 2178 static uint32_t rotl(uint32_t v, unsigned count) 2179 { 2180 count &= 31; 2181 return (v << count) | (v >> (32 - count)); 2182 } 2183 2184 2185 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2186 { 2187 uint32_t val; 2188 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2189 val += rotl(lo + 0x49434878, hi & 0x1F); 2190 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2191 return ~val; 2192 } 2193 2194 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2195 { 2196 uint32_t buf[8]; 2197 uint32_t obuf[8]; 2198 dma_addr_t paddr = xhci_mask64(addr); 2199 2200 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2201 2202 memcpy(obuf, buf, sizeof(obuf)); 2203 2204 if ((buf[0] & 0xff) == 2) { 2205 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2206 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2207 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2208 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2209 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2210 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2211 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2212 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2213 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2214 } 2215 2216 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2217 } 2218 2219 static void xhci_process_commands(XHCIState *xhci) 2220 { 2221 XHCITRB trb; 2222 TRBType type; 2223 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2224 dma_addr_t addr; 2225 unsigned int i, slotid = 0; 2226 2227 DPRINTF("xhci_process_commands()\n"); 2228 if (!xhci_running(xhci)) { 2229 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2230 return; 2231 } 2232 2233 xhci->crcr_low |= CRCR_CRR; 2234 2235 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2236 event.ptr = addr; 2237 switch (type) { 2238 case CR_ENABLE_SLOT: 2239 for (i = 0; i < xhci->numslots; i++) { 2240 if (!xhci->slots[i].enabled) { 2241 break; 2242 } 2243 } 2244 if (i >= xhci->numslots) { 2245 fprintf(stderr, "xhci: no device slots available\n"); 2246 event.ccode = CC_NO_SLOTS_ERROR; 2247 } else { 2248 slotid = i+1; 2249 event.ccode = xhci_enable_slot(xhci, slotid); 2250 } 2251 break; 2252 case CR_DISABLE_SLOT: 2253 slotid = xhci_get_slot(xhci, &event, &trb); 2254 if (slotid) { 2255 event.ccode = xhci_disable_slot(xhci, slotid); 2256 } 2257 break; 2258 case CR_ADDRESS_DEVICE: 2259 slotid = xhci_get_slot(xhci, &event, &trb); 2260 if (slotid) { 2261 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2262 trb.control & TRB_CR_BSR); 2263 } 2264 break; 2265 case CR_CONFIGURE_ENDPOINT: 2266 slotid = xhci_get_slot(xhci, &event, &trb); 2267 if (slotid) { 2268 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2269 trb.control & TRB_CR_DC); 2270 } 2271 break; 2272 case CR_EVALUATE_CONTEXT: 2273 slotid = xhci_get_slot(xhci, &event, &trb); 2274 if (slotid) { 2275 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2276 } 2277 break; 2278 case CR_STOP_ENDPOINT: 2279 slotid = xhci_get_slot(xhci, &event, &trb); 2280 if (slotid) { 2281 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2282 & TRB_CR_EPID_MASK; 2283 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2284 } 2285 break; 2286 case CR_RESET_ENDPOINT: 2287 slotid = xhci_get_slot(xhci, &event, &trb); 2288 if (slotid) { 2289 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2290 & TRB_CR_EPID_MASK; 2291 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2292 } 2293 break; 2294 case CR_SET_TR_DEQUEUE: 2295 slotid = xhci_get_slot(xhci, &event, &trb); 2296 if (slotid) { 2297 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2298 & TRB_CR_EPID_MASK; 2299 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2300 trb.parameter); 2301 } 2302 break; 2303 case CR_RESET_DEVICE: 2304 slotid = xhci_get_slot(xhci, &event, &trb); 2305 if (slotid) { 2306 event.ccode = xhci_reset_slot(xhci, slotid); 2307 } 2308 break; 2309 case CR_GET_PORT_BANDWIDTH: 2310 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2311 break; 2312 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2313 xhci_via_challenge(xhci, trb.parameter); 2314 break; 2315 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2316 event.type = 48; /* NEC reply */ 2317 event.length = 0x3025; 2318 break; 2319 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2320 { 2321 uint32_t chi = trb.parameter >> 32; 2322 uint32_t clo = trb.parameter; 2323 uint32_t val = xhci_nec_challenge(chi, clo); 2324 event.length = val & 0xFFFF; 2325 event.epid = val >> 16; 2326 slotid = val >> 24; 2327 event.type = 48; /* NEC reply */ 2328 } 2329 break; 2330 default: 2331 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2332 event.ccode = CC_TRB_ERROR; 2333 break; 2334 } 2335 event.slotid = slotid; 2336 xhci_event(xhci, &event, 0); 2337 } 2338 } 2339 2340 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2341 { 2342 port->portsc = PORTSC_PP; 2343 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2344 (1 << port->uport->dev->speed) & port->speedmask) { 2345 port->portsc |= PORTSC_CCS; 2346 switch (port->uport->dev->speed) { 2347 case USB_SPEED_LOW: 2348 port->portsc |= PORTSC_SPEED_LOW; 2349 break; 2350 case USB_SPEED_FULL: 2351 port->portsc |= PORTSC_SPEED_FULL; 2352 break; 2353 case USB_SPEED_HIGH: 2354 port->portsc |= PORTSC_SPEED_HIGH; 2355 break; 2356 case USB_SPEED_SUPER: 2357 port->portsc |= PORTSC_SPEED_SUPER; 2358 break; 2359 } 2360 } 2361 2362 if (xhci_running(port->xhci)) { 2363 port->portsc |= PORTSC_CSC; 2364 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2365 port->portnr << 24}; 2366 xhci_event(xhci, &ev, 0); 2367 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2368 } 2369 } 2370 2371 static void xhci_reset(DeviceState *dev) 2372 { 2373 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2374 int i; 2375 2376 trace_usb_xhci_reset(); 2377 if (!(xhci->usbsts & USBSTS_HCH)) { 2378 fprintf(stderr, "xhci: reset while running!\n"); 2379 } 2380 2381 xhci->usbcmd = 0; 2382 xhci->usbsts = USBSTS_HCH; 2383 xhci->dnctrl = 0; 2384 xhci->crcr_low = 0; 2385 xhci->crcr_high = 0; 2386 xhci->dcbaap_low = 0; 2387 xhci->dcbaap_high = 0; 2388 xhci->config = 0; 2389 xhci->devaddr = 2; 2390 2391 for (i = 0; i < xhci->numslots; i++) { 2392 xhci_disable_slot(xhci, i+1); 2393 } 2394 2395 for (i = 0; i < xhci->numports; i++) { 2396 xhci_update_port(xhci->ports + i, 0); 2397 } 2398 2399 for (i = 0; i < xhci->numintrs; i++) { 2400 xhci->intr[i].iman = 0; 2401 xhci->intr[i].imod = 0; 2402 xhci->intr[i].erstsz = 0; 2403 xhci->intr[i].erstba_low = 0; 2404 xhci->intr[i].erstba_high = 0; 2405 xhci->intr[i].erdp_low = 0; 2406 xhci->intr[i].erdp_high = 0; 2407 xhci->intr[i].msix_used = 0; 2408 2409 xhci->intr[i].er_ep_idx = 0; 2410 xhci->intr[i].er_pcs = 1; 2411 xhci->intr[i].er_full = 0; 2412 xhci->intr[i].ev_buffer_put = 0; 2413 xhci->intr[i].ev_buffer_get = 0; 2414 } 2415 2416 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2417 xhci_mfwrap_update(xhci); 2418 } 2419 2420 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2421 { 2422 XHCIState *xhci = ptr; 2423 uint32_t ret; 2424 2425 switch (reg) { 2426 case 0x00: /* HCIVERSION, CAPLENGTH */ 2427 ret = 0x01000000 | LEN_CAP; 2428 break; 2429 case 0x04: /* HCSPARAMS 1 */ 2430 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2431 | (xhci->numintrs<<8) | xhci->numslots; 2432 break; 2433 case 0x08: /* HCSPARAMS 2 */ 2434 ret = 0x0000000f; 2435 break; 2436 case 0x0c: /* HCSPARAMS 3 */ 2437 ret = 0x00000000; 2438 break; 2439 case 0x10: /* HCCPARAMS */ 2440 if (sizeof(dma_addr_t) == 4) { 2441 ret = 0x00081000; 2442 } else { 2443 ret = 0x00081001; 2444 } 2445 break; 2446 case 0x14: /* DBOFF */ 2447 ret = OFF_DOORBELL; 2448 break; 2449 case 0x18: /* RTSOFF */ 2450 ret = OFF_RUNTIME; 2451 break; 2452 2453 /* extended capabilities */ 2454 case 0x20: /* Supported Protocol:00 */ 2455 ret = 0x02000402; /* USB 2.0 */ 2456 break; 2457 case 0x24: /* Supported Protocol:04 */ 2458 ret = 0x20425355; /* "USB " */ 2459 break; 2460 case 0x28: /* Supported Protocol:08 */ 2461 ret = 0x00000001 | (xhci->numports_2<<8); 2462 break; 2463 case 0x2c: /* Supported Protocol:0c */ 2464 ret = 0x00000000; /* reserved */ 2465 break; 2466 case 0x30: /* Supported Protocol:00 */ 2467 ret = 0x03000002; /* USB 3.0 */ 2468 break; 2469 case 0x34: /* Supported Protocol:04 */ 2470 ret = 0x20425355; /* "USB " */ 2471 break; 2472 case 0x38: /* Supported Protocol:08 */ 2473 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2474 break; 2475 case 0x3c: /* Supported Protocol:0c */ 2476 ret = 0x00000000; /* reserved */ 2477 break; 2478 default: 2479 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2480 ret = 0; 2481 } 2482 2483 trace_usb_xhci_cap_read(reg, ret); 2484 return ret; 2485 } 2486 2487 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2488 { 2489 XHCIPort *port = ptr; 2490 uint32_t ret; 2491 2492 switch (reg) { 2493 case 0x00: /* PORTSC */ 2494 ret = port->portsc; 2495 break; 2496 case 0x04: /* PORTPMSC */ 2497 case 0x08: /* PORTLI */ 2498 ret = 0; 2499 break; 2500 case 0x0c: /* reserved */ 2501 default: 2502 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2503 port->portnr, (uint32_t)reg); 2504 ret = 0; 2505 } 2506 2507 trace_usb_xhci_port_read(port->portnr, reg, ret); 2508 return ret; 2509 } 2510 2511 static void xhci_port_write(void *ptr, hwaddr reg, 2512 uint64_t val, unsigned size) 2513 { 2514 XHCIPort *port = ptr; 2515 uint32_t portsc; 2516 2517 trace_usb_xhci_port_write(port->portnr, reg, val); 2518 2519 switch (reg) { 2520 case 0x00: /* PORTSC */ 2521 portsc = port->portsc; 2522 /* write-1-to-clear bits*/ 2523 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2524 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2525 if (val & PORTSC_LWS) { 2526 /* overwrite PLS only when LWS=1 */ 2527 uint32_t pls = get_field(val, PORTSC_PLS); 2528 set_field(&portsc, pls, PORTSC_PLS); 2529 } 2530 /* read/write bits */ 2531 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2532 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2533 /* write-1-to-start bits */ 2534 if (val & PORTSC_PR) { 2535 DPRINTF("xhci: port %d reset\n", port); 2536 usb_device_reset(port->uport->dev); 2537 portsc |= PORTSC_PRC | PORTSC_PED; 2538 } 2539 port->portsc = portsc; 2540 break; 2541 case 0x04: /* PORTPMSC */ 2542 case 0x08: /* PORTLI */ 2543 default: 2544 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2545 port->portnr, (uint32_t)reg); 2546 } 2547 } 2548 2549 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2550 { 2551 XHCIState *xhci = ptr; 2552 uint32_t ret; 2553 2554 switch (reg) { 2555 case 0x00: /* USBCMD */ 2556 ret = xhci->usbcmd; 2557 break; 2558 case 0x04: /* USBSTS */ 2559 ret = xhci->usbsts; 2560 break; 2561 case 0x08: /* PAGESIZE */ 2562 ret = 1; /* 4KiB */ 2563 break; 2564 case 0x14: /* DNCTRL */ 2565 ret = xhci->dnctrl; 2566 break; 2567 case 0x18: /* CRCR low */ 2568 ret = xhci->crcr_low & ~0xe; 2569 break; 2570 case 0x1c: /* CRCR high */ 2571 ret = xhci->crcr_high; 2572 break; 2573 case 0x30: /* DCBAAP low */ 2574 ret = xhci->dcbaap_low; 2575 break; 2576 case 0x34: /* DCBAAP high */ 2577 ret = xhci->dcbaap_high; 2578 break; 2579 case 0x38: /* CONFIG */ 2580 ret = xhci->config; 2581 break; 2582 default: 2583 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2584 ret = 0; 2585 } 2586 2587 trace_usb_xhci_oper_read(reg, ret); 2588 return ret; 2589 } 2590 2591 static void xhci_oper_write(void *ptr, hwaddr reg, 2592 uint64_t val, unsigned size) 2593 { 2594 XHCIState *xhci = ptr; 2595 2596 trace_usb_xhci_oper_write(reg, val); 2597 2598 switch (reg) { 2599 case 0x00: /* USBCMD */ 2600 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2601 xhci_run(xhci); 2602 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2603 xhci_stop(xhci); 2604 } 2605 xhci->usbcmd = val & 0xc0f; 2606 xhci_mfwrap_update(xhci); 2607 if (val & USBCMD_HCRST) { 2608 xhci_reset(&xhci->pci_dev.qdev); 2609 } 2610 xhci_intx_update(xhci); 2611 break; 2612 2613 case 0x04: /* USBSTS */ 2614 /* these bits are write-1-to-clear */ 2615 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2616 xhci_intx_update(xhci); 2617 break; 2618 2619 case 0x14: /* DNCTRL */ 2620 xhci->dnctrl = val & 0xffff; 2621 break; 2622 case 0x18: /* CRCR low */ 2623 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2624 break; 2625 case 0x1c: /* CRCR high */ 2626 xhci->crcr_high = val; 2627 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2628 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2629 xhci->crcr_low &= ~CRCR_CRR; 2630 xhci_event(xhci, &event, 0); 2631 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2632 } else { 2633 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2634 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2635 } 2636 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2637 break; 2638 case 0x30: /* DCBAAP low */ 2639 xhci->dcbaap_low = val & 0xffffffc0; 2640 break; 2641 case 0x34: /* DCBAAP high */ 2642 xhci->dcbaap_high = val; 2643 break; 2644 case 0x38: /* CONFIG */ 2645 xhci->config = val & 0xff; 2646 break; 2647 default: 2648 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2649 } 2650 } 2651 2652 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2653 unsigned size) 2654 { 2655 XHCIState *xhci = ptr; 2656 uint32_t ret = 0; 2657 2658 if (reg < 0x20) { 2659 switch (reg) { 2660 case 0x00: /* MFINDEX */ 2661 ret = xhci_mfindex_get(xhci) & 0x3fff; 2662 break; 2663 default: 2664 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2665 (int)reg); 2666 break; 2667 } 2668 } else { 2669 int v = (reg - 0x20) / 0x20; 2670 XHCIInterrupter *intr = &xhci->intr[v]; 2671 switch (reg & 0x1f) { 2672 case 0x00: /* IMAN */ 2673 ret = intr->iman; 2674 break; 2675 case 0x04: /* IMOD */ 2676 ret = intr->imod; 2677 break; 2678 case 0x08: /* ERSTSZ */ 2679 ret = intr->erstsz; 2680 break; 2681 case 0x10: /* ERSTBA low */ 2682 ret = intr->erstba_low; 2683 break; 2684 case 0x14: /* ERSTBA high */ 2685 ret = intr->erstba_high; 2686 break; 2687 case 0x18: /* ERDP low */ 2688 ret = intr->erdp_low; 2689 break; 2690 case 0x1c: /* ERDP high */ 2691 ret = intr->erdp_high; 2692 break; 2693 } 2694 } 2695 2696 trace_usb_xhci_runtime_read(reg, ret); 2697 return ret; 2698 } 2699 2700 static void xhci_runtime_write(void *ptr, hwaddr reg, 2701 uint64_t val, unsigned size) 2702 { 2703 XHCIState *xhci = ptr; 2704 int v = (reg - 0x20) / 0x20; 2705 XHCIInterrupter *intr = &xhci->intr[v]; 2706 trace_usb_xhci_runtime_write(reg, val); 2707 2708 if (reg < 0x20) { 2709 fprintf(stderr, "%s: reg 0x%x unimplemented\n", __func__, (int)reg); 2710 return; 2711 } 2712 2713 switch (reg & 0x1f) { 2714 case 0x00: /* IMAN */ 2715 if (val & IMAN_IP) { 2716 intr->iman &= ~IMAN_IP; 2717 } 2718 intr->iman &= ~IMAN_IE; 2719 intr->iman |= val & IMAN_IE; 2720 if (v == 0) { 2721 xhci_intx_update(xhci); 2722 } 2723 xhci_msix_update(xhci, v); 2724 break; 2725 case 0x04: /* IMOD */ 2726 intr->imod = val; 2727 break; 2728 case 0x08: /* ERSTSZ */ 2729 intr->erstsz = val & 0xffff; 2730 break; 2731 case 0x10: /* ERSTBA low */ 2732 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2733 intr->erstba_low = val & 0xffffffc0; */ 2734 intr->erstba_low = val & 0xfffffff0; 2735 break; 2736 case 0x14: /* ERSTBA high */ 2737 intr->erstba_high = val; 2738 xhci_er_reset(xhci, v); 2739 break; 2740 case 0x18: /* ERDP low */ 2741 if (val & ERDP_EHB) { 2742 intr->erdp_low &= ~ERDP_EHB; 2743 } 2744 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2745 break; 2746 case 0x1c: /* ERDP high */ 2747 intr->erdp_high = val; 2748 xhci_events_update(xhci, v); 2749 break; 2750 default: 2751 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2752 (int)reg); 2753 } 2754 } 2755 2756 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 2757 unsigned size) 2758 { 2759 /* doorbells always read as 0 */ 2760 trace_usb_xhci_doorbell_read(reg, 0); 2761 return 0; 2762 } 2763 2764 static void xhci_doorbell_write(void *ptr, hwaddr reg, 2765 uint64_t val, unsigned size) 2766 { 2767 XHCIState *xhci = ptr; 2768 2769 trace_usb_xhci_doorbell_write(reg, val); 2770 2771 if (!xhci_running(xhci)) { 2772 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2773 return; 2774 } 2775 2776 reg >>= 2; 2777 2778 if (reg == 0) { 2779 if (val == 0) { 2780 xhci_process_commands(xhci); 2781 } else { 2782 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2783 (uint32_t)val); 2784 } 2785 } else { 2786 if (reg > xhci->numslots) { 2787 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2788 } else if (val > 31) { 2789 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2790 (int)reg, (uint32_t)val); 2791 } else { 2792 xhci_kick_ep(xhci, reg, val); 2793 } 2794 } 2795 } 2796 2797 static const MemoryRegionOps xhci_cap_ops = { 2798 .read = xhci_cap_read, 2799 .valid.min_access_size = 1, 2800 .valid.max_access_size = 4, 2801 .impl.min_access_size = 4, 2802 .impl.max_access_size = 4, 2803 .endianness = DEVICE_LITTLE_ENDIAN, 2804 }; 2805 2806 static const MemoryRegionOps xhci_oper_ops = { 2807 .read = xhci_oper_read, 2808 .write = xhci_oper_write, 2809 .valid.min_access_size = 4, 2810 .valid.max_access_size = 4, 2811 .endianness = DEVICE_LITTLE_ENDIAN, 2812 }; 2813 2814 static const MemoryRegionOps xhci_port_ops = { 2815 .read = xhci_port_read, 2816 .write = xhci_port_write, 2817 .valid.min_access_size = 4, 2818 .valid.max_access_size = 4, 2819 .endianness = DEVICE_LITTLE_ENDIAN, 2820 }; 2821 2822 static const MemoryRegionOps xhci_runtime_ops = { 2823 .read = xhci_runtime_read, 2824 .write = xhci_runtime_write, 2825 .valid.min_access_size = 4, 2826 .valid.max_access_size = 4, 2827 .endianness = DEVICE_LITTLE_ENDIAN, 2828 }; 2829 2830 static const MemoryRegionOps xhci_doorbell_ops = { 2831 .read = xhci_doorbell_read, 2832 .write = xhci_doorbell_write, 2833 .valid.min_access_size = 4, 2834 .valid.max_access_size = 4, 2835 .endianness = DEVICE_LITTLE_ENDIAN, 2836 }; 2837 2838 static void xhci_attach(USBPort *usbport) 2839 { 2840 XHCIState *xhci = usbport->opaque; 2841 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2842 2843 xhci_update_port(xhci, port, 0); 2844 } 2845 2846 static void xhci_detach(USBPort *usbport) 2847 { 2848 XHCIState *xhci = usbport->opaque; 2849 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2850 2851 xhci_update_port(xhci, port, 1); 2852 } 2853 2854 static void xhci_wakeup(USBPort *usbport) 2855 { 2856 XHCIState *xhci = usbport->opaque; 2857 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2858 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2859 port->portnr << 24}; 2860 2861 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 2862 return; 2863 } 2864 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 2865 if (port->portsc & PORTSC_PLC) { 2866 return; 2867 } 2868 port->portsc |= PORTSC_PLC; 2869 xhci_event(xhci, &ev, 0); 2870 } 2871 2872 static void xhci_complete(USBPort *port, USBPacket *packet) 2873 { 2874 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2875 2876 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) { 2877 xhci_ep_nuke_one_xfer(xfer); 2878 return; 2879 } 2880 xhci_complete_packet(xfer, packet->result); 2881 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2882 } 2883 2884 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2885 { 2886 USBBus *bus = usb_bus_from_device(child); 2887 XHCIState *xhci = container_of(bus, XHCIState, bus); 2888 int i; 2889 2890 for (i = 0; i < xhci->numslots; i++) { 2891 if (xhci->slots[i].uport == uport) { 2892 xhci->slots[i].uport = NULL; 2893 } 2894 } 2895 } 2896 2897 static USBPortOps xhci_uport_ops = { 2898 .attach = xhci_attach, 2899 .detach = xhci_detach, 2900 .wakeup = xhci_wakeup, 2901 .complete = xhci_complete, 2902 .child_detach = xhci_child_detach, 2903 }; 2904 2905 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2906 { 2907 XHCISlot *slot; 2908 int slotid; 2909 2910 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 2911 slot = &xhci->slots[slotid-1]; 2912 if (slot->devaddr == dev->addr) { 2913 return slotid; 2914 } 2915 } 2916 return 0; 2917 } 2918 2919 static int xhci_find_epid(USBEndpoint *ep) 2920 { 2921 if (ep->nr == 0) { 2922 return 1; 2923 } 2924 if (ep->pid == USB_TOKEN_IN) { 2925 return ep->nr * 2 + 1; 2926 } else { 2927 return ep->nr * 2; 2928 } 2929 } 2930 2931 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2932 { 2933 XHCIState *xhci = container_of(bus, XHCIState, bus); 2934 int slotid; 2935 2936 DPRINTF("%s\n", __func__); 2937 slotid = xhci_find_slotid(xhci, ep->dev); 2938 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2939 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2940 return; 2941 } 2942 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2943 } 2944 2945 static USBBusOps xhci_bus_ops = { 2946 .wakeup_endpoint = xhci_wakeup_endpoint, 2947 }; 2948 2949 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2950 { 2951 XHCIPort *port; 2952 int i, usbports, speedmask; 2953 2954 xhci->usbsts = USBSTS_HCH; 2955 2956 if (xhci->numports_2 > MAXPORTS_2) { 2957 xhci->numports_2 = MAXPORTS_2; 2958 } 2959 if (xhci->numports_3 > MAXPORTS_3) { 2960 xhci->numports_3 = MAXPORTS_3; 2961 } 2962 usbports = MAX(xhci->numports_2, xhci->numports_3); 2963 xhci->numports = xhci->numports_2 + xhci->numports_3; 2964 2965 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2966 2967 for (i = 0; i < usbports; i++) { 2968 speedmask = 0; 2969 if (i < xhci->numports_2) { 2970 port = &xhci->ports[i]; 2971 port->portnr = i + 1; 2972 port->uport = &xhci->uports[i]; 2973 port->speedmask = 2974 USB_SPEED_MASK_LOW | 2975 USB_SPEED_MASK_FULL | 2976 USB_SPEED_MASK_HIGH; 2977 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 2978 speedmask |= port->speedmask; 2979 } 2980 if (i < xhci->numports_3) { 2981 port = &xhci->ports[i + xhci->numports_2]; 2982 port->portnr = i + 1 + xhci->numports_2; 2983 port->uport = &xhci->uports[i]; 2984 port->speedmask = USB_SPEED_MASK_SUPER; 2985 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 2986 speedmask |= port->speedmask; 2987 } 2988 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2989 &xhci_uport_ops, speedmask); 2990 } 2991 } 2992 2993 static int usb_xhci_initfn(struct PCIDevice *dev) 2994 { 2995 int i, ret; 2996 2997 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2998 2999 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3000 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3001 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 3002 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 3003 3004 usb_xhci_init(xhci, &dev->qdev); 3005 3006 if (xhci->numintrs > MAXINTRS) { 3007 xhci->numintrs = MAXINTRS; 3008 } 3009 if (xhci->numintrs < 1) { 3010 xhci->numintrs = 1; 3011 } 3012 if (xhci->numslots > MAXSLOTS) { 3013 xhci->numslots = MAXSLOTS; 3014 } 3015 if (xhci->numslots < 1) { 3016 xhci->numslots = 1; 3017 } 3018 3019 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 3020 3021 xhci->irq = xhci->pci_dev.irq[0]; 3022 3023 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 3024 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 3025 "capabilities", LEN_CAP); 3026 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 3027 "operational", 0x400); 3028 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 3029 "runtime", LEN_RUNTIME); 3030 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 3031 "doorbell", LEN_DOORBELL); 3032 3033 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3034 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3035 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3036 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3037 3038 for (i = 0; i < xhci->numports; i++) { 3039 XHCIPort *port = &xhci->ports[i]; 3040 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3041 port->xhci = xhci; 3042 memory_region_init_io(&port->mem, &xhci_port_ops, port, 3043 port->name, 0x10); 3044 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3045 } 3046 3047 pci_register_bar(&xhci->pci_dev, 0, 3048 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3049 &xhci->mem); 3050 3051 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 3052 assert(ret >= 0); 3053 3054 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3055 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); 3056 } 3057 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3058 msix_init(&xhci->pci_dev, xhci->numintrs, 3059 &xhci->mem, 0, OFF_MSIX_TABLE, 3060 &xhci->mem, 0, OFF_MSIX_PBA, 3061 0x90); 3062 } 3063 3064 return 0; 3065 } 3066 3067 static const VMStateDescription vmstate_xhci = { 3068 .name = "xhci", 3069 .unmigratable = 1, 3070 }; 3071 3072 static Property xhci_properties[] = { 3073 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3074 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3075 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3076 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3077 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3078 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3079 DEFINE_PROP_END_OF_LIST(), 3080 }; 3081 3082 static void xhci_class_init(ObjectClass *klass, void *data) 3083 { 3084 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3085 DeviceClass *dc = DEVICE_CLASS(klass); 3086 3087 dc->vmsd = &vmstate_xhci; 3088 dc->props = xhci_properties; 3089 dc->reset = xhci_reset; 3090 k->init = usb_xhci_initfn; 3091 k->vendor_id = PCI_VENDOR_ID_NEC; 3092 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3093 k->class_id = PCI_CLASS_SERIAL_USB; 3094 k->revision = 0x03; 3095 k->is_express = 1; 3096 } 3097 3098 static TypeInfo xhci_info = { 3099 .name = "nec-usb-xhci", 3100 .parent = TYPE_PCI_DEVICE, 3101 .instance_size = sizeof(XHCIState), 3102 .class_init = xhci_class_init, 3103 }; 3104 3105 static void xhci_register_types(void) 3106 { 3107 type_register_static(&xhci_info); 3108 } 3109 3110 type_init(xhci_register_types) 3111