1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 150 typedef enum TRBType { 151 TRB_RESERVED = 0, 152 TR_NORMAL, 153 TR_SETUP, 154 TR_DATA, 155 TR_STATUS, 156 TR_ISOCH, 157 TR_LINK, 158 TR_EVDATA, 159 TR_NOOP, 160 CR_ENABLE_SLOT, 161 CR_DISABLE_SLOT, 162 CR_ADDRESS_DEVICE, 163 CR_CONFIGURE_ENDPOINT, 164 CR_EVALUATE_CONTEXT, 165 CR_RESET_ENDPOINT, 166 CR_STOP_ENDPOINT, 167 CR_SET_TR_DEQUEUE, 168 CR_RESET_DEVICE, 169 CR_FORCE_EVENT, 170 CR_NEGOTIATE_BW, 171 CR_SET_LATENCY_TOLERANCE, 172 CR_GET_PORT_BANDWIDTH, 173 CR_FORCE_HEADER, 174 CR_NOOP, 175 ER_TRANSFER = 32, 176 ER_COMMAND_COMPLETE, 177 ER_PORT_STATUS_CHANGE, 178 ER_BANDWIDTH_REQUEST, 179 ER_DOORBELL, 180 ER_HOST_CONTROLLER, 181 ER_DEVICE_NOTIFICATION, 182 ER_MFINDEX_WRAP, 183 /* vendor specific bits */ 184 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 185 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 186 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 187 } TRBType; 188 189 #define CR_LINK TR_LINK 190 191 typedef enum TRBCCode { 192 CC_INVALID = 0, 193 CC_SUCCESS, 194 CC_DATA_BUFFER_ERROR, 195 CC_BABBLE_DETECTED, 196 CC_USB_TRANSACTION_ERROR, 197 CC_TRB_ERROR, 198 CC_STALL_ERROR, 199 CC_RESOURCE_ERROR, 200 CC_BANDWIDTH_ERROR, 201 CC_NO_SLOTS_ERROR, 202 CC_INVALID_STREAM_TYPE_ERROR, 203 CC_SLOT_NOT_ENABLED_ERROR, 204 CC_EP_NOT_ENABLED_ERROR, 205 CC_SHORT_PACKET, 206 CC_RING_UNDERRUN, 207 CC_RING_OVERRUN, 208 CC_VF_ER_FULL, 209 CC_PARAMETER_ERROR, 210 CC_BANDWIDTH_OVERRUN, 211 CC_CONTEXT_STATE_ERROR, 212 CC_NO_PING_RESPONSE_ERROR, 213 CC_EVENT_RING_FULL_ERROR, 214 CC_INCOMPATIBLE_DEVICE_ERROR, 215 CC_MISSED_SERVICE_ERROR, 216 CC_COMMAND_RING_STOPPED, 217 CC_COMMAND_ABORTED, 218 CC_STOPPED, 219 CC_STOPPED_LENGTH_INVALID, 220 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 221 CC_ISOCH_BUFFER_OVERRUN = 31, 222 CC_EVENT_LOST_ERROR, 223 CC_UNDEFINED_ERROR, 224 CC_INVALID_STREAM_ID_ERROR, 225 CC_SECONDARY_BANDWIDTH_ERROR, 226 CC_SPLIT_TRANSACTION_ERROR 227 } TRBCCode; 228 229 #define TRB_C (1<<0) 230 #define TRB_TYPE_SHIFT 10 231 #define TRB_TYPE_MASK 0x3f 232 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 233 234 #define TRB_EV_ED (1<<2) 235 236 #define TRB_TR_ENT (1<<1) 237 #define TRB_TR_ISP (1<<2) 238 #define TRB_TR_NS (1<<3) 239 #define TRB_TR_CH (1<<4) 240 #define TRB_TR_IOC (1<<5) 241 #define TRB_TR_IDT (1<<6) 242 #define TRB_TR_TBC_SHIFT 7 243 #define TRB_TR_TBC_MASK 0x3 244 #define TRB_TR_BEI (1<<9) 245 #define TRB_TR_TLBPC_SHIFT 16 246 #define TRB_TR_TLBPC_MASK 0xf 247 #define TRB_TR_FRAMEID_SHIFT 20 248 #define TRB_TR_FRAMEID_MASK 0x7ff 249 #define TRB_TR_SIA (1<<31) 250 251 #define TRB_TR_DIR (1<<16) 252 253 #define TRB_CR_SLOTID_SHIFT 24 254 #define TRB_CR_SLOTID_MASK 0xff 255 #define TRB_CR_EPID_SHIFT 16 256 #define TRB_CR_EPID_MASK 0x1f 257 258 #define TRB_CR_BSR (1<<9) 259 #define TRB_CR_DC (1<<9) 260 261 #define TRB_LK_TC (1<<1) 262 263 #define TRB_INTR_SHIFT 22 264 #define TRB_INTR_MASK 0x3ff 265 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef struct XHCIState XHCIState; 289 290 typedef enum EPType { 291 ET_INVALID = 0, 292 ET_ISO_OUT, 293 ET_BULK_OUT, 294 ET_INTR_OUT, 295 ET_CONTROL, 296 ET_ISO_IN, 297 ET_BULK_IN, 298 ET_INTR_IN, 299 } EPType; 300 301 typedef struct XHCIRing { 302 dma_addr_t base; 303 dma_addr_t dequeue; 304 bool ccs; 305 } XHCIRing; 306 307 typedef struct XHCIPort { 308 XHCIState *xhci; 309 uint32_t portsc; 310 uint32_t portnr; 311 USBPort *uport; 312 uint32_t speedmask; 313 char name[16]; 314 MemoryRegion mem; 315 } XHCIPort; 316 317 typedef struct XHCITransfer { 318 XHCIState *xhci; 319 USBPacket packet; 320 QEMUSGList sgl; 321 bool running_async; 322 bool running_retry; 323 bool cancelled; 324 bool complete; 325 unsigned int iso_pkts; 326 unsigned int slotid; 327 unsigned int epid; 328 bool in_xfer; 329 bool iso_xfer; 330 331 unsigned int trb_count; 332 unsigned int trb_alloced; 333 XHCITRB *trbs; 334 335 TRBCCode status; 336 337 unsigned int pkts; 338 unsigned int pktsize; 339 unsigned int cur_pkt; 340 341 uint64_t mfindex_kick; 342 } XHCITransfer; 343 344 typedef struct XHCIEPContext { 345 XHCIState *xhci; 346 unsigned int slotid; 347 unsigned int epid; 348 349 XHCIRing ring; 350 unsigned int next_xfer; 351 unsigned int comp_xfer; 352 XHCITransfer transfers[TD_QUEUE]; 353 XHCITransfer *retry; 354 EPType type; 355 dma_addr_t pctx; 356 unsigned int max_psize; 357 uint32_t state; 358 359 /* iso xfer scheduling */ 360 unsigned int interval; 361 int64_t mfindex_last; 362 QEMUTimer *kick_timer; 363 } XHCIEPContext; 364 365 typedef struct XHCISlot { 366 bool enabled; 367 dma_addr_t ctx; 368 USBPort *uport; 369 unsigned int devaddr; 370 XHCIEPContext * eps[31]; 371 } XHCISlot; 372 373 typedef struct XHCIEvent { 374 TRBType type; 375 TRBCCode ccode; 376 uint64_t ptr; 377 uint32_t length; 378 uint32_t flags; 379 uint8_t slotid; 380 uint8_t epid; 381 } XHCIEvent; 382 383 typedef struct XHCIInterrupter { 384 uint32_t iman; 385 uint32_t imod; 386 uint32_t erstsz; 387 uint32_t erstba_low; 388 uint32_t erstba_high; 389 uint32_t erdp_low; 390 uint32_t erdp_high; 391 392 bool msix_used, er_pcs, er_full; 393 394 dma_addr_t er_start; 395 uint32_t er_size; 396 unsigned int er_ep_idx; 397 398 XHCIEvent ev_buffer[EV_QUEUE]; 399 unsigned int ev_buffer_put; 400 unsigned int ev_buffer_get; 401 402 } XHCIInterrupter; 403 404 struct XHCIState { 405 PCIDevice pci_dev; 406 USBBus bus; 407 qemu_irq irq; 408 MemoryRegion mem; 409 MemoryRegion mem_cap; 410 MemoryRegion mem_oper; 411 MemoryRegion mem_runtime; 412 MemoryRegion mem_doorbell; 413 const char *name; 414 unsigned int devaddr; 415 416 /* properties */ 417 uint32_t numports_2; 418 uint32_t numports_3; 419 uint32_t flags; 420 421 /* Operational Registers */ 422 uint32_t usbcmd; 423 uint32_t usbsts; 424 uint32_t dnctrl; 425 uint32_t crcr_low; 426 uint32_t crcr_high; 427 uint32_t dcbaap_low; 428 uint32_t dcbaap_high; 429 uint32_t config; 430 431 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 432 XHCIPort ports[MAXPORTS]; 433 XHCISlot slots[MAXSLOTS]; 434 uint32_t numports; 435 436 /* Runtime Registers */ 437 int64_t mfindex_start; 438 QEMUTimer *mfwrap_timer; 439 XHCIInterrupter intr[MAXINTRS]; 440 441 XHCIRing cmd_ring; 442 }; 443 444 typedef struct XHCIEvRingSeg { 445 uint32_t addr_low; 446 uint32_t addr_high; 447 uint32_t size; 448 uint32_t rsvd; 449 } XHCIEvRingSeg; 450 451 enum xhci_flags { 452 XHCI_FLAG_USE_MSI = 1, 453 XHCI_FLAG_USE_MSI_X, 454 }; 455 456 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 457 unsigned int epid); 458 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 459 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 460 461 static const char *TRBType_names[] = { 462 [TRB_RESERVED] = "TRB_RESERVED", 463 [TR_NORMAL] = "TR_NORMAL", 464 [TR_SETUP] = "TR_SETUP", 465 [TR_DATA] = "TR_DATA", 466 [TR_STATUS] = "TR_STATUS", 467 [TR_ISOCH] = "TR_ISOCH", 468 [TR_LINK] = "TR_LINK", 469 [TR_EVDATA] = "TR_EVDATA", 470 [TR_NOOP] = "TR_NOOP", 471 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 472 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 473 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 474 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 475 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 476 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 477 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 478 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 479 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 480 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 481 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 482 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 483 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 484 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 485 [CR_NOOP] = "CR_NOOP", 486 [ER_TRANSFER] = "ER_TRANSFER", 487 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 488 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 489 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 490 [ER_DOORBELL] = "ER_DOORBELL", 491 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 492 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 493 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 494 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 495 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 496 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 497 }; 498 499 static const char *TRBCCode_names[] = { 500 [CC_INVALID] = "CC_INVALID", 501 [CC_SUCCESS] = "CC_SUCCESS", 502 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 503 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 504 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 505 [CC_TRB_ERROR] = "CC_TRB_ERROR", 506 [CC_STALL_ERROR] = "CC_STALL_ERROR", 507 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 508 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 509 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 510 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 511 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 512 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 513 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 514 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 515 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 516 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 517 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 518 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 519 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 520 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 521 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 522 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 523 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 524 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 525 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 526 [CC_STOPPED] = "CC_STOPPED", 527 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 528 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 529 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 530 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 531 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 532 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 533 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 534 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 535 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 536 }; 537 538 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 539 { 540 if (index >= llen || list[index] == NULL) { 541 return "???"; 542 } 543 return list[index]; 544 } 545 546 static const char *trb_name(XHCITRB *trb) 547 { 548 return lookup_name(TRB_TYPE(*trb), TRBType_names, 549 ARRAY_SIZE(TRBType_names)); 550 } 551 552 static const char *event_name(XHCIEvent *event) 553 { 554 return lookup_name(event->ccode, TRBCCode_names, 555 ARRAY_SIZE(TRBCCode_names)); 556 } 557 558 static uint64_t xhci_mfindex_get(XHCIState *xhci) 559 { 560 int64_t now = qemu_get_clock_ns(vm_clock); 561 return (now - xhci->mfindex_start) / 125000; 562 } 563 564 static void xhci_mfwrap_update(XHCIState *xhci) 565 { 566 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 567 uint32_t mfindex, left; 568 int64_t now; 569 570 if ((xhci->usbcmd & bits) == bits) { 571 now = qemu_get_clock_ns(vm_clock); 572 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 573 left = 0x4000 - mfindex; 574 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 575 } else { 576 qemu_del_timer(xhci->mfwrap_timer); 577 } 578 } 579 580 static void xhci_mfwrap_timer(void *opaque) 581 { 582 XHCIState *xhci = opaque; 583 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 584 585 xhci_event(xhci, &wrap, 0); 586 xhci_mfwrap_update(xhci); 587 } 588 589 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 590 { 591 if (sizeof(dma_addr_t) == 4) { 592 return low; 593 } else { 594 return low | (((dma_addr_t)high << 16) << 16); 595 } 596 } 597 598 static inline dma_addr_t xhci_mask64(uint64_t addr) 599 { 600 if (sizeof(dma_addr_t) == 4) { 601 return addr & 0xffffffff; 602 } else { 603 return addr; 604 } 605 } 606 607 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 608 { 609 int index; 610 611 if (!uport->dev) { 612 return NULL; 613 } 614 switch (uport->dev->speed) { 615 case USB_SPEED_LOW: 616 case USB_SPEED_FULL: 617 case USB_SPEED_HIGH: 618 index = uport->index; 619 break; 620 case USB_SPEED_SUPER: 621 index = uport->index + xhci->numports_2; 622 break; 623 default: 624 return NULL; 625 } 626 return &xhci->ports[index]; 627 } 628 629 static void xhci_intx_update(XHCIState *xhci) 630 { 631 int level = 0; 632 633 if (msix_enabled(&xhci->pci_dev) || 634 msi_enabled(&xhci->pci_dev)) { 635 return; 636 } 637 638 if (xhci->intr[0].iman & IMAN_IP && 639 xhci->intr[0].iman & IMAN_IE && 640 xhci->usbcmd & USBCMD_INTE) { 641 level = 1; 642 } 643 644 trace_usb_xhci_irq_intx(level); 645 qemu_set_irq(xhci->irq, level); 646 } 647 648 static void xhci_msix_update(XHCIState *xhci, int v) 649 { 650 bool enabled; 651 652 if (!msix_enabled(&xhci->pci_dev)) { 653 return; 654 } 655 656 enabled = xhci->intr[v].iman & IMAN_IE; 657 if (enabled == xhci->intr[v].msix_used) { 658 return; 659 } 660 661 if (enabled) { 662 trace_usb_xhci_irq_msix_use(v); 663 msix_vector_use(&xhci->pci_dev, v); 664 xhci->intr[v].msix_used = true; 665 } else { 666 trace_usb_xhci_irq_msix_unuse(v); 667 msix_vector_unuse(&xhci->pci_dev, v); 668 xhci->intr[v].msix_used = false; 669 } 670 } 671 672 static void xhci_intr_raise(XHCIState *xhci, int v) 673 { 674 xhci->intr[v].erdp_low |= ERDP_EHB; 675 xhci->intr[v].iman |= IMAN_IP; 676 xhci->usbsts |= USBSTS_EINT; 677 678 if (!(xhci->intr[v].iman & IMAN_IE)) { 679 return; 680 } 681 682 if (!(xhci->usbcmd & USBCMD_INTE)) { 683 return; 684 } 685 686 if (msix_enabled(&xhci->pci_dev)) { 687 trace_usb_xhci_irq_msix(v); 688 msix_notify(&xhci->pci_dev, v); 689 return; 690 } 691 692 if (msi_enabled(&xhci->pci_dev)) { 693 trace_usb_xhci_irq_msi(v); 694 msi_notify(&xhci->pci_dev, v); 695 return; 696 } 697 698 if (v == 0) { 699 trace_usb_xhci_irq_intx(1); 700 qemu_set_irq(xhci->irq, 1); 701 } 702 } 703 704 static inline int xhci_running(XHCIState *xhci) 705 { 706 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 707 } 708 709 static void xhci_die(XHCIState *xhci) 710 { 711 xhci->usbsts |= USBSTS_HCE; 712 fprintf(stderr, "xhci: asserted controller error\n"); 713 } 714 715 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 716 { 717 XHCIInterrupter *intr = &xhci->intr[v]; 718 XHCITRB ev_trb; 719 dma_addr_t addr; 720 721 ev_trb.parameter = cpu_to_le64(event->ptr); 722 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 723 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 724 event->flags | (event->type << TRB_TYPE_SHIFT); 725 if (intr->er_pcs) { 726 ev_trb.control |= TRB_C; 727 } 728 ev_trb.control = cpu_to_le32(ev_trb.control); 729 730 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 731 event_name(event), ev_trb.parameter, 732 ev_trb.status, ev_trb.control); 733 734 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 735 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 736 737 intr->er_ep_idx++; 738 if (intr->er_ep_idx >= intr->er_size) { 739 intr->er_ep_idx = 0; 740 intr->er_pcs = !intr->er_pcs; 741 } 742 } 743 744 static void xhci_events_update(XHCIState *xhci, int v) 745 { 746 XHCIInterrupter *intr = &xhci->intr[v]; 747 dma_addr_t erdp; 748 unsigned int dp_idx; 749 bool do_irq = 0; 750 751 if (xhci->usbsts & USBSTS_HCH) { 752 return; 753 } 754 755 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 756 if (erdp < intr->er_start || 757 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 758 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 759 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 760 v, intr->er_start, intr->er_size); 761 xhci_die(xhci); 762 return; 763 } 764 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 765 assert(dp_idx < intr->er_size); 766 767 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 768 * deadlocks when the ER is full. Hack it by holding off events until 769 * the driver decides to free at least half of the ring */ 770 if (intr->er_full) { 771 int er_free = dp_idx - intr->er_ep_idx; 772 if (er_free <= 0) { 773 er_free += intr->er_size; 774 } 775 if (er_free < (intr->er_size/2)) { 776 DPRINTF("xhci_events_update(): event ring still " 777 "more than half full (hack)\n"); 778 return; 779 } 780 } 781 782 while (intr->ev_buffer_put != intr->ev_buffer_get) { 783 assert(intr->er_full); 784 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 785 DPRINTF("xhci_events_update(): event ring full again\n"); 786 #ifndef ER_FULL_HACK 787 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 788 xhci_write_event(xhci, &full, v); 789 #endif 790 do_irq = 1; 791 break; 792 } 793 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 794 xhci_write_event(xhci, event, v); 795 intr->ev_buffer_get++; 796 do_irq = 1; 797 if (intr->ev_buffer_get == EV_QUEUE) { 798 intr->ev_buffer_get = 0; 799 } 800 } 801 802 if (do_irq) { 803 xhci_intr_raise(xhci, v); 804 } 805 806 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 807 DPRINTF("xhci_events_update(): event ring no longer full\n"); 808 intr->er_full = 0; 809 } 810 return; 811 } 812 813 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 814 { 815 XHCIInterrupter *intr; 816 dma_addr_t erdp; 817 unsigned int dp_idx; 818 819 if (v >= MAXINTRS) { 820 DPRINTF("intr nr out of range (%d >= %d)\n", v, MAXINTRS); 821 return; 822 } 823 intr = &xhci->intr[v]; 824 825 if (intr->er_full) { 826 DPRINTF("xhci_event(): ER full, queueing\n"); 827 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 828 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 829 return; 830 } 831 intr->ev_buffer[intr->ev_buffer_put++] = *event; 832 if (intr->ev_buffer_put == EV_QUEUE) { 833 intr->ev_buffer_put = 0; 834 } 835 return; 836 } 837 838 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 839 if (erdp < intr->er_start || 840 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 841 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 842 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 843 v, intr->er_start, intr->er_size); 844 xhci_die(xhci); 845 return; 846 } 847 848 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 849 assert(dp_idx < intr->er_size); 850 851 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 852 DPRINTF("xhci_event(): ER full, queueing\n"); 853 #ifndef ER_FULL_HACK 854 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 855 xhci_write_event(xhci, &full); 856 #endif 857 intr->er_full = 1; 858 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 859 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 860 return; 861 } 862 intr->ev_buffer[intr->ev_buffer_put++] = *event; 863 if (intr->ev_buffer_put == EV_QUEUE) { 864 intr->ev_buffer_put = 0; 865 } 866 } else { 867 xhci_write_event(xhci, event, v); 868 } 869 870 xhci_intr_raise(xhci, v); 871 } 872 873 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 874 dma_addr_t base) 875 { 876 ring->base = base; 877 ring->dequeue = base; 878 ring->ccs = 1; 879 } 880 881 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 882 dma_addr_t *addr) 883 { 884 while (1) { 885 TRBType type; 886 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 887 trb->addr = ring->dequeue; 888 trb->ccs = ring->ccs; 889 le64_to_cpus(&trb->parameter); 890 le32_to_cpus(&trb->status); 891 le32_to_cpus(&trb->control); 892 893 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 894 trb->parameter, trb->status, trb->control); 895 896 if ((trb->control & TRB_C) != ring->ccs) { 897 return 0; 898 } 899 900 type = TRB_TYPE(*trb); 901 902 if (type != TR_LINK) { 903 if (addr) { 904 *addr = ring->dequeue; 905 } 906 ring->dequeue += TRB_SIZE; 907 return type; 908 } else { 909 ring->dequeue = xhci_mask64(trb->parameter); 910 if (trb->control & TRB_LK_TC) { 911 ring->ccs = !ring->ccs; 912 } 913 } 914 } 915 } 916 917 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 918 { 919 XHCITRB trb; 920 int length = 0; 921 dma_addr_t dequeue = ring->dequeue; 922 bool ccs = ring->ccs; 923 /* hack to bundle together the two/three TDs that make a setup transfer */ 924 bool control_td_set = 0; 925 926 while (1) { 927 TRBType type; 928 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 929 le64_to_cpus(&trb.parameter); 930 le32_to_cpus(&trb.status); 931 le32_to_cpus(&trb.control); 932 933 if ((trb.control & TRB_C) != ccs) { 934 return -length; 935 } 936 937 type = TRB_TYPE(trb); 938 939 if (type == TR_LINK) { 940 dequeue = xhci_mask64(trb.parameter); 941 if (trb.control & TRB_LK_TC) { 942 ccs = !ccs; 943 } 944 continue; 945 } 946 947 length += 1; 948 dequeue += TRB_SIZE; 949 950 if (type == TR_SETUP) { 951 control_td_set = 1; 952 } else if (type == TR_STATUS) { 953 control_td_set = 0; 954 } 955 956 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 957 return length; 958 } 959 } 960 } 961 962 static void xhci_er_reset(XHCIState *xhci, int v) 963 { 964 XHCIInterrupter *intr = &xhci->intr[v]; 965 XHCIEvRingSeg seg; 966 967 /* cache the (sole) event ring segment location */ 968 if (intr->erstsz != 1) { 969 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 970 xhci_die(xhci); 971 return; 972 } 973 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 974 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 975 le32_to_cpus(&seg.addr_low); 976 le32_to_cpus(&seg.addr_high); 977 le32_to_cpus(&seg.size); 978 if (seg.size < 16 || seg.size > 4096) { 979 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 980 xhci_die(xhci); 981 return; 982 } 983 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 984 intr->er_size = seg.size; 985 986 intr->er_ep_idx = 0; 987 intr->er_pcs = 1; 988 intr->er_full = 0; 989 990 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 991 v, intr->er_start, intr->er_size); 992 } 993 994 static void xhci_run(XHCIState *xhci) 995 { 996 trace_usb_xhci_run(); 997 xhci->usbsts &= ~USBSTS_HCH; 998 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 999 } 1000 1001 static void xhci_stop(XHCIState *xhci) 1002 { 1003 trace_usb_xhci_stop(); 1004 xhci->usbsts |= USBSTS_HCH; 1005 xhci->crcr_low &= ~CRCR_CRR; 1006 } 1007 1008 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1009 uint32_t state) 1010 { 1011 uint32_t ctx[5]; 1012 if (epctx->state == state) { 1013 return; 1014 } 1015 1016 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1017 ctx[0] &= ~EP_STATE_MASK; 1018 ctx[0] |= state; 1019 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1020 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1021 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1022 epctx->pctx, state, ctx[3], ctx[2]); 1023 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1024 epctx->state = state; 1025 } 1026 1027 static void xhci_ep_kick_timer(void *opaque) 1028 { 1029 XHCIEPContext *epctx = opaque; 1030 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1031 } 1032 1033 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1034 unsigned int epid, dma_addr_t pctx, 1035 uint32_t *ctx) 1036 { 1037 XHCISlot *slot; 1038 XHCIEPContext *epctx; 1039 dma_addr_t dequeue; 1040 int i; 1041 1042 trace_usb_xhci_ep_enable(slotid, epid); 1043 assert(slotid >= 1 && slotid <= MAXSLOTS); 1044 assert(epid >= 1 && epid <= 31); 1045 1046 slot = &xhci->slots[slotid-1]; 1047 if (slot->eps[epid-1]) { 1048 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1049 return CC_TRB_ERROR; 1050 } 1051 1052 epctx = g_malloc(sizeof(XHCIEPContext)); 1053 memset(epctx, 0, sizeof(XHCIEPContext)); 1054 epctx->xhci = xhci; 1055 epctx->slotid = slotid; 1056 epctx->epid = epid; 1057 1058 slot->eps[epid-1] = epctx; 1059 1060 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1061 xhci_ring_init(xhci, &epctx->ring, dequeue); 1062 epctx->ring.ccs = ctx[2] & 1; 1063 1064 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1065 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1066 epctx->pctx = pctx; 1067 epctx->max_psize = ctx[1]>>16; 1068 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1069 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1070 epid/2, epid%2, epctx->max_psize); 1071 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1072 usb_packet_init(&epctx->transfers[i].packet); 1073 } 1074 1075 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1076 epctx->mfindex_last = 0; 1077 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1078 1079 epctx->state = EP_RUNNING; 1080 ctx[0] &= ~EP_STATE_MASK; 1081 ctx[0] |= EP_RUNNING; 1082 1083 return CC_SUCCESS; 1084 } 1085 1086 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1087 unsigned int epid) 1088 { 1089 XHCISlot *slot; 1090 XHCIEPContext *epctx; 1091 int i, xferi, killed = 0; 1092 assert(slotid >= 1 && slotid <= MAXSLOTS); 1093 assert(epid >= 1 && epid <= 31); 1094 1095 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1096 1097 slot = &xhci->slots[slotid-1]; 1098 1099 if (!slot->eps[epid-1]) { 1100 return 0; 1101 } 1102 1103 epctx = slot->eps[epid-1]; 1104 1105 xferi = epctx->next_xfer; 1106 for (i = 0; i < TD_QUEUE; i++) { 1107 XHCITransfer *t = &epctx->transfers[xferi]; 1108 if (t->running_async) { 1109 usb_cancel_packet(&t->packet); 1110 t->running_async = 0; 1111 t->cancelled = 1; 1112 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i); 1113 killed++; 1114 } 1115 if (t->running_retry) { 1116 t->running_retry = 0; 1117 epctx->retry = NULL; 1118 qemu_del_timer(epctx->kick_timer); 1119 } 1120 if (t->trbs) { 1121 g_free(t->trbs); 1122 } 1123 1124 t->trbs = NULL; 1125 t->trb_count = t->trb_alloced = 0; 1126 xferi = (xferi + 1) % TD_QUEUE; 1127 } 1128 return killed; 1129 } 1130 1131 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1132 unsigned int epid) 1133 { 1134 XHCISlot *slot; 1135 XHCIEPContext *epctx; 1136 1137 trace_usb_xhci_ep_disable(slotid, epid); 1138 assert(slotid >= 1 && slotid <= MAXSLOTS); 1139 assert(epid >= 1 && epid <= 31); 1140 1141 slot = &xhci->slots[slotid-1]; 1142 1143 if (!slot->eps[epid-1]) { 1144 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1145 return CC_SUCCESS; 1146 } 1147 1148 xhci_ep_nuke_xfers(xhci, slotid, epid); 1149 1150 epctx = slot->eps[epid-1]; 1151 1152 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1153 1154 qemu_free_timer(epctx->kick_timer); 1155 g_free(epctx); 1156 slot->eps[epid-1] = NULL; 1157 1158 return CC_SUCCESS; 1159 } 1160 1161 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1162 unsigned int epid) 1163 { 1164 XHCISlot *slot; 1165 XHCIEPContext *epctx; 1166 1167 trace_usb_xhci_ep_stop(slotid, epid); 1168 assert(slotid >= 1 && slotid <= MAXSLOTS); 1169 1170 if (epid < 1 || epid > 31) { 1171 fprintf(stderr, "xhci: bad ep %d\n", epid); 1172 return CC_TRB_ERROR; 1173 } 1174 1175 slot = &xhci->slots[slotid-1]; 1176 1177 if (!slot->eps[epid-1]) { 1178 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1179 return CC_EP_NOT_ENABLED_ERROR; 1180 } 1181 1182 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1183 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1184 "data might be lost\n"); 1185 } 1186 1187 epctx = slot->eps[epid-1]; 1188 1189 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1190 1191 return CC_SUCCESS; 1192 } 1193 1194 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1195 unsigned int epid) 1196 { 1197 XHCISlot *slot; 1198 XHCIEPContext *epctx; 1199 USBDevice *dev; 1200 1201 trace_usb_xhci_ep_reset(slotid, epid); 1202 assert(slotid >= 1 && slotid <= MAXSLOTS); 1203 1204 if (epid < 1 || epid > 31) { 1205 fprintf(stderr, "xhci: bad ep %d\n", epid); 1206 return CC_TRB_ERROR; 1207 } 1208 1209 slot = &xhci->slots[slotid-1]; 1210 1211 if (!slot->eps[epid-1]) { 1212 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1213 return CC_EP_NOT_ENABLED_ERROR; 1214 } 1215 1216 epctx = slot->eps[epid-1]; 1217 1218 if (epctx->state != EP_HALTED) { 1219 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1220 epid, epctx->state); 1221 return CC_CONTEXT_STATE_ERROR; 1222 } 1223 1224 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1225 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1226 "data might be lost\n"); 1227 } 1228 1229 uint8_t ep = epid>>1; 1230 1231 if (epid & 1) { 1232 ep |= 0x80; 1233 } 1234 1235 dev = xhci->slots[slotid-1].uport->dev; 1236 if (!dev) { 1237 return CC_USB_TRANSACTION_ERROR; 1238 } 1239 1240 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1241 1242 return CC_SUCCESS; 1243 } 1244 1245 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1246 unsigned int epid, uint64_t pdequeue) 1247 { 1248 XHCISlot *slot; 1249 XHCIEPContext *epctx; 1250 dma_addr_t dequeue; 1251 1252 assert(slotid >= 1 && slotid <= MAXSLOTS); 1253 1254 if (epid < 1 || epid > 31) { 1255 fprintf(stderr, "xhci: bad ep %d\n", epid); 1256 return CC_TRB_ERROR; 1257 } 1258 1259 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1260 dequeue = xhci_mask64(pdequeue); 1261 1262 slot = &xhci->slots[slotid-1]; 1263 1264 if (!slot->eps[epid-1]) { 1265 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1266 return CC_EP_NOT_ENABLED_ERROR; 1267 } 1268 1269 epctx = slot->eps[epid-1]; 1270 1271 1272 if (epctx->state != EP_STOPPED) { 1273 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1274 return CC_CONTEXT_STATE_ERROR; 1275 } 1276 1277 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1278 epctx->ring.ccs = dequeue & 1; 1279 1280 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1281 1282 return CC_SUCCESS; 1283 } 1284 1285 static int xhci_xfer_map(XHCITransfer *xfer) 1286 { 1287 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN); 1288 XHCIState *xhci = xfer->xhci; 1289 int i; 1290 1291 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1292 for (i = 0; i < xfer->trb_count; i++) { 1293 XHCITRB *trb = &xfer->trbs[i]; 1294 dma_addr_t addr; 1295 unsigned int chunk = 0; 1296 1297 switch (TRB_TYPE(*trb)) { 1298 case TR_DATA: 1299 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1300 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1301 goto err; 1302 } 1303 /* fallthrough */ 1304 case TR_NORMAL: 1305 case TR_ISOCH: 1306 addr = xhci_mask64(trb->parameter); 1307 chunk = trb->status & 0x1ffff; 1308 if (trb->control & TRB_TR_IDT) { 1309 if (chunk > 8 || in_xfer) { 1310 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1311 goto err; 1312 } 1313 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1314 } else { 1315 qemu_sglist_add(&xfer->sgl, addr, chunk); 1316 } 1317 break; 1318 } 1319 } 1320 1321 usb_packet_map(&xfer->packet, &xfer->sgl); 1322 return 0; 1323 1324 err: 1325 qemu_sglist_destroy(&xfer->sgl); 1326 xhci_die(xhci); 1327 return -1; 1328 } 1329 1330 static void xhci_xfer_unmap(XHCITransfer *xfer) 1331 { 1332 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1333 qemu_sglist_destroy(&xfer->sgl); 1334 } 1335 1336 static void xhci_xfer_report(XHCITransfer *xfer) 1337 { 1338 uint32_t edtla = 0; 1339 unsigned int left; 1340 bool reported = 0; 1341 bool shortpkt = 0; 1342 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1343 XHCIState *xhci = xfer->xhci; 1344 int i; 1345 1346 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1347 1348 for (i = 0; i < xfer->trb_count; i++) { 1349 XHCITRB *trb = &xfer->trbs[i]; 1350 unsigned int chunk = 0; 1351 1352 switch (TRB_TYPE(*trb)) { 1353 case TR_DATA: 1354 case TR_NORMAL: 1355 case TR_ISOCH: 1356 chunk = trb->status & 0x1ffff; 1357 if (chunk > left) { 1358 chunk = left; 1359 if (xfer->status == CC_SUCCESS) { 1360 shortpkt = 1; 1361 } 1362 } 1363 left -= chunk; 1364 edtla += chunk; 1365 break; 1366 case TR_STATUS: 1367 reported = 0; 1368 shortpkt = 0; 1369 break; 1370 } 1371 1372 if (!reported && ((trb->control & TRB_TR_IOC) || 1373 (shortpkt && (trb->control & TRB_TR_ISP)) || 1374 (xfer->status != CC_SUCCESS))) { 1375 event.slotid = xfer->slotid; 1376 event.epid = xfer->epid; 1377 event.length = (trb->status & 0x1ffff) - chunk; 1378 event.flags = 0; 1379 event.ptr = trb->addr; 1380 if (xfer->status == CC_SUCCESS) { 1381 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1382 } else { 1383 event.ccode = xfer->status; 1384 } 1385 if (TRB_TYPE(*trb) == TR_EVDATA) { 1386 event.ptr = trb->parameter; 1387 event.flags |= TRB_EV_ED; 1388 event.length = edtla & 0xffffff; 1389 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1390 edtla = 0; 1391 } 1392 xhci_event(xhci, &event, TRB_INTR(*trb)); 1393 reported = 1; 1394 if (xfer->status != CC_SUCCESS) { 1395 return; 1396 } 1397 } 1398 } 1399 } 1400 1401 static void xhci_stall_ep(XHCITransfer *xfer) 1402 { 1403 XHCIState *xhci = xfer->xhci; 1404 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1405 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1406 1407 epctx->ring.dequeue = xfer->trbs[0].addr; 1408 epctx->ring.ccs = xfer->trbs[0].ccs; 1409 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1410 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1411 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1412 } 1413 1414 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1415 XHCIEPContext *epctx); 1416 1417 static int xhci_setup_packet(XHCITransfer *xfer) 1418 { 1419 XHCIState *xhci = xfer->xhci; 1420 USBDevice *dev; 1421 USBEndpoint *ep; 1422 int dir; 1423 1424 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1425 1426 if (xfer->packet.ep) { 1427 ep = xfer->packet.ep; 1428 dev = ep->dev; 1429 } else { 1430 if (!xhci->slots[xfer->slotid-1].uport) { 1431 fprintf(stderr, "xhci: slot %d has no device\n", 1432 xfer->slotid); 1433 return -1; 1434 } 1435 dev = xhci->slots[xfer->slotid-1].uport->dev; 1436 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1437 } 1438 1439 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr); 1440 xhci_xfer_map(xfer); 1441 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1442 xfer->packet.pid, dev->addr, ep->nr); 1443 return 0; 1444 } 1445 1446 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1447 { 1448 if (ret == USB_RET_ASYNC) { 1449 trace_usb_xhci_xfer_async(xfer); 1450 xfer->running_async = 1; 1451 xfer->running_retry = 0; 1452 xfer->complete = 0; 1453 xfer->cancelled = 0; 1454 return 0; 1455 } else if (ret == USB_RET_NAK) { 1456 trace_usb_xhci_xfer_nak(xfer); 1457 xfer->running_async = 0; 1458 xfer->running_retry = 1; 1459 xfer->complete = 0; 1460 xfer->cancelled = 0; 1461 return 0; 1462 } else { 1463 xfer->running_async = 0; 1464 xfer->running_retry = 0; 1465 xfer->complete = 1; 1466 xhci_xfer_unmap(xfer); 1467 } 1468 1469 if (ret >= 0) { 1470 trace_usb_xhci_xfer_success(xfer, ret); 1471 xfer->status = CC_SUCCESS; 1472 xhci_xfer_report(xfer); 1473 return 0; 1474 } 1475 1476 /* error */ 1477 trace_usb_xhci_xfer_error(xfer, ret); 1478 switch (ret) { 1479 case USB_RET_NODEV: 1480 xfer->status = CC_USB_TRANSACTION_ERROR; 1481 xhci_xfer_report(xfer); 1482 xhci_stall_ep(xfer); 1483 break; 1484 case USB_RET_STALL: 1485 xfer->status = CC_STALL_ERROR; 1486 xhci_xfer_report(xfer); 1487 xhci_stall_ep(xfer); 1488 break; 1489 default: 1490 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1491 FIXME(); 1492 } 1493 return 0; 1494 } 1495 1496 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1497 { 1498 XHCITRB *trb_setup, *trb_status; 1499 uint8_t bmRequestType; 1500 int ret; 1501 1502 trb_setup = &xfer->trbs[0]; 1503 trb_status = &xfer->trbs[xfer->trb_count-1]; 1504 1505 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1506 1507 /* at most one Event Data TRB allowed after STATUS */ 1508 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1509 trb_status--; 1510 } 1511 1512 /* do some sanity checks */ 1513 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1514 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1515 TRB_TYPE(*trb_setup)); 1516 return -1; 1517 } 1518 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1519 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1520 TRB_TYPE(*trb_status)); 1521 return -1; 1522 } 1523 if (!(trb_setup->control & TRB_TR_IDT)) { 1524 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1525 return -1; 1526 } 1527 if ((trb_setup->status & 0x1ffff) != 8) { 1528 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1529 (trb_setup->status & 0x1ffff)); 1530 return -1; 1531 } 1532 1533 bmRequestType = trb_setup->parameter; 1534 1535 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1536 xfer->iso_xfer = false; 1537 1538 if (xhci_setup_packet(xfer) < 0) { 1539 return -1; 1540 } 1541 xfer->packet.parameter = trb_setup->parameter; 1542 1543 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1544 1545 xhci_complete_packet(xfer, ret); 1546 if (!xfer->running_async && !xfer->running_retry) { 1547 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1548 } 1549 return 0; 1550 } 1551 1552 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1553 XHCIEPContext *epctx, uint64_t mfindex) 1554 { 1555 if (xfer->trbs[0].control & TRB_TR_SIA) { 1556 uint64_t asap = ((mfindex + epctx->interval - 1) & 1557 ~(epctx->interval-1)); 1558 if (asap >= epctx->mfindex_last && 1559 asap <= epctx->mfindex_last + epctx->interval * 4) { 1560 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1561 } else { 1562 xfer->mfindex_kick = asap; 1563 } 1564 } else { 1565 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1566 & TRB_TR_FRAMEID_MASK; 1567 xfer->mfindex_kick |= mfindex & ~0x3fff; 1568 if (xfer->mfindex_kick < mfindex) { 1569 xfer->mfindex_kick += 0x4000; 1570 } 1571 } 1572 } 1573 1574 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1575 XHCIEPContext *epctx, uint64_t mfindex) 1576 { 1577 if (xfer->mfindex_kick > mfindex) { 1578 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1579 (xfer->mfindex_kick - mfindex) * 125000); 1580 xfer->running_retry = 1; 1581 } else { 1582 epctx->mfindex_last = xfer->mfindex_kick; 1583 qemu_del_timer(epctx->kick_timer); 1584 xfer->running_retry = 0; 1585 } 1586 } 1587 1588 1589 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1590 { 1591 uint64_t mfindex; 1592 int ret; 1593 1594 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1595 1596 xfer->in_xfer = epctx->type>>2; 1597 1598 switch(epctx->type) { 1599 case ET_INTR_OUT: 1600 case ET_INTR_IN: 1601 case ET_BULK_OUT: 1602 case ET_BULK_IN: 1603 xfer->pkts = 0; 1604 xfer->iso_xfer = false; 1605 break; 1606 case ET_ISO_OUT: 1607 case ET_ISO_IN: 1608 xfer->pkts = 1; 1609 xfer->iso_xfer = true; 1610 mfindex = xhci_mfindex_get(xhci); 1611 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1612 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1613 if (xfer->running_retry) { 1614 return -1; 1615 } 1616 break; 1617 default: 1618 fprintf(stderr, "xhci: unknown or unhandled EP " 1619 "(type %d, in %d, ep %02x)\n", 1620 epctx->type, xfer->in_xfer, xfer->epid); 1621 return -1; 1622 } 1623 1624 if (xhci_setup_packet(xfer) < 0) { 1625 return -1; 1626 } 1627 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1628 1629 xhci_complete_packet(xfer, ret); 1630 if (!xfer->running_async && !xfer->running_retry) { 1631 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1632 } 1633 return 0; 1634 } 1635 1636 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1637 { 1638 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1639 return xhci_submit(xhci, xfer, epctx); 1640 } 1641 1642 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1643 { 1644 XHCIEPContext *epctx; 1645 uint64_t mfindex; 1646 int length; 1647 int i; 1648 1649 trace_usb_xhci_ep_kick(slotid, epid); 1650 assert(slotid >= 1 && slotid <= MAXSLOTS); 1651 assert(epid >= 1 && epid <= 31); 1652 1653 if (!xhci->slots[slotid-1].enabled) { 1654 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1655 return; 1656 } 1657 epctx = xhci->slots[slotid-1].eps[epid-1]; 1658 if (!epctx) { 1659 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1660 epid, slotid); 1661 return; 1662 } 1663 1664 if (epctx->retry) { 1665 XHCITransfer *xfer = epctx->retry; 1666 int result; 1667 1668 trace_usb_xhci_xfer_retry(xfer); 1669 assert(xfer->running_retry); 1670 if (xfer->iso_xfer) { 1671 /* retry delayed iso transfer */ 1672 mfindex = xhci_mfindex_get(xhci); 1673 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1674 if (xfer->running_retry) { 1675 return; 1676 } 1677 if (xhci_setup_packet(xfer) < 0) { 1678 return; 1679 } 1680 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1681 assert(result != USB_RET_NAK); 1682 xhci_complete_packet(xfer, result); 1683 } else { 1684 /* retry nak'ed transfer */ 1685 if (xhci_setup_packet(xfer) < 0) { 1686 return; 1687 } 1688 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1689 if (result == USB_RET_NAK) { 1690 return; 1691 } 1692 xhci_complete_packet(xfer, result); 1693 } 1694 assert(!xfer->running_retry); 1695 epctx->retry = NULL; 1696 } 1697 1698 if (epctx->state == EP_HALTED) { 1699 DPRINTF("xhci: ep halted, not running schedule\n"); 1700 return; 1701 } 1702 1703 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1704 1705 while (1) { 1706 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1707 if (xfer->running_async || xfer->running_retry) { 1708 break; 1709 } 1710 length = xhci_ring_chain_length(xhci, &epctx->ring); 1711 if (length < 0) { 1712 break; 1713 } else if (length == 0) { 1714 break; 1715 } 1716 if (xfer->trbs && xfer->trb_alloced < length) { 1717 xfer->trb_count = 0; 1718 xfer->trb_alloced = 0; 1719 g_free(xfer->trbs); 1720 xfer->trbs = NULL; 1721 } 1722 if (!xfer->trbs) { 1723 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1724 xfer->trb_alloced = length; 1725 } 1726 xfer->trb_count = length; 1727 1728 for (i = 0; i < length; i++) { 1729 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1730 } 1731 xfer->xhci = xhci; 1732 xfer->epid = epid; 1733 xfer->slotid = slotid; 1734 1735 if (epid == 1) { 1736 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1737 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1738 } else { 1739 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1740 } 1741 } else { 1742 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1743 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1744 } else { 1745 if (!xfer->iso_xfer) { 1746 fprintf(stderr, "xhci: error firing data transfer\n"); 1747 } 1748 } 1749 } 1750 1751 if (epctx->state == EP_HALTED) { 1752 break; 1753 } 1754 if (xfer->running_retry) { 1755 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1756 epctx->retry = xfer; 1757 break; 1758 } 1759 } 1760 } 1761 1762 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1763 { 1764 trace_usb_xhci_slot_enable(slotid); 1765 assert(slotid >= 1 && slotid <= MAXSLOTS); 1766 xhci->slots[slotid-1].enabled = 1; 1767 xhci->slots[slotid-1].uport = NULL; 1768 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1769 1770 return CC_SUCCESS; 1771 } 1772 1773 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1774 { 1775 int i; 1776 1777 trace_usb_xhci_slot_disable(slotid); 1778 assert(slotid >= 1 && slotid <= MAXSLOTS); 1779 1780 for (i = 1; i <= 31; i++) { 1781 if (xhci->slots[slotid-1].eps[i-1]) { 1782 xhci_disable_ep(xhci, slotid, i); 1783 } 1784 } 1785 1786 xhci->slots[slotid-1].enabled = 0; 1787 return CC_SUCCESS; 1788 } 1789 1790 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1791 { 1792 USBPort *uport; 1793 char path[32]; 1794 int i, pos, port; 1795 1796 port = (slot_ctx[1]>>16) & 0xFF; 1797 port = xhci->ports[port-1].uport->index+1; 1798 pos = snprintf(path, sizeof(path), "%d", port); 1799 for (i = 0; i < 5; i++) { 1800 port = (slot_ctx[0] >> 4*i) & 0x0f; 1801 if (!port) { 1802 break; 1803 } 1804 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1805 } 1806 1807 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1808 if (strcmp(uport->path, path) == 0) { 1809 return uport; 1810 } 1811 } 1812 return NULL; 1813 } 1814 1815 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1816 uint64_t pictx, bool bsr) 1817 { 1818 XHCISlot *slot; 1819 USBPort *uport; 1820 USBDevice *dev; 1821 dma_addr_t ictx, octx, dcbaap; 1822 uint64_t poctx; 1823 uint32_t ictl_ctx[2]; 1824 uint32_t slot_ctx[4]; 1825 uint32_t ep0_ctx[5]; 1826 int i; 1827 TRBCCode res; 1828 1829 trace_usb_xhci_slot_address(slotid); 1830 assert(slotid >= 1 && slotid <= MAXSLOTS); 1831 1832 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1833 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1834 ictx = xhci_mask64(pictx); 1835 octx = xhci_mask64(le64_to_cpu(poctx)); 1836 1837 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1838 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1839 1840 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1841 1842 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1843 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1844 ictl_ctx[0], ictl_ctx[1]); 1845 return CC_TRB_ERROR; 1846 } 1847 1848 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1849 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1850 1851 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1852 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1853 1854 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1855 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1856 1857 uport = xhci_lookup_uport(xhci, slot_ctx); 1858 if (uport == NULL) { 1859 fprintf(stderr, "xhci: port not found\n"); 1860 return CC_TRB_ERROR; 1861 } 1862 1863 dev = uport->dev; 1864 if (!dev) { 1865 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1866 return CC_USB_TRANSACTION_ERROR; 1867 } 1868 1869 for (i = 0; i < MAXSLOTS; i++) { 1870 if (xhci->slots[i].uport == uport) { 1871 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1872 uport->path, i+1); 1873 return CC_TRB_ERROR; 1874 } 1875 } 1876 1877 slot = &xhci->slots[slotid-1]; 1878 slot->uport = uport; 1879 slot->ctx = octx; 1880 1881 if (bsr) { 1882 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1883 } else { 1884 slot->devaddr = xhci->devaddr++; 1885 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1886 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1887 usb_device_handle_control(dev, NULL, 1888 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1889 slot->devaddr, 0, 0, NULL); 1890 } 1891 1892 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1893 1894 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1895 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1896 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1897 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1898 1899 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1900 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1901 1902 return res; 1903 } 1904 1905 1906 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1907 uint64_t pictx, bool dc) 1908 { 1909 dma_addr_t ictx, octx; 1910 uint32_t ictl_ctx[2]; 1911 uint32_t slot_ctx[4]; 1912 uint32_t islot_ctx[4]; 1913 uint32_t ep_ctx[5]; 1914 int i; 1915 TRBCCode res; 1916 1917 trace_usb_xhci_slot_configure(slotid); 1918 assert(slotid >= 1 && slotid <= MAXSLOTS); 1919 1920 ictx = xhci_mask64(pictx); 1921 octx = xhci->slots[slotid-1].ctx; 1922 1923 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1924 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1925 1926 if (dc) { 1927 for (i = 2; i <= 31; i++) { 1928 if (xhci->slots[slotid-1].eps[i-1]) { 1929 xhci_disable_ep(xhci, slotid, i); 1930 } 1931 } 1932 1933 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1934 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1935 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1936 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1937 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1938 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1939 1940 return CC_SUCCESS; 1941 } 1942 1943 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1944 1945 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1946 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1947 ictl_ctx[0], ictl_ctx[1]); 1948 return CC_TRB_ERROR; 1949 } 1950 1951 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1952 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1953 1954 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1955 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1956 return CC_CONTEXT_STATE_ERROR; 1957 } 1958 1959 for (i = 2; i <= 31; i++) { 1960 if (ictl_ctx[0] & (1<<i)) { 1961 xhci_disable_ep(xhci, slotid, i); 1962 } 1963 if (ictl_ctx[1] & (1<<i)) { 1964 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1965 sizeof(ep_ctx)); 1966 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1967 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1968 ep_ctx[3], ep_ctx[4]); 1969 xhci_disable_ep(xhci, slotid, i); 1970 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1971 if (res != CC_SUCCESS) { 1972 return res; 1973 } 1974 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 1975 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1976 ep_ctx[3], ep_ctx[4]); 1977 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 1978 } 1979 } 1980 1981 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1982 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 1983 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 1984 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 1985 SLOT_CONTEXT_ENTRIES_SHIFT); 1986 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1987 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1988 1989 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1990 1991 return CC_SUCCESS; 1992 } 1993 1994 1995 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 1996 uint64_t pictx) 1997 { 1998 dma_addr_t ictx, octx; 1999 uint32_t ictl_ctx[2]; 2000 uint32_t iep0_ctx[5]; 2001 uint32_t ep0_ctx[5]; 2002 uint32_t islot_ctx[4]; 2003 uint32_t slot_ctx[4]; 2004 2005 trace_usb_xhci_slot_evaluate(slotid); 2006 assert(slotid >= 1 && slotid <= MAXSLOTS); 2007 2008 ictx = xhci_mask64(pictx); 2009 octx = xhci->slots[slotid-1].ctx; 2010 2011 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2012 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2013 2014 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 2015 2016 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2017 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2018 ictl_ctx[0], ictl_ctx[1]); 2019 return CC_TRB_ERROR; 2020 } 2021 2022 if (ictl_ctx[1] & 0x1) { 2023 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2024 2025 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2026 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2027 2028 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2029 2030 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2031 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2032 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2033 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2034 2035 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2036 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2037 2038 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2039 } 2040 2041 if (ictl_ctx[1] & 0x2) { 2042 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2043 2044 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2045 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2046 iep0_ctx[3], iep0_ctx[4]); 2047 2048 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2049 2050 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2051 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2052 2053 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2054 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2055 2056 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2057 } 2058 2059 return CC_SUCCESS; 2060 } 2061 2062 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2063 { 2064 uint32_t slot_ctx[4]; 2065 dma_addr_t octx; 2066 int i; 2067 2068 trace_usb_xhci_slot_reset(slotid); 2069 assert(slotid >= 1 && slotid <= MAXSLOTS); 2070 2071 octx = xhci->slots[slotid-1].ctx; 2072 2073 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2074 2075 for (i = 2; i <= 31; i++) { 2076 if (xhci->slots[slotid-1].eps[i-1]) { 2077 xhci_disable_ep(xhci, slotid, i); 2078 } 2079 } 2080 2081 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2082 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2083 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2084 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2085 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2086 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2087 2088 return CC_SUCCESS; 2089 } 2090 2091 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2092 { 2093 unsigned int slotid; 2094 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2095 if (slotid < 1 || slotid > MAXSLOTS) { 2096 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2097 event->ccode = CC_TRB_ERROR; 2098 return 0; 2099 } else if (!xhci->slots[slotid-1].enabled) { 2100 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2101 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2102 return 0; 2103 } 2104 return slotid; 2105 } 2106 2107 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2108 { 2109 dma_addr_t ctx; 2110 uint8_t bw_ctx[xhci->numports+1]; 2111 2112 DPRINTF("xhci_get_port_bandwidth()\n"); 2113 2114 ctx = xhci_mask64(pctx); 2115 2116 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2117 2118 /* TODO: actually implement real values here */ 2119 bw_ctx[0] = 0; 2120 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2121 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2122 2123 return CC_SUCCESS; 2124 } 2125 2126 static uint32_t rotl(uint32_t v, unsigned count) 2127 { 2128 count &= 31; 2129 return (v << count) | (v >> (32 - count)); 2130 } 2131 2132 2133 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2134 { 2135 uint32_t val; 2136 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2137 val += rotl(lo + 0x49434878, hi & 0x1F); 2138 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2139 return ~val; 2140 } 2141 2142 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2143 { 2144 uint32_t buf[8]; 2145 uint32_t obuf[8]; 2146 dma_addr_t paddr = xhci_mask64(addr); 2147 2148 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2149 2150 memcpy(obuf, buf, sizeof(obuf)); 2151 2152 if ((buf[0] & 0xff) == 2) { 2153 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2154 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2155 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2156 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2157 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2158 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2159 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2160 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2161 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2162 } 2163 2164 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2165 } 2166 2167 static void xhci_process_commands(XHCIState *xhci) 2168 { 2169 XHCITRB trb; 2170 TRBType type; 2171 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2172 dma_addr_t addr; 2173 unsigned int i, slotid = 0; 2174 2175 DPRINTF("xhci_process_commands()\n"); 2176 if (!xhci_running(xhci)) { 2177 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2178 return; 2179 } 2180 2181 xhci->crcr_low |= CRCR_CRR; 2182 2183 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2184 event.ptr = addr; 2185 switch (type) { 2186 case CR_ENABLE_SLOT: 2187 for (i = 0; i < MAXSLOTS; i++) { 2188 if (!xhci->slots[i].enabled) { 2189 break; 2190 } 2191 } 2192 if (i >= MAXSLOTS) { 2193 fprintf(stderr, "xhci: no device slots available\n"); 2194 event.ccode = CC_NO_SLOTS_ERROR; 2195 } else { 2196 slotid = i+1; 2197 event.ccode = xhci_enable_slot(xhci, slotid); 2198 } 2199 break; 2200 case CR_DISABLE_SLOT: 2201 slotid = xhci_get_slot(xhci, &event, &trb); 2202 if (slotid) { 2203 event.ccode = xhci_disable_slot(xhci, slotid); 2204 } 2205 break; 2206 case CR_ADDRESS_DEVICE: 2207 slotid = xhci_get_slot(xhci, &event, &trb); 2208 if (slotid) { 2209 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2210 trb.control & TRB_CR_BSR); 2211 } 2212 break; 2213 case CR_CONFIGURE_ENDPOINT: 2214 slotid = xhci_get_slot(xhci, &event, &trb); 2215 if (slotid) { 2216 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2217 trb.control & TRB_CR_DC); 2218 } 2219 break; 2220 case CR_EVALUATE_CONTEXT: 2221 slotid = xhci_get_slot(xhci, &event, &trb); 2222 if (slotid) { 2223 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2224 } 2225 break; 2226 case CR_STOP_ENDPOINT: 2227 slotid = xhci_get_slot(xhci, &event, &trb); 2228 if (slotid) { 2229 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2230 & TRB_CR_EPID_MASK; 2231 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2232 } 2233 break; 2234 case CR_RESET_ENDPOINT: 2235 slotid = xhci_get_slot(xhci, &event, &trb); 2236 if (slotid) { 2237 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2238 & TRB_CR_EPID_MASK; 2239 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2240 } 2241 break; 2242 case CR_SET_TR_DEQUEUE: 2243 slotid = xhci_get_slot(xhci, &event, &trb); 2244 if (slotid) { 2245 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2246 & TRB_CR_EPID_MASK; 2247 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2248 trb.parameter); 2249 } 2250 break; 2251 case CR_RESET_DEVICE: 2252 slotid = xhci_get_slot(xhci, &event, &trb); 2253 if (slotid) { 2254 event.ccode = xhci_reset_slot(xhci, slotid); 2255 } 2256 break; 2257 case CR_GET_PORT_BANDWIDTH: 2258 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2259 break; 2260 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2261 xhci_via_challenge(xhci, trb.parameter); 2262 break; 2263 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2264 event.type = 48; /* NEC reply */ 2265 event.length = 0x3025; 2266 break; 2267 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2268 { 2269 uint32_t chi = trb.parameter >> 32; 2270 uint32_t clo = trb.parameter; 2271 uint32_t val = xhci_nec_challenge(chi, clo); 2272 event.length = val & 0xFFFF; 2273 event.epid = val >> 16; 2274 slotid = val >> 24; 2275 event.type = 48; /* NEC reply */ 2276 } 2277 break; 2278 default: 2279 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2280 event.ccode = CC_TRB_ERROR; 2281 break; 2282 } 2283 event.slotid = slotid; 2284 xhci_event(xhci, &event, 0); 2285 } 2286 } 2287 2288 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2289 { 2290 port->portsc = PORTSC_PP; 2291 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2292 (1 << port->uport->dev->speed) & port->speedmask) { 2293 port->portsc |= PORTSC_CCS; 2294 switch (port->uport->dev->speed) { 2295 case USB_SPEED_LOW: 2296 port->portsc |= PORTSC_SPEED_LOW; 2297 break; 2298 case USB_SPEED_FULL: 2299 port->portsc |= PORTSC_SPEED_FULL; 2300 break; 2301 case USB_SPEED_HIGH: 2302 port->portsc |= PORTSC_SPEED_HIGH; 2303 break; 2304 case USB_SPEED_SUPER: 2305 port->portsc |= PORTSC_SPEED_SUPER; 2306 break; 2307 } 2308 } 2309 2310 if (xhci_running(xhci)) { 2311 port->portsc |= PORTSC_CSC; 2312 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2313 port->portnr << 24}; 2314 xhci_event(xhci, &ev, 0); 2315 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2316 } 2317 } 2318 2319 static void xhci_reset(DeviceState *dev) 2320 { 2321 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2322 int i; 2323 2324 trace_usb_xhci_reset(); 2325 if (!(xhci->usbsts & USBSTS_HCH)) { 2326 fprintf(stderr, "xhci: reset while running!\n"); 2327 } 2328 2329 xhci->usbcmd = 0; 2330 xhci->usbsts = USBSTS_HCH; 2331 xhci->dnctrl = 0; 2332 xhci->crcr_low = 0; 2333 xhci->crcr_high = 0; 2334 xhci->dcbaap_low = 0; 2335 xhci->dcbaap_high = 0; 2336 xhci->config = 0; 2337 xhci->devaddr = 2; 2338 2339 for (i = 0; i < MAXSLOTS; i++) { 2340 xhci_disable_slot(xhci, i+1); 2341 } 2342 2343 for (i = 0; i < xhci->numports; i++) { 2344 xhci_update_port(xhci, xhci->ports + i, 0); 2345 } 2346 2347 for (i = 0; i < MAXINTRS; i++) { 2348 xhci->intr[i].iman = 0; 2349 xhci->intr[i].imod = 0; 2350 xhci->intr[i].erstsz = 0; 2351 xhci->intr[i].erstba_low = 0; 2352 xhci->intr[i].erstba_high = 0; 2353 xhci->intr[i].erdp_low = 0; 2354 xhci->intr[i].erdp_high = 0; 2355 xhci->intr[i].msix_used = 0; 2356 2357 xhci->intr[i].er_ep_idx = 0; 2358 xhci->intr[i].er_pcs = 1; 2359 xhci->intr[i].er_full = 0; 2360 xhci->intr[i].ev_buffer_put = 0; 2361 xhci->intr[i].ev_buffer_get = 0; 2362 } 2363 2364 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2365 xhci_mfwrap_update(xhci); 2366 } 2367 2368 static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size) 2369 { 2370 XHCIState *xhci = ptr; 2371 uint32_t ret; 2372 2373 switch (reg) { 2374 case 0x00: /* HCIVERSION, CAPLENGTH */ 2375 ret = 0x01000000 | LEN_CAP; 2376 break; 2377 case 0x04: /* HCSPARAMS 1 */ 2378 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2379 | (MAXINTRS<<8) | MAXSLOTS; 2380 break; 2381 case 0x08: /* HCSPARAMS 2 */ 2382 ret = 0x0000000f; 2383 break; 2384 case 0x0c: /* HCSPARAMS 3 */ 2385 ret = 0x00000000; 2386 break; 2387 case 0x10: /* HCCPARAMS */ 2388 if (sizeof(dma_addr_t) == 4) { 2389 ret = 0x00081000; 2390 } else { 2391 ret = 0x00081001; 2392 } 2393 break; 2394 case 0x14: /* DBOFF */ 2395 ret = OFF_DOORBELL; 2396 break; 2397 case 0x18: /* RTSOFF */ 2398 ret = OFF_RUNTIME; 2399 break; 2400 2401 /* extended capabilities */ 2402 case 0x20: /* Supported Protocol:00 */ 2403 ret = 0x02000402; /* USB 2.0 */ 2404 break; 2405 case 0x24: /* Supported Protocol:04 */ 2406 ret = 0x20425455; /* "USB " */ 2407 break; 2408 case 0x28: /* Supported Protocol:08 */ 2409 ret = 0x00000001 | (xhci->numports_2<<8); 2410 break; 2411 case 0x2c: /* Supported Protocol:0c */ 2412 ret = 0x00000000; /* reserved */ 2413 break; 2414 case 0x30: /* Supported Protocol:00 */ 2415 ret = 0x03000002; /* USB 3.0 */ 2416 break; 2417 case 0x34: /* Supported Protocol:04 */ 2418 ret = 0x20425455; /* "USB " */ 2419 break; 2420 case 0x38: /* Supported Protocol:08 */ 2421 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2422 break; 2423 case 0x3c: /* Supported Protocol:0c */ 2424 ret = 0x00000000; /* reserved */ 2425 break; 2426 default: 2427 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2428 ret = 0; 2429 } 2430 2431 trace_usb_xhci_cap_read(reg, ret); 2432 return ret; 2433 } 2434 2435 static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size) 2436 { 2437 XHCIPort *port = ptr; 2438 uint32_t ret; 2439 2440 switch (reg) { 2441 case 0x00: /* PORTSC */ 2442 ret = port->portsc; 2443 break; 2444 case 0x04: /* PORTPMSC */ 2445 case 0x08: /* PORTLI */ 2446 ret = 0; 2447 break; 2448 case 0x0c: /* reserved */ 2449 default: 2450 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2451 port->portnr, (uint32_t)reg); 2452 ret = 0; 2453 } 2454 2455 trace_usb_xhci_port_read(port->portnr, reg, ret); 2456 return ret; 2457 } 2458 2459 static void xhci_port_write(void *ptr, target_phys_addr_t reg, 2460 uint64_t val, unsigned size) 2461 { 2462 XHCIPort *port = ptr; 2463 uint32_t portsc; 2464 2465 trace_usb_xhci_port_write(port->portnr, reg, val); 2466 2467 switch (reg) { 2468 case 0x00: /* PORTSC */ 2469 portsc = port->portsc; 2470 /* write-1-to-clear bits*/ 2471 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2472 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2473 if (val & PORTSC_LWS) { 2474 /* overwrite PLS only when LWS=1 */ 2475 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2476 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2477 } 2478 /* read/write bits */ 2479 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2480 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2481 /* write-1-to-start bits */ 2482 if (val & PORTSC_PR) { 2483 DPRINTF("xhci: port %d reset\n", port); 2484 usb_device_reset(port->uport->dev); 2485 portsc |= PORTSC_PRC | PORTSC_PED; 2486 } 2487 port->portsc = portsc; 2488 break; 2489 case 0x04: /* PORTPMSC */ 2490 case 0x08: /* PORTLI */ 2491 default: 2492 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2493 port->portnr, (uint32_t)reg); 2494 } 2495 } 2496 2497 static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size) 2498 { 2499 XHCIState *xhci = ptr; 2500 uint32_t ret; 2501 2502 switch (reg) { 2503 case 0x00: /* USBCMD */ 2504 ret = xhci->usbcmd; 2505 break; 2506 case 0x04: /* USBSTS */ 2507 ret = xhci->usbsts; 2508 break; 2509 case 0x08: /* PAGESIZE */ 2510 ret = 1; /* 4KiB */ 2511 break; 2512 case 0x14: /* DNCTRL */ 2513 ret = xhci->dnctrl; 2514 break; 2515 case 0x18: /* CRCR low */ 2516 ret = xhci->crcr_low & ~0xe; 2517 break; 2518 case 0x1c: /* CRCR high */ 2519 ret = xhci->crcr_high; 2520 break; 2521 case 0x30: /* DCBAAP low */ 2522 ret = xhci->dcbaap_low; 2523 break; 2524 case 0x34: /* DCBAAP high */ 2525 ret = xhci->dcbaap_high; 2526 break; 2527 case 0x38: /* CONFIG */ 2528 ret = xhci->config; 2529 break; 2530 default: 2531 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2532 ret = 0; 2533 } 2534 2535 trace_usb_xhci_oper_read(reg, ret); 2536 return ret; 2537 } 2538 2539 static void xhci_oper_write(void *ptr, target_phys_addr_t reg, 2540 uint64_t val, unsigned size) 2541 { 2542 XHCIState *xhci = ptr; 2543 2544 trace_usb_xhci_oper_write(reg, val); 2545 2546 switch (reg) { 2547 case 0x00: /* USBCMD */ 2548 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2549 xhci_run(xhci); 2550 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2551 xhci_stop(xhci); 2552 } 2553 xhci->usbcmd = val & 0xc0f; 2554 xhci_mfwrap_update(xhci); 2555 if (val & USBCMD_HCRST) { 2556 xhci_reset(&xhci->pci_dev.qdev); 2557 } 2558 xhci_intx_update(xhci); 2559 break; 2560 2561 case 0x04: /* USBSTS */ 2562 /* these bits are write-1-to-clear */ 2563 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2564 xhci_intx_update(xhci); 2565 break; 2566 2567 case 0x14: /* DNCTRL */ 2568 xhci->dnctrl = val & 0xffff; 2569 break; 2570 case 0x18: /* CRCR low */ 2571 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2572 break; 2573 case 0x1c: /* CRCR high */ 2574 xhci->crcr_high = val; 2575 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2576 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2577 xhci->crcr_low &= ~CRCR_CRR; 2578 xhci_event(xhci, &event, 0); 2579 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2580 } else { 2581 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2582 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2583 } 2584 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2585 break; 2586 case 0x30: /* DCBAAP low */ 2587 xhci->dcbaap_low = val & 0xffffffc0; 2588 break; 2589 case 0x34: /* DCBAAP high */ 2590 xhci->dcbaap_high = val; 2591 break; 2592 case 0x38: /* CONFIG */ 2593 xhci->config = val & 0xff; 2594 break; 2595 default: 2596 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2597 } 2598 } 2599 2600 static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg, 2601 unsigned size) 2602 { 2603 XHCIState *xhci = ptr; 2604 uint32_t ret = 0; 2605 2606 if (reg < 0x20) { 2607 switch (reg) { 2608 case 0x00: /* MFINDEX */ 2609 ret = xhci_mfindex_get(xhci) & 0x3fff; 2610 break; 2611 default: 2612 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2613 (int)reg); 2614 break; 2615 } 2616 } else { 2617 int v = (reg - 0x20) / 0x20; 2618 XHCIInterrupter *intr = &xhci->intr[v]; 2619 switch (reg & 0x1f) { 2620 case 0x00: /* IMAN */ 2621 ret = intr->iman; 2622 break; 2623 case 0x04: /* IMOD */ 2624 ret = intr->imod; 2625 break; 2626 case 0x08: /* ERSTSZ */ 2627 ret = intr->erstsz; 2628 break; 2629 case 0x10: /* ERSTBA low */ 2630 ret = intr->erstba_low; 2631 break; 2632 case 0x14: /* ERSTBA high */ 2633 ret = intr->erstba_high; 2634 break; 2635 case 0x18: /* ERDP low */ 2636 ret = intr->erdp_low; 2637 break; 2638 case 0x1c: /* ERDP high */ 2639 ret = intr->erdp_high; 2640 break; 2641 } 2642 } 2643 2644 trace_usb_xhci_runtime_read(reg, ret); 2645 return ret; 2646 } 2647 2648 static void xhci_runtime_write(void *ptr, target_phys_addr_t reg, 2649 uint64_t val, unsigned size) 2650 { 2651 XHCIState *xhci = ptr; 2652 int v = (reg - 0x20) / 0x20; 2653 XHCIInterrupter *intr = &xhci->intr[v]; 2654 trace_usb_xhci_runtime_write(reg, val); 2655 2656 if (reg < 0x20) { 2657 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2658 return; 2659 } 2660 2661 switch (reg & 0x1f) { 2662 case 0x00: /* IMAN */ 2663 if (val & IMAN_IP) { 2664 intr->iman &= ~IMAN_IP; 2665 } 2666 intr->iman &= ~IMAN_IE; 2667 intr->iman |= val & IMAN_IE; 2668 if (v == 0) { 2669 xhci_intx_update(xhci); 2670 } 2671 xhci_msix_update(xhci, v); 2672 break; 2673 case 0x04: /* IMOD */ 2674 intr->imod = val; 2675 break; 2676 case 0x08: /* ERSTSZ */ 2677 intr->erstsz = val & 0xffff; 2678 break; 2679 case 0x10: /* ERSTBA low */ 2680 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2681 intr->erstba_low = val & 0xffffffc0; */ 2682 intr->erstba_low = val & 0xfffffff0; 2683 break; 2684 case 0x14: /* ERSTBA high */ 2685 intr->erstba_high = val; 2686 xhci_er_reset(xhci, v); 2687 break; 2688 case 0x18: /* ERDP low */ 2689 if (val & ERDP_EHB) { 2690 intr->erdp_low &= ~ERDP_EHB; 2691 } 2692 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2693 break; 2694 case 0x1c: /* ERDP high */ 2695 intr->erdp_high = val; 2696 xhci_events_update(xhci, v); 2697 break; 2698 default: 2699 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2700 (int)reg); 2701 } 2702 } 2703 2704 static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg, 2705 unsigned size) 2706 { 2707 /* doorbells always read as 0 */ 2708 trace_usb_xhci_doorbell_read(reg, 0); 2709 return 0; 2710 } 2711 2712 static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg, 2713 uint64_t val, unsigned size) 2714 { 2715 XHCIState *xhci = ptr; 2716 2717 trace_usb_xhci_doorbell_write(reg, val); 2718 2719 if (!xhci_running(xhci)) { 2720 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2721 return; 2722 } 2723 2724 reg >>= 2; 2725 2726 if (reg == 0) { 2727 if (val == 0) { 2728 xhci_process_commands(xhci); 2729 } else { 2730 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2731 (uint32_t)val); 2732 } 2733 } else { 2734 if (reg > MAXSLOTS) { 2735 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2736 } else if (val > 31) { 2737 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2738 (int)reg, (uint32_t)val); 2739 } else { 2740 xhci_kick_ep(xhci, reg, val); 2741 } 2742 } 2743 } 2744 2745 static const MemoryRegionOps xhci_cap_ops = { 2746 .read = xhci_cap_read, 2747 .valid.min_access_size = 1, 2748 .valid.max_access_size = 4, 2749 .impl.min_access_size = 4, 2750 .impl.max_access_size = 4, 2751 .endianness = DEVICE_LITTLE_ENDIAN, 2752 }; 2753 2754 static const MemoryRegionOps xhci_oper_ops = { 2755 .read = xhci_oper_read, 2756 .write = xhci_oper_write, 2757 .valid.min_access_size = 4, 2758 .valid.max_access_size = 4, 2759 .endianness = DEVICE_LITTLE_ENDIAN, 2760 }; 2761 2762 static const MemoryRegionOps xhci_port_ops = { 2763 .read = xhci_port_read, 2764 .write = xhci_port_write, 2765 .valid.min_access_size = 4, 2766 .valid.max_access_size = 4, 2767 .endianness = DEVICE_LITTLE_ENDIAN, 2768 }; 2769 2770 static const MemoryRegionOps xhci_runtime_ops = { 2771 .read = xhci_runtime_read, 2772 .write = xhci_runtime_write, 2773 .valid.min_access_size = 4, 2774 .valid.max_access_size = 4, 2775 .endianness = DEVICE_LITTLE_ENDIAN, 2776 }; 2777 2778 static const MemoryRegionOps xhci_doorbell_ops = { 2779 .read = xhci_doorbell_read, 2780 .write = xhci_doorbell_write, 2781 .valid.min_access_size = 4, 2782 .valid.max_access_size = 4, 2783 .endianness = DEVICE_LITTLE_ENDIAN, 2784 }; 2785 2786 static void xhci_attach(USBPort *usbport) 2787 { 2788 XHCIState *xhci = usbport->opaque; 2789 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2790 2791 xhci_update_port(xhci, port, 0); 2792 } 2793 2794 static void xhci_detach(USBPort *usbport) 2795 { 2796 XHCIState *xhci = usbport->opaque; 2797 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2798 2799 xhci_update_port(xhci, port, 1); 2800 } 2801 2802 static void xhci_wakeup(USBPort *usbport) 2803 { 2804 XHCIState *xhci = usbport->opaque; 2805 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2806 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2807 port->portnr << 24}; 2808 uint32_t pls; 2809 2810 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2811 if (pls != 3) { 2812 return; 2813 } 2814 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2815 if (port->portsc & PORTSC_PLC) { 2816 return; 2817 } 2818 port->portsc |= PORTSC_PLC; 2819 xhci_event(xhci, &ev, 0); 2820 } 2821 2822 static void xhci_complete(USBPort *port, USBPacket *packet) 2823 { 2824 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2825 2826 xhci_complete_packet(xfer, packet->result); 2827 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2828 } 2829 2830 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2831 { 2832 USBBus *bus = usb_bus_from_device(child); 2833 XHCIState *xhci = container_of(bus, XHCIState, bus); 2834 int i; 2835 2836 for (i = 0; i < MAXSLOTS; i++) { 2837 if (xhci->slots[i].uport == uport) { 2838 xhci->slots[i].uport = NULL; 2839 } 2840 } 2841 } 2842 2843 static USBPortOps xhci_uport_ops = { 2844 .attach = xhci_attach, 2845 .detach = xhci_detach, 2846 .wakeup = xhci_wakeup, 2847 .complete = xhci_complete, 2848 .child_detach = xhci_child_detach, 2849 }; 2850 2851 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2852 { 2853 XHCISlot *slot; 2854 int slotid; 2855 2856 for (slotid = 1; slotid <= MAXSLOTS; slotid++) { 2857 slot = &xhci->slots[slotid-1]; 2858 if (slot->devaddr == dev->addr) { 2859 return slotid; 2860 } 2861 } 2862 return 0; 2863 } 2864 2865 static int xhci_find_epid(USBEndpoint *ep) 2866 { 2867 if (ep->nr == 0) { 2868 return 1; 2869 } 2870 if (ep->pid == USB_TOKEN_IN) { 2871 return ep->nr * 2 + 1; 2872 } else { 2873 return ep->nr * 2; 2874 } 2875 } 2876 2877 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2878 { 2879 XHCIState *xhci = container_of(bus, XHCIState, bus); 2880 int slotid; 2881 2882 DPRINTF("%s\n", __func__); 2883 slotid = xhci_find_slotid(xhci, ep->dev); 2884 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2885 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2886 return; 2887 } 2888 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2889 } 2890 2891 static USBBusOps xhci_bus_ops = { 2892 .wakeup_endpoint = xhci_wakeup_endpoint, 2893 }; 2894 2895 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2896 { 2897 XHCIPort *port; 2898 int i, usbports, speedmask; 2899 2900 xhci->usbsts = USBSTS_HCH; 2901 2902 if (xhci->numports_2 > MAXPORTS_2) { 2903 xhci->numports_2 = MAXPORTS_2; 2904 } 2905 if (xhci->numports_3 > MAXPORTS_3) { 2906 xhci->numports_3 = MAXPORTS_3; 2907 } 2908 usbports = MAX(xhci->numports_2, xhci->numports_3); 2909 xhci->numports = xhci->numports_2 + xhci->numports_3; 2910 2911 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2912 2913 for (i = 0; i < usbports; i++) { 2914 speedmask = 0; 2915 if (i < xhci->numports_2) { 2916 port = &xhci->ports[i]; 2917 port->portnr = i + 1; 2918 port->uport = &xhci->uports[i]; 2919 port->speedmask = 2920 USB_SPEED_MASK_LOW | 2921 USB_SPEED_MASK_FULL | 2922 USB_SPEED_MASK_HIGH; 2923 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 2924 speedmask |= port->speedmask; 2925 } 2926 if (i < xhci->numports_3) { 2927 port = &xhci->ports[i + xhci->numports_2]; 2928 port->portnr = i + 1 + xhci->numports_2; 2929 port->uport = &xhci->uports[i]; 2930 port->speedmask = USB_SPEED_MASK_SUPER; 2931 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 2932 speedmask |= port->speedmask; 2933 } 2934 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2935 &xhci_uport_ops, speedmask); 2936 } 2937 } 2938 2939 static int usb_xhci_initfn(struct PCIDevice *dev) 2940 { 2941 int i, ret; 2942 2943 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2944 2945 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2946 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2947 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2948 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2949 2950 usb_xhci_init(xhci, &dev->qdev); 2951 2952 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2953 2954 xhci->irq = xhci->pci_dev.irq[0]; 2955 2956 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 2957 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 2958 "capabilities", LEN_CAP); 2959 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 2960 "operational", 0x400); 2961 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 2962 "runtime", LEN_RUNTIME); 2963 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 2964 "doorbell", LEN_DOORBELL); 2965 2966 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 2967 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 2968 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 2969 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 2970 2971 for (i = 0; i < xhci->numports; i++) { 2972 XHCIPort *port = &xhci->ports[i]; 2973 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 2974 port->xhci = xhci; 2975 memory_region_init_io(&port->mem, &xhci_port_ops, port, 2976 port->name, 0x10); 2977 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 2978 } 2979 2980 pci_register_bar(&xhci->pci_dev, 0, 2981 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 2982 &xhci->mem); 2983 2984 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 2985 assert(ret >= 0); 2986 2987 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 2988 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); 2989 } 2990 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 2991 msix_init(&xhci->pci_dev, MAXINTRS, 2992 &xhci->mem, 0, OFF_MSIX_TABLE, 2993 &xhci->mem, 0, OFF_MSIX_PBA, 2994 0x90); 2995 } 2996 2997 return 0; 2998 } 2999 3000 static const VMStateDescription vmstate_xhci = { 3001 .name = "xhci", 3002 .unmigratable = 1, 3003 }; 3004 3005 static Property xhci_properties[] = { 3006 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3007 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3008 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3009 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3010 DEFINE_PROP_END_OF_LIST(), 3011 }; 3012 3013 static void xhci_class_init(ObjectClass *klass, void *data) 3014 { 3015 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3016 DeviceClass *dc = DEVICE_CLASS(klass); 3017 3018 dc->vmsd = &vmstate_xhci; 3019 dc->props = xhci_properties; 3020 dc->reset = xhci_reset; 3021 k->init = usb_xhci_initfn; 3022 k->vendor_id = PCI_VENDOR_ID_NEC; 3023 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3024 k->class_id = PCI_CLASS_SERIAL_USB; 3025 k->revision = 0x03; 3026 k->is_express = 1; 3027 } 3028 3029 static TypeInfo xhci_info = { 3030 .name = "nec-usb-xhci", 3031 .parent = TYPE_PCI_DEVICE, 3032 .instance_size = sizeof(XHCIState), 3033 .class_init = xhci_class_init, 3034 }; 3035 3036 static void xhci_register_types(void) 3037 { 3038 type_register_static(&xhci_info); 3039 } 3040 3041 type_init(xhci_register_types) 3042