1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool cancelled; 350 bool complete; 351 bool int_req; 352 unsigned int iso_pkts; 353 unsigned int slotid; 354 unsigned int epid; 355 unsigned int streamid; 356 bool in_xfer; 357 bool iso_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 XHCIStreamContext *sstreams; 377 }; 378 379 struct XHCIEPContext { 380 XHCIState *xhci; 381 unsigned int slotid; 382 unsigned int epid; 383 384 XHCIRing ring; 385 unsigned int next_xfer; 386 unsigned int comp_xfer; 387 XHCITransfer transfers[TD_QUEUE]; 388 XHCITransfer *retry; 389 EPType type; 390 dma_addr_t pctx; 391 unsigned int max_psize; 392 uint32_t state; 393 394 /* streams */ 395 unsigned int max_pstreams; 396 bool lsa; 397 unsigned int nr_pstreams; 398 XHCIStreamContext *pstreams; 399 400 /* iso xfer scheduling */ 401 unsigned int interval; 402 int64_t mfindex_last; 403 QEMUTimer *kick_timer; 404 }; 405 406 typedef struct XHCISlot { 407 bool enabled; 408 bool addressed; 409 dma_addr_t ctx; 410 USBPort *uport; 411 XHCIEPContext * eps[31]; 412 } XHCISlot; 413 414 typedef struct XHCIEvent { 415 TRBType type; 416 TRBCCode ccode; 417 uint64_t ptr; 418 uint32_t length; 419 uint32_t flags; 420 uint8_t slotid; 421 uint8_t epid; 422 } XHCIEvent; 423 424 typedef struct XHCIInterrupter { 425 uint32_t iman; 426 uint32_t imod; 427 uint32_t erstsz; 428 uint32_t erstba_low; 429 uint32_t erstba_high; 430 uint32_t erdp_low; 431 uint32_t erdp_high; 432 433 bool msix_used, er_pcs, er_full; 434 435 dma_addr_t er_start; 436 uint32_t er_size; 437 unsigned int er_ep_idx; 438 439 XHCIEvent ev_buffer[EV_QUEUE]; 440 unsigned int ev_buffer_put; 441 unsigned int ev_buffer_get; 442 443 } XHCIInterrupter; 444 445 struct XHCIState { 446 /*< private >*/ 447 PCIDevice parent_obj; 448 /*< public >*/ 449 450 USBBus bus; 451 qemu_irq irq; 452 MemoryRegion mem; 453 MemoryRegion mem_cap; 454 MemoryRegion mem_oper; 455 MemoryRegion mem_runtime; 456 MemoryRegion mem_doorbell; 457 458 /* properties */ 459 uint32_t numports_2; 460 uint32_t numports_3; 461 uint32_t numintrs; 462 uint32_t numslots; 463 uint32_t flags; 464 465 /* Operational Registers */ 466 uint32_t usbcmd; 467 uint32_t usbsts; 468 uint32_t dnctrl; 469 uint32_t crcr_low; 470 uint32_t crcr_high; 471 uint32_t dcbaap_low; 472 uint32_t dcbaap_high; 473 uint32_t config; 474 475 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 476 XHCIPort ports[MAXPORTS]; 477 XHCISlot slots[MAXSLOTS]; 478 uint32_t numports; 479 480 /* Runtime Registers */ 481 int64_t mfindex_start; 482 QEMUTimer *mfwrap_timer; 483 XHCIInterrupter intr[MAXINTRS]; 484 485 XHCIRing cmd_ring; 486 }; 487 488 #define TYPE_XHCI "nec-usb-xhci" 489 490 #define XHCI(obj) \ 491 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 492 493 typedef struct XHCIEvRingSeg { 494 uint32_t addr_low; 495 uint32_t addr_high; 496 uint32_t size; 497 uint32_t rsvd; 498 } XHCIEvRingSeg; 499 500 enum xhci_flags { 501 XHCI_FLAG_USE_MSI = 1, 502 XHCI_FLAG_USE_MSI_X, 503 }; 504 505 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 506 unsigned int epid, unsigned int streamid); 507 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 508 unsigned int epid); 509 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 510 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 511 512 static const char *TRBType_names[] = { 513 [TRB_RESERVED] = "TRB_RESERVED", 514 [TR_NORMAL] = "TR_NORMAL", 515 [TR_SETUP] = "TR_SETUP", 516 [TR_DATA] = "TR_DATA", 517 [TR_STATUS] = "TR_STATUS", 518 [TR_ISOCH] = "TR_ISOCH", 519 [TR_LINK] = "TR_LINK", 520 [TR_EVDATA] = "TR_EVDATA", 521 [TR_NOOP] = "TR_NOOP", 522 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 523 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 524 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 525 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 526 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 527 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 528 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 529 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 530 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 531 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 532 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 533 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 534 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 535 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 536 [CR_NOOP] = "CR_NOOP", 537 [ER_TRANSFER] = "ER_TRANSFER", 538 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 539 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 540 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 541 [ER_DOORBELL] = "ER_DOORBELL", 542 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 543 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 544 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 545 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 546 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 547 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 548 }; 549 550 static const char *TRBCCode_names[] = { 551 [CC_INVALID] = "CC_INVALID", 552 [CC_SUCCESS] = "CC_SUCCESS", 553 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 554 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 555 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 556 [CC_TRB_ERROR] = "CC_TRB_ERROR", 557 [CC_STALL_ERROR] = "CC_STALL_ERROR", 558 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 559 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 560 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 561 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 562 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 563 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 564 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 565 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 566 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 567 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 568 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 569 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 570 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 571 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 572 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 573 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 574 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 575 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 576 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 577 [CC_STOPPED] = "CC_STOPPED", 578 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 579 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 580 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 581 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 582 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 583 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 584 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 585 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 586 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 587 }; 588 589 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 590 { 591 if (index >= llen || list[index] == NULL) { 592 return "???"; 593 } 594 return list[index]; 595 } 596 597 static const char *trb_name(XHCITRB *trb) 598 { 599 return lookup_name(TRB_TYPE(*trb), TRBType_names, 600 ARRAY_SIZE(TRBType_names)); 601 } 602 603 static const char *event_name(XHCIEvent *event) 604 { 605 return lookup_name(event->ccode, TRBCCode_names, 606 ARRAY_SIZE(TRBCCode_names)); 607 } 608 609 static uint64_t xhci_mfindex_get(XHCIState *xhci) 610 { 611 int64_t now = qemu_get_clock_ns(vm_clock); 612 return (now - xhci->mfindex_start) / 125000; 613 } 614 615 static void xhci_mfwrap_update(XHCIState *xhci) 616 { 617 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 618 uint32_t mfindex, left; 619 int64_t now; 620 621 if ((xhci->usbcmd & bits) == bits) { 622 now = qemu_get_clock_ns(vm_clock); 623 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 624 left = 0x4000 - mfindex; 625 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 626 } else { 627 qemu_del_timer(xhci->mfwrap_timer); 628 } 629 } 630 631 static void xhci_mfwrap_timer(void *opaque) 632 { 633 XHCIState *xhci = opaque; 634 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 635 636 xhci_event(xhci, &wrap, 0); 637 xhci_mfwrap_update(xhci); 638 } 639 640 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 641 { 642 if (sizeof(dma_addr_t) == 4) { 643 return low; 644 } else { 645 return low | (((dma_addr_t)high << 16) << 16); 646 } 647 } 648 649 static inline dma_addr_t xhci_mask64(uint64_t addr) 650 { 651 if (sizeof(dma_addr_t) == 4) { 652 return addr & 0xffffffff; 653 } else { 654 return addr; 655 } 656 } 657 658 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 659 uint32_t *buf, size_t len) 660 { 661 int i; 662 663 assert((len % sizeof(uint32_t)) == 0); 664 665 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 666 667 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 668 buf[i] = le32_to_cpu(buf[i]); 669 } 670 } 671 672 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 673 uint32_t *buf, size_t len) 674 { 675 int i; 676 uint32_t tmp[len / sizeof(uint32_t)]; 677 678 assert((len % sizeof(uint32_t)) == 0); 679 680 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 681 tmp[i] = cpu_to_le32(buf[i]); 682 } 683 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 684 } 685 686 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 687 { 688 int index; 689 690 if (!uport->dev) { 691 return NULL; 692 } 693 switch (uport->dev->speed) { 694 case USB_SPEED_LOW: 695 case USB_SPEED_FULL: 696 case USB_SPEED_HIGH: 697 index = uport->index; 698 break; 699 case USB_SPEED_SUPER: 700 index = uport->index + xhci->numports_2; 701 break; 702 default: 703 return NULL; 704 } 705 return &xhci->ports[index]; 706 } 707 708 static void xhci_intx_update(XHCIState *xhci) 709 { 710 PCIDevice *pci_dev = PCI_DEVICE(xhci); 711 int level = 0; 712 713 if (msix_enabled(pci_dev) || 714 msi_enabled(pci_dev)) { 715 return; 716 } 717 718 if (xhci->intr[0].iman & IMAN_IP && 719 xhci->intr[0].iman & IMAN_IE && 720 xhci->usbcmd & USBCMD_INTE) { 721 level = 1; 722 } 723 724 trace_usb_xhci_irq_intx(level); 725 qemu_set_irq(xhci->irq, level); 726 } 727 728 static void xhci_msix_update(XHCIState *xhci, int v) 729 { 730 PCIDevice *pci_dev = PCI_DEVICE(xhci); 731 bool enabled; 732 733 if (!msix_enabled(pci_dev)) { 734 return; 735 } 736 737 enabled = xhci->intr[v].iman & IMAN_IE; 738 if (enabled == xhci->intr[v].msix_used) { 739 return; 740 } 741 742 if (enabled) { 743 trace_usb_xhci_irq_msix_use(v); 744 msix_vector_use(pci_dev, v); 745 xhci->intr[v].msix_used = true; 746 } else { 747 trace_usb_xhci_irq_msix_unuse(v); 748 msix_vector_unuse(pci_dev, v); 749 xhci->intr[v].msix_used = false; 750 } 751 } 752 753 static void xhci_intr_raise(XHCIState *xhci, int v) 754 { 755 PCIDevice *pci_dev = PCI_DEVICE(xhci); 756 757 xhci->intr[v].erdp_low |= ERDP_EHB; 758 xhci->intr[v].iman |= IMAN_IP; 759 xhci->usbsts |= USBSTS_EINT; 760 761 if (!(xhci->intr[v].iman & IMAN_IE)) { 762 return; 763 } 764 765 if (!(xhci->usbcmd & USBCMD_INTE)) { 766 return; 767 } 768 769 if (msix_enabled(pci_dev)) { 770 trace_usb_xhci_irq_msix(v); 771 msix_notify(pci_dev, v); 772 return; 773 } 774 775 if (msi_enabled(pci_dev)) { 776 trace_usb_xhci_irq_msi(v); 777 msi_notify(pci_dev, v); 778 return; 779 } 780 781 if (v == 0) { 782 trace_usb_xhci_irq_intx(1); 783 qemu_set_irq(xhci->irq, 1); 784 } 785 } 786 787 static inline int xhci_running(XHCIState *xhci) 788 { 789 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 790 } 791 792 static void xhci_die(XHCIState *xhci) 793 { 794 xhci->usbsts |= USBSTS_HCE; 795 fprintf(stderr, "xhci: asserted controller error\n"); 796 } 797 798 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 799 { 800 PCIDevice *pci_dev = PCI_DEVICE(xhci); 801 XHCIInterrupter *intr = &xhci->intr[v]; 802 XHCITRB ev_trb; 803 dma_addr_t addr; 804 805 ev_trb.parameter = cpu_to_le64(event->ptr); 806 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 807 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 808 event->flags | (event->type << TRB_TYPE_SHIFT); 809 if (intr->er_pcs) { 810 ev_trb.control |= TRB_C; 811 } 812 ev_trb.control = cpu_to_le32(ev_trb.control); 813 814 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 815 event_name(event), ev_trb.parameter, 816 ev_trb.status, ev_trb.control); 817 818 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 819 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 820 821 intr->er_ep_idx++; 822 if (intr->er_ep_idx >= intr->er_size) { 823 intr->er_ep_idx = 0; 824 intr->er_pcs = !intr->er_pcs; 825 } 826 } 827 828 static void xhci_events_update(XHCIState *xhci, int v) 829 { 830 XHCIInterrupter *intr = &xhci->intr[v]; 831 dma_addr_t erdp; 832 unsigned int dp_idx; 833 bool do_irq = 0; 834 835 if (xhci->usbsts & USBSTS_HCH) { 836 return; 837 } 838 839 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 840 if (erdp < intr->er_start || 841 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 842 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 843 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 844 v, intr->er_start, intr->er_size); 845 xhci_die(xhci); 846 return; 847 } 848 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 849 assert(dp_idx < intr->er_size); 850 851 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 852 * deadlocks when the ER is full. Hack it by holding off events until 853 * the driver decides to free at least half of the ring */ 854 if (intr->er_full) { 855 int er_free = dp_idx - intr->er_ep_idx; 856 if (er_free <= 0) { 857 er_free += intr->er_size; 858 } 859 if (er_free < (intr->er_size/2)) { 860 DPRINTF("xhci_events_update(): event ring still " 861 "more than half full (hack)\n"); 862 return; 863 } 864 } 865 866 while (intr->ev_buffer_put != intr->ev_buffer_get) { 867 assert(intr->er_full); 868 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 869 DPRINTF("xhci_events_update(): event ring full again\n"); 870 #ifndef ER_FULL_HACK 871 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 872 xhci_write_event(xhci, &full, v); 873 #endif 874 do_irq = 1; 875 break; 876 } 877 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 878 xhci_write_event(xhci, event, v); 879 intr->ev_buffer_get++; 880 do_irq = 1; 881 if (intr->ev_buffer_get == EV_QUEUE) { 882 intr->ev_buffer_get = 0; 883 } 884 } 885 886 if (do_irq) { 887 xhci_intr_raise(xhci, v); 888 } 889 890 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 891 DPRINTF("xhci_events_update(): event ring no longer full\n"); 892 intr->er_full = 0; 893 } 894 } 895 896 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 897 { 898 XHCIInterrupter *intr; 899 dma_addr_t erdp; 900 unsigned int dp_idx; 901 902 if (v >= xhci->numintrs) { 903 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 904 return; 905 } 906 intr = &xhci->intr[v]; 907 908 if (intr->er_full) { 909 DPRINTF("xhci_event(): ER full, queueing\n"); 910 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 911 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 912 return; 913 } 914 intr->ev_buffer[intr->ev_buffer_put++] = *event; 915 if (intr->ev_buffer_put == EV_QUEUE) { 916 intr->ev_buffer_put = 0; 917 } 918 return; 919 } 920 921 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 922 if (erdp < intr->er_start || 923 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 924 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 925 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 926 v, intr->er_start, intr->er_size); 927 xhci_die(xhci); 928 return; 929 } 930 931 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 932 assert(dp_idx < intr->er_size); 933 934 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 935 DPRINTF("xhci_event(): ER full, queueing\n"); 936 #ifndef ER_FULL_HACK 937 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 938 xhci_write_event(xhci, &full); 939 #endif 940 intr->er_full = 1; 941 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 942 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 943 return; 944 } 945 intr->ev_buffer[intr->ev_buffer_put++] = *event; 946 if (intr->ev_buffer_put == EV_QUEUE) { 947 intr->ev_buffer_put = 0; 948 } 949 } else { 950 xhci_write_event(xhci, event, v); 951 } 952 953 xhci_intr_raise(xhci, v); 954 } 955 956 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 957 dma_addr_t base) 958 { 959 ring->dequeue = base; 960 ring->ccs = 1; 961 } 962 963 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 964 dma_addr_t *addr) 965 { 966 PCIDevice *pci_dev = PCI_DEVICE(xhci); 967 968 while (1) { 969 TRBType type; 970 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 971 trb->addr = ring->dequeue; 972 trb->ccs = ring->ccs; 973 le64_to_cpus(&trb->parameter); 974 le32_to_cpus(&trb->status); 975 le32_to_cpus(&trb->control); 976 977 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 978 trb->parameter, trb->status, trb->control); 979 980 if ((trb->control & TRB_C) != ring->ccs) { 981 return 0; 982 } 983 984 type = TRB_TYPE(*trb); 985 986 if (type != TR_LINK) { 987 if (addr) { 988 *addr = ring->dequeue; 989 } 990 ring->dequeue += TRB_SIZE; 991 return type; 992 } else { 993 ring->dequeue = xhci_mask64(trb->parameter); 994 if (trb->control & TRB_LK_TC) { 995 ring->ccs = !ring->ccs; 996 } 997 } 998 } 999 } 1000 1001 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1002 { 1003 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1004 XHCITRB trb; 1005 int length = 0; 1006 dma_addr_t dequeue = ring->dequeue; 1007 bool ccs = ring->ccs; 1008 /* hack to bundle together the two/three TDs that make a setup transfer */ 1009 bool control_td_set = 0; 1010 1011 while (1) { 1012 TRBType type; 1013 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1014 le64_to_cpus(&trb.parameter); 1015 le32_to_cpus(&trb.status); 1016 le32_to_cpus(&trb.control); 1017 1018 if ((trb.control & TRB_C) != ccs) { 1019 return -length; 1020 } 1021 1022 type = TRB_TYPE(trb); 1023 1024 if (type == TR_LINK) { 1025 dequeue = xhci_mask64(trb.parameter); 1026 if (trb.control & TRB_LK_TC) { 1027 ccs = !ccs; 1028 } 1029 continue; 1030 } 1031 1032 length += 1; 1033 dequeue += TRB_SIZE; 1034 1035 if (type == TR_SETUP) { 1036 control_td_set = 1; 1037 } else if (type == TR_STATUS) { 1038 control_td_set = 0; 1039 } 1040 1041 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1042 return length; 1043 } 1044 } 1045 } 1046 1047 static void xhci_er_reset(XHCIState *xhci, int v) 1048 { 1049 XHCIInterrupter *intr = &xhci->intr[v]; 1050 XHCIEvRingSeg seg; 1051 1052 if (intr->erstsz == 0) { 1053 /* disabled */ 1054 intr->er_start = 0; 1055 intr->er_size = 0; 1056 return; 1057 } 1058 /* cache the (sole) event ring segment location */ 1059 if (intr->erstsz != 1) { 1060 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1061 xhci_die(xhci); 1062 return; 1063 } 1064 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1065 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1066 le32_to_cpus(&seg.addr_low); 1067 le32_to_cpus(&seg.addr_high); 1068 le32_to_cpus(&seg.size); 1069 if (seg.size < 16 || seg.size > 4096) { 1070 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1071 xhci_die(xhci); 1072 return; 1073 } 1074 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1075 intr->er_size = seg.size; 1076 1077 intr->er_ep_idx = 0; 1078 intr->er_pcs = 1; 1079 intr->er_full = 0; 1080 1081 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1082 v, intr->er_start, intr->er_size); 1083 } 1084 1085 static void xhci_run(XHCIState *xhci) 1086 { 1087 trace_usb_xhci_run(); 1088 xhci->usbsts &= ~USBSTS_HCH; 1089 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1090 } 1091 1092 static void xhci_stop(XHCIState *xhci) 1093 { 1094 trace_usb_xhci_stop(); 1095 xhci->usbsts |= USBSTS_HCH; 1096 xhci->crcr_low &= ~CRCR_CRR; 1097 } 1098 1099 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1100 dma_addr_t base) 1101 { 1102 XHCIStreamContext *stctx; 1103 unsigned int i; 1104 1105 stctx = g_new0(XHCIStreamContext, count); 1106 for (i = 0; i < count; i++) { 1107 stctx[i].pctx = base + i * 16; 1108 stctx[i].sct = -1; 1109 } 1110 return stctx; 1111 } 1112 1113 static void xhci_reset_streams(XHCIEPContext *epctx) 1114 { 1115 unsigned int i; 1116 1117 for (i = 0; i < epctx->nr_pstreams; i++) { 1118 epctx->pstreams[i].sct = -1; 1119 g_free(epctx->pstreams[i].sstreams); 1120 } 1121 } 1122 1123 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1124 { 1125 assert(epctx->pstreams == NULL); 1126 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1127 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1128 } 1129 1130 static void xhci_free_streams(XHCIEPContext *epctx) 1131 { 1132 int i; 1133 1134 assert(epctx->pstreams != NULL); 1135 1136 if (!epctx->lsa) { 1137 for (i = 0; i < epctx->nr_pstreams; i++) { 1138 g_free(epctx->pstreams[i].sstreams); 1139 } 1140 } 1141 g_free(epctx->pstreams); 1142 epctx->pstreams = NULL; 1143 epctx->nr_pstreams = 0; 1144 } 1145 1146 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1147 unsigned int streamid, 1148 uint32_t *cc_error) 1149 { 1150 XHCIStreamContext *sctx; 1151 dma_addr_t base; 1152 uint32_t ctx[2], sct; 1153 1154 assert(streamid != 0); 1155 if (epctx->lsa) { 1156 if (streamid >= epctx->nr_pstreams) { 1157 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1158 return NULL; 1159 } 1160 sctx = epctx->pstreams + streamid; 1161 } else { 1162 FIXME("secondary streams not implemented yet"); 1163 } 1164 1165 if (sctx->sct == -1) { 1166 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1167 fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n", 1168 __func__, streamid, sctx->pctx, ctx[0], ctx[1]); 1169 sct = (ctx[0] >> 1) & 0x07; 1170 if (epctx->lsa && sct != 1) { 1171 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1172 return NULL; 1173 } 1174 sctx->sct = sct; 1175 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1176 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1177 } 1178 return sctx; 1179 } 1180 1181 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1182 XHCIStreamContext *sctx, uint32_t state) 1183 { 1184 uint32_t ctx[5]; 1185 uint32_t ctx2[2]; 1186 1187 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1188 ctx[0] &= ~EP_STATE_MASK; 1189 ctx[0] |= state; 1190 1191 /* update ring dequeue ptr */ 1192 if (epctx->nr_pstreams) { 1193 if (sctx != NULL) { 1194 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1195 ctx2[0] &= 0xe; 1196 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1197 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1198 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1199 } 1200 } else { 1201 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1202 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1203 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1204 epctx->pctx, state, ctx[3], ctx[2]); 1205 } 1206 1207 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1208 epctx->state = state; 1209 } 1210 1211 static void xhci_ep_kick_timer(void *opaque) 1212 { 1213 XHCIEPContext *epctx = opaque; 1214 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1215 } 1216 1217 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1218 unsigned int slotid, 1219 unsigned int epid) 1220 { 1221 XHCIEPContext *epctx; 1222 int i; 1223 1224 epctx = g_new0(XHCIEPContext, 1); 1225 epctx->xhci = xhci; 1226 epctx->slotid = slotid; 1227 epctx->epid = epid; 1228 1229 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1230 usb_packet_init(&epctx->transfers[i].packet); 1231 } 1232 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1233 1234 return epctx; 1235 } 1236 1237 static void xhci_init_epctx(XHCIEPContext *epctx, 1238 dma_addr_t pctx, uint32_t *ctx) 1239 { 1240 dma_addr_t dequeue; 1241 1242 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1243 1244 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1245 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1246 epctx->pctx = pctx; 1247 epctx->max_psize = ctx[1]>>16; 1248 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1249 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1250 epctx->lsa = (ctx[0] >> 15) & 1; 1251 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1252 epid/2, epid%2, epctx->max_psize); 1253 if (epctx->max_pstreams) { 1254 xhci_alloc_streams(epctx, dequeue); 1255 } else { 1256 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1257 epctx->ring.ccs = ctx[2] & 1; 1258 } 1259 1260 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1261 } 1262 1263 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1264 unsigned int epid, dma_addr_t pctx, 1265 uint32_t *ctx) 1266 { 1267 XHCISlot *slot; 1268 XHCIEPContext *epctx; 1269 1270 trace_usb_xhci_ep_enable(slotid, epid); 1271 assert(slotid >= 1 && slotid <= xhci->numslots); 1272 assert(epid >= 1 && epid <= 31); 1273 1274 slot = &xhci->slots[slotid-1]; 1275 if (slot->eps[epid-1]) { 1276 xhci_disable_ep(xhci, slotid, epid); 1277 } 1278 1279 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1280 slot->eps[epid-1] = epctx; 1281 xhci_init_epctx(epctx, pctx, ctx); 1282 1283 epctx->mfindex_last = 0; 1284 1285 epctx->state = EP_RUNNING; 1286 ctx[0] &= ~EP_STATE_MASK; 1287 ctx[0] |= EP_RUNNING; 1288 1289 return CC_SUCCESS; 1290 } 1291 1292 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1293 { 1294 int killed = 0; 1295 1296 if (t->running_async) { 1297 usb_cancel_packet(&t->packet); 1298 t->running_async = 0; 1299 t->cancelled = 1; 1300 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1301 killed = 1; 1302 } 1303 if (t->running_retry) { 1304 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1305 if (epctx) { 1306 epctx->retry = NULL; 1307 qemu_del_timer(epctx->kick_timer); 1308 } 1309 t->running_retry = 0; 1310 } 1311 if (t->trbs) { 1312 g_free(t->trbs); 1313 } 1314 1315 t->trbs = NULL; 1316 t->trb_count = t->trb_alloced = 0; 1317 1318 return killed; 1319 } 1320 1321 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1322 unsigned int epid) 1323 { 1324 XHCISlot *slot; 1325 XHCIEPContext *epctx; 1326 int i, xferi, killed = 0; 1327 USBEndpoint *ep = NULL; 1328 assert(slotid >= 1 && slotid <= xhci->numslots); 1329 assert(epid >= 1 && epid <= 31); 1330 1331 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1332 1333 slot = &xhci->slots[slotid-1]; 1334 1335 if (!slot->eps[epid-1]) { 1336 return 0; 1337 } 1338 1339 epctx = slot->eps[epid-1]; 1340 1341 xferi = epctx->next_xfer; 1342 for (i = 0; i < TD_QUEUE; i++) { 1343 if (epctx->transfers[xferi].packet.ep) { 1344 ep = epctx->transfers[xferi].packet.ep; 1345 } 1346 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1347 epctx->transfers[xferi].packet.ep = NULL; 1348 xferi = (xferi + 1) % TD_QUEUE; 1349 } 1350 if (ep) { 1351 usb_device_ep_stopped(ep->dev, ep); 1352 } 1353 return killed; 1354 } 1355 1356 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1357 unsigned int epid) 1358 { 1359 XHCISlot *slot; 1360 XHCIEPContext *epctx; 1361 1362 trace_usb_xhci_ep_disable(slotid, epid); 1363 assert(slotid >= 1 && slotid <= xhci->numslots); 1364 assert(epid >= 1 && epid <= 31); 1365 1366 slot = &xhci->slots[slotid-1]; 1367 1368 if (!slot->eps[epid-1]) { 1369 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1370 return CC_SUCCESS; 1371 } 1372 1373 xhci_ep_nuke_xfers(xhci, slotid, epid); 1374 1375 epctx = slot->eps[epid-1]; 1376 1377 if (epctx->nr_pstreams) { 1378 xhci_free_streams(epctx); 1379 } 1380 1381 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1382 1383 qemu_free_timer(epctx->kick_timer); 1384 g_free(epctx); 1385 slot->eps[epid-1] = NULL; 1386 1387 return CC_SUCCESS; 1388 } 1389 1390 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1391 unsigned int epid) 1392 { 1393 XHCISlot *slot; 1394 XHCIEPContext *epctx; 1395 1396 trace_usb_xhci_ep_stop(slotid, epid); 1397 assert(slotid >= 1 && slotid <= xhci->numslots); 1398 1399 if (epid < 1 || epid > 31) { 1400 fprintf(stderr, "xhci: bad ep %d\n", epid); 1401 return CC_TRB_ERROR; 1402 } 1403 1404 slot = &xhci->slots[slotid-1]; 1405 1406 if (!slot->eps[epid-1]) { 1407 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1408 return CC_EP_NOT_ENABLED_ERROR; 1409 } 1410 1411 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1412 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1413 "data might be lost\n"); 1414 } 1415 1416 epctx = slot->eps[epid-1]; 1417 1418 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1419 1420 if (epctx->nr_pstreams) { 1421 xhci_reset_streams(epctx); 1422 } 1423 1424 return CC_SUCCESS; 1425 } 1426 1427 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1428 unsigned int epid) 1429 { 1430 XHCISlot *slot; 1431 XHCIEPContext *epctx; 1432 1433 trace_usb_xhci_ep_reset(slotid, epid); 1434 assert(slotid >= 1 && slotid <= xhci->numslots); 1435 1436 if (epid < 1 || epid > 31) { 1437 fprintf(stderr, "xhci: bad ep %d\n", epid); 1438 return CC_TRB_ERROR; 1439 } 1440 1441 slot = &xhci->slots[slotid-1]; 1442 1443 if (!slot->eps[epid-1]) { 1444 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1445 return CC_EP_NOT_ENABLED_ERROR; 1446 } 1447 1448 epctx = slot->eps[epid-1]; 1449 1450 if (epctx->state != EP_HALTED) { 1451 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1452 epid, epctx->state); 1453 return CC_CONTEXT_STATE_ERROR; 1454 } 1455 1456 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1457 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1458 "data might be lost\n"); 1459 } 1460 1461 uint8_t ep = epid>>1; 1462 1463 if (epid & 1) { 1464 ep |= 0x80; 1465 } 1466 1467 if (!xhci->slots[slotid-1].uport || 1468 !xhci->slots[slotid-1].uport->dev) { 1469 return CC_USB_TRANSACTION_ERROR; 1470 } 1471 1472 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1473 1474 if (epctx->nr_pstreams) { 1475 xhci_reset_streams(epctx); 1476 } 1477 1478 return CC_SUCCESS; 1479 } 1480 1481 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1482 unsigned int epid, unsigned int streamid, 1483 uint64_t pdequeue) 1484 { 1485 XHCISlot *slot; 1486 XHCIEPContext *epctx; 1487 XHCIStreamContext *sctx; 1488 dma_addr_t dequeue; 1489 1490 assert(slotid >= 1 && slotid <= xhci->numslots); 1491 1492 if (epid < 1 || epid > 31) { 1493 fprintf(stderr, "xhci: bad ep %d\n", epid); 1494 return CC_TRB_ERROR; 1495 } 1496 1497 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1498 dequeue = xhci_mask64(pdequeue); 1499 1500 slot = &xhci->slots[slotid-1]; 1501 1502 if (!slot->eps[epid-1]) { 1503 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1504 return CC_EP_NOT_ENABLED_ERROR; 1505 } 1506 1507 epctx = slot->eps[epid-1]; 1508 1509 if (epctx->state != EP_STOPPED) { 1510 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1511 return CC_CONTEXT_STATE_ERROR; 1512 } 1513 1514 if (epctx->nr_pstreams) { 1515 uint32_t err; 1516 sctx = xhci_find_stream(epctx, streamid, &err); 1517 if (sctx == NULL) { 1518 return err; 1519 } 1520 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1521 sctx->ring.ccs = dequeue & 1; 1522 } else { 1523 sctx = NULL; 1524 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1525 epctx->ring.ccs = dequeue & 1; 1526 } 1527 1528 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1529 1530 return CC_SUCCESS; 1531 } 1532 1533 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1534 { 1535 XHCIState *xhci = xfer->xhci; 1536 int i; 1537 1538 xfer->int_req = false; 1539 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1540 for (i = 0; i < xfer->trb_count; i++) { 1541 XHCITRB *trb = &xfer->trbs[i]; 1542 dma_addr_t addr; 1543 unsigned int chunk = 0; 1544 1545 if (trb->control & TRB_TR_IOC) { 1546 xfer->int_req = true; 1547 } 1548 1549 switch (TRB_TYPE(*trb)) { 1550 case TR_DATA: 1551 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1552 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1553 goto err; 1554 } 1555 /* fallthrough */ 1556 case TR_NORMAL: 1557 case TR_ISOCH: 1558 addr = xhci_mask64(trb->parameter); 1559 chunk = trb->status & 0x1ffff; 1560 if (trb->control & TRB_TR_IDT) { 1561 if (chunk > 8 || in_xfer) { 1562 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1563 goto err; 1564 } 1565 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1566 } else { 1567 qemu_sglist_add(&xfer->sgl, addr, chunk); 1568 } 1569 break; 1570 } 1571 } 1572 1573 return 0; 1574 1575 err: 1576 qemu_sglist_destroy(&xfer->sgl); 1577 xhci_die(xhci); 1578 return -1; 1579 } 1580 1581 static void xhci_xfer_unmap(XHCITransfer *xfer) 1582 { 1583 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1584 qemu_sglist_destroy(&xfer->sgl); 1585 } 1586 1587 static void xhci_xfer_report(XHCITransfer *xfer) 1588 { 1589 uint32_t edtla = 0; 1590 unsigned int left; 1591 bool reported = 0; 1592 bool shortpkt = 0; 1593 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1594 XHCIState *xhci = xfer->xhci; 1595 int i; 1596 1597 left = xfer->packet.actual_length; 1598 1599 for (i = 0; i < xfer->trb_count; i++) { 1600 XHCITRB *trb = &xfer->trbs[i]; 1601 unsigned int chunk = 0; 1602 1603 switch (TRB_TYPE(*trb)) { 1604 case TR_DATA: 1605 case TR_NORMAL: 1606 case TR_ISOCH: 1607 chunk = trb->status & 0x1ffff; 1608 if (chunk > left) { 1609 chunk = left; 1610 if (xfer->status == CC_SUCCESS) { 1611 shortpkt = 1; 1612 } 1613 } 1614 left -= chunk; 1615 edtla += chunk; 1616 break; 1617 case TR_STATUS: 1618 reported = 0; 1619 shortpkt = 0; 1620 break; 1621 } 1622 1623 if (!reported && ((trb->control & TRB_TR_IOC) || 1624 (shortpkt && (trb->control & TRB_TR_ISP)) || 1625 (xfer->status != CC_SUCCESS && left == 0))) { 1626 event.slotid = xfer->slotid; 1627 event.epid = xfer->epid; 1628 event.length = (trb->status & 0x1ffff) - chunk; 1629 event.flags = 0; 1630 event.ptr = trb->addr; 1631 if (xfer->status == CC_SUCCESS) { 1632 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1633 } else { 1634 event.ccode = xfer->status; 1635 } 1636 if (TRB_TYPE(*trb) == TR_EVDATA) { 1637 event.ptr = trb->parameter; 1638 event.flags |= TRB_EV_ED; 1639 event.length = edtla & 0xffffff; 1640 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1641 edtla = 0; 1642 } 1643 xhci_event(xhci, &event, TRB_INTR(*trb)); 1644 reported = 1; 1645 if (xfer->status != CC_SUCCESS) { 1646 return; 1647 } 1648 } 1649 } 1650 } 1651 1652 static void xhci_stall_ep(XHCITransfer *xfer) 1653 { 1654 XHCIState *xhci = xfer->xhci; 1655 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1656 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1657 uint32_t err; 1658 XHCIStreamContext *sctx; 1659 1660 if (epctx->nr_pstreams) { 1661 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1662 if (sctx == NULL) { 1663 return; 1664 } 1665 sctx->ring.dequeue = xfer->trbs[0].addr; 1666 sctx->ring.ccs = xfer->trbs[0].ccs; 1667 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1668 } else { 1669 epctx->ring.dequeue = xfer->trbs[0].addr; 1670 epctx->ring.ccs = xfer->trbs[0].ccs; 1671 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1672 } 1673 } 1674 1675 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1676 XHCIEPContext *epctx); 1677 1678 static int xhci_setup_packet(XHCITransfer *xfer) 1679 { 1680 XHCIState *xhci = xfer->xhci; 1681 USBDevice *dev; 1682 USBEndpoint *ep; 1683 int dir; 1684 1685 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1686 1687 if (xfer->packet.ep) { 1688 ep = xfer->packet.ep; 1689 dev = ep->dev; 1690 } else { 1691 if (!xhci->slots[xfer->slotid-1].uport) { 1692 fprintf(stderr, "xhci: slot %d has no device\n", 1693 xfer->slotid); 1694 return -1; 1695 } 1696 dev = xhci->slots[xfer->slotid-1].uport->dev; 1697 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1698 } 1699 1700 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1701 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1702 xfer->trbs[0].addr, false, xfer->int_req); 1703 usb_packet_map(&xfer->packet, &xfer->sgl); 1704 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1705 xfer->packet.pid, dev->addr, ep->nr); 1706 return 0; 1707 } 1708 1709 static int xhci_complete_packet(XHCITransfer *xfer) 1710 { 1711 if (xfer->packet.status == USB_RET_ASYNC) { 1712 trace_usb_xhci_xfer_async(xfer); 1713 xfer->running_async = 1; 1714 xfer->running_retry = 0; 1715 xfer->complete = 0; 1716 xfer->cancelled = 0; 1717 return 0; 1718 } else if (xfer->packet.status == USB_RET_NAK) { 1719 trace_usb_xhci_xfer_nak(xfer); 1720 xfer->running_async = 0; 1721 xfer->running_retry = 1; 1722 xfer->complete = 0; 1723 xfer->cancelled = 0; 1724 return 0; 1725 } else { 1726 xfer->running_async = 0; 1727 xfer->running_retry = 0; 1728 xfer->complete = 1; 1729 xhci_xfer_unmap(xfer); 1730 } 1731 1732 if (xfer->packet.status == USB_RET_SUCCESS) { 1733 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1734 xfer->status = CC_SUCCESS; 1735 xhci_xfer_report(xfer); 1736 return 0; 1737 } 1738 1739 /* error */ 1740 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1741 switch (xfer->packet.status) { 1742 case USB_RET_NODEV: 1743 case USB_RET_IOERROR: 1744 xfer->status = CC_USB_TRANSACTION_ERROR; 1745 xhci_xfer_report(xfer); 1746 xhci_stall_ep(xfer); 1747 break; 1748 case USB_RET_STALL: 1749 xfer->status = CC_STALL_ERROR; 1750 xhci_xfer_report(xfer); 1751 xhci_stall_ep(xfer); 1752 break; 1753 case USB_RET_BABBLE: 1754 xfer->status = CC_BABBLE_DETECTED; 1755 xhci_xfer_report(xfer); 1756 xhci_stall_ep(xfer); 1757 break; 1758 default: 1759 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1760 xfer->packet.status); 1761 FIXME("unhandled USB_RET_*"); 1762 } 1763 return 0; 1764 } 1765 1766 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1767 { 1768 XHCITRB *trb_setup, *trb_status; 1769 uint8_t bmRequestType; 1770 1771 trb_setup = &xfer->trbs[0]; 1772 trb_status = &xfer->trbs[xfer->trb_count-1]; 1773 1774 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1775 1776 /* at most one Event Data TRB allowed after STATUS */ 1777 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1778 trb_status--; 1779 } 1780 1781 /* do some sanity checks */ 1782 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1783 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1784 TRB_TYPE(*trb_setup)); 1785 return -1; 1786 } 1787 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1788 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1789 TRB_TYPE(*trb_status)); 1790 return -1; 1791 } 1792 if (!(trb_setup->control & TRB_TR_IDT)) { 1793 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1794 return -1; 1795 } 1796 if ((trb_setup->status & 0x1ffff) != 8) { 1797 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1798 (trb_setup->status & 0x1ffff)); 1799 return -1; 1800 } 1801 1802 bmRequestType = trb_setup->parameter; 1803 1804 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1805 xfer->iso_xfer = false; 1806 1807 if (xhci_setup_packet(xfer) < 0) { 1808 return -1; 1809 } 1810 xfer->packet.parameter = trb_setup->parameter; 1811 1812 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1813 1814 xhci_complete_packet(xfer); 1815 if (!xfer->running_async && !xfer->running_retry) { 1816 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1817 } 1818 return 0; 1819 } 1820 1821 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1822 XHCIEPContext *epctx, uint64_t mfindex) 1823 { 1824 if (xfer->trbs[0].control & TRB_TR_SIA) { 1825 uint64_t asap = ((mfindex + epctx->interval - 1) & 1826 ~(epctx->interval-1)); 1827 if (asap >= epctx->mfindex_last && 1828 asap <= epctx->mfindex_last + epctx->interval * 4) { 1829 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1830 } else { 1831 xfer->mfindex_kick = asap; 1832 } 1833 } else { 1834 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1835 & TRB_TR_FRAMEID_MASK; 1836 xfer->mfindex_kick |= mfindex & ~0x3fff; 1837 if (xfer->mfindex_kick < mfindex) { 1838 xfer->mfindex_kick += 0x4000; 1839 } 1840 } 1841 } 1842 1843 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1844 XHCIEPContext *epctx, uint64_t mfindex) 1845 { 1846 if (xfer->mfindex_kick > mfindex) { 1847 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1848 (xfer->mfindex_kick - mfindex) * 125000); 1849 xfer->running_retry = 1; 1850 } else { 1851 epctx->mfindex_last = xfer->mfindex_kick; 1852 qemu_del_timer(epctx->kick_timer); 1853 xfer->running_retry = 0; 1854 } 1855 } 1856 1857 1858 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1859 { 1860 uint64_t mfindex; 1861 1862 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1863 1864 xfer->in_xfer = epctx->type>>2; 1865 1866 switch(epctx->type) { 1867 case ET_INTR_OUT: 1868 case ET_INTR_IN: 1869 case ET_BULK_OUT: 1870 case ET_BULK_IN: 1871 xfer->pkts = 0; 1872 xfer->iso_xfer = false; 1873 break; 1874 case ET_ISO_OUT: 1875 case ET_ISO_IN: 1876 xfer->pkts = 1; 1877 xfer->iso_xfer = true; 1878 mfindex = xhci_mfindex_get(xhci); 1879 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1880 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1881 if (xfer->running_retry) { 1882 return -1; 1883 } 1884 break; 1885 default: 1886 fprintf(stderr, "xhci: unknown or unhandled EP " 1887 "(type %d, in %d, ep %02x)\n", 1888 epctx->type, xfer->in_xfer, xfer->epid); 1889 return -1; 1890 } 1891 1892 if (xhci_setup_packet(xfer) < 0) { 1893 return -1; 1894 } 1895 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1896 1897 xhci_complete_packet(xfer); 1898 if (!xfer->running_async && !xfer->running_retry) { 1899 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1900 } 1901 return 0; 1902 } 1903 1904 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1905 { 1906 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1907 return xhci_submit(xhci, xfer, epctx); 1908 } 1909 1910 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1911 unsigned int epid, unsigned int streamid) 1912 { 1913 XHCIStreamContext *stctx; 1914 XHCIEPContext *epctx; 1915 XHCIRing *ring; 1916 USBEndpoint *ep = NULL; 1917 uint64_t mfindex; 1918 int length; 1919 int i; 1920 1921 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1922 assert(slotid >= 1 && slotid <= xhci->numslots); 1923 assert(epid >= 1 && epid <= 31); 1924 1925 if (!xhci->slots[slotid-1].enabled) { 1926 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1927 return; 1928 } 1929 epctx = xhci->slots[slotid-1].eps[epid-1]; 1930 if (!epctx) { 1931 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1932 epid, slotid); 1933 return; 1934 } 1935 1936 if (epctx->retry) { 1937 XHCITransfer *xfer = epctx->retry; 1938 1939 trace_usb_xhci_xfer_retry(xfer); 1940 assert(xfer->running_retry); 1941 if (xfer->iso_xfer) { 1942 /* retry delayed iso transfer */ 1943 mfindex = xhci_mfindex_get(xhci); 1944 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1945 if (xfer->running_retry) { 1946 return; 1947 } 1948 if (xhci_setup_packet(xfer) < 0) { 1949 return; 1950 } 1951 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1952 assert(xfer->packet.status != USB_RET_NAK); 1953 xhci_complete_packet(xfer); 1954 } else { 1955 /* retry nak'ed transfer */ 1956 if (xhci_setup_packet(xfer) < 0) { 1957 return; 1958 } 1959 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1960 if (xfer->packet.status == USB_RET_NAK) { 1961 return; 1962 } 1963 xhci_complete_packet(xfer); 1964 } 1965 assert(!xfer->running_retry); 1966 epctx->retry = NULL; 1967 } 1968 1969 if (epctx->state == EP_HALTED) { 1970 DPRINTF("xhci: ep halted, not running schedule\n"); 1971 return; 1972 } 1973 1974 1975 if (epctx->nr_pstreams) { 1976 uint32_t err; 1977 stctx = xhci_find_stream(epctx, streamid, &err); 1978 if (stctx == NULL) { 1979 return; 1980 } 1981 ring = &stctx->ring; 1982 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 1983 } else { 1984 ring = &epctx->ring; 1985 streamid = 0; 1986 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 1987 } 1988 assert(ring->dequeue != 0); 1989 1990 while (1) { 1991 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1992 if (xfer->running_async || xfer->running_retry) { 1993 break; 1994 } 1995 length = xhci_ring_chain_length(xhci, ring); 1996 if (length < 0) { 1997 break; 1998 } else if (length == 0) { 1999 break; 2000 } 2001 if (xfer->trbs && xfer->trb_alloced < length) { 2002 xfer->trb_count = 0; 2003 xfer->trb_alloced = 0; 2004 g_free(xfer->trbs); 2005 xfer->trbs = NULL; 2006 } 2007 if (!xfer->trbs) { 2008 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 2009 xfer->trb_alloced = length; 2010 } 2011 xfer->trb_count = length; 2012 2013 for (i = 0; i < length; i++) { 2014 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2015 } 2016 xfer->xhci = xhci; 2017 xfer->epid = epid; 2018 xfer->slotid = slotid; 2019 xfer->streamid = streamid; 2020 2021 if (epid == 1) { 2022 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2023 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2024 ep = xfer->packet.ep; 2025 } else { 2026 fprintf(stderr, "xhci: error firing CTL transfer\n"); 2027 } 2028 } else { 2029 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2030 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2031 ep = xfer->packet.ep; 2032 } else { 2033 if (!xfer->iso_xfer) { 2034 fprintf(stderr, "xhci: error firing data transfer\n"); 2035 } 2036 } 2037 } 2038 2039 if (epctx->state == EP_HALTED) { 2040 break; 2041 } 2042 if (xfer->running_retry) { 2043 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2044 epctx->retry = xfer; 2045 break; 2046 } 2047 } 2048 if (ep) { 2049 usb_device_flush_ep_queue(ep->dev, ep); 2050 } 2051 } 2052 2053 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2054 { 2055 trace_usb_xhci_slot_enable(slotid); 2056 assert(slotid >= 1 && slotid <= xhci->numslots); 2057 xhci->slots[slotid-1].enabled = 1; 2058 xhci->slots[slotid-1].uport = NULL; 2059 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2060 2061 return CC_SUCCESS; 2062 } 2063 2064 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2065 { 2066 int i; 2067 2068 trace_usb_xhci_slot_disable(slotid); 2069 assert(slotid >= 1 && slotid <= xhci->numslots); 2070 2071 for (i = 1; i <= 31; i++) { 2072 if (xhci->slots[slotid-1].eps[i-1]) { 2073 xhci_disable_ep(xhci, slotid, i); 2074 } 2075 } 2076 2077 xhci->slots[slotid-1].enabled = 0; 2078 xhci->slots[slotid-1].addressed = 0; 2079 return CC_SUCCESS; 2080 } 2081 2082 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2083 { 2084 USBPort *uport; 2085 char path[32]; 2086 int i, pos, port; 2087 2088 port = (slot_ctx[1]>>16) & 0xFF; 2089 port = xhci->ports[port-1].uport->index+1; 2090 pos = snprintf(path, sizeof(path), "%d", port); 2091 for (i = 0; i < 5; i++) { 2092 port = (slot_ctx[0] >> 4*i) & 0x0f; 2093 if (!port) { 2094 break; 2095 } 2096 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2097 } 2098 2099 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2100 if (strcmp(uport->path, path) == 0) { 2101 return uport; 2102 } 2103 } 2104 return NULL; 2105 } 2106 2107 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2108 uint64_t pictx, bool bsr) 2109 { 2110 XHCISlot *slot; 2111 USBPort *uport; 2112 USBDevice *dev; 2113 dma_addr_t ictx, octx, dcbaap; 2114 uint64_t poctx; 2115 uint32_t ictl_ctx[2]; 2116 uint32_t slot_ctx[4]; 2117 uint32_t ep0_ctx[5]; 2118 int i; 2119 TRBCCode res; 2120 2121 trace_usb_xhci_slot_address(slotid); 2122 assert(slotid >= 1 && slotid <= xhci->numslots); 2123 2124 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2125 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2126 ictx = xhci_mask64(pictx); 2127 octx = xhci_mask64(poctx); 2128 2129 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2130 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2131 2132 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2133 2134 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2135 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2136 ictl_ctx[0], ictl_ctx[1]); 2137 return CC_TRB_ERROR; 2138 } 2139 2140 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2141 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2142 2143 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2144 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2145 2146 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2147 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2148 2149 uport = xhci_lookup_uport(xhci, slot_ctx); 2150 if (uport == NULL) { 2151 fprintf(stderr, "xhci: port not found\n"); 2152 return CC_TRB_ERROR; 2153 } 2154 2155 dev = uport->dev; 2156 if (!dev) { 2157 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2158 return CC_USB_TRANSACTION_ERROR; 2159 } 2160 2161 for (i = 0; i < xhci->numslots; i++) { 2162 if (i == slotid-1) { 2163 continue; 2164 } 2165 if (xhci->slots[i].uport == uport) { 2166 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2167 uport->path, i+1); 2168 return CC_TRB_ERROR; 2169 } 2170 } 2171 2172 slot = &xhci->slots[slotid-1]; 2173 slot->uport = uport; 2174 slot->ctx = octx; 2175 2176 if (bsr) { 2177 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2178 } else { 2179 USBPacket p; 2180 uint8_t buf[1]; 2181 2182 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2183 usb_device_reset(dev); 2184 memset(&p, 0, sizeof(p)); 2185 usb_packet_addbuf(&p, buf, sizeof(buf)); 2186 usb_packet_setup(&p, USB_TOKEN_OUT, 2187 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2188 0, false, false); 2189 usb_device_handle_control(dev, &p, 2190 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2191 slotid, 0, 0, NULL); 2192 assert(p.status != USB_RET_ASYNC); 2193 } 2194 2195 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2196 2197 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2198 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2199 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2200 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2201 2202 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2203 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2204 2205 xhci->slots[slotid-1].addressed = 1; 2206 return res; 2207 } 2208 2209 2210 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2211 uint64_t pictx, bool dc) 2212 { 2213 dma_addr_t ictx, octx; 2214 uint32_t ictl_ctx[2]; 2215 uint32_t slot_ctx[4]; 2216 uint32_t islot_ctx[4]; 2217 uint32_t ep_ctx[5]; 2218 int i; 2219 TRBCCode res; 2220 2221 trace_usb_xhci_slot_configure(slotid); 2222 assert(slotid >= 1 && slotid <= xhci->numslots); 2223 2224 ictx = xhci_mask64(pictx); 2225 octx = xhci->slots[slotid-1].ctx; 2226 2227 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2228 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2229 2230 if (dc) { 2231 for (i = 2; i <= 31; i++) { 2232 if (xhci->slots[slotid-1].eps[i-1]) { 2233 xhci_disable_ep(xhci, slotid, i); 2234 } 2235 } 2236 2237 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2238 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2239 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2240 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2241 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2242 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2243 2244 return CC_SUCCESS; 2245 } 2246 2247 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2248 2249 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2250 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2251 ictl_ctx[0], ictl_ctx[1]); 2252 return CC_TRB_ERROR; 2253 } 2254 2255 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2256 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2257 2258 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2259 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2260 return CC_CONTEXT_STATE_ERROR; 2261 } 2262 2263 for (i = 2; i <= 31; i++) { 2264 if (ictl_ctx[0] & (1<<i)) { 2265 xhci_disable_ep(xhci, slotid, i); 2266 } 2267 if (ictl_ctx[1] & (1<<i)) { 2268 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2269 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2270 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2271 ep_ctx[3], ep_ctx[4]); 2272 xhci_disable_ep(xhci, slotid, i); 2273 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2274 if (res != CC_SUCCESS) { 2275 return res; 2276 } 2277 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2278 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2279 ep_ctx[3], ep_ctx[4]); 2280 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2281 } 2282 } 2283 2284 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2285 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2286 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2287 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2288 SLOT_CONTEXT_ENTRIES_SHIFT); 2289 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2290 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2291 2292 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2293 2294 return CC_SUCCESS; 2295 } 2296 2297 2298 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2299 uint64_t pictx) 2300 { 2301 dma_addr_t ictx, octx; 2302 uint32_t ictl_ctx[2]; 2303 uint32_t iep0_ctx[5]; 2304 uint32_t ep0_ctx[5]; 2305 uint32_t islot_ctx[4]; 2306 uint32_t slot_ctx[4]; 2307 2308 trace_usb_xhci_slot_evaluate(slotid); 2309 assert(slotid >= 1 && slotid <= xhci->numslots); 2310 2311 ictx = xhci_mask64(pictx); 2312 octx = xhci->slots[slotid-1].ctx; 2313 2314 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2315 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2316 2317 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2318 2319 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2320 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2321 ictl_ctx[0], ictl_ctx[1]); 2322 return CC_TRB_ERROR; 2323 } 2324 2325 if (ictl_ctx[1] & 0x1) { 2326 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2327 2328 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2329 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2330 2331 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2332 2333 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2334 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2335 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2336 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2337 2338 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2339 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2340 2341 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2342 } 2343 2344 if (ictl_ctx[1] & 0x2) { 2345 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2346 2347 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2348 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2349 iep0_ctx[3], iep0_ctx[4]); 2350 2351 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2352 2353 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2354 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2355 2356 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2357 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2358 2359 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2360 } 2361 2362 return CC_SUCCESS; 2363 } 2364 2365 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2366 { 2367 uint32_t slot_ctx[4]; 2368 dma_addr_t octx; 2369 int i; 2370 2371 trace_usb_xhci_slot_reset(slotid); 2372 assert(slotid >= 1 && slotid <= xhci->numslots); 2373 2374 octx = xhci->slots[slotid-1].ctx; 2375 2376 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2377 2378 for (i = 2; i <= 31; i++) { 2379 if (xhci->slots[slotid-1].eps[i-1]) { 2380 xhci_disable_ep(xhci, slotid, i); 2381 } 2382 } 2383 2384 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2385 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2386 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2387 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2388 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2389 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2390 2391 return CC_SUCCESS; 2392 } 2393 2394 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2395 { 2396 unsigned int slotid; 2397 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2398 if (slotid < 1 || slotid > xhci->numslots) { 2399 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2400 event->ccode = CC_TRB_ERROR; 2401 return 0; 2402 } else if (!xhci->slots[slotid-1].enabled) { 2403 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2404 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2405 return 0; 2406 } 2407 return slotid; 2408 } 2409 2410 /* cleanup slot state on usb device detach */ 2411 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2412 { 2413 int slot, ep; 2414 2415 for (slot = 0; slot < xhci->numslots; slot++) { 2416 if (xhci->slots[slot].uport == uport) { 2417 break; 2418 } 2419 } 2420 if (slot == xhci->numslots) { 2421 return; 2422 } 2423 2424 for (ep = 0; ep < 31; ep++) { 2425 if (xhci->slots[slot].eps[ep]) { 2426 xhci_ep_nuke_xfers(xhci, slot+1, ep+1); 2427 } 2428 } 2429 xhci->slots[slot].uport = NULL; 2430 } 2431 2432 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2433 { 2434 dma_addr_t ctx; 2435 uint8_t bw_ctx[xhci->numports+1]; 2436 2437 DPRINTF("xhci_get_port_bandwidth()\n"); 2438 2439 ctx = xhci_mask64(pctx); 2440 2441 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2442 2443 /* TODO: actually implement real values here */ 2444 bw_ctx[0] = 0; 2445 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2446 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2447 2448 return CC_SUCCESS; 2449 } 2450 2451 static uint32_t rotl(uint32_t v, unsigned count) 2452 { 2453 count &= 31; 2454 return (v << count) | (v >> (32 - count)); 2455 } 2456 2457 2458 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2459 { 2460 uint32_t val; 2461 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2462 val += rotl(lo + 0x49434878, hi & 0x1F); 2463 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2464 return ~val; 2465 } 2466 2467 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2468 { 2469 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2470 uint32_t buf[8]; 2471 uint32_t obuf[8]; 2472 dma_addr_t paddr = xhci_mask64(addr); 2473 2474 pci_dma_read(pci_dev, paddr, &buf, 32); 2475 2476 memcpy(obuf, buf, sizeof(obuf)); 2477 2478 if ((buf[0] & 0xff) == 2) { 2479 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2480 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2481 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2482 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2483 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2484 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2485 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2486 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2487 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2488 } 2489 2490 pci_dma_write(pci_dev, paddr, &obuf, 32); 2491 } 2492 2493 static void xhci_process_commands(XHCIState *xhci) 2494 { 2495 XHCITRB trb; 2496 TRBType type; 2497 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2498 dma_addr_t addr; 2499 unsigned int i, slotid = 0; 2500 2501 DPRINTF("xhci_process_commands()\n"); 2502 if (!xhci_running(xhci)) { 2503 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2504 return; 2505 } 2506 2507 xhci->crcr_low |= CRCR_CRR; 2508 2509 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2510 event.ptr = addr; 2511 switch (type) { 2512 case CR_ENABLE_SLOT: 2513 for (i = 0; i < xhci->numslots; i++) { 2514 if (!xhci->slots[i].enabled) { 2515 break; 2516 } 2517 } 2518 if (i >= xhci->numslots) { 2519 fprintf(stderr, "xhci: no device slots available\n"); 2520 event.ccode = CC_NO_SLOTS_ERROR; 2521 } else { 2522 slotid = i+1; 2523 event.ccode = xhci_enable_slot(xhci, slotid); 2524 } 2525 break; 2526 case CR_DISABLE_SLOT: 2527 slotid = xhci_get_slot(xhci, &event, &trb); 2528 if (slotid) { 2529 event.ccode = xhci_disable_slot(xhci, slotid); 2530 } 2531 break; 2532 case CR_ADDRESS_DEVICE: 2533 slotid = xhci_get_slot(xhci, &event, &trb); 2534 if (slotid) { 2535 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2536 trb.control & TRB_CR_BSR); 2537 } 2538 break; 2539 case CR_CONFIGURE_ENDPOINT: 2540 slotid = xhci_get_slot(xhci, &event, &trb); 2541 if (slotid) { 2542 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2543 trb.control & TRB_CR_DC); 2544 } 2545 break; 2546 case CR_EVALUATE_CONTEXT: 2547 slotid = xhci_get_slot(xhci, &event, &trb); 2548 if (slotid) { 2549 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2550 } 2551 break; 2552 case CR_STOP_ENDPOINT: 2553 slotid = xhci_get_slot(xhci, &event, &trb); 2554 if (slotid) { 2555 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2556 & TRB_CR_EPID_MASK; 2557 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2558 } 2559 break; 2560 case CR_RESET_ENDPOINT: 2561 slotid = xhci_get_slot(xhci, &event, &trb); 2562 if (slotid) { 2563 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2564 & TRB_CR_EPID_MASK; 2565 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2566 } 2567 break; 2568 case CR_SET_TR_DEQUEUE: 2569 slotid = xhci_get_slot(xhci, &event, &trb); 2570 if (slotid) { 2571 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2572 & TRB_CR_EPID_MASK; 2573 unsigned int streamid = (trb.status >> 16) & 0xffff; 2574 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2575 epid, streamid, 2576 trb.parameter); 2577 } 2578 break; 2579 case CR_RESET_DEVICE: 2580 slotid = xhci_get_slot(xhci, &event, &trb); 2581 if (slotid) { 2582 event.ccode = xhci_reset_slot(xhci, slotid); 2583 } 2584 break; 2585 case CR_GET_PORT_BANDWIDTH: 2586 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2587 break; 2588 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2589 xhci_via_challenge(xhci, trb.parameter); 2590 break; 2591 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2592 event.type = 48; /* NEC reply */ 2593 event.length = 0x3025; 2594 break; 2595 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2596 { 2597 uint32_t chi = trb.parameter >> 32; 2598 uint32_t clo = trb.parameter; 2599 uint32_t val = xhci_nec_challenge(chi, clo); 2600 event.length = val & 0xFFFF; 2601 event.epid = val >> 16; 2602 slotid = val >> 24; 2603 event.type = 48; /* NEC reply */ 2604 } 2605 break; 2606 default: 2607 trace_usb_xhci_unimplemented("command", type); 2608 event.ccode = CC_TRB_ERROR; 2609 break; 2610 } 2611 event.slotid = slotid; 2612 xhci_event(xhci, &event, 0); 2613 } 2614 } 2615 2616 static bool xhci_port_have_device(XHCIPort *port) 2617 { 2618 if (!port->uport->dev || !port->uport->dev->attached) { 2619 return false; /* no device present */ 2620 } 2621 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2622 return false; /* speed mismatch */ 2623 } 2624 return true; 2625 } 2626 2627 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2628 { 2629 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2630 port->portnr << 24 }; 2631 2632 if ((port->portsc & bits) == bits) { 2633 return; 2634 } 2635 trace_usb_xhci_port_notify(port->portnr, bits); 2636 port->portsc |= bits; 2637 if (!xhci_running(port->xhci)) { 2638 return; 2639 } 2640 xhci_event(port->xhci, &ev, 0); 2641 } 2642 2643 static void xhci_port_update(XHCIPort *port, int is_detach) 2644 { 2645 uint32_t pls = PLS_RX_DETECT; 2646 2647 port->portsc = PORTSC_PP; 2648 if (!is_detach && xhci_port_have_device(port)) { 2649 port->portsc |= PORTSC_CCS; 2650 switch (port->uport->dev->speed) { 2651 case USB_SPEED_LOW: 2652 port->portsc |= PORTSC_SPEED_LOW; 2653 pls = PLS_POLLING; 2654 break; 2655 case USB_SPEED_FULL: 2656 port->portsc |= PORTSC_SPEED_FULL; 2657 pls = PLS_POLLING; 2658 break; 2659 case USB_SPEED_HIGH: 2660 port->portsc |= PORTSC_SPEED_HIGH; 2661 pls = PLS_POLLING; 2662 break; 2663 case USB_SPEED_SUPER: 2664 port->portsc |= PORTSC_SPEED_SUPER; 2665 port->portsc |= PORTSC_PED; 2666 pls = PLS_U0; 2667 break; 2668 } 2669 } 2670 set_field(&port->portsc, pls, PORTSC_PLS); 2671 trace_usb_xhci_port_link(port->portnr, pls); 2672 xhci_port_notify(port, PORTSC_CSC); 2673 } 2674 2675 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2676 { 2677 trace_usb_xhci_port_reset(port->portnr); 2678 2679 if (!xhci_port_have_device(port)) { 2680 return; 2681 } 2682 2683 usb_device_reset(port->uport->dev); 2684 2685 switch (port->uport->dev->speed) { 2686 case USB_SPEED_SUPER: 2687 if (warm_reset) { 2688 port->portsc |= PORTSC_WRC; 2689 } 2690 /* fall through */ 2691 case USB_SPEED_LOW: 2692 case USB_SPEED_FULL: 2693 case USB_SPEED_HIGH: 2694 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2695 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2696 port->portsc |= PORTSC_PED; 2697 break; 2698 } 2699 2700 port->portsc &= ~PORTSC_PR; 2701 xhci_port_notify(port, PORTSC_PRC); 2702 } 2703 2704 static void xhci_reset(DeviceState *dev) 2705 { 2706 XHCIState *xhci = XHCI(dev); 2707 int i; 2708 2709 trace_usb_xhci_reset(); 2710 if (!(xhci->usbsts & USBSTS_HCH)) { 2711 fprintf(stderr, "xhci: reset while running!\n"); 2712 } 2713 2714 xhci->usbcmd = 0; 2715 xhci->usbsts = USBSTS_HCH; 2716 xhci->dnctrl = 0; 2717 xhci->crcr_low = 0; 2718 xhci->crcr_high = 0; 2719 xhci->dcbaap_low = 0; 2720 xhci->dcbaap_high = 0; 2721 xhci->config = 0; 2722 2723 for (i = 0; i < xhci->numslots; i++) { 2724 xhci_disable_slot(xhci, i+1); 2725 } 2726 2727 for (i = 0; i < xhci->numports; i++) { 2728 xhci_port_update(xhci->ports + i, 0); 2729 } 2730 2731 for (i = 0; i < xhci->numintrs; i++) { 2732 xhci->intr[i].iman = 0; 2733 xhci->intr[i].imod = 0; 2734 xhci->intr[i].erstsz = 0; 2735 xhci->intr[i].erstba_low = 0; 2736 xhci->intr[i].erstba_high = 0; 2737 xhci->intr[i].erdp_low = 0; 2738 xhci->intr[i].erdp_high = 0; 2739 xhci->intr[i].msix_used = 0; 2740 2741 xhci->intr[i].er_ep_idx = 0; 2742 xhci->intr[i].er_pcs = 1; 2743 xhci->intr[i].er_full = 0; 2744 xhci->intr[i].ev_buffer_put = 0; 2745 xhci->intr[i].ev_buffer_get = 0; 2746 } 2747 2748 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2749 xhci_mfwrap_update(xhci); 2750 } 2751 2752 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2753 { 2754 XHCIState *xhci = ptr; 2755 uint32_t ret; 2756 2757 switch (reg) { 2758 case 0x00: /* HCIVERSION, CAPLENGTH */ 2759 ret = 0x01000000 | LEN_CAP; 2760 break; 2761 case 0x04: /* HCSPARAMS 1 */ 2762 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2763 | (xhci->numintrs<<8) | xhci->numslots; 2764 break; 2765 case 0x08: /* HCSPARAMS 2 */ 2766 ret = 0x0000000f; 2767 break; 2768 case 0x0c: /* HCSPARAMS 3 */ 2769 ret = 0x00000000; 2770 break; 2771 case 0x10: /* HCCPARAMS */ 2772 if (sizeof(dma_addr_t) == 4) { 2773 ret = 0x00087000; 2774 } else { 2775 ret = 0x00087001; 2776 } 2777 break; 2778 case 0x14: /* DBOFF */ 2779 ret = OFF_DOORBELL; 2780 break; 2781 case 0x18: /* RTSOFF */ 2782 ret = OFF_RUNTIME; 2783 break; 2784 2785 /* extended capabilities */ 2786 case 0x20: /* Supported Protocol:00 */ 2787 ret = 0x02000402; /* USB 2.0 */ 2788 break; 2789 case 0x24: /* Supported Protocol:04 */ 2790 ret = 0x20425355; /* "USB " */ 2791 break; 2792 case 0x28: /* Supported Protocol:08 */ 2793 ret = 0x00000001 | (xhci->numports_2<<8); 2794 break; 2795 case 0x2c: /* Supported Protocol:0c */ 2796 ret = 0x00000000; /* reserved */ 2797 break; 2798 case 0x30: /* Supported Protocol:00 */ 2799 ret = 0x03000002; /* USB 3.0 */ 2800 break; 2801 case 0x34: /* Supported Protocol:04 */ 2802 ret = 0x20425355; /* "USB " */ 2803 break; 2804 case 0x38: /* Supported Protocol:08 */ 2805 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2806 break; 2807 case 0x3c: /* Supported Protocol:0c */ 2808 ret = 0x00000000; /* reserved */ 2809 break; 2810 default: 2811 trace_usb_xhci_unimplemented("cap read", reg); 2812 ret = 0; 2813 } 2814 2815 trace_usb_xhci_cap_read(reg, ret); 2816 return ret; 2817 } 2818 2819 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2820 { 2821 XHCIPort *port = ptr; 2822 uint32_t ret; 2823 2824 switch (reg) { 2825 case 0x00: /* PORTSC */ 2826 ret = port->portsc; 2827 break; 2828 case 0x04: /* PORTPMSC */ 2829 case 0x08: /* PORTLI */ 2830 ret = 0; 2831 break; 2832 case 0x0c: /* reserved */ 2833 default: 2834 trace_usb_xhci_unimplemented("port read", reg); 2835 ret = 0; 2836 } 2837 2838 trace_usb_xhci_port_read(port->portnr, reg, ret); 2839 return ret; 2840 } 2841 2842 static void xhci_port_write(void *ptr, hwaddr reg, 2843 uint64_t val, unsigned size) 2844 { 2845 XHCIPort *port = ptr; 2846 uint32_t portsc, notify; 2847 2848 trace_usb_xhci_port_write(port->portnr, reg, val); 2849 2850 switch (reg) { 2851 case 0x00: /* PORTSC */ 2852 /* write-1-to-start bits */ 2853 if (val & PORTSC_WPR) { 2854 xhci_port_reset(port, true); 2855 break; 2856 } 2857 if (val & PORTSC_PR) { 2858 xhci_port_reset(port, false); 2859 break; 2860 } 2861 2862 portsc = port->portsc; 2863 notify = 0; 2864 /* write-1-to-clear bits*/ 2865 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2866 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2867 if (val & PORTSC_LWS) { 2868 /* overwrite PLS only when LWS=1 */ 2869 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2870 uint32_t new_pls = get_field(val, PORTSC_PLS); 2871 switch (new_pls) { 2872 case PLS_U0: 2873 if (old_pls != PLS_U0) { 2874 set_field(&portsc, new_pls, PORTSC_PLS); 2875 trace_usb_xhci_port_link(port->portnr, new_pls); 2876 notify = PORTSC_PLC; 2877 } 2878 break; 2879 case PLS_U3: 2880 if (old_pls < PLS_U3) { 2881 set_field(&portsc, new_pls, PORTSC_PLS); 2882 trace_usb_xhci_port_link(port->portnr, new_pls); 2883 } 2884 break; 2885 case PLS_RESUME: 2886 /* windows does this for some reason, don't spam stderr */ 2887 break; 2888 default: 2889 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2890 __func__, old_pls, new_pls); 2891 break; 2892 } 2893 } 2894 /* read/write bits */ 2895 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2896 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2897 port->portsc = portsc; 2898 if (notify) { 2899 xhci_port_notify(port, notify); 2900 } 2901 break; 2902 case 0x04: /* PORTPMSC */ 2903 case 0x08: /* PORTLI */ 2904 default: 2905 trace_usb_xhci_unimplemented("port write", reg); 2906 } 2907 } 2908 2909 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2910 { 2911 XHCIState *xhci = ptr; 2912 uint32_t ret; 2913 2914 switch (reg) { 2915 case 0x00: /* USBCMD */ 2916 ret = xhci->usbcmd; 2917 break; 2918 case 0x04: /* USBSTS */ 2919 ret = xhci->usbsts; 2920 break; 2921 case 0x08: /* PAGESIZE */ 2922 ret = 1; /* 4KiB */ 2923 break; 2924 case 0x14: /* DNCTRL */ 2925 ret = xhci->dnctrl; 2926 break; 2927 case 0x18: /* CRCR low */ 2928 ret = xhci->crcr_low & ~0xe; 2929 break; 2930 case 0x1c: /* CRCR high */ 2931 ret = xhci->crcr_high; 2932 break; 2933 case 0x30: /* DCBAAP low */ 2934 ret = xhci->dcbaap_low; 2935 break; 2936 case 0x34: /* DCBAAP high */ 2937 ret = xhci->dcbaap_high; 2938 break; 2939 case 0x38: /* CONFIG */ 2940 ret = xhci->config; 2941 break; 2942 default: 2943 trace_usb_xhci_unimplemented("oper read", reg); 2944 ret = 0; 2945 } 2946 2947 trace_usb_xhci_oper_read(reg, ret); 2948 return ret; 2949 } 2950 2951 static void xhci_oper_write(void *ptr, hwaddr reg, 2952 uint64_t val, unsigned size) 2953 { 2954 XHCIState *xhci = ptr; 2955 DeviceState *d = DEVICE(ptr); 2956 2957 trace_usb_xhci_oper_write(reg, val); 2958 2959 switch (reg) { 2960 case 0x00: /* USBCMD */ 2961 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2962 xhci_run(xhci); 2963 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2964 xhci_stop(xhci); 2965 } 2966 xhci->usbcmd = val & 0xc0f; 2967 xhci_mfwrap_update(xhci); 2968 if (val & USBCMD_HCRST) { 2969 xhci_reset(d); 2970 } 2971 xhci_intx_update(xhci); 2972 break; 2973 2974 case 0x04: /* USBSTS */ 2975 /* these bits are write-1-to-clear */ 2976 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2977 xhci_intx_update(xhci); 2978 break; 2979 2980 case 0x14: /* DNCTRL */ 2981 xhci->dnctrl = val & 0xffff; 2982 break; 2983 case 0x18: /* CRCR low */ 2984 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2985 break; 2986 case 0x1c: /* CRCR high */ 2987 xhci->crcr_high = val; 2988 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2989 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2990 xhci->crcr_low &= ~CRCR_CRR; 2991 xhci_event(xhci, &event, 0); 2992 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2993 } else { 2994 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2995 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2996 } 2997 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2998 break; 2999 case 0x30: /* DCBAAP low */ 3000 xhci->dcbaap_low = val & 0xffffffc0; 3001 break; 3002 case 0x34: /* DCBAAP high */ 3003 xhci->dcbaap_high = val; 3004 break; 3005 case 0x38: /* CONFIG */ 3006 xhci->config = val & 0xff; 3007 break; 3008 default: 3009 trace_usb_xhci_unimplemented("oper write", reg); 3010 } 3011 } 3012 3013 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3014 unsigned size) 3015 { 3016 XHCIState *xhci = ptr; 3017 uint32_t ret = 0; 3018 3019 if (reg < 0x20) { 3020 switch (reg) { 3021 case 0x00: /* MFINDEX */ 3022 ret = xhci_mfindex_get(xhci) & 0x3fff; 3023 break; 3024 default: 3025 trace_usb_xhci_unimplemented("runtime read", reg); 3026 break; 3027 } 3028 } else { 3029 int v = (reg - 0x20) / 0x20; 3030 XHCIInterrupter *intr = &xhci->intr[v]; 3031 switch (reg & 0x1f) { 3032 case 0x00: /* IMAN */ 3033 ret = intr->iman; 3034 break; 3035 case 0x04: /* IMOD */ 3036 ret = intr->imod; 3037 break; 3038 case 0x08: /* ERSTSZ */ 3039 ret = intr->erstsz; 3040 break; 3041 case 0x10: /* ERSTBA low */ 3042 ret = intr->erstba_low; 3043 break; 3044 case 0x14: /* ERSTBA high */ 3045 ret = intr->erstba_high; 3046 break; 3047 case 0x18: /* ERDP low */ 3048 ret = intr->erdp_low; 3049 break; 3050 case 0x1c: /* ERDP high */ 3051 ret = intr->erdp_high; 3052 break; 3053 } 3054 } 3055 3056 trace_usb_xhci_runtime_read(reg, ret); 3057 return ret; 3058 } 3059 3060 static void xhci_runtime_write(void *ptr, hwaddr reg, 3061 uint64_t val, unsigned size) 3062 { 3063 XHCIState *xhci = ptr; 3064 int v = (reg - 0x20) / 0x20; 3065 XHCIInterrupter *intr = &xhci->intr[v]; 3066 trace_usb_xhci_runtime_write(reg, val); 3067 3068 if (reg < 0x20) { 3069 trace_usb_xhci_unimplemented("runtime write", reg); 3070 return; 3071 } 3072 3073 switch (reg & 0x1f) { 3074 case 0x00: /* IMAN */ 3075 if (val & IMAN_IP) { 3076 intr->iman &= ~IMAN_IP; 3077 } 3078 intr->iman &= ~IMAN_IE; 3079 intr->iman |= val & IMAN_IE; 3080 if (v == 0) { 3081 xhci_intx_update(xhci); 3082 } 3083 xhci_msix_update(xhci, v); 3084 break; 3085 case 0x04: /* IMOD */ 3086 intr->imod = val; 3087 break; 3088 case 0x08: /* ERSTSZ */ 3089 intr->erstsz = val & 0xffff; 3090 break; 3091 case 0x10: /* ERSTBA low */ 3092 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3093 intr->erstba_low = val & 0xffffffc0; */ 3094 intr->erstba_low = val & 0xfffffff0; 3095 break; 3096 case 0x14: /* ERSTBA high */ 3097 intr->erstba_high = val; 3098 xhci_er_reset(xhci, v); 3099 break; 3100 case 0x18: /* ERDP low */ 3101 if (val & ERDP_EHB) { 3102 intr->erdp_low &= ~ERDP_EHB; 3103 } 3104 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3105 break; 3106 case 0x1c: /* ERDP high */ 3107 intr->erdp_high = val; 3108 xhci_events_update(xhci, v); 3109 break; 3110 default: 3111 trace_usb_xhci_unimplemented("oper write", reg); 3112 } 3113 } 3114 3115 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3116 unsigned size) 3117 { 3118 /* doorbells always read as 0 */ 3119 trace_usb_xhci_doorbell_read(reg, 0); 3120 return 0; 3121 } 3122 3123 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3124 uint64_t val, unsigned size) 3125 { 3126 XHCIState *xhci = ptr; 3127 unsigned int epid, streamid; 3128 3129 trace_usb_xhci_doorbell_write(reg, val); 3130 3131 if (!xhci_running(xhci)) { 3132 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3133 return; 3134 } 3135 3136 reg >>= 2; 3137 3138 if (reg == 0) { 3139 if (val == 0) { 3140 xhci_process_commands(xhci); 3141 } else { 3142 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3143 (uint32_t)val); 3144 } 3145 } else { 3146 epid = val & 0xff; 3147 streamid = (val >> 16) & 0xffff; 3148 if (reg > xhci->numslots) { 3149 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3150 } else if (epid > 31) { 3151 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3152 (int)reg, (uint32_t)val); 3153 } else { 3154 xhci_kick_ep(xhci, reg, epid, streamid); 3155 } 3156 } 3157 } 3158 3159 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3160 unsigned width) 3161 { 3162 /* nothing */ 3163 } 3164 3165 static const MemoryRegionOps xhci_cap_ops = { 3166 .read = xhci_cap_read, 3167 .write = xhci_cap_write, 3168 .valid.min_access_size = 1, 3169 .valid.max_access_size = 4, 3170 .impl.min_access_size = 4, 3171 .impl.max_access_size = 4, 3172 .endianness = DEVICE_LITTLE_ENDIAN, 3173 }; 3174 3175 static const MemoryRegionOps xhci_oper_ops = { 3176 .read = xhci_oper_read, 3177 .write = xhci_oper_write, 3178 .valid.min_access_size = 4, 3179 .valid.max_access_size = 4, 3180 .endianness = DEVICE_LITTLE_ENDIAN, 3181 }; 3182 3183 static const MemoryRegionOps xhci_port_ops = { 3184 .read = xhci_port_read, 3185 .write = xhci_port_write, 3186 .valid.min_access_size = 4, 3187 .valid.max_access_size = 4, 3188 .endianness = DEVICE_LITTLE_ENDIAN, 3189 }; 3190 3191 static const MemoryRegionOps xhci_runtime_ops = { 3192 .read = xhci_runtime_read, 3193 .write = xhci_runtime_write, 3194 .valid.min_access_size = 4, 3195 .valid.max_access_size = 4, 3196 .endianness = DEVICE_LITTLE_ENDIAN, 3197 }; 3198 3199 static const MemoryRegionOps xhci_doorbell_ops = { 3200 .read = xhci_doorbell_read, 3201 .write = xhci_doorbell_write, 3202 .valid.min_access_size = 4, 3203 .valid.max_access_size = 4, 3204 .endianness = DEVICE_LITTLE_ENDIAN, 3205 }; 3206 3207 static void xhci_attach(USBPort *usbport) 3208 { 3209 XHCIState *xhci = usbport->opaque; 3210 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3211 3212 xhci_port_update(port, 0); 3213 } 3214 3215 static void xhci_detach(USBPort *usbport) 3216 { 3217 XHCIState *xhci = usbport->opaque; 3218 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3219 3220 xhci_detach_slot(xhci, usbport); 3221 xhci_port_update(port, 1); 3222 } 3223 3224 static void xhci_wakeup(USBPort *usbport) 3225 { 3226 XHCIState *xhci = usbport->opaque; 3227 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3228 3229 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3230 return; 3231 } 3232 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3233 xhci_port_notify(port, PORTSC_PLC); 3234 } 3235 3236 static void xhci_complete(USBPort *port, USBPacket *packet) 3237 { 3238 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3239 3240 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3241 xhci_ep_nuke_one_xfer(xfer); 3242 return; 3243 } 3244 xhci_complete_packet(xfer); 3245 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3246 } 3247 3248 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3249 { 3250 USBBus *bus = usb_bus_from_device(child); 3251 XHCIState *xhci = container_of(bus, XHCIState, bus); 3252 3253 xhci_detach_slot(xhci, uport); 3254 } 3255 3256 static USBPortOps xhci_uport_ops = { 3257 .attach = xhci_attach, 3258 .detach = xhci_detach, 3259 .wakeup = xhci_wakeup, 3260 .complete = xhci_complete, 3261 .child_detach = xhci_child_detach, 3262 }; 3263 3264 static int xhci_find_epid(USBEndpoint *ep) 3265 { 3266 if (ep->nr == 0) { 3267 return 1; 3268 } 3269 if (ep->pid == USB_TOKEN_IN) { 3270 return ep->nr * 2 + 1; 3271 } else { 3272 return ep->nr * 2; 3273 } 3274 } 3275 3276 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3277 unsigned int stream) 3278 { 3279 XHCIState *xhci = container_of(bus, XHCIState, bus); 3280 int slotid; 3281 3282 DPRINTF("%s\n", __func__); 3283 slotid = ep->dev->addr; 3284 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3285 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3286 return; 3287 } 3288 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3289 } 3290 3291 static USBBusOps xhci_bus_ops = { 3292 .wakeup_endpoint = xhci_wakeup_endpoint, 3293 }; 3294 3295 static void usb_xhci_init(XHCIState *xhci) 3296 { 3297 DeviceState *dev = DEVICE(xhci); 3298 XHCIPort *port; 3299 int i, usbports, speedmask; 3300 3301 xhci->usbsts = USBSTS_HCH; 3302 3303 if (xhci->numports_2 > MAXPORTS_2) { 3304 xhci->numports_2 = MAXPORTS_2; 3305 } 3306 if (xhci->numports_3 > MAXPORTS_3) { 3307 xhci->numports_3 = MAXPORTS_3; 3308 } 3309 usbports = MAX(xhci->numports_2, xhci->numports_3); 3310 xhci->numports = xhci->numports_2 + xhci->numports_3; 3311 3312 usb_bus_new(&xhci->bus, &xhci_bus_ops, dev); 3313 3314 for (i = 0; i < usbports; i++) { 3315 speedmask = 0; 3316 if (i < xhci->numports_2) { 3317 port = &xhci->ports[i]; 3318 port->portnr = i + 1; 3319 port->uport = &xhci->uports[i]; 3320 port->speedmask = 3321 USB_SPEED_MASK_LOW | 3322 USB_SPEED_MASK_FULL | 3323 USB_SPEED_MASK_HIGH; 3324 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3325 speedmask |= port->speedmask; 3326 } 3327 if (i < xhci->numports_3) { 3328 port = &xhci->ports[i + xhci->numports_2]; 3329 port->portnr = i + 1 + xhci->numports_2; 3330 port->uport = &xhci->uports[i]; 3331 port->speedmask = USB_SPEED_MASK_SUPER; 3332 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3333 speedmask |= port->speedmask; 3334 } 3335 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3336 &xhci_uport_ops, speedmask); 3337 } 3338 } 3339 3340 static int usb_xhci_initfn(struct PCIDevice *dev) 3341 { 3342 int i, ret; 3343 3344 XHCIState *xhci = XHCI(dev); 3345 3346 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3347 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3348 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3349 dev->config[0x60] = 0x30; /* release number */ 3350 3351 usb_xhci_init(xhci); 3352 3353 if (xhci->numintrs > MAXINTRS) { 3354 xhci->numintrs = MAXINTRS; 3355 } 3356 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3357 xhci->numintrs++; 3358 } 3359 if (xhci->numintrs < 1) { 3360 xhci->numintrs = 1; 3361 } 3362 if (xhci->numslots > MAXSLOTS) { 3363 xhci->numslots = MAXSLOTS; 3364 } 3365 if (xhci->numslots < 1) { 3366 xhci->numslots = 1; 3367 } 3368 3369 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 3370 3371 xhci->irq = dev->irq[0]; 3372 3373 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3374 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3375 "capabilities", LEN_CAP); 3376 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3377 "operational", 0x400); 3378 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3379 "runtime", LEN_RUNTIME); 3380 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3381 "doorbell", LEN_DOORBELL); 3382 3383 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3384 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3385 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3386 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3387 3388 for (i = 0; i < xhci->numports; i++) { 3389 XHCIPort *port = &xhci->ports[i]; 3390 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3391 port->xhci = xhci; 3392 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3393 port->name, 0x10); 3394 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3395 } 3396 3397 pci_register_bar(dev, 0, 3398 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3399 &xhci->mem); 3400 3401 ret = pcie_endpoint_cap_init(dev, 0xa0); 3402 assert(ret >= 0); 3403 3404 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3405 msi_init(dev, 0x70, xhci->numintrs, true, false); 3406 } 3407 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3408 msix_init(dev, xhci->numintrs, 3409 &xhci->mem, 0, OFF_MSIX_TABLE, 3410 &xhci->mem, 0, OFF_MSIX_PBA, 3411 0x90); 3412 } 3413 3414 return 0; 3415 } 3416 3417 static int usb_xhci_post_load(void *opaque, int version_id) 3418 { 3419 XHCIState *xhci = opaque; 3420 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3421 XHCISlot *slot; 3422 XHCIEPContext *epctx; 3423 dma_addr_t dcbaap, pctx; 3424 uint32_t slot_ctx[4]; 3425 uint32_t ep_ctx[5]; 3426 int slotid, epid, state, intr; 3427 3428 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3429 3430 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3431 slot = &xhci->slots[slotid-1]; 3432 if (!slot->addressed) { 3433 continue; 3434 } 3435 slot->ctx = 3436 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3437 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3438 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3439 assert(slot->uport && slot->uport->dev); 3440 3441 for (epid = 1; epid <= 32; epid++) { 3442 pctx = slot->ctx + 32 * epid; 3443 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3444 state = ep_ctx[0] & EP_STATE_MASK; 3445 if (state == EP_DISABLED) { 3446 continue; 3447 } 3448 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3449 slot->eps[epid-1] = epctx; 3450 xhci_init_epctx(epctx, pctx, ep_ctx); 3451 epctx->state = state; 3452 if (state == EP_RUNNING) { 3453 /* kick endpoint after vmload is finished */ 3454 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock)); 3455 } 3456 } 3457 } 3458 3459 for (intr = 0; intr < xhci->numintrs; intr++) { 3460 if (xhci->intr[intr].msix_used) { 3461 msix_vector_use(pci_dev, intr); 3462 } else { 3463 msix_vector_unuse(pci_dev, intr); 3464 } 3465 } 3466 3467 return 0; 3468 } 3469 3470 static const VMStateDescription vmstate_xhci_ring = { 3471 .name = "xhci-ring", 3472 .version_id = 1, 3473 .fields = (VMStateField[]) { 3474 VMSTATE_UINT64(dequeue, XHCIRing), 3475 VMSTATE_BOOL(ccs, XHCIRing), 3476 VMSTATE_END_OF_LIST() 3477 } 3478 }; 3479 3480 static const VMStateDescription vmstate_xhci_port = { 3481 .name = "xhci-port", 3482 .version_id = 1, 3483 .fields = (VMStateField[]) { 3484 VMSTATE_UINT32(portsc, XHCIPort), 3485 VMSTATE_END_OF_LIST() 3486 } 3487 }; 3488 3489 static const VMStateDescription vmstate_xhci_slot = { 3490 .name = "xhci-slot", 3491 .version_id = 1, 3492 .fields = (VMStateField[]) { 3493 VMSTATE_BOOL(enabled, XHCISlot), 3494 VMSTATE_BOOL(addressed, XHCISlot), 3495 VMSTATE_END_OF_LIST() 3496 } 3497 }; 3498 3499 static const VMStateDescription vmstate_xhci_event = { 3500 .name = "xhci-event", 3501 .version_id = 1, 3502 .fields = (VMStateField[]) { 3503 VMSTATE_UINT32(type, XHCIEvent), 3504 VMSTATE_UINT32(ccode, XHCIEvent), 3505 VMSTATE_UINT64(ptr, XHCIEvent), 3506 VMSTATE_UINT32(length, XHCIEvent), 3507 VMSTATE_UINT32(flags, XHCIEvent), 3508 VMSTATE_UINT8(slotid, XHCIEvent), 3509 VMSTATE_UINT8(epid, XHCIEvent), 3510 } 3511 }; 3512 3513 static bool xhci_er_full(void *opaque, int version_id) 3514 { 3515 struct XHCIInterrupter *intr = opaque; 3516 return intr->er_full; 3517 } 3518 3519 static const VMStateDescription vmstate_xhci_intr = { 3520 .name = "xhci-intr", 3521 .version_id = 1, 3522 .fields = (VMStateField[]) { 3523 /* registers */ 3524 VMSTATE_UINT32(iman, XHCIInterrupter), 3525 VMSTATE_UINT32(imod, XHCIInterrupter), 3526 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3527 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3528 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3529 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3530 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3531 3532 /* state */ 3533 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3534 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3535 VMSTATE_UINT64(er_start, XHCIInterrupter), 3536 VMSTATE_UINT32(er_size, XHCIInterrupter), 3537 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3538 3539 /* event queue (used if ring is full) */ 3540 VMSTATE_BOOL(er_full, XHCIInterrupter), 3541 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3542 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3543 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3544 xhci_er_full, 1, 3545 vmstate_xhci_event, XHCIEvent), 3546 3547 VMSTATE_END_OF_LIST() 3548 } 3549 }; 3550 3551 static const VMStateDescription vmstate_xhci = { 3552 .name = "xhci", 3553 .version_id = 1, 3554 .post_load = usb_xhci_post_load, 3555 .fields = (VMStateField[]) { 3556 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3557 VMSTATE_MSIX(parent_obj, XHCIState), 3558 3559 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3560 vmstate_xhci_port, XHCIPort), 3561 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3562 vmstate_xhci_slot, XHCISlot), 3563 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3564 vmstate_xhci_intr, XHCIInterrupter), 3565 3566 /* Operational Registers */ 3567 VMSTATE_UINT32(usbcmd, XHCIState), 3568 VMSTATE_UINT32(usbsts, XHCIState), 3569 VMSTATE_UINT32(dnctrl, XHCIState), 3570 VMSTATE_UINT32(crcr_low, XHCIState), 3571 VMSTATE_UINT32(crcr_high, XHCIState), 3572 VMSTATE_UINT32(dcbaap_low, XHCIState), 3573 VMSTATE_UINT32(dcbaap_high, XHCIState), 3574 VMSTATE_UINT32(config, XHCIState), 3575 3576 /* Runtime Registers & state */ 3577 VMSTATE_INT64(mfindex_start, XHCIState), 3578 VMSTATE_TIMER(mfwrap_timer, XHCIState), 3579 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3580 3581 VMSTATE_END_OF_LIST() 3582 } 3583 }; 3584 3585 static Property xhci_properties[] = { 3586 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3587 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3588 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3589 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3590 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3591 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3592 DEFINE_PROP_END_OF_LIST(), 3593 }; 3594 3595 static void xhci_class_init(ObjectClass *klass, void *data) 3596 { 3597 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3598 DeviceClass *dc = DEVICE_CLASS(klass); 3599 3600 dc->vmsd = &vmstate_xhci; 3601 dc->props = xhci_properties; 3602 dc->reset = xhci_reset; 3603 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3604 k->init = usb_xhci_initfn; 3605 k->vendor_id = PCI_VENDOR_ID_NEC; 3606 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3607 k->class_id = PCI_CLASS_SERIAL_USB; 3608 k->revision = 0x03; 3609 k->is_express = 1; 3610 k->no_hotplug = 1; 3611 } 3612 3613 static const TypeInfo xhci_info = { 3614 .name = TYPE_XHCI, 3615 .parent = TYPE_PCI_DEVICE, 3616 .instance_size = sizeof(XHCIState), 3617 .class_init = xhci_class_init, 3618 }; 3619 3620 static void xhci_register_types(void) 3621 { 3622 type_register_static(&xhci_info); 3623 } 3624 3625 type_init(xhci_register_types) 3626