1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu/timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci/pci.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 38 __func__, __LINE__, _msg); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 typedef struct XHCIStreamContext XHCIStreamContext; 305 typedef struct XHCIEPContext XHCIEPContext; 306 307 #define get_field(data, field) \ 308 (((data) >> field##_SHIFT) & field##_MASK) 309 310 #define set_field(data, newval, field) do { \ 311 uint32_t val = *data; \ 312 val &= ~(field##_MASK << field##_SHIFT); \ 313 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 314 *data = val; \ 315 } while (0) 316 317 typedef enum EPType { 318 ET_INVALID = 0, 319 ET_ISO_OUT, 320 ET_BULK_OUT, 321 ET_INTR_OUT, 322 ET_CONTROL, 323 ET_ISO_IN, 324 ET_BULK_IN, 325 ET_INTR_IN, 326 } EPType; 327 328 typedef struct XHCIRing { 329 dma_addr_t dequeue; 330 bool ccs; 331 } XHCIRing; 332 333 typedef struct XHCIPort { 334 XHCIState *xhci; 335 uint32_t portsc; 336 uint32_t portnr; 337 USBPort *uport; 338 uint32_t speedmask; 339 char name[16]; 340 MemoryRegion mem; 341 } XHCIPort; 342 343 typedef struct XHCITransfer { 344 XHCIState *xhci; 345 USBPacket packet; 346 QEMUSGList sgl; 347 bool running_async; 348 bool running_retry; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 unsigned int streamid; 355 bool in_xfer; 356 bool iso_xfer; 357 bool timed_xfer; 358 359 unsigned int trb_count; 360 unsigned int trb_alloced; 361 XHCITRB *trbs; 362 363 TRBCCode status; 364 365 unsigned int pkts; 366 unsigned int pktsize; 367 unsigned int cur_pkt; 368 369 uint64_t mfindex_kick; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 unsigned int next_xfer; 385 unsigned int comp_xfer; 386 XHCITransfer transfers[TD_QUEUE]; 387 XHCITransfer *retry; 388 EPType type; 389 dma_addr_t pctx; 390 unsigned int max_psize; 391 uint32_t state; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs, er_full; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 XHCIEvent ev_buffer[EV_QUEUE]; 439 unsigned int ev_buffer_put; 440 unsigned int ev_buffer_get; 441 442 } XHCIInterrupter; 443 444 struct XHCIState { 445 /*< private >*/ 446 PCIDevice parent_obj; 447 /*< public >*/ 448 449 USBBus bus; 450 qemu_irq irq; 451 MemoryRegion mem; 452 MemoryRegion mem_cap; 453 MemoryRegion mem_oper; 454 MemoryRegion mem_runtime; 455 MemoryRegion mem_doorbell; 456 457 /* properties */ 458 uint32_t numports_2; 459 uint32_t numports_3; 460 uint32_t numintrs; 461 uint32_t numslots; 462 uint32_t flags; 463 464 /* Operational Registers */ 465 uint32_t usbcmd; 466 uint32_t usbsts; 467 uint32_t dnctrl; 468 uint32_t crcr_low; 469 uint32_t crcr_high; 470 uint32_t dcbaap_low; 471 uint32_t dcbaap_high; 472 uint32_t config; 473 474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 475 XHCIPort ports[MAXPORTS]; 476 XHCISlot slots[MAXSLOTS]; 477 uint32_t numports; 478 479 /* Runtime Registers */ 480 int64_t mfindex_start; 481 QEMUTimer *mfwrap_timer; 482 XHCIInterrupter intr[MAXINTRS]; 483 484 XHCIRing cmd_ring; 485 }; 486 487 #define TYPE_XHCI "nec-usb-xhci" 488 489 #define XHCI(obj) \ 490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 491 492 typedef struct XHCIEvRingSeg { 493 uint32_t addr_low; 494 uint32_t addr_high; 495 uint32_t size; 496 uint32_t rsvd; 497 } XHCIEvRingSeg; 498 499 enum xhci_flags { 500 XHCI_FLAG_USE_MSI = 1, 501 XHCI_FLAG_USE_MSI_X, 502 }; 503 504 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 505 unsigned int epid, unsigned int streamid); 506 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 507 unsigned int epid); 508 static void xhci_xfer_report(XHCITransfer *xfer); 509 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 510 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 511 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 512 unsigned int slotid, unsigned int epid); 513 514 static const char *TRBType_names[] = { 515 [TRB_RESERVED] = "TRB_RESERVED", 516 [TR_NORMAL] = "TR_NORMAL", 517 [TR_SETUP] = "TR_SETUP", 518 [TR_DATA] = "TR_DATA", 519 [TR_STATUS] = "TR_STATUS", 520 [TR_ISOCH] = "TR_ISOCH", 521 [TR_LINK] = "TR_LINK", 522 [TR_EVDATA] = "TR_EVDATA", 523 [TR_NOOP] = "TR_NOOP", 524 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 525 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 526 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 527 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 528 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 529 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 530 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 531 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 532 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 533 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 534 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 535 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 536 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 537 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 538 [CR_NOOP] = "CR_NOOP", 539 [ER_TRANSFER] = "ER_TRANSFER", 540 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 541 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 542 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 543 [ER_DOORBELL] = "ER_DOORBELL", 544 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 545 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 546 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 547 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 548 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 549 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 550 }; 551 552 static const char *TRBCCode_names[] = { 553 [CC_INVALID] = "CC_INVALID", 554 [CC_SUCCESS] = "CC_SUCCESS", 555 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 556 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 557 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 558 [CC_TRB_ERROR] = "CC_TRB_ERROR", 559 [CC_STALL_ERROR] = "CC_STALL_ERROR", 560 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 561 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 562 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 563 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 564 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 565 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 566 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 567 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 568 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 569 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 570 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 571 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 572 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 573 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 574 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 575 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 576 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 577 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 578 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 579 [CC_STOPPED] = "CC_STOPPED", 580 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 581 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 582 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 583 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 584 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 585 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 586 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 587 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 588 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 589 }; 590 591 static const char *ep_state_names[] = { 592 [EP_DISABLED] = "disabled", 593 [EP_RUNNING] = "running", 594 [EP_HALTED] = "halted", 595 [EP_STOPPED] = "stopped", 596 [EP_ERROR] = "error", 597 }; 598 599 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 600 { 601 if (index >= llen || list[index] == NULL) { 602 return "???"; 603 } 604 return list[index]; 605 } 606 607 static const char *trb_name(XHCITRB *trb) 608 { 609 return lookup_name(TRB_TYPE(*trb), TRBType_names, 610 ARRAY_SIZE(TRBType_names)); 611 } 612 613 static const char *event_name(XHCIEvent *event) 614 { 615 return lookup_name(event->ccode, TRBCCode_names, 616 ARRAY_SIZE(TRBCCode_names)); 617 } 618 619 static const char *ep_state_name(uint32_t state) 620 { 621 return lookup_name(state, ep_state_names, 622 ARRAY_SIZE(ep_state_names)); 623 } 624 625 static uint64_t xhci_mfindex_get(XHCIState *xhci) 626 { 627 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 628 return (now - xhci->mfindex_start) / 125000; 629 } 630 631 static void xhci_mfwrap_update(XHCIState *xhci) 632 { 633 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 634 uint32_t mfindex, left; 635 int64_t now; 636 637 if ((xhci->usbcmd & bits) == bits) { 638 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 639 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 640 left = 0x4000 - mfindex; 641 timer_mod(xhci->mfwrap_timer, now + left * 125000); 642 } else { 643 timer_del(xhci->mfwrap_timer); 644 } 645 } 646 647 static void xhci_mfwrap_timer(void *opaque) 648 { 649 XHCIState *xhci = opaque; 650 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 651 652 xhci_event(xhci, &wrap, 0); 653 xhci_mfwrap_update(xhci); 654 } 655 656 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 657 { 658 if (sizeof(dma_addr_t) == 4) { 659 return low; 660 } else { 661 return low | (((dma_addr_t)high << 16) << 16); 662 } 663 } 664 665 static inline dma_addr_t xhci_mask64(uint64_t addr) 666 { 667 if (sizeof(dma_addr_t) == 4) { 668 return addr & 0xffffffff; 669 } else { 670 return addr; 671 } 672 } 673 674 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 675 uint32_t *buf, size_t len) 676 { 677 int i; 678 679 assert((len % sizeof(uint32_t)) == 0); 680 681 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 682 683 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 684 buf[i] = le32_to_cpu(buf[i]); 685 } 686 } 687 688 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 689 uint32_t *buf, size_t len) 690 { 691 int i; 692 uint32_t tmp[len / sizeof(uint32_t)]; 693 694 assert((len % sizeof(uint32_t)) == 0); 695 696 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 697 tmp[i] = cpu_to_le32(buf[i]); 698 } 699 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 700 } 701 702 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 703 { 704 int index; 705 706 if (!uport->dev) { 707 return NULL; 708 } 709 switch (uport->dev->speed) { 710 case USB_SPEED_LOW: 711 case USB_SPEED_FULL: 712 case USB_SPEED_HIGH: 713 index = uport->index; 714 break; 715 case USB_SPEED_SUPER: 716 index = uport->index + xhci->numports_2; 717 break; 718 default: 719 return NULL; 720 } 721 return &xhci->ports[index]; 722 } 723 724 static void xhci_intx_update(XHCIState *xhci) 725 { 726 PCIDevice *pci_dev = PCI_DEVICE(xhci); 727 int level = 0; 728 729 if (msix_enabled(pci_dev) || 730 msi_enabled(pci_dev)) { 731 return; 732 } 733 734 if (xhci->intr[0].iman & IMAN_IP && 735 xhci->intr[0].iman & IMAN_IE && 736 xhci->usbcmd & USBCMD_INTE) { 737 level = 1; 738 } 739 740 trace_usb_xhci_irq_intx(level); 741 qemu_set_irq(xhci->irq, level); 742 } 743 744 static void xhci_msix_update(XHCIState *xhci, int v) 745 { 746 PCIDevice *pci_dev = PCI_DEVICE(xhci); 747 bool enabled; 748 749 if (!msix_enabled(pci_dev)) { 750 return; 751 } 752 753 enabled = xhci->intr[v].iman & IMAN_IE; 754 if (enabled == xhci->intr[v].msix_used) { 755 return; 756 } 757 758 if (enabled) { 759 trace_usb_xhci_irq_msix_use(v); 760 msix_vector_use(pci_dev, v); 761 xhci->intr[v].msix_used = true; 762 } else { 763 trace_usb_xhci_irq_msix_unuse(v); 764 msix_vector_unuse(pci_dev, v); 765 xhci->intr[v].msix_used = false; 766 } 767 } 768 769 static void xhci_intr_raise(XHCIState *xhci, int v) 770 { 771 PCIDevice *pci_dev = PCI_DEVICE(xhci); 772 773 xhci->intr[v].erdp_low |= ERDP_EHB; 774 xhci->intr[v].iman |= IMAN_IP; 775 xhci->usbsts |= USBSTS_EINT; 776 777 if (!(xhci->intr[v].iman & IMAN_IE)) { 778 return; 779 } 780 781 if (!(xhci->usbcmd & USBCMD_INTE)) { 782 return; 783 } 784 785 if (msix_enabled(pci_dev)) { 786 trace_usb_xhci_irq_msix(v); 787 msix_notify(pci_dev, v); 788 return; 789 } 790 791 if (msi_enabled(pci_dev)) { 792 trace_usb_xhci_irq_msi(v); 793 msi_notify(pci_dev, v); 794 return; 795 } 796 797 if (v == 0) { 798 trace_usb_xhci_irq_intx(1); 799 qemu_set_irq(xhci->irq, 1); 800 } 801 } 802 803 static inline int xhci_running(XHCIState *xhci) 804 { 805 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 806 } 807 808 static void xhci_die(XHCIState *xhci) 809 { 810 xhci->usbsts |= USBSTS_HCE; 811 fprintf(stderr, "xhci: asserted controller error\n"); 812 } 813 814 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 815 { 816 PCIDevice *pci_dev = PCI_DEVICE(xhci); 817 XHCIInterrupter *intr = &xhci->intr[v]; 818 XHCITRB ev_trb; 819 dma_addr_t addr; 820 821 ev_trb.parameter = cpu_to_le64(event->ptr); 822 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 823 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 824 event->flags | (event->type << TRB_TYPE_SHIFT); 825 if (intr->er_pcs) { 826 ev_trb.control |= TRB_C; 827 } 828 ev_trb.control = cpu_to_le32(ev_trb.control); 829 830 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 831 event_name(event), ev_trb.parameter, 832 ev_trb.status, ev_trb.control); 833 834 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 835 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 836 837 intr->er_ep_idx++; 838 if (intr->er_ep_idx >= intr->er_size) { 839 intr->er_ep_idx = 0; 840 intr->er_pcs = !intr->er_pcs; 841 } 842 } 843 844 static void xhci_events_update(XHCIState *xhci, int v) 845 { 846 XHCIInterrupter *intr = &xhci->intr[v]; 847 dma_addr_t erdp; 848 unsigned int dp_idx; 849 bool do_irq = 0; 850 851 if (xhci->usbsts & USBSTS_HCH) { 852 return; 853 } 854 855 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 856 if (erdp < intr->er_start || 857 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 858 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 859 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 860 v, intr->er_start, intr->er_size); 861 xhci_die(xhci); 862 return; 863 } 864 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 865 assert(dp_idx < intr->er_size); 866 867 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 868 * deadlocks when the ER is full. Hack it by holding off events until 869 * the driver decides to free at least half of the ring */ 870 if (intr->er_full) { 871 int er_free = dp_idx - intr->er_ep_idx; 872 if (er_free <= 0) { 873 er_free += intr->er_size; 874 } 875 if (er_free < (intr->er_size/2)) { 876 DPRINTF("xhci_events_update(): event ring still " 877 "more than half full (hack)\n"); 878 return; 879 } 880 } 881 882 while (intr->ev_buffer_put != intr->ev_buffer_get) { 883 assert(intr->er_full); 884 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 885 DPRINTF("xhci_events_update(): event ring full again\n"); 886 #ifndef ER_FULL_HACK 887 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 888 xhci_write_event(xhci, &full, v); 889 #endif 890 do_irq = 1; 891 break; 892 } 893 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 894 xhci_write_event(xhci, event, v); 895 intr->ev_buffer_get++; 896 do_irq = 1; 897 if (intr->ev_buffer_get == EV_QUEUE) { 898 intr->ev_buffer_get = 0; 899 } 900 } 901 902 if (do_irq) { 903 xhci_intr_raise(xhci, v); 904 } 905 906 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 907 DPRINTF("xhci_events_update(): event ring no longer full\n"); 908 intr->er_full = 0; 909 } 910 } 911 912 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 913 { 914 XHCIInterrupter *intr; 915 dma_addr_t erdp; 916 unsigned int dp_idx; 917 918 if (v >= xhci->numintrs) { 919 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 920 return; 921 } 922 intr = &xhci->intr[v]; 923 924 if (intr->er_full) { 925 DPRINTF("xhci_event(): ER full, queueing\n"); 926 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 927 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 928 return; 929 } 930 intr->ev_buffer[intr->ev_buffer_put++] = *event; 931 if (intr->ev_buffer_put == EV_QUEUE) { 932 intr->ev_buffer_put = 0; 933 } 934 return; 935 } 936 937 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 938 if (erdp < intr->er_start || 939 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 940 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 941 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 942 v, intr->er_start, intr->er_size); 943 xhci_die(xhci); 944 return; 945 } 946 947 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 948 assert(dp_idx < intr->er_size); 949 950 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 951 DPRINTF("xhci_event(): ER full, queueing\n"); 952 #ifndef ER_FULL_HACK 953 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 954 xhci_write_event(xhci, &full); 955 #endif 956 intr->er_full = 1; 957 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 958 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 959 return; 960 } 961 intr->ev_buffer[intr->ev_buffer_put++] = *event; 962 if (intr->ev_buffer_put == EV_QUEUE) { 963 intr->ev_buffer_put = 0; 964 } 965 } else { 966 xhci_write_event(xhci, event, v); 967 } 968 969 xhci_intr_raise(xhci, v); 970 } 971 972 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 973 dma_addr_t base) 974 { 975 ring->dequeue = base; 976 ring->ccs = 1; 977 } 978 979 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 980 dma_addr_t *addr) 981 { 982 PCIDevice *pci_dev = PCI_DEVICE(xhci); 983 984 while (1) { 985 TRBType type; 986 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 987 trb->addr = ring->dequeue; 988 trb->ccs = ring->ccs; 989 le64_to_cpus(&trb->parameter); 990 le32_to_cpus(&trb->status); 991 le32_to_cpus(&trb->control); 992 993 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 994 trb->parameter, trb->status, trb->control); 995 996 if ((trb->control & TRB_C) != ring->ccs) { 997 return 0; 998 } 999 1000 type = TRB_TYPE(*trb); 1001 1002 if (type != TR_LINK) { 1003 if (addr) { 1004 *addr = ring->dequeue; 1005 } 1006 ring->dequeue += TRB_SIZE; 1007 return type; 1008 } else { 1009 ring->dequeue = xhci_mask64(trb->parameter); 1010 if (trb->control & TRB_LK_TC) { 1011 ring->ccs = !ring->ccs; 1012 } 1013 } 1014 } 1015 } 1016 1017 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1018 { 1019 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1020 XHCITRB trb; 1021 int length = 0; 1022 dma_addr_t dequeue = ring->dequeue; 1023 bool ccs = ring->ccs; 1024 /* hack to bundle together the two/three TDs that make a setup transfer */ 1025 bool control_td_set = 0; 1026 1027 while (1) { 1028 TRBType type; 1029 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1030 le64_to_cpus(&trb.parameter); 1031 le32_to_cpus(&trb.status); 1032 le32_to_cpus(&trb.control); 1033 1034 if ((trb.control & TRB_C) != ccs) { 1035 return -length; 1036 } 1037 1038 type = TRB_TYPE(trb); 1039 1040 if (type == TR_LINK) { 1041 dequeue = xhci_mask64(trb.parameter); 1042 if (trb.control & TRB_LK_TC) { 1043 ccs = !ccs; 1044 } 1045 continue; 1046 } 1047 1048 length += 1; 1049 dequeue += TRB_SIZE; 1050 1051 if (type == TR_SETUP) { 1052 control_td_set = 1; 1053 } else if (type == TR_STATUS) { 1054 control_td_set = 0; 1055 } 1056 1057 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1058 return length; 1059 } 1060 } 1061 } 1062 1063 static void xhci_er_reset(XHCIState *xhci, int v) 1064 { 1065 XHCIInterrupter *intr = &xhci->intr[v]; 1066 XHCIEvRingSeg seg; 1067 1068 if (intr->erstsz == 0) { 1069 /* disabled */ 1070 intr->er_start = 0; 1071 intr->er_size = 0; 1072 return; 1073 } 1074 /* cache the (sole) event ring segment location */ 1075 if (intr->erstsz != 1) { 1076 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1077 xhci_die(xhci); 1078 return; 1079 } 1080 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1081 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1082 le32_to_cpus(&seg.addr_low); 1083 le32_to_cpus(&seg.addr_high); 1084 le32_to_cpus(&seg.size); 1085 if (seg.size < 16 || seg.size > 4096) { 1086 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1087 xhci_die(xhci); 1088 return; 1089 } 1090 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1091 intr->er_size = seg.size; 1092 1093 intr->er_ep_idx = 0; 1094 intr->er_pcs = 1; 1095 intr->er_full = 0; 1096 1097 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1098 v, intr->er_start, intr->er_size); 1099 } 1100 1101 static void xhci_run(XHCIState *xhci) 1102 { 1103 trace_usb_xhci_run(); 1104 xhci->usbsts &= ~USBSTS_HCH; 1105 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1106 } 1107 1108 static void xhci_stop(XHCIState *xhci) 1109 { 1110 trace_usb_xhci_stop(); 1111 xhci->usbsts |= USBSTS_HCH; 1112 xhci->crcr_low &= ~CRCR_CRR; 1113 } 1114 1115 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1116 dma_addr_t base) 1117 { 1118 XHCIStreamContext *stctx; 1119 unsigned int i; 1120 1121 stctx = g_new0(XHCIStreamContext, count); 1122 for (i = 0; i < count; i++) { 1123 stctx[i].pctx = base + i * 16; 1124 stctx[i].sct = -1; 1125 } 1126 return stctx; 1127 } 1128 1129 static void xhci_reset_streams(XHCIEPContext *epctx) 1130 { 1131 unsigned int i; 1132 1133 for (i = 0; i < epctx->nr_pstreams; i++) { 1134 epctx->pstreams[i].sct = -1; 1135 } 1136 } 1137 1138 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1139 { 1140 assert(epctx->pstreams == NULL); 1141 epctx->nr_pstreams = 2 << (epctx->max_pstreams + 1); 1142 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1143 } 1144 1145 static void xhci_free_streams(XHCIEPContext *epctx) 1146 { 1147 assert(epctx->pstreams != NULL); 1148 1149 g_free(epctx->pstreams); 1150 epctx->pstreams = NULL; 1151 epctx->nr_pstreams = 0; 1152 } 1153 1154 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1155 unsigned int streamid, 1156 uint32_t *cc_error) 1157 { 1158 XHCIStreamContext *sctx; 1159 dma_addr_t base; 1160 uint32_t ctx[2], sct; 1161 1162 assert(streamid != 0); 1163 if (epctx->lsa) { 1164 if (streamid >= epctx->nr_pstreams) { 1165 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1166 return NULL; 1167 } 1168 sctx = epctx->pstreams + streamid; 1169 } else { 1170 FIXME("secondary streams not implemented yet"); 1171 } 1172 1173 if (sctx->sct == -1) { 1174 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1175 sct = (ctx[0] >> 1) & 0x07; 1176 if (epctx->lsa && sct != 1) { 1177 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1178 return NULL; 1179 } 1180 sctx->sct = sct; 1181 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1182 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1183 } 1184 return sctx; 1185 } 1186 1187 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1188 XHCIStreamContext *sctx, uint32_t state) 1189 { 1190 uint32_t ctx[5]; 1191 uint32_t ctx2[2]; 1192 1193 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1194 ctx[0] &= ~EP_STATE_MASK; 1195 ctx[0] |= state; 1196 1197 /* update ring dequeue ptr */ 1198 if (epctx->nr_pstreams) { 1199 if (sctx != NULL) { 1200 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1201 ctx2[0] &= 0xe; 1202 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1203 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1204 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1205 } 1206 } else { 1207 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1208 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1209 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1210 epctx->pctx, state, ctx[3], ctx[2]); 1211 } 1212 1213 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1214 if (epctx->state != state) { 1215 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1216 ep_state_name(epctx->state), 1217 ep_state_name(state)); 1218 } 1219 epctx->state = state; 1220 } 1221 1222 static void xhci_ep_kick_timer(void *opaque) 1223 { 1224 XHCIEPContext *epctx = opaque; 1225 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1226 } 1227 1228 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1229 unsigned int slotid, 1230 unsigned int epid) 1231 { 1232 XHCIEPContext *epctx; 1233 int i; 1234 1235 epctx = g_new0(XHCIEPContext, 1); 1236 epctx->xhci = xhci; 1237 epctx->slotid = slotid; 1238 epctx->epid = epid; 1239 1240 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1241 epctx->transfers[i].xhci = xhci; 1242 epctx->transfers[i].slotid = slotid; 1243 epctx->transfers[i].epid = epid; 1244 usb_packet_init(&epctx->transfers[i].packet); 1245 } 1246 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1247 1248 return epctx; 1249 } 1250 1251 static void xhci_init_epctx(XHCIEPContext *epctx, 1252 dma_addr_t pctx, uint32_t *ctx) 1253 { 1254 dma_addr_t dequeue; 1255 1256 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1257 1258 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1259 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1260 epctx->pctx = pctx; 1261 epctx->max_psize = ctx[1]>>16; 1262 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1263 epctx->max_pstreams = (ctx[0] >> 10) & 0xf; 1264 epctx->lsa = (ctx[0] >> 15) & 1; 1265 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1266 epid/2, epid%2, epctx->max_psize); 1267 if (epctx->max_pstreams) { 1268 xhci_alloc_streams(epctx, dequeue); 1269 } else { 1270 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1271 epctx->ring.ccs = ctx[2] & 1; 1272 } 1273 1274 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1275 } 1276 1277 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1278 unsigned int epid, dma_addr_t pctx, 1279 uint32_t *ctx) 1280 { 1281 XHCISlot *slot; 1282 XHCIEPContext *epctx; 1283 1284 trace_usb_xhci_ep_enable(slotid, epid); 1285 assert(slotid >= 1 && slotid <= xhci->numslots); 1286 assert(epid >= 1 && epid <= 31); 1287 1288 slot = &xhci->slots[slotid-1]; 1289 if (slot->eps[epid-1]) { 1290 xhci_disable_ep(xhci, slotid, epid); 1291 } 1292 1293 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1294 slot->eps[epid-1] = epctx; 1295 xhci_init_epctx(epctx, pctx, ctx); 1296 1297 epctx->mfindex_last = 0; 1298 1299 epctx->state = EP_RUNNING; 1300 ctx[0] &= ~EP_STATE_MASK; 1301 ctx[0] |= EP_RUNNING; 1302 1303 return CC_SUCCESS; 1304 } 1305 1306 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1307 { 1308 int killed = 0; 1309 1310 if (report && (t->running_async || t->running_retry)) { 1311 t->status = report; 1312 xhci_xfer_report(t); 1313 } 1314 1315 if (t->running_async) { 1316 usb_cancel_packet(&t->packet); 1317 t->running_async = 0; 1318 killed = 1; 1319 } 1320 if (t->running_retry) { 1321 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1322 if (epctx) { 1323 epctx->retry = NULL; 1324 timer_del(epctx->kick_timer); 1325 } 1326 t->running_retry = 0; 1327 killed = 1; 1328 } 1329 if (t->trbs) { 1330 g_free(t->trbs); 1331 } 1332 1333 t->trbs = NULL; 1334 t->trb_count = t->trb_alloced = 0; 1335 1336 return killed; 1337 } 1338 1339 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1340 unsigned int epid, TRBCCode report) 1341 { 1342 XHCISlot *slot; 1343 XHCIEPContext *epctx; 1344 int i, xferi, killed = 0; 1345 USBEndpoint *ep = NULL; 1346 assert(slotid >= 1 && slotid <= xhci->numslots); 1347 assert(epid >= 1 && epid <= 31); 1348 1349 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1350 1351 slot = &xhci->slots[slotid-1]; 1352 1353 if (!slot->eps[epid-1]) { 1354 return 0; 1355 } 1356 1357 epctx = slot->eps[epid-1]; 1358 1359 xferi = epctx->next_xfer; 1360 for (i = 0; i < TD_QUEUE; i++) { 1361 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report); 1362 if (killed) { 1363 report = 0; /* Only report once */ 1364 } 1365 epctx->transfers[xferi].packet.ep = NULL; 1366 xferi = (xferi + 1) % TD_QUEUE; 1367 } 1368 1369 ep = xhci_epid_to_usbep(xhci, slotid, epid); 1370 if (ep) { 1371 usb_device_ep_stopped(ep->dev, ep); 1372 } 1373 return killed; 1374 } 1375 1376 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1377 unsigned int epid) 1378 { 1379 XHCISlot *slot; 1380 XHCIEPContext *epctx; 1381 int i; 1382 1383 trace_usb_xhci_ep_disable(slotid, epid); 1384 assert(slotid >= 1 && slotid <= xhci->numslots); 1385 assert(epid >= 1 && epid <= 31); 1386 1387 slot = &xhci->slots[slotid-1]; 1388 1389 if (!slot->eps[epid-1]) { 1390 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1391 return CC_SUCCESS; 1392 } 1393 1394 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1395 1396 epctx = slot->eps[epid-1]; 1397 1398 if (epctx->nr_pstreams) { 1399 xhci_free_streams(epctx); 1400 } 1401 1402 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1403 usb_packet_cleanup(&epctx->transfers[i].packet); 1404 } 1405 1406 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1407 1408 timer_free(epctx->kick_timer); 1409 g_free(epctx); 1410 slot->eps[epid-1] = NULL; 1411 1412 return CC_SUCCESS; 1413 } 1414 1415 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1416 unsigned int epid) 1417 { 1418 XHCISlot *slot; 1419 XHCIEPContext *epctx; 1420 1421 trace_usb_xhci_ep_stop(slotid, epid); 1422 assert(slotid >= 1 && slotid <= xhci->numslots); 1423 1424 if (epid < 1 || epid > 31) { 1425 fprintf(stderr, "xhci: bad ep %d\n", epid); 1426 return CC_TRB_ERROR; 1427 } 1428 1429 slot = &xhci->slots[slotid-1]; 1430 1431 if (!slot->eps[epid-1]) { 1432 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1433 return CC_EP_NOT_ENABLED_ERROR; 1434 } 1435 1436 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1437 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1438 "data might be lost\n"); 1439 } 1440 1441 epctx = slot->eps[epid-1]; 1442 1443 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1444 1445 if (epctx->nr_pstreams) { 1446 xhci_reset_streams(epctx); 1447 } 1448 1449 return CC_SUCCESS; 1450 } 1451 1452 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1453 unsigned int epid) 1454 { 1455 XHCISlot *slot; 1456 XHCIEPContext *epctx; 1457 1458 trace_usb_xhci_ep_reset(slotid, epid); 1459 assert(slotid >= 1 && slotid <= xhci->numslots); 1460 1461 if (epid < 1 || epid > 31) { 1462 fprintf(stderr, "xhci: bad ep %d\n", epid); 1463 return CC_TRB_ERROR; 1464 } 1465 1466 slot = &xhci->slots[slotid-1]; 1467 1468 if (!slot->eps[epid-1]) { 1469 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1470 return CC_EP_NOT_ENABLED_ERROR; 1471 } 1472 1473 epctx = slot->eps[epid-1]; 1474 1475 if (epctx->state != EP_HALTED) { 1476 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1477 epid, epctx->state); 1478 return CC_CONTEXT_STATE_ERROR; 1479 } 1480 1481 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1482 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1483 "data might be lost\n"); 1484 } 1485 1486 uint8_t ep = epid>>1; 1487 1488 if (epid & 1) { 1489 ep |= 0x80; 1490 } 1491 1492 if (!xhci->slots[slotid-1].uport || 1493 !xhci->slots[slotid-1].uport->dev) { 1494 return CC_USB_TRANSACTION_ERROR; 1495 } 1496 1497 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1498 1499 if (epctx->nr_pstreams) { 1500 xhci_reset_streams(epctx); 1501 } 1502 1503 return CC_SUCCESS; 1504 } 1505 1506 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1507 unsigned int epid, unsigned int streamid, 1508 uint64_t pdequeue) 1509 { 1510 XHCISlot *slot; 1511 XHCIEPContext *epctx; 1512 XHCIStreamContext *sctx; 1513 dma_addr_t dequeue; 1514 1515 assert(slotid >= 1 && slotid <= xhci->numslots); 1516 1517 if (epid < 1 || epid > 31) { 1518 fprintf(stderr, "xhci: bad ep %d\n", epid); 1519 return CC_TRB_ERROR; 1520 } 1521 1522 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1523 dequeue = xhci_mask64(pdequeue); 1524 1525 slot = &xhci->slots[slotid-1]; 1526 1527 if (!slot->eps[epid-1]) { 1528 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1529 return CC_EP_NOT_ENABLED_ERROR; 1530 } 1531 1532 epctx = slot->eps[epid-1]; 1533 1534 if (epctx->state != EP_STOPPED) { 1535 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1536 return CC_CONTEXT_STATE_ERROR; 1537 } 1538 1539 if (epctx->nr_pstreams) { 1540 uint32_t err; 1541 sctx = xhci_find_stream(epctx, streamid, &err); 1542 if (sctx == NULL) { 1543 return err; 1544 } 1545 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1546 sctx->ring.ccs = dequeue & 1; 1547 } else { 1548 sctx = NULL; 1549 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1550 epctx->ring.ccs = dequeue & 1; 1551 } 1552 1553 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1554 1555 return CC_SUCCESS; 1556 } 1557 1558 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1559 { 1560 XHCIState *xhci = xfer->xhci; 1561 int i; 1562 1563 xfer->int_req = false; 1564 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1565 for (i = 0; i < xfer->trb_count; i++) { 1566 XHCITRB *trb = &xfer->trbs[i]; 1567 dma_addr_t addr; 1568 unsigned int chunk = 0; 1569 1570 if (trb->control & TRB_TR_IOC) { 1571 xfer->int_req = true; 1572 } 1573 1574 switch (TRB_TYPE(*trb)) { 1575 case TR_DATA: 1576 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1577 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1578 goto err; 1579 } 1580 /* fallthrough */ 1581 case TR_NORMAL: 1582 case TR_ISOCH: 1583 addr = xhci_mask64(trb->parameter); 1584 chunk = trb->status & 0x1ffff; 1585 if (trb->control & TRB_TR_IDT) { 1586 if (chunk > 8 || in_xfer) { 1587 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1588 goto err; 1589 } 1590 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1591 } else { 1592 qemu_sglist_add(&xfer->sgl, addr, chunk); 1593 } 1594 break; 1595 } 1596 } 1597 1598 return 0; 1599 1600 err: 1601 qemu_sglist_destroy(&xfer->sgl); 1602 xhci_die(xhci); 1603 return -1; 1604 } 1605 1606 static void xhci_xfer_unmap(XHCITransfer *xfer) 1607 { 1608 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1609 qemu_sglist_destroy(&xfer->sgl); 1610 } 1611 1612 static void xhci_xfer_report(XHCITransfer *xfer) 1613 { 1614 uint32_t edtla = 0; 1615 unsigned int left; 1616 bool reported = 0; 1617 bool shortpkt = 0; 1618 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1619 XHCIState *xhci = xfer->xhci; 1620 int i; 1621 1622 left = xfer->packet.actual_length; 1623 1624 for (i = 0; i < xfer->trb_count; i++) { 1625 XHCITRB *trb = &xfer->trbs[i]; 1626 unsigned int chunk = 0; 1627 1628 switch (TRB_TYPE(*trb)) { 1629 case TR_DATA: 1630 case TR_NORMAL: 1631 case TR_ISOCH: 1632 chunk = trb->status & 0x1ffff; 1633 if (chunk > left) { 1634 chunk = left; 1635 if (xfer->status == CC_SUCCESS) { 1636 shortpkt = 1; 1637 } 1638 } 1639 left -= chunk; 1640 edtla += chunk; 1641 break; 1642 case TR_STATUS: 1643 reported = 0; 1644 shortpkt = 0; 1645 break; 1646 } 1647 1648 if (!reported && ((trb->control & TRB_TR_IOC) || 1649 (shortpkt && (trb->control & TRB_TR_ISP)) || 1650 (xfer->status != CC_SUCCESS && left == 0))) { 1651 event.slotid = xfer->slotid; 1652 event.epid = xfer->epid; 1653 event.length = (trb->status & 0x1ffff) - chunk; 1654 event.flags = 0; 1655 event.ptr = trb->addr; 1656 if (xfer->status == CC_SUCCESS) { 1657 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1658 } else { 1659 event.ccode = xfer->status; 1660 } 1661 if (TRB_TYPE(*trb) == TR_EVDATA) { 1662 event.ptr = trb->parameter; 1663 event.flags |= TRB_EV_ED; 1664 event.length = edtla & 0xffffff; 1665 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1666 edtla = 0; 1667 } 1668 xhci_event(xhci, &event, TRB_INTR(*trb)); 1669 reported = 1; 1670 if (xfer->status != CC_SUCCESS) { 1671 return; 1672 } 1673 } 1674 } 1675 } 1676 1677 static void xhci_stall_ep(XHCITransfer *xfer) 1678 { 1679 XHCIState *xhci = xfer->xhci; 1680 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1681 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1682 uint32_t err; 1683 XHCIStreamContext *sctx; 1684 1685 if (epctx->nr_pstreams) { 1686 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1687 if (sctx == NULL) { 1688 return; 1689 } 1690 sctx->ring.dequeue = xfer->trbs[0].addr; 1691 sctx->ring.ccs = xfer->trbs[0].ccs; 1692 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1693 } else { 1694 epctx->ring.dequeue = xfer->trbs[0].addr; 1695 epctx->ring.ccs = xfer->trbs[0].ccs; 1696 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1697 } 1698 } 1699 1700 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1701 XHCIEPContext *epctx); 1702 1703 static int xhci_setup_packet(XHCITransfer *xfer) 1704 { 1705 XHCIState *xhci = xfer->xhci; 1706 USBEndpoint *ep; 1707 int dir; 1708 1709 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1710 1711 if (xfer->packet.ep) { 1712 ep = xfer->packet.ep; 1713 } else { 1714 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); 1715 if (!ep) { 1716 fprintf(stderr, "xhci: slot %d has no device\n", 1717 xfer->slotid); 1718 return -1; 1719 } 1720 } 1721 1722 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1723 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1724 xfer->trbs[0].addr, false, xfer->int_req); 1725 usb_packet_map(&xfer->packet, &xfer->sgl); 1726 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1727 xfer->packet.pid, ep->dev->addr, ep->nr); 1728 return 0; 1729 } 1730 1731 static int xhci_complete_packet(XHCITransfer *xfer) 1732 { 1733 if (xfer->packet.status == USB_RET_ASYNC) { 1734 trace_usb_xhci_xfer_async(xfer); 1735 xfer->running_async = 1; 1736 xfer->running_retry = 0; 1737 xfer->complete = 0; 1738 return 0; 1739 } else if (xfer->packet.status == USB_RET_NAK) { 1740 trace_usb_xhci_xfer_nak(xfer); 1741 xfer->running_async = 0; 1742 xfer->running_retry = 1; 1743 xfer->complete = 0; 1744 return 0; 1745 } else { 1746 xfer->running_async = 0; 1747 xfer->running_retry = 0; 1748 xfer->complete = 1; 1749 xhci_xfer_unmap(xfer); 1750 } 1751 1752 if (xfer->packet.status == USB_RET_SUCCESS) { 1753 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1754 xfer->status = CC_SUCCESS; 1755 xhci_xfer_report(xfer); 1756 return 0; 1757 } 1758 1759 /* error */ 1760 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1761 switch (xfer->packet.status) { 1762 case USB_RET_NODEV: 1763 case USB_RET_IOERROR: 1764 xfer->status = CC_USB_TRANSACTION_ERROR; 1765 xhci_xfer_report(xfer); 1766 xhci_stall_ep(xfer); 1767 break; 1768 case USB_RET_STALL: 1769 xfer->status = CC_STALL_ERROR; 1770 xhci_xfer_report(xfer); 1771 xhci_stall_ep(xfer); 1772 break; 1773 case USB_RET_BABBLE: 1774 xfer->status = CC_BABBLE_DETECTED; 1775 xhci_xfer_report(xfer); 1776 xhci_stall_ep(xfer); 1777 break; 1778 default: 1779 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1780 xfer->packet.status); 1781 FIXME("unhandled USB_RET_*"); 1782 } 1783 return 0; 1784 } 1785 1786 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1787 { 1788 XHCITRB *trb_setup, *trb_status; 1789 uint8_t bmRequestType; 1790 1791 trb_setup = &xfer->trbs[0]; 1792 trb_status = &xfer->trbs[xfer->trb_count-1]; 1793 1794 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1795 1796 /* at most one Event Data TRB allowed after STATUS */ 1797 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1798 trb_status--; 1799 } 1800 1801 /* do some sanity checks */ 1802 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1803 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1804 TRB_TYPE(*trb_setup)); 1805 return -1; 1806 } 1807 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1808 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1809 TRB_TYPE(*trb_status)); 1810 return -1; 1811 } 1812 if (!(trb_setup->control & TRB_TR_IDT)) { 1813 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1814 return -1; 1815 } 1816 if ((trb_setup->status & 0x1ffff) != 8) { 1817 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1818 (trb_setup->status & 0x1ffff)); 1819 return -1; 1820 } 1821 1822 bmRequestType = trb_setup->parameter; 1823 1824 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1825 xfer->iso_xfer = false; 1826 xfer->timed_xfer = false; 1827 1828 if (xhci_setup_packet(xfer) < 0) { 1829 return -1; 1830 } 1831 xfer->packet.parameter = trb_setup->parameter; 1832 1833 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1834 1835 xhci_complete_packet(xfer); 1836 if (!xfer->running_async && !xfer->running_retry) { 1837 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1838 } 1839 return 0; 1840 } 1841 1842 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1843 XHCIEPContext *epctx, uint64_t mfindex) 1844 { 1845 uint64_t asap = ((mfindex + epctx->interval - 1) & 1846 ~(epctx->interval-1)); 1847 uint64_t kick = epctx->mfindex_last + epctx->interval; 1848 1849 assert(epctx->interval != 0); 1850 xfer->mfindex_kick = MAX(asap, kick); 1851 } 1852 1853 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1854 XHCIEPContext *epctx, uint64_t mfindex) 1855 { 1856 if (xfer->trbs[0].control & TRB_TR_SIA) { 1857 uint64_t asap = ((mfindex + epctx->interval - 1) & 1858 ~(epctx->interval-1)); 1859 if (asap >= epctx->mfindex_last && 1860 asap <= epctx->mfindex_last + epctx->interval * 4) { 1861 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1862 } else { 1863 xfer->mfindex_kick = asap; 1864 } 1865 } else { 1866 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1867 & TRB_TR_FRAMEID_MASK; 1868 xfer->mfindex_kick |= mfindex & ~0x3fff; 1869 if (xfer->mfindex_kick < mfindex) { 1870 xfer->mfindex_kick += 0x4000; 1871 } 1872 } 1873 } 1874 1875 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1876 XHCIEPContext *epctx, uint64_t mfindex) 1877 { 1878 if (xfer->mfindex_kick > mfindex) { 1879 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1880 (xfer->mfindex_kick - mfindex) * 125000); 1881 xfer->running_retry = 1; 1882 } else { 1883 epctx->mfindex_last = xfer->mfindex_kick; 1884 timer_del(epctx->kick_timer); 1885 xfer->running_retry = 0; 1886 } 1887 } 1888 1889 1890 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1891 { 1892 uint64_t mfindex; 1893 1894 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1895 1896 xfer->in_xfer = epctx->type>>2; 1897 1898 switch(epctx->type) { 1899 case ET_INTR_OUT: 1900 case ET_INTR_IN: 1901 xfer->pkts = 0; 1902 xfer->iso_xfer = false; 1903 xfer->timed_xfer = true; 1904 mfindex = xhci_mfindex_get(xhci); 1905 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1906 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1907 if (xfer->running_retry) { 1908 return -1; 1909 } 1910 break; 1911 case ET_BULK_OUT: 1912 case ET_BULK_IN: 1913 xfer->pkts = 0; 1914 xfer->iso_xfer = false; 1915 xfer->timed_xfer = false; 1916 break; 1917 case ET_ISO_OUT: 1918 case ET_ISO_IN: 1919 xfer->pkts = 1; 1920 xfer->iso_xfer = true; 1921 xfer->timed_xfer = true; 1922 mfindex = xhci_mfindex_get(xhci); 1923 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1924 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1925 if (xfer->running_retry) { 1926 return -1; 1927 } 1928 break; 1929 default: 1930 fprintf(stderr, "xhci: unknown or unhandled EP " 1931 "(type %d, in %d, ep %02x)\n", 1932 epctx->type, xfer->in_xfer, xfer->epid); 1933 return -1; 1934 } 1935 1936 if (xhci_setup_packet(xfer) < 0) { 1937 return -1; 1938 } 1939 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1940 1941 xhci_complete_packet(xfer); 1942 if (!xfer->running_async && !xfer->running_retry) { 1943 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 1944 } 1945 return 0; 1946 } 1947 1948 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1949 { 1950 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1951 return xhci_submit(xhci, xfer, epctx); 1952 } 1953 1954 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 1955 unsigned int epid, unsigned int streamid) 1956 { 1957 XHCIStreamContext *stctx; 1958 XHCIEPContext *epctx; 1959 XHCIRing *ring; 1960 USBEndpoint *ep = NULL; 1961 uint64_t mfindex; 1962 int length; 1963 int i; 1964 1965 trace_usb_xhci_ep_kick(slotid, epid, streamid); 1966 assert(slotid >= 1 && slotid <= xhci->numslots); 1967 assert(epid >= 1 && epid <= 31); 1968 1969 if (!xhci->slots[slotid-1].enabled) { 1970 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1971 return; 1972 } 1973 epctx = xhci->slots[slotid-1].eps[epid-1]; 1974 if (!epctx) { 1975 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1976 epid, slotid); 1977 return; 1978 } 1979 1980 if (epctx->retry) { 1981 XHCITransfer *xfer = epctx->retry; 1982 1983 trace_usb_xhci_xfer_retry(xfer); 1984 assert(xfer->running_retry); 1985 if (xfer->timed_xfer) { 1986 /* time to kick the transfer? */ 1987 mfindex = xhci_mfindex_get(xhci); 1988 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1989 if (xfer->running_retry) { 1990 return; 1991 } 1992 xfer->timed_xfer = 0; 1993 xfer->running_retry = 1; 1994 } 1995 if (xfer->iso_xfer) { 1996 /* retry iso transfer */ 1997 if (xhci_setup_packet(xfer) < 0) { 1998 return; 1999 } 2000 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2001 assert(xfer->packet.status != USB_RET_NAK); 2002 xhci_complete_packet(xfer); 2003 } else { 2004 /* retry nak'ed transfer */ 2005 if (xhci_setup_packet(xfer) < 0) { 2006 return; 2007 } 2008 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2009 if (xfer->packet.status == USB_RET_NAK) { 2010 return; 2011 } 2012 xhci_complete_packet(xfer); 2013 } 2014 assert(!xfer->running_retry); 2015 epctx->retry = NULL; 2016 } 2017 2018 if (epctx->state == EP_HALTED) { 2019 DPRINTF("xhci: ep halted, not running schedule\n"); 2020 return; 2021 } 2022 2023 2024 if (epctx->nr_pstreams) { 2025 uint32_t err; 2026 stctx = xhci_find_stream(epctx, streamid, &err); 2027 if (stctx == NULL) { 2028 return; 2029 } 2030 ring = &stctx->ring; 2031 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2032 } else { 2033 ring = &epctx->ring; 2034 streamid = 0; 2035 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2036 } 2037 assert(ring->dequeue != 0); 2038 2039 while (1) { 2040 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 2041 if (xfer->running_async || xfer->running_retry) { 2042 break; 2043 } 2044 length = xhci_ring_chain_length(xhci, ring); 2045 if (length < 0) { 2046 break; 2047 } else if (length == 0) { 2048 break; 2049 } 2050 if (xfer->trbs && xfer->trb_alloced < length) { 2051 xfer->trb_count = 0; 2052 xfer->trb_alloced = 0; 2053 g_free(xfer->trbs); 2054 xfer->trbs = NULL; 2055 } 2056 if (!xfer->trbs) { 2057 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 2058 xfer->trb_alloced = length; 2059 } 2060 xfer->trb_count = length; 2061 2062 for (i = 0; i < length; i++) { 2063 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2064 } 2065 xfer->streamid = streamid; 2066 2067 if (epid == 1) { 2068 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2069 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2070 ep = xfer->packet.ep; 2071 } else { 2072 fprintf(stderr, "xhci: error firing CTL transfer\n"); 2073 } 2074 } else { 2075 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2076 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2077 } else { 2078 if (!xfer->timed_xfer) { 2079 fprintf(stderr, "xhci: error firing data transfer\n"); 2080 } 2081 } 2082 } 2083 2084 if (epctx->state == EP_HALTED) { 2085 break; 2086 } 2087 if (xfer->running_retry) { 2088 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2089 epctx->retry = xfer; 2090 break; 2091 } 2092 } 2093 2094 ep = xhci_epid_to_usbep(xhci, slotid, epid); 2095 if (ep) { 2096 usb_device_flush_ep_queue(ep->dev, ep); 2097 } 2098 } 2099 2100 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2101 { 2102 trace_usb_xhci_slot_enable(slotid); 2103 assert(slotid >= 1 && slotid <= xhci->numslots); 2104 xhci->slots[slotid-1].enabled = 1; 2105 xhci->slots[slotid-1].uport = NULL; 2106 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2107 2108 return CC_SUCCESS; 2109 } 2110 2111 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2112 { 2113 int i; 2114 2115 trace_usb_xhci_slot_disable(slotid); 2116 assert(slotid >= 1 && slotid <= xhci->numslots); 2117 2118 for (i = 1; i <= 31; i++) { 2119 if (xhci->slots[slotid-1].eps[i-1]) { 2120 xhci_disable_ep(xhci, slotid, i); 2121 } 2122 } 2123 2124 xhci->slots[slotid-1].enabled = 0; 2125 xhci->slots[slotid-1].addressed = 0; 2126 xhci->slots[slotid-1].uport = NULL; 2127 return CC_SUCCESS; 2128 } 2129 2130 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2131 { 2132 USBPort *uport; 2133 char path[32]; 2134 int i, pos, port; 2135 2136 port = (slot_ctx[1]>>16) & 0xFF; 2137 port = xhci->ports[port-1].uport->index+1; 2138 pos = snprintf(path, sizeof(path), "%d", port); 2139 for (i = 0; i < 5; i++) { 2140 port = (slot_ctx[0] >> 4*i) & 0x0f; 2141 if (!port) { 2142 break; 2143 } 2144 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2145 } 2146 2147 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2148 if (strcmp(uport->path, path) == 0) { 2149 return uport; 2150 } 2151 } 2152 return NULL; 2153 } 2154 2155 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2156 uint64_t pictx, bool bsr) 2157 { 2158 XHCISlot *slot; 2159 USBPort *uport; 2160 USBDevice *dev; 2161 dma_addr_t ictx, octx, dcbaap; 2162 uint64_t poctx; 2163 uint32_t ictl_ctx[2]; 2164 uint32_t slot_ctx[4]; 2165 uint32_t ep0_ctx[5]; 2166 int i; 2167 TRBCCode res; 2168 2169 assert(slotid >= 1 && slotid <= xhci->numslots); 2170 2171 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2172 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2173 ictx = xhci_mask64(pictx); 2174 octx = xhci_mask64(poctx); 2175 2176 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2177 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2178 2179 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2180 2181 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2182 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2183 ictl_ctx[0], ictl_ctx[1]); 2184 return CC_TRB_ERROR; 2185 } 2186 2187 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2188 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2189 2190 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2191 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2192 2193 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2194 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2195 2196 uport = xhci_lookup_uport(xhci, slot_ctx); 2197 if (uport == NULL) { 2198 fprintf(stderr, "xhci: port not found\n"); 2199 return CC_TRB_ERROR; 2200 } 2201 trace_usb_xhci_slot_address(slotid, uport->path); 2202 2203 dev = uport->dev; 2204 if (!dev) { 2205 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 2206 return CC_USB_TRANSACTION_ERROR; 2207 } 2208 2209 for (i = 0; i < xhci->numslots; i++) { 2210 if (i == slotid-1) { 2211 continue; 2212 } 2213 if (xhci->slots[i].uport == uport) { 2214 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 2215 uport->path, i+1); 2216 return CC_TRB_ERROR; 2217 } 2218 } 2219 2220 slot = &xhci->slots[slotid-1]; 2221 slot->uport = uport; 2222 slot->ctx = octx; 2223 2224 if (bsr) { 2225 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2226 } else { 2227 USBPacket p; 2228 uint8_t buf[1]; 2229 2230 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2231 usb_device_reset(dev); 2232 memset(&p, 0, sizeof(p)); 2233 usb_packet_addbuf(&p, buf, sizeof(buf)); 2234 usb_packet_setup(&p, USB_TOKEN_OUT, 2235 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2236 0, false, false); 2237 usb_device_handle_control(dev, &p, 2238 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2239 slotid, 0, 0, NULL); 2240 assert(p.status != USB_RET_ASYNC); 2241 } 2242 2243 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2244 2245 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2246 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2247 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2248 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2249 2250 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2251 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2252 2253 xhci->slots[slotid-1].addressed = 1; 2254 return res; 2255 } 2256 2257 2258 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2259 uint64_t pictx, bool dc) 2260 { 2261 dma_addr_t ictx, octx; 2262 uint32_t ictl_ctx[2]; 2263 uint32_t slot_ctx[4]; 2264 uint32_t islot_ctx[4]; 2265 uint32_t ep_ctx[5]; 2266 int i; 2267 TRBCCode res; 2268 2269 trace_usb_xhci_slot_configure(slotid); 2270 assert(slotid >= 1 && slotid <= xhci->numslots); 2271 2272 ictx = xhci_mask64(pictx); 2273 octx = xhci->slots[slotid-1].ctx; 2274 2275 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2276 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2277 2278 if (dc) { 2279 for (i = 2; i <= 31; i++) { 2280 if (xhci->slots[slotid-1].eps[i-1]) { 2281 xhci_disable_ep(xhci, slotid, i); 2282 } 2283 } 2284 2285 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2286 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2287 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2288 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2289 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2290 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2291 2292 return CC_SUCCESS; 2293 } 2294 2295 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2296 2297 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2298 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2299 ictl_ctx[0], ictl_ctx[1]); 2300 return CC_TRB_ERROR; 2301 } 2302 2303 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2304 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2305 2306 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2307 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2308 return CC_CONTEXT_STATE_ERROR; 2309 } 2310 2311 for (i = 2; i <= 31; i++) { 2312 if (ictl_ctx[0] & (1<<i)) { 2313 xhci_disable_ep(xhci, slotid, i); 2314 } 2315 if (ictl_ctx[1] & (1<<i)) { 2316 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2317 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2318 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2319 ep_ctx[3], ep_ctx[4]); 2320 xhci_disable_ep(xhci, slotid, i); 2321 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2322 if (res != CC_SUCCESS) { 2323 return res; 2324 } 2325 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2326 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2327 ep_ctx[3], ep_ctx[4]); 2328 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2329 } 2330 } 2331 2332 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2333 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2334 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2335 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2336 SLOT_CONTEXT_ENTRIES_SHIFT); 2337 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2338 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2339 2340 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2341 2342 return CC_SUCCESS; 2343 } 2344 2345 2346 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2347 uint64_t pictx) 2348 { 2349 dma_addr_t ictx, octx; 2350 uint32_t ictl_ctx[2]; 2351 uint32_t iep0_ctx[5]; 2352 uint32_t ep0_ctx[5]; 2353 uint32_t islot_ctx[4]; 2354 uint32_t slot_ctx[4]; 2355 2356 trace_usb_xhci_slot_evaluate(slotid); 2357 assert(slotid >= 1 && slotid <= xhci->numslots); 2358 2359 ictx = xhci_mask64(pictx); 2360 octx = xhci->slots[slotid-1].ctx; 2361 2362 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2363 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2364 2365 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2366 2367 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2368 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2369 ictl_ctx[0], ictl_ctx[1]); 2370 return CC_TRB_ERROR; 2371 } 2372 2373 if (ictl_ctx[1] & 0x1) { 2374 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2375 2376 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2377 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2378 2379 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2380 2381 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2382 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2383 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2384 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2385 2386 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2387 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2388 2389 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2390 } 2391 2392 if (ictl_ctx[1] & 0x2) { 2393 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2394 2395 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2396 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2397 iep0_ctx[3], iep0_ctx[4]); 2398 2399 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2400 2401 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2402 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2403 2404 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2405 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2406 2407 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2408 } 2409 2410 return CC_SUCCESS; 2411 } 2412 2413 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2414 { 2415 uint32_t slot_ctx[4]; 2416 dma_addr_t octx; 2417 int i; 2418 2419 trace_usb_xhci_slot_reset(slotid); 2420 assert(slotid >= 1 && slotid <= xhci->numslots); 2421 2422 octx = xhci->slots[slotid-1].ctx; 2423 2424 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2425 2426 for (i = 2; i <= 31; i++) { 2427 if (xhci->slots[slotid-1].eps[i-1]) { 2428 xhci_disable_ep(xhci, slotid, i); 2429 } 2430 } 2431 2432 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2433 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2434 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2435 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2436 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2437 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2438 2439 return CC_SUCCESS; 2440 } 2441 2442 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2443 { 2444 unsigned int slotid; 2445 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2446 if (slotid < 1 || slotid > xhci->numslots) { 2447 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2448 event->ccode = CC_TRB_ERROR; 2449 return 0; 2450 } else if (!xhci->slots[slotid-1].enabled) { 2451 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2452 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2453 return 0; 2454 } 2455 return slotid; 2456 } 2457 2458 /* cleanup slot state on usb device detach */ 2459 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2460 { 2461 int slot, ep; 2462 2463 for (slot = 0; slot < xhci->numslots; slot++) { 2464 if (xhci->slots[slot].uport == uport) { 2465 break; 2466 } 2467 } 2468 if (slot == xhci->numslots) { 2469 return; 2470 } 2471 2472 for (ep = 0; ep < 31; ep++) { 2473 if (xhci->slots[slot].eps[ep]) { 2474 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2475 } 2476 } 2477 xhci->slots[slot].uport = NULL; 2478 } 2479 2480 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2481 { 2482 dma_addr_t ctx; 2483 uint8_t bw_ctx[xhci->numports+1]; 2484 2485 DPRINTF("xhci_get_port_bandwidth()\n"); 2486 2487 ctx = xhci_mask64(pctx); 2488 2489 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2490 2491 /* TODO: actually implement real values here */ 2492 bw_ctx[0] = 0; 2493 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2494 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2495 2496 return CC_SUCCESS; 2497 } 2498 2499 static uint32_t rotl(uint32_t v, unsigned count) 2500 { 2501 count &= 31; 2502 return (v << count) | (v >> (32 - count)); 2503 } 2504 2505 2506 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2507 { 2508 uint32_t val; 2509 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2510 val += rotl(lo + 0x49434878, hi & 0x1F); 2511 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2512 return ~val; 2513 } 2514 2515 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2516 { 2517 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2518 uint32_t buf[8]; 2519 uint32_t obuf[8]; 2520 dma_addr_t paddr = xhci_mask64(addr); 2521 2522 pci_dma_read(pci_dev, paddr, &buf, 32); 2523 2524 memcpy(obuf, buf, sizeof(obuf)); 2525 2526 if ((buf[0] & 0xff) == 2) { 2527 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2528 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2529 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2530 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2531 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2532 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2533 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2534 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2535 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2536 } 2537 2538 pci_dma_write(pci_dev, paddr, &obuf, 32); 2539 } 2540 2541 static void xhci_process_commands(XHCIState *xhci) 2542 { 2543 XHCITRB trb; 2544 TRBType type; 2545 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2546 dma_addr_t addr; 2547 unsigned int i, slotid = 0; 2548 2549 DPRINTF("xhci_process_commands()\n"); 2550 if (!xhci_running(xhci)) { 2551 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2552 return; 2553 } 2554 2555 xhci->crcr_low |= CRCR_CRR; 2556 2557 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2558 event.ptr = addr; 2559 switch (type) { 2560 case CR_ENABLE_SLOT: 2561 for (i = 0; i < xhci->numslots; i++) { 2562 if (!xhci->slots[i].enabled) { 2563 break; 2564 } 2565 } 2566 if (i >= xhci->numslots) { 2567 fprintf(stderr, "xhci: no device slots available\n"); 2568 event.ccode = CC_NO_SLOTS_ERROR; 2569 } else { 2570 slotid = i+1; 2571 event.ccode = xhci_enable_slot(xhci, slotid); 2572 } 2573 break; 2574 case CR_DISABLE_SLOT: 2575 slotid = xhci_get_slot(xhci, &event, &trb); 2576 if (slotid) { 2577 event.ccode = xhci_disable_slot(xhci, slotid); 2578 } 2579 break; 2580 case CR_ADDRESS_DEVICE: 2581 slotid = xhci_get_slot(xhci, &event, &trb); 2582 if (slotid) { 2583 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2584 trb.control & TRB_CR_BSR); 2585 } 2586 break; 2587 case CR_CONFIGURE_ENDPOINT: 2588 slotid = xhci_get_slot(xhci, &event, &trb); 2589 if (slotid) { 2590 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2591 trb.control & TRB_CR_DC); 2592 } 2593 break; 2594 case CR_EVALUATE_CONTEXT: 2595 slotid = xhci_get_slot(xhci, &event, &trb); 2596 if (slotid) { 2597 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2598 } 2599 break; 2600 case CR_STOP_ENDPOINT: 2601 slotid = xhci_get_slot(xhci, &event, &trb); 2602 if (slotid) { 2603 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2604 & TRB_CR_EPID_MASK; 2605 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2606 } 2607 break; 2608 case CR_RESET_ENDPOINT: 2609 slotid = xhci_get_slot(xhci, &event, &trb); 2610 if (slotid) { 2611 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2612 & TRB_CR_EPID_MASK; 2613 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2614 } 2615 break; 2616 case CR_SET_TR_DEQUEUE: 2617 slotid = xhci_get_slot(xhci, &event, &trb); 2618 if (slotid) { 2619 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2620 & TRB_CR_EPID_MASK; 2621 unsigned int streamid = (trb.status >> 16) & 0xffff; 2622 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2623 epid, streamid, 2624 trb.parameter); 2625 } 2626 break; 2627 case CR_RESET_DEVICE: 2628 slotid = xhci_get_slot(xhci, &event, &trb); 2629 if (slotid) { 2630 event.ccode = xhci_reset_slot(xhci, slotid); 2631 } 2632 break; 2633 case CR_GET_PORT_BANDWIDTH: 2634 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2635 break; 2636 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2637 xhci_via_challenge(xhci, trb.parameter); 2638 break; 2639 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2640 event.type = 48; /* NEC reply */ 2641 event.length = 0x3025; 2642 break; 2643 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2644 { 2645 uint32_t chi = trb.parameter >> 32; 2646 uint32_t clo = trb.parameter; 2647 uint32_t val = xhci_nec_challenge(chi, clo); 2648 event.length = val & 0xFFFF; 2649 event.epid = val >> 16; 2650 slotid = val >> 24; 2651 event.type = 48; /* NEC reply */ 2652 } 2653 break; 2654 default: 2655 trace_usb_xhci_unimplemented("command", type); 2656 event.ccode = CC_TRB_ERROR; 2657 break; 2658 } 2659 event.slotid = slotid; 2660 xhci_event(xhci, &event, 0); 2661 } 2662 } 2663 2664 static bool xhci_port_have_device(XHCIPort *port) 2665 { 2666 if (!port->uport->dev || !port->uport->dev->attached) { 2667 return false; /* no device present */ 2668 } 2669 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2670 return false; /* speed mismatch */ 2671 } 2672 return true; 2673 } 2674 2675 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2676 { 2677 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2678 port->portnr << 24 }; 2679 2680 if ((port->portsc & bits) == bits) { 2681 return; 2682 } 2683 trace_usb_xhci_port_notify(port->portnr, bits); 2684 port->portsc |= bits; 2685 if (!xhci_running(port->xhci)) { 2686 return; 2687 } 2688 xhci_event(port->xhci, &ev, 0); 2689 } 2690 2691 static void xhci_port_update(XHCIPort *port, int is_detach) 2692 { 2693 uint32_t pls = PLS_RX_DETECT; 2694 2695 port->portsc = PORTSC_PP; 2696 if (!is_detach && xhci_port_have_device(port)) { 2697 port->portsc |= PORTSC_CCS; 2698 switch (port->uport->dev->speed) { 2699 case USB_SPEED_LOW: 2700 port->portsc |= PORTSC_SPEED_LOW; 2701 pls = PLS_POLLING; 2702 break; 2703 case USB_SPEED_FULL: 2704 port->portsc |= PORTSC_SPEED_FULL; 2705 pls = PLS_POLLING; 2706 break; 2707 case USB_SPEED_HIGH: 2708 port->portsc |= PORTSC_SPEED_HIGH; 2709 pls = PLS_POLLING; 2710 break; 2711 case USB_SPEED_SUPER: 2712 port->portsc |= PORTSC_SPEED_SUPER; 2713 port->portsc |= PORTSC_PED; 2714 pls = PLS_U0; 2715 break; 2716 } 2717 } 2718 set_field(&port->portsc, pls, PORTSC_PLS); 2719 trace_usb_xhci_port_link(port->portnr, pls); 2720 xhci_port_notify(port, PORTSC_CSC); 2721 } 2722 2723 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2724 { 2725 trace_usb_xhci_port_reset(port->portnr); 2726 2727 if (!xhci_port_have_device(port)) { 2728 return; 2729 } 2730 2731 usb_device_reset(port->uport->dev); 2732 2733 switch (port->uport->dev->speed) { 2734 case USB_SPEED_SUPER: 2735 if (warm_reset) { 2736 port->portsc |= PORTSC_WRC; 2737 } 2738 /* fall through */ 2739 case USB_SPEED_LOW: 2740 case USB_SPEED_FULL: 2741 case USB_SPEED_HIGH: 2742 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2743 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2744 port->portsc |= PORTSC_PED; 2745 break; 2746 } 2747 2748 port->portsc &= ~PORTSC_PR; 2749 xhci_port_notify(port, PORTSC_PRC); 2750 } 2751 2752 static void xhci_reset(DeviceState *dev) 2753 { 2754 XHCIState *xhci = XHCI(dev); 2755 int i; 2756 2757 trace_usb_xhci_reset(); 2758 if (!(xhci->usbsts & USBSTS_HCH)) { 2759 fprintf(stderr, "xhci: reset while running!\n"); 2760 } 2761 2762 xhci->usbcmd = 0; 2763 xhci->usbsts = USBSTS_HCH; 2764 xhci->dnctrl = 0; 2765 xhci->crcr_low = 0; 2766 xhci->crcr_high = 0; 2767 xhci->dcbaap_low = 0; 2768 xhci->dcbaap_high = 0; 2769 xhci->config = 0; 2770 2771 for (i = 0; i < xhci->numslots; i++) { 2772 xhci_disable_slot(xhci, i+1); 2773 } 2774 2775 for (i = 0; i < xhci->numports; i++) { 2776 xhci_port_update(xhci->ports + i, 0); 2777 } 2778 2779 for (i = 0; i < xhci->numintrs; i++) { 2780 xhci->intr[i].iman = 0; 2781 xhci->intr[i].imod = 0; 2782 xhci->intr[i].erstsz = 0; 2783 xhci->intr[i].erstba_low = 0; 2784 xhci->intr[i].erstba_high = 0; 2785 xhci->intr[i].erdp_low = 0; 2786 xhci->intr[i].erdp_high = 0; 2787 xhci->intr[i].msix_used = 0; 2788 2789 xhci->intr[i].er_ep_idx = 0; 2790 xhci->intr[i].er_pcs = 1; 2791 xhci->intr[i].er_full = 0; 2792 xhci->intr[i].ev_buffer_put = 0; 2793 xhci->intr[i].ev_buffer_get = 0; 2794 } 2795 2796 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2797 xhci_mfwrap_update(xhci); 2798 } 2799 2800 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2801 { 2802 XHCIState *xhci = ptr; 2803 uint32_t ret; 2804 2805 switch (reg) { 2806 case 0x00: /* HCIVERSION, CAPLENGTH */ 2807 ret = 0x01000000 | LEN_CAP; 2808 break; 2809 case 0x04: /* HCSPARAMS 1 */ 2810 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2811 | (xhci->numintrs<<8) | xhci->numslots; 2812 break; 2813 case 0x08: /* HCSPARAMS 2 */ 2814 ret = 0x0000000f; 2815 break; 2816 case 0x0c: /* HCSPARAMS 3 */ 2817 ret = 0x00000000; 2818 break; 2819 case 0x10: /* HCCPARAMS */ 2820 if (sizeof(dma_addr_t) == 4) { 2821 ret = 0x00087000; 2822 } else { 2823 ret = 0x00087001; 2824 } 2825 break; 2826 case 0x14: /* DBOFF */ 2827 ret = OFF_DOORBELL; 2828 break; 2829 case 0x18: /* RTSOFF */ 2830 ret = OFF_RUNTIME; 2831 break; 2832 2833 /* extended capabilities */ 2834 case 0x20: /* Supported Protocol:00 */ 2835 ret = 0x02000402; /* USB 2.0 */ 2836 break; 2837 case 0x24: /* Supported Protocol:04 */ 2838 ret = 0x20425355; /* "USB " */ 2839 break; 2840 case 0x28: /* Supported Protocol:08 */ 2841 ret = 0x00000001 | (xhci->numports_2<<8); 2842 break; 2843 case 0x2c: /* Supported Protocol:0c */ 2844 ret = 0x00000000; /* reserved */ 2845 break; 2846 case 0x30: /* Supported Protocol:00 */ 2847 ret = 0x03000002; /* USB 3.0 */ 2848 break; 2849 case 0x34: /* Supported Protocol:04 */ 2850 ret = 0x20425355; /* "USB " */ 2851 break; 2852 case 0x38: /* Supported Protocol:08 */ 2853 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2854 break; 2855 case 0x3c: /* Supported Protocol:0c */ 2856 ret = 0x00000000; /* reserved */ 2857 break; 2858 default: 2859 trace_usb_xhci_unimplemented("cap read", reg); 2860 ret = 0; 2861 } 2862 2863 trace_usb_xhci_cap_read(reg, ret); 2864 return ret; 2865 } 2866 2867 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2868 { 2869 XHCIPort *port = ptr; 2870 uint32_t ret; 2871 2872 switch (reg) { 2873 case 0x00: /* PORTSC */ 2874 ret = port->portsc; 2875 break; 2876 case 0x04: /* PORTPMSC */ 2877 case 0x08: /* PORTLI */ 2878 ret = 0; 2879 break; 2880 case 0x0c: /* reserved */ 2881 default: 2882 trace_usb_xhci_unimplemented("port read", reg); 2883 ret = 0; 2884 } 2885 2886 trace_usb_xhci_port_read(port->portnr, reg, ret); 2887 return ret; 2888 } 2889 2890 static void xhci_port_write(void *ptr, hwaddr reg, 2891 uint64_t val, unsigned size) 2892 { 2893 XHCIPort *port = ptr; 2894 uint32_t portsc, notify; 2895 2896 trace_usb_xhci_port_write(port->portnr, reg, val); 2897 2898 switch (reg) { 2899 case 0x00: /* PORTSC */ 2900 /* write-1-to-start bits */ 2901 if (val & PORTSC_WPR) { 2902 xhci_port_reset(port, true); 2903 break; 2904 } 2905 if (val & PORTSC_PR) { 2906 xhci_port_reset(port, false); 2907 break; 2908 } 2909 2910 portsc = port->portsc; 2911 notify = 0; 2912 /* write-1-to-clear bits*/ 2913 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2914 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2915 if (val & PORTSC_LWS) { 2916 /* overwrite PLS only when LWS=1 */ 2917 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 2918 uint32_t new_pls = get_field(val, PORTSC_PLS); 2919 switch (new_pls) { 2920 case PLS_U0: 2921 if (old_pls != PLS_U0) { 2922 set_field(&portsc, new_pls, PORTSC_PLS); 2923 trace_usb_xhci_port_link(port->portnr, new_pls); 2924 notify = PORTSC_PLC; 2925 } 2926 break; 2927 case PLS_U3: 2928 if (old_pls < PLS_U3) { 2929 set_field(&portsc, new_pls, PORTSC_PLS); 2930 trace_usb_xhci_port_link(port->portnr, new_pls); 2931 } 2932 break; 2933 case PLS_RESUME: 2934 /* windows does this for some reason, don't spam stderr */ 2935 break; 2936 default: 2937 fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", 2938 __func__, old_pls, new_pls); 2939 break; 2940 } 2941 } 2942 /* read/write bits */ 2943 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2944 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2945 port->portsc = portsc; 2946 if (notify) { 2947 xhci_port_notify(port, notify); 2948 } 2949 break; 2950 case 0x04: /* PORTPMSC */ 2951 case 0x08: /* PORTLI */ 2952 default: 2953 trace_usb_xhci_unimplemented("port write", reg); 2954 } 2955 } 2956 2957 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2958 { 2959 XHCIState *xhci = ptr; 2960 uint32_t ret; 2961 2962 switch (reg) { 2963 case 0x00: /* USBCMD */ 2964 ret = xhci->usbcmd; 2965 break; 2966 case 0x04: /* USBSTS */ 2967 ret = xhci->usbsts; 2968 break; 2969 case 0x08: /* PAGESIZE */ 2970 ret = 1; /* 4KiB */ 2971 break; 2972 case 0x14: /* DNCTRL */ 2973 ret = xhci->dnctrl; 2974 break; 2975 case 0x18: /* CRCR low */ 2976 ret = xhci->crcr_low & ~0xe; 2977 break; 2978 case 0x1c: /* CRCR high */ 2979 ret = xhci->crcr_high; 2980 break; 2981 case 0x30: /* DCBAAP low */ 2982 ret = xhci->dcbaap_low; 2983 break; 2984 case 0x34: /* DCBAAP high */ 2985 ret = xhci->dcbaap_high; 2986 break; 2987 case 0x38: /* CONFIG */ 2988 ret = xhci->config; 2989 break; 2990 default: 2991 trace_usb_xhci_unimplemented("oper read", reg); 2992 ret = 0; 2993 } 2994 2995 trace_usb_xhci_oper_read(reg, ret); 2996 return ret; 2997 } 2998 2999 static void xhci_oper_write(void *ptr, hwaddr reg, 3000 uint64_t val, unsigned size) 3001 { 3002 XHCIState *xhci = ptr; 3003 DeviceState *d = DEVICE(ptr); 3004 3005 trace_usb_xhci_oper_write(reg, val); 3006 3007 switch (reg) { 3008 case 0x00: /* USBCMD */ 3009 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3010 xhci_run(xhci); 3011 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3012 xhci_stop(xhci); 3013 } 3014 xhci->usbcmd = val & 0xc0f; 3015 xhci_mfwrap_update(xhci); 3016 if (val & USBCMD_HCRST) { 3017 xhci_reset(d); 3018 } 3019 xhci_intx_update(xhci); 3020 break; 3021 3022 case 0x04: /* USBSTS */ 3023 /* these bits are write-1-to-clear */ 3024 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3025 xhci_intx_update(xhci); 3026 break; 3027 3028 case 0x14: /* DNCTRL */ 3029 xhci->dnctrl = val & 0xffff; 3030 break; 3031 case 0x18: /* CRCR low */ 3032 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3033 break; 3034 case 0x1c: /* CRCR high */ 3035 xhci->crcr_high = val; 3036 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3037 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3038 xhci->crcr_low &= ~CRCR_CRR; 3039 xhci_event(xhci, &event, 0); 3040 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3041 } else { 3042 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3043 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3044 } 3045 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3046 break; 3047 case 0x30: /* DCBAAP low */ 3048 xhci->dcbaap_low = val & 0xffffffc0; 3049 break; 3050 case 0x34: /* DCBAAP high */ 3051 xhci->dcbaap_high = val; 3052 break; 3053 case 0x38: /* CONFIG */ 3054 xhci->config = val & 0xff; 3055 break; 3056 default: 3057 trace_usb_xhci_unimplemented("oper write", reg); 3058 } 3059 } 3060 3061 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3062 unsigned size) 3063 { 3064 XHCIState *xhci = ptr; 3065 uint32_t ret = 0; 3066 3067 if (reg < 0x20) { 3068 switch (reg) { 3069 case 0x00: /* MFINDEX */ 3070 ret = xhci_mfindex_get(xhci) & 0x3fff; 3071 break; 3072 default: 3073 trace_usb_xhci_unimplemented("runtime read", reg); 3074 break; 3075 } 3076 } else { 3077 int v = (reg - 0x20) / 0x20; 3078 XHCIInterrupter *intr = &xhci->intr[v]; 3079 switch (reg & 0x1f) { 3080 case 0x00: /* IMAN */ 3081 ret = intr->iman; 3082 break; 3083 case 0x04: /* IMOD */ 3084 ret = intr->imod; 3085 break; 3086 case 0x08: /* ERSTSZ */ 3087 ret = intr->erstsz; 3088 break; 3089 case 0x10: /* ERSTBA low */ 3090 ret = intr->erstba_low; 3091 break; 3092 case 0x14: /* ERSTBA high */ 3093 ret = intr->erstba_high; 3094 break; 3095 case 0x18: /* ERDP low */ 3096 ret = intr->erdp_low; 3097 break; 3098 case 0x1c: /* ERDP high */ 3099 ret = intr->erdp_high; 3100 break; 3101 } 3102 } 3103 3104 trace_usb_xhci_runtime_read(reg, ret); 3105 return ret; 3106 } 3107 3108 static void xhci_runtime_write(void *ptr, hwaddr reg, 3109 uint64_t val, unsigned size) 3110 { 3111 XHCIState *xhci = ptr; 3112 int v = (reg - 0x20) / 0x20; 3113 XHCIInterrupter *intr = &xhci->intr[v]; 3114 trace_usb_xhci_runtime_write(reg, val); 3115 3116 if (reg < 0x20) { 3117 trace_usb_xhci_unimplemented("runtime write", reg); 3118 return; 3119 } 3120 3121 switch (reg & 0x1f) { 3122 case 0x00: /* IMAN */ 3123 if (val & IMAN_IP) { 3124 intr->iman &= ~IMAN_IP; 3125 } 3126 intr->iman &= ~IMAN_IE; 3127 intr->iman |= val & IMAN_IE; 3128 if (v == 0) { 3129 xhci_intx_update(xhci); 3130 } 3131 xhci_msix_update(xhci, v); 3132 break; 3133 case 0x04: /* IMOD */ 3134 intr->imod = val; 3135 break; 3136 case 0x08: /* ERSTSZ */ 3137 intr->erstsz = val & 0xffff; 3138 break; 3139 case 0x10: /* ERSTBA low */ 3140 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3141 intr->erstba_low = val & 0xffffffc0; */ 3142 intr->erstba_low = val & 0xfffffff0; 3143 break; 3144 case 0x14: /* ERSTBA high */ 3145 intr->erstba_high = val; 3146 xhci_er_reset(xhci, v); 3147 break; 3148 case 0x18: /* ERDP low */ 3149 if (val & ERDP_EHB) { 3150 intr->erdp_low &= ~ERDP_EHB; 3151 } 3152 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3153 break; 3154 case 0x1c: /* ERDP high */ 3155 intr->erdp_high = val; 3156 xhci_events_update(xhci, v); 3157 break; 3158 default: 3159 trace_usb_xhci_unimplemented("oper write", reg); 3160 } 3161 } 3162 3163 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3164 unsigned size) 3165 { 3166 /* doorbells always read as 0 */ 3167 trace_usb_xhci_doorbell_read(reg, 0); 3168 return 0; 3169 } 3170 3171 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3172 uint64_t val, unsigned size) 3173 { 3174 XHCIState *xhci = ptr; 3175 unsigned int epid, streamid; 3176 3177 trace_usb_xhci_doorbell_write(reg, val); 3178 3179 if (!xhci_running(xhci)) { 3180 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 3181 return; 3182 } 3183 3184 reg >>= 2; 3185 3186 if (reg == 0) { 3187 if (val == 0) { 3188 xhci_process_commands(xhci); 3189 } else { 3190 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 3191 (uint32_t)val); 3192 } 3193 } else { 3194 epid = val & 0xff; 3195 streamid = (val >> 16) & 0xffff; 3196 if (reg > xhci->numslots) { 3197 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 3198 } else if (epid > 31) { 3199 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 3200 (int)reg, (uint32_t)val); 3201 } else { 3202 xhci_kick_ep(xhci, reg, epid, streamid); 3203 } 3204 } 3205 } 3206 3207 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3208 unsigned width) 3209 { 3210 /* nothing */ 3211 } 3212 3213 static const MemoryRegionOps xhci_cap_ops = { 3214 .read = xhci_cap_read, 3215 .write = xhci_cap_write, 3216 .valid.min_access_size = 1, 3217 .valid.max_access_size = 4, 3218 .impl.min_access_size = 4, 3219 .impl.max_access_size = 4, 3220 .endianness = DEVICE_LITTLE_ENDIAN, 3221 }; 3222 3223 static const MemoryRegionOps xhci_oper_ops = { 3224 .read = xhci_oper_read, 3225 .write = xhci_oper_write, 3226 .valid.min_access_size = 4, 3227 .valid.max_access_size = 4, 3228 .endianness = DEVICE_LITTLE_ENDIAN, 3229 }; 3230 3231 static const MemoryRegionOps xhci_port_ops = { 3232 .read = xhci_port_read, 3233 .write = xhci_port_write, 3234 .valid.min_access_size = 4, 3235 .valid.max_access_size = 4, 3236 .endianness = DEVICE_LITTLE_ENDIAN, 3237 }; 3238 3239 static const MemoryRegionOps xhci_runtime_ops = { 3240 .read = xhci_runtime_read, 3241 .write = xhci_runtime_write, 3242 .valid.min_access_size = 4, 3243 .valid.max_access_size = 4, 3244 .endianness = DEVICE_LITTLE_ENDIAN, 3245 }; 3246 3247 static const MemoryRegionOps xhci_doorbell_ops = { 3248 .read = xhci_doorbell_read, 3249 .write = xhci_doorbell_write, 3250 .valid.min_access_size = 4, 3251 .valid.max_access_size = 4, 3252 .endianness = DEVICE_LITTLE_ENDIAN, 3253 }; 3254 3255 static void xhci_attach(USBPort *usbport) 3256 { 3257 XHCIState *xhci = usbport->opaque; 3258 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3259 3260 xhci_port_update(port, 0); 3261 } 3262 3263 static void xhci_detach(USBPort *usbport) 3264 { 3265 XHCIState *xhci = usbport->opaque; 3266 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3267 3268 xhci_detach_slot(xhci, usbport); 3269 xhci_port_update(port, 1); 3270 } 3271 3272 static void xhci_wakeup(USBPort *usbport) 3273 { 3274 XHCIState *xhci = usbport->opaque; 3275 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3276 3277 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3278 return; 3279 } 3280 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3281 xhci_port_notify(port, PORTSC_PLC); 3282 } 3283 3284 static void xhci_complete(USBPort *port, USBPacket *packet) 3285 { 3286 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3287 3288 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3289 xhci_ep_nuke_one_xfer(xfer, 0); 3290 return; 3291 } 3292 xhci_complete_packet(xfer); 3293 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3294 } 3295 3296 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3297 { 3298 USBBus *bus = usb_bus_from_device(child); 3299 XHCIState *xhci = container_of(bus, XHCIState, bus); 3300 3301 xhci_detach_slot(xhci, uport); 3302 } 3303 3304 static USBPortOps xhci_uport_ops = { 3305 .attach = xhci_attach, 3306 .detach = xhci_detach, 3307 .wakeup = xhci_wakeup, 3308 .complete = xhci_complete, 3309 .child_detach = xhci_child_detach, 3310 }; 3311 3312 static int xhci_find_epid(USBEndpoint *ep) 3313 { 3314 if (ep->nr == 0) { 3315 return 1; 3316 } 3317 if (ep->pid == USB_TOKEN_IN) { 3318 return ep->nr * 2 + 1; 3319 } else { 3320 return ep->nr * 2; 3321 } 3322 } 3323 3324 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 3325 unsigned int slotid, unsigned int epid) 3326 { 3327 assert(slotid >= 1 && slotid <= xhci->numslots); 3328 3329 if (!xhci->slots[slotid - 1].uport) { 3330 return NULL; 3331 } 3332 3333 return usb_ep_get(xhci->slots[slotid - 1].uport->dev, 3334 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); 3335 } 3336 3337 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3338 unsigned int stream) 3339 { 3340 XHCIState *xhci = container_of(bus, XHCIState, bus); 3341 int slotid; 3342 3343 DPRINTF("%s\n", __func__); 3344 slotid = ep->dev->addr; 3345 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3346 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3347 return; 3348 } 3349 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3350 } 3351 3352 static USBBusOps xhci_bus_ops = { 3353 .wakeup_endpoint = xhci_wakeup_endpoint, 3354 }; 3355 3356 static void usb_xhci_init(XHCIState *xhci) 3357 { 3358 DeviceState *dev = DEVICE(xhci); 3359 XHCIPort *port; 3360 int i, usbports, speedmask; 3361 3362 xhci->usbsts = USBSTS_HCH; 3363 3364 if (xhci->numports_2 > MAXPORTS_2) { 3365 xhci->numports_2 = MAXPORTS_2; 3366 } 3367 if (xhci->numports_3 > MAXPORTS_3) { 3368 xhci->numports_3 = MAXPORTS_3; 3369 } 3370 usbports = MAX(xhci->numports_2, xhci->numports_3); 3371 xhci->numports = xhci->numports_2 + xhci->numports_3; 3372 3373 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3374 3375 for (i = 0; i < usbports; i++) { 3376 speedmask = 0; 3377 if (i < xhci->numports_2) { 3378 port = &xhci->ports[i]; 3379 port->portnr = i + 1; 3380 port->uport = &xhci->uports[i]; 3381 port->speedmask = 3382 USB_SPEED_MASK_LOW | 3383 USB_SPEED_MASK_FULL | 3384 USB_SPEED_MASK_HIGH; 3385 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3386 speedmask |= port->speedmask; 3387 } 3388 if (i < xhci->numports_3) { 3389 port = &xhci->ports[i + xhci->numports_2]; 3390 port->portnr = i + 1 + xhci->numports_2; 3391 port->uport = &xhci->uports[i]; 3392 port->speedmask = USB_SPEED_MASK_SUPER; 3393 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3394 speedmask |= port->speedmask; 3395 } 3396 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3397 &xhci_uport_ops, speedmask); 3398 } 3399 } 3400 3401 static int usb_xhci_initfn(struct PCIDevice *dev) 3402 { 3403 int i, ret; 3404 3405 XHCIState *xhci = XHCI(dev); 3406 3407 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3408 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3409 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3410 dev->config[0x60] = 0x30; /* release number */ 3411 3412 usb_xhci_init(xhci); 3413 3414 if (xhci->numintrs > MAXINTRS) { 3415 xhci->numintrs = MAXINTRS; 3416 } 3417 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3418 xhci->numintrs++; 3419 } 3420 if (xhci->numintrs < 1) { 3421 xhci->numintrs = 1; 3422 } 3423 if (xhci->numslots > MAXSLOTS) { 3424 xhci->numslots = MAXSLOTS; 3425 } 3426 if (xhci->numslots < 1) { 3427 xhci->numslots = 1; 3428 } 3429 3430 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3431 3432 xhci->irq = dev->irq[0]; 3433 3434 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3435 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3436 "capabilities", LEN_CAP); 3437 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3438 "operational", 0x400); 3439 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3440 "runtime", LEN_RUNTIME); 3441 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3442 "doorbell", LEN_DOORBELL); 3443 3444 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3445 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3446 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3447 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3448 3449 for (i = 0; i < xhci->numports; i++) { 3450 XHCIPort *port = &xhci->ports[i]; 3451 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3452 port->xhci = xhci; 3453 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3454 port->name, 0x10); 3455 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3456 } 3457 3458 pci_register_bar(dev, 0, 3459 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3460 &xhci->mem); 3461 3462 ret = pcie_endpoint_cap_init(dev, 0xa0); 3463 assert(ret >= 0); 3464 3465 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3466 msi_init(dev, 0x70, xhci->numintrs, true, false); 3467 } 3468 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3469 msix_init(dev, xhci->numintrs, 3470 &xhci->mem, 0, OFF_MSIX_TABLE, 3471 &xhci->mem, 0, OFF_MSIX_PBA, 3472 0x90); 3473 } 3474 3475 return 0; 3476 } 3477 3478 static int usb_xhci_post_load(void *opaque, int version_id) 3479 { 3480 XHCIState *xhci = opaque; 3481 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3482 XHCISlot *slot; 3483 XHCIEPContext *epctx; 3484 dma_addr_t dcbaap, pctx; 3485 uint32_t slot_ctx[4]; 3486 uint32_t ep_ctx[5]; 3487 int slotid, epid, state, intr; 3488 3489 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3490 3491 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3492 slot = &xhci->slots[slotid-1]; 3493 if (!slot->addressed) { 3494 continue; 3495 } 3496 slot->ctx = 3497 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3498 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3499 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3500 assert(slot->uport && slot->uport->dev); 3501 3502 for (epid = 1; epid <= 32; epid++) { 3503 pctx = slot->ctx + 32 * epid; 3504 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3505 state = ep_ctx[0] & EP_STATE_MASK; 3506 if (state == EP_DISABLED) { 3507 continue; 3508 } 3509 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3510 slot->eps[epid-1] = epctx; 3511 xhci_init_epctx(epctx, pctx, ep_ctx); 3512 epctx->state = state; 3513 if (state == EP_RUNNING) { 3514 /* kick endpoint after vmload is finished */ 3515 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3516 } 3517 } 3518 } 3519 3520 for (intr = 0; intr < xhci->numintrs; intr++) { 3521 if (xhci->intr[intr].msix_used) { 3522 msix_vector_use(pci_dev, intr); 3523 } else { 3524 msix_vector_unuse(pci_dev, intr); 3525 } 3526 } 3527 3528 return 0; 3529 } 3530 3531 static const VMStateDescription vmstate_xhci_ring = { 3532 .name = "xhci-ring", 3533 .version_id = 1, 3534 .fields = (VMStateField[]) { 3535 VMSTATE_UINT64(dequeue, XHCIRing), 3536 VMSTATE_BOOL(ccs, XHCIRing), 3537 VMSTATE_END_OF_LIST() 3538 } 3539 }; 3540 3541 static const VMStateDescription vmstate_xhci_port = { 3542 .name = "xhci-port", 3543 .version_id = 1, 3544 .fields = (VMStateField[]) { 3545 VMSTATE_UINT32(portsc, XHCIPort), 3546 VMSTATE_END_OF_LIST() 3547 } 3548 }; 3549 3550 static const VMStateDescription vmstate_xhci_slot = { 3551 .name = "xhci-slot", 3552 .version_id = 1, 3553 .fields = (VMStateField[]) { 3554 VMSTATE_BOOL(enabled, XHCISlot), 3555 VMSTATE_BOOL(addressed, XHCISlot), 3556 VMSTATE_END_OF_LIST() 3557 } 3558 }; 3559 3560 static const VMStateDescription vmstate_xhci_event = { 3561 .name = "xhci-event", 3562 .version_id = 1, 3563 .fields = (VMStateField[]) { 3564 VMSTATE_UINT32(type, XHCIEvent), 3565 VMSTATE_UINT32(ccode, XHCIEvent), 3566 VMSTATE_UINT64(ptr, XHCIEvent), 3567 VMSTATE_UINT32(length, XHCIEvent), 3568 VMSTATE_UINT32(flags, XHCIEvent), 3569 VMSTATE_UINT8(slotid, XHCIEvent), 3570 VMSTATE_UINT8(epid, XHCIEvent), 3571 } 3572 }; 3573 3574 static bool xhci_er_full(void *opaque, int version_id) 3575 { 3576 struct XHCIInterrupter *intr = opaque; 3577 return intr->er_full; 3578 } 3579 3580 static const VMStateDescription vmstate_xhci_intr = { 3581 .name = "xhci-intr", 3582 .version_id = 1, 3583 .fields = (VMStateField[]) { 3584 /* registers */ 3585 VMSTATE_UINT32(iman, XHCIInterrupter), 3586 VMSTATE_UINT32(imod, XHCIInterrupter), 3587 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3588 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3589 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3590 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3591 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3592 3593 /* state */ 3594 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3595 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3596 VMSTATE_UINT64(er_start, XHCIInterrupter), 3597 VMSTATE_UINT32(er_size, XHCIInterrupter), 3598 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3599 3600 /* event queue (used if ring is full) */ 3601 VMSTATE_BOOL(er_full, XHCIInterrupter), 3602 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3603 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3604 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3605 xhci_er_full, 1, 3606 vmstate_xhci_event, XHCIEvent), 3607 3608 VMSTATE_END_OF_LIST() 3609 } 3610 }; 3611 3612 static const VMStateDescription vmstate_xhci = { 3613 .name = "xhci", 3614 .version_id = 1, 3615 .post_load = usb_xhci_post_load, 3616 .fields = (VMStateField[]) { 3617 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3618 VMSTATE_MSIX(parent_obj, XHCIState), 3619 3620 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3621 vmstate_xhci_port, XHCIPort), 3622 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3623 vmstate_xhci_slot, XHCISlot), 3624 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3625 vmstate_xhci_intr, XHCIInterrupter), 3626 3627 /* Operational Registers */ 3628 VMSTATE_UINT32(usbcmd, XHCIState), 3629 VMSTATE_UINT32(usbsts, XHCIState), 3630 VMSTATE_UINT32(dnctrl, XHCIState), 3631 VMSTATE_UINT32(crcr_low, XHCIState), 3632 VMSTATE_UINT32(crcr_high, XHCIState), 3633 VMSTATE_UINT32(dcbaap_low, XHCIState), 3634 VMSTATE_UINT32(dcbaap_high, XHCIState), 3635 VMSTATE_UINT32(config, XHCIState), 3636 3637 /* Runtime Registers & state */ 3638 VMSTATE_INT64(mfindex_start, XHCIState), 3639 VMSTATE_TIMER(mfwrap_timer, XHCIState), 3640 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3641 3642 VMSTATE_END_OF_LIST() 3643 } 3644 }; 3645 3646 static Property xhci_properties[] = { 3647 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3648 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3649 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3650 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3651 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3652 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3653 DEFINE_PROP_END_OF_LIST(), 3654 }; 3655 3656 static void xhci_class_init(ObjectClass *klass, void *data) 3657 { 3658 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3659 DeviceClass *dc = DEVICE_CLASS(klass); 3660 3661 dc->vmsd = &vmstate_xhci; 3662 dc->props = xhci_properties; 3663 dc->reset = xhci_reset; 3664 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3665 k->init = usb_xhci_initfn; 3666 k->vendor_id = PCI_VENDOR_ID_NEC; 3667 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3668 k->class_id = PCI_CLASS_SERIAL_USB; 3669 k->revision = 0x03; 3670 k->is_express = 1; 3671 k->no_hotplug = 1; 3672 } 3673 3674 static const TypeInfo xhci_info = { 3675 .name = TYPE_XHCI, 3676 .parent = TYPE_PCI_DEVICE, 3677 .instance_size = sizeof(XHCIState), 3678 .class_init = xhci_class_init, 3679 }; 3680 3681 static void xhci_register_types(void) 3682 { 3683 type_register_static(&xhci_info); 3684 } 3685 3686 type_init(xhci_register_types) 3687