1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "hw/usb.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/msi.h" 27 #include "hw/pci/msix.h" 28 #include "trace.h" 29 #include "qapi/error.h" 30 31 //#define DEBUG_XHCI 32 //#define DEBUG_DATA 33 34 #ifdef DEBUG_XHCI 35 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 36 #else 37 #define DPRINTF(...) do {} while (0) 38 #endif 39 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 40 __func__, __LINE__, _msg); abort(); } while (0) 41 42 #define MAXPORTS_2 15 43 #define MAXPORTS_3 15 44 45 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 46 #define MAXSLOTS 64 47 #define MAXINTRS 16 48 49 #define TD_QUEUE 24 50 51 /* Very pessimistic, let's hope it's enough for all cases */ 52 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 53 /* Do not deliver ER Full events. NEC's driver does some things not bound 54 * to the specs when it gets them */ 55 #define ER_FULL_HACK 56 57 #define LEN_CAP 0x40 58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 59 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 60 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 61 62 #define OFF_OPER LEN_CAP 63 #define OFF_RUNTIME 0x1000 64 #define OFF_DOORBELL 0x2000 65 #define OFF_MSIX_TABLE 0x3000 66 #define OFF_MSIX_PBA 0x3800 67 /* must be power of 2 */ 68 #define LEN_REGS 0x4000 69 70 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 71 #error Increase OFF_RUNTIME 72 #endif 73 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 74 #error Increase OFF_DOORBELL 75 #endif 76 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 77 # error Increase LEN_REGS 78 #endif 79 80 /* bit definitions */ 81 #define USBCMD_RS (1<<0) 82 #define USBCMD_HCRST (1<<1) 83 #define USBCMD_INTE (1<<2) 84 #define USBCMD_HSEE (1<<3) 85 #define USBCMD_LHCRST (1<<7) 86 #define USBCMD_CSS (1<<8) 87 #define USBCMD_CRS (1<<9) 88 #define USBCMD_EWE (1<<10) 89 #define USBCMD_EU3S (1<<11) 90 91 #define USBSTS_HCH (1<<0) 92 #define USBSTS_HSE (1<<2) 93 #define USBSTS_EINT (1<<3) 94 #define USBSTS_PCD (1<<4) 95 #define USBSTS_SSS (1<<8) 96 #define USBSTS_RSS (1<<9) 97 #define USBSTS_SRE (1<<10) 98 #define USBSTS_CNR (1<<11) 99 #define USBSTS_HCE (1<<12) 100 101 102 #define PORTSC_CCS (1<<0) 103 #define PORTSC_PED (1<<1) 104 #define PORTSC_OCA (1<<3) 105 #define PORTSC_PR (1<<4) 106 #define PORTSC_PLS_SHIFT 5 107 #define PORTSC_PLS_MASK 0xf 108 #define PORTSC_PP (1<<9) 109 #define PORTSC_SPEED_SHIFT 10 110 #define PORTSC_SPEED_MASK 0xf 111 #define PORTSC_SPEED_FULL (1<<10) 112 #define PORTSC_SPEED_LOW (2<<10) 113 #define PORTSC_SPEED_HIGH (3<<10) 114 #define PORTSC_SPEED_SUPER (4<<10) 115 #define PORTSC_PIC_SHIFT 14 116 #define PORTSC_PIC_MASK 0x3 117 #define PORTSC_LWS (1<<16) 118 #define PORTSC_CSC (1<<17) 119 #define PORTSC_PEC (1<<18) 120 #define PORTSC_WRC (1<<19) 121 #define PORTSC_OCC (1<<20) 122 #define PORTSC_PRC (1<<21) 123 #define PORTSC_PLC (1<<22) 124 #define PORTSC_CEC (1<<23) 125 #define PORTSC_CAS (1<<24) 126 #define PORTSC_WCE (1<<25) 127 #define PORTSC_WDE (1<<26) 128 #define PORTSC_WOE (1<<27) 129 #define PORTSC_DR (1<<30) 130 #define PORTSC_WPR (1<<31) 131 132 #define CRCR_RCS (1<<0) 133 #define CRCR_CS (1<<1) 134 #define CRCR_CA (1<<2) 135 #define CRCR_CRR (1<<3) 136 137 #define IMAN_IP (1<<0) 138 #define IMAN_IE (1<<1) 139 140 #define ERDP_EHB (1<<3) 141 142 #define TRB_SIZE 16 143 typedef struct XHCITRB { 144 uint64_t parameter; 145 uint32_t status; 146 uint32_t control; 147 dma_addr_t addr; 148 bool ccs; 149 } XHCITRB; 150 151 enum { 152 PLS_U0 = 0, 153 PLS_U1 = 1, 154 PLS_U2 = 2, 155 PLS_U3 = 3, 156 PLS_DISABLED = 4, 157 PLS_RX_DETECT = 5, 158 PLS_INACTIVE = 6, 159 PLS_POLLING = 7, 160 PLS_RECOVERY = 8, 161 PLS_HOT_RESET = 9, 162 PLS_COMPILANCE_MODE = 10, 163 PLS_TEST_MODE = 11, 164 PLS_RESUME = 15, 165 }; 166 167 typedef enum TRBType { 168 TRB_RESERVED = 0, 169 TR_NORMAL, 170 TR_SETUP, 171 TR_DATA, 172 TR_STATUS, 173 TR_ISOCH, 174 TR_LINK, 175 TR_EVDATA, 176 TR_NOOP, 177 CR_ENABLE_SLOT, 178 CR_DISABLE_SLOT, 179 CR_ADDRESS_DEVICE, 180 CR_CONFIGURE_ENDPOINT, 181 CR_EVALUATE_CONTEXT, 182 CR_RESET_ENDPOINT, 183 CR_STOP_ENDPOINT, 184 CR_SET_TR_DEQUEUE, 185 CR_RESET_DEVICE, 186 CR_FORCE_EVENT, 187 CR_NEGOTIATE_BW, 188 CR_SET_LATENCY_TOLERANCE, 189 CR_GET_PORT_BANDWIDTH, 190 CR_FORCE_HEADER, 191 CR_NOOP, 192 ER_TRANSFER = 32, 193 ER_COMMAND_COMPLETE, 194 ER_PORT_STATUS_CHANGE, 195 ER_BANDWIDTH_REQUEST, 196 ER_DOORBELL, 197 ER_HOST_CONTROLLER, 198 ER_DEVICE_NOTIFICATION, 199 ER_MFINDEX_WRAP, 200 /* vendor specific bits */ 201 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 202 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 203 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 204 } TRBType; 205 206 #define CR_LINK TR_LINK 207 208 typedef enum TRBCCode { 209 CC_INVALID = 0, 210 CC_SUCCESS, 211 CC_DATA_BUFFER_ERROR, 212 CC_BABBLE_DETECTED, 213 CC_USB_TRANSACTION_ERROR, 214 CC_TRB_ERROR, 215 CC_STALL_ERROR, 216 CC_RESOURCE_ERROR, 217 CC_BANDWIDTH_ERROR, 218 CC_NO_SLOTS_ERROR, 219 CC_INVALID_STREAM_TYPE_ERROR, 220 CC_SLOT_NOT_ENABLED_ERROR, 221 CC_EP_NOT_ENABLED_ERROR, 222 CC_SHORT_PACKET, 223 CC_RING_UNDERRUN, 224 CC_RING_OVERRUN, 225 CC_VF_ER_FULL, 226 CC_PARAMETER_ERROR, 227 CC_BANDWIDTH_OVERRUN, 228 CC_CONTEXT_STATE_ERROR, 229 CC_NO_PING_RESPONSE_ERROR, 230 CC_EVENT_RING_FULL_ERROR, 231 CC_INCOMPATIBLE_DEVICE_ERROR, 232 CC_MISSED_SERVICE_ERROR, 233 CC_COMMAND_RING_STOPPED, 234 CC_COMMAND_ABORTED, 235 CC_STOPPED, 236 CC_STOPPED_LENGTH_INVALID, 237 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 238 CC_ISOCH_BUFFER_OVERRUN = 31, 239 CC_EVENT_LOST_ERROR, 240 CC_UNDEFINED_ERROR, 241 CC_INVALID_STREAM_ID_ERROR, 242 CC_SECONDARY_BANDWIDTH_ERROR, 243 CC_SPLIT_TRANSACTION_ERROR 244 } TRBCCode; 245 246 #define TRB_C (1<<0) 247 #define TRB_TYPE_SHIFT 10 248 #define TRB_TYPE_MASK 0x3f 249 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 250 251 #define TRB_EV_ED (1<<2) 252 253 #define TRB_TR_ENT (1<<1) 254 #define TRB_TR_ISP (1<<2) 255 #define TRB_TR_NS (1<<3) 256 #define TRB_TR_CH (1<<4) 257 #define TRB_TR_IOC (1<<5) 258 #define TRB_TR_IDT (1<<6) 259 #define TRB_TR_TBC_SHIFT 7 260 #define TRB_TR_TBC_MASK 0x3 261 #define TRB_TR_BEI (1<<9) 262 #define TRB_TR_TLBPC_SHIFT 16 263 #define TRB_TR_TLBPC_MASK 0xf 264 #define TRB_TR_FRAMEID_SHIFT 20 265 #define TRB_TR_FRAMEID_MASK 0x7ff 266 #define TRB_TR_SIA (1<<31) 267 268 #define TRB_TR_DIR (1<<16) 269 270 #define TRB_CR_SLOTID_SHIFT 24 271 #define TRB_CR_SLOTID_MASK 0xff 272 #define TRB_CR_EPID_SHIFT 16 273 #define TRB_CR_EPID_MASK 0x1f 274 275 #define TRB_CR_BSR (1<<9) 276 #define TRB_CR_DC (1<<9) 277 278 #define TRB_LK_TC (1<<1) 279 280 #define TRB_INTR_SHIFT 22 281 #define TRB_INTR_MASK 0x3ff 282 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 283 284 #define EP_TYPE_MASK 0x7 285 #define EP_TYPE_SHIFT 3 286 287 #define EP_STATE_MASK 0x7 288 #define EP_DISABLED (0<<0) 289 #define EP_RUNNING (1<<0) 290 #define EP_HALTED (2<<0) 291 #define EP_STOPPED (3<<0) 292 #define EP_ERROR (4<<0) 293 294 #define SLOT_STATE_MASK 0x1f 295 #define SLOT_STATE_SHIFT 27 296 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 297 #define SLOT_ENABLED 0 298 #define SLOT_DEFAULT 1 299 #define SLOT_ADDRESSED 2 300 #define SLOT_CONFIGURED 3 301 302 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 303 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 304 305 typedef struct XHCIState XHCIState; 306 typedef struct XHCIStreamContext XHCIStreamContext; 307 typedef struct XHCIEPContext XHCIEPContext; 308 309 #define get_field(data, field) \ 310 (((data) >> field##_SHIFT) & field##_MASK) 311 312 #define set_field(data, newval, field) do { \ 313 uint32_t val = *data; \ 314 val &= ~(field##_MASK << field##_SHIFT); \ 315 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 316 *data = val; \ 317 } while (0) 318 319 typedef enum EPType { 320 ET_INVALID = 0, 321 ET_ISO_OUT, 322 ET_BULK_OUT, 323 ET_INTR_OUT, 324 ET_CONTROL, 325 ET_ISO_IN, 326 ET_BULK_IN, 327 ET_INTR_IN, 328 } EPType; 329 330 typedef struct XHCIRing { 331 dma_addr_t dequeue; 332 bool ccs; 333 } XHCIRing; 334 335 typedef struct XHCIPort { 336 XHCIState *xhci; 337 uint32_t portsc; 338 uint32_t portnr; 339 USBPort *uport; 340 uint32_t speedmask; 341 char name[16]; 342 MemoryRegion mem; 343 } XHCIPort; 344 345 typedef struct XHCITransfer { 346 XHCIState *xhci; 347 USBPacket packet; 348 QEMUSGList sgl; 349 bool running_async; 350 bool running_retry; 351 bool complete; 352 bool int_req; 353 unsigned int iso_pkts; 354 unsigned int slotid; 355 unsigned int epid; 356 unsigned int streamid; 357 bool in_xfer; 358 bool iso_xfer; 359 bool timed_xfer; 360 361 unsigned int trb_count; 362 unsigned int trb_alloced; 363 XHCITRB *trbs; 364 365 TRBCCode status; 366 367 unsigned int pkts; 368 unsigned int pktsize; 369 unsigned int cur_pkt; 370 371 uint64_t mfindex_kick; 372 } XHCITransfer; 373 374 struct XHCIStreamContext { 375 dma_addr_t pctx; 376 unsigned int sct; 377 XHCIRing ring; 378 }; 379 380 struct XHCIEPContext { 381 XHCIState *xhci; 382 unsigned int slotid; 383 unsigned int epid; 384 385 XHCIRing ring; 386 unsigned int next_xfer; 387 unsigned int comp_xfer; 388 XHCITransfer transfers[TD_QUEUE]; 389 XHCITransfer *retry; 390 EPType type; 391 dma_addr_t pctx; 392 unsigned int max_psize; 393 uint32_t state; 394 395 /* streams */ 396 unsigned int max_pstreams; 397 bool lsa; 398 unsigned int nr_pstreams; 399 XHCIStreamContext *pstreams; 400 401 /* iso xfer scheduling */ 402 unsigned int interval; 403 int64_t mfindex_last; 404 QEMUTimer *kick_timer; 405 }; 406 407 typedef struct XHCISlot { 408 bool enabled; 409 bool addressed; 410 dma_addr_t ctx; 411 USBPort *uport; 412 XHCIEPContext * eps[31]; 413 } XHCISlot; 414 415 typedef struct XHCIEvent { 416 TRBType type; 417 TRBCCode ccode; 418 uint64_t ptr; 419 uint32_t length; 420 uint32_t flags; 421 uint8_t slotid; 422 uint8_t epid; 423 } XHCIEvent; 424 425 typedef struct XHCIInterrupter { 426 uint32_t iman; 427 uint32_t imod; 428 uint32_t erstsz; 429 uint32_t erstba_low; 430 uint32_t erstba_high; 431 uint32_t erdp_low; 432 uint32_t erdp_high; 433 434 bool msix_used, er_pcs, er_full; 435 436 dma_addr_t er_start; 437 uint32_t er_size; 438 unsigned int er_ep_idx; 439 440 XHCIEvent ev_buffer[EV_QUEUE]; 441 unsigned int ev_buffer_put; 442 unsigned int ev_buffer_get; 443 444 } XHCIInterrupter; 445 446 struct XHCIState { 447 /*< private >*/ 448 PCIDevice parent_obj; 449 /*< public >*/ 450 451 USBBus bus; 452 MemoryRegion mem; 453 MemoryRegion mem_cap; 454 MemoryRegion mem_oper; 455 MemoryRegion mem_runtime; 456 MemoryRegion mem_doorbell; 457 458 /* properties */ 459 uint32_t numports_2; 460 uint32_t numports_3; 461 uint32_t numintrs; 462 uint32_t numslots; 463 uint32_t flags; 464 uint32_t max_pstreams_mask; 465 OnOffAuto msi; 466 OnOffAuto msix; 467 468 /* Operational Registers */ 469 uint32_t usbcmd; 470 uint32_t usbsts; 471 uint32_t dnctrl; 472 uint32_t crcr_low; 473 uint32_t crcr_high; 474 uint32_t dcbaap_low; 475 uint32_t dcbaap_high; 476 uint32_t config; 477 478 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 479 XHCIPort ports[MAXPORTS]; 480 XHCISlot slots[MAXSLOTS]; 481 uint32_t numports; 482 483 /* Runtime Registers */ 484 int64_t mfindex_start; 485 QEMUTimer *mfwrap_timer; 486 XHCIInterrupter intr[MAXINTRS]; 487 488 XHCIRing cmd_ring; 489 }; 490 491 #define TYPE_XHCI "nec-usb-xhci" 492 493 #define XHCI(obj) \ 494 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 495 496 typedef struct XHCIEvRingSeg { 497 uint32_t addr_low; 498 uint32_t addr_high; 499 uint32_t size; 500 uint32_t rsvd; 501 } XHCIEvRingSeg; 502 503 enum xhci_flags { 504 XHCI_FLAG_SS_FIRST = 1, 505 XHCI_FLAG_FORCE_PCIE_ENDCAP, 506 XHCI_FLAG_ENABLE_STREAMS, 507 }; 508 509 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 510 unsigned int epid, unsigned int streamid); 511 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 512 unsigned int epid); 513 static void xhci_xfer_report(XHCITransfer *xfer); 514 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 515 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 516 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 517 unsigned int slotid, unsigned int epid); 518 519 static const char *TRBType_names[] = { 520 [TRB_RESERVED] = "TRB_RESERVED", 521 [TR_NORMAL] = "TR_NORMAL", 522 [TR_SETUP] = "TR_SETUP", 523 [TR_DATA] = "TR_DATA", 524 [TR_STATUS] = "TR_STATUS", 525 [TR_ISOCH] = "TR_ISOCH", 526 [TR_LINK] = "TR_LINK", 527 [TR_EVDATA] = "TR_EVDATA", 528 [TR_NOOP] = "TR_NOOP", 529 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 530 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 531 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 532 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 533 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 534 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 535 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 536 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 537 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 538 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 539 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 540 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 541 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 542 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 543 [CR_NOOP] = "CR_NOOP", 544 [ER_TRANSFER] = "ER_TRANSFER", 545 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 546 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 547 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 548 [ER_DOORBELL] = "ER_DOORBELL", 549 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 550 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 551 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 552 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 553 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 554 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 555 }; 556 557 static const char *TRBCCode_names[] = { 558 [CC_INVALID] = "CC_INVALID", 559 [CC_SUCCESS] = "CC_SUCCESS", 560 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 561 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 562 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 563 [CC_TRB_ERROR] = "CC_TRB_ERROR", 564 [CC_STALL_ERROR] = "CC_STALL_ERROR", 565 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 566 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 567 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 568 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 569 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 570 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 571 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 572 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 573 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 574 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 575 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 576 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 577 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 578 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 579 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 580 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 581 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 582 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 583 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 584 [CC_STOPPED] = "CC_STOPPED", 585 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 586 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 587 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 588 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 589 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 590 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 591 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 592 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 593 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 594 }; 595 596 static const char *ep_state_names[] = { 597 [EP_DISABLED] = "disabled", 598 [EP_RUNNING] = "running", 599 [EP_HALTED] = "halted", 600 [EP_STOPPED] = "stopped", 601 [EP_ERROR] = "error", 602 }; 603 604 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 605 { 606 if (index >= llen || list[index] == NULL) { 607 return "???"; 608 } 609 return list[index]; 610 } 611 612 static const char *trb_name(XHCITRB *trb) 613 { 614 return lookup_name(TRB_TYPE(*trb), TRBType_names, 615 ARRAY_SIZE(TRBType_names)); 616 } 617 618 static const char *event_name(XHCIEvent *event) 619 { 620 return lookup_name(event->ccode, TRBCCode_names, 621 ARRAY_SIZE(TRBCCode_names)); 622 } 623 624 static const char *ep_state_name(uint32_t state) 625 { 626 return lookup_name(state, ep_state_names, 627 ARRAY_SIZE(ep_state_names)); 628 } 629 630 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 631 { 632 return xhci->flags & (1 << bit); 633 } 634 635 static uint64_t xhci_mfindex_get(XHCIState *xhci) 636 { 637 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 638 return (now - xhci->mfindex_start) / 125000; 639 } 640 641 static void xhci_mfwrap_update(XHCIState *xhci) 642 { 643 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 644 uint32_t mfindex, left; 645 int64_t now; 646 647 if ((xhci->usbcmd & bits) == bits) { 648 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 649 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 650 left = 0x4000 - mfindex; 651 timer_mod(xhci->mfwrap_timer, now + left * 125000); 652 } else { 653 timer_del(xhci->mfwrap_timer); 654 } 655 } 656 657 static void xhci_mfwrap_timer(void *opaque) 658 { 659 XHCIState *xhci = opaque; 660 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 661 662 xhci_event(xhci, &wrap, 0); 663 xhci_mfwrap_update(xhci); 664 } 665 666 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 667 { 668 if (sizeof(dma_addr_t) == 4) { 669 return low; 670 } else { 671 return low | (((dma_addr_t)high << 16) << 16); 672 } 673 } 674 675 static inline dma_addr_t xhci_mask64(uint64_t addr) 676 { 677 if (sizeof(dma_addr_t) == 4) { 678 return addr & 0xffffffff; 679 } else { 680 return addr; 681 } 682 } 683 684 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 685 uint32_t *buf, size_t len) 686 { 687 int i; 688 689 assert((len % sizeof(uint32_t)) == 0); 690 691 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 692 693 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 694 buf[i] = le32_to_cpu(buf[i]); 695 } 696 } 697 698 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 699 uint32_t *buf, size_t len) 700 { 701 int i; 702 uint32_t tmp[5]; 703 uint32_t n = len / sizeof(uint32_t); 704 705 assert((len % sizeof(uint32_t)) == 0); 706 assert(n <= ARRAY_SIZE(tmp)); 707 708 for (i = 0; i < n; i++) { 709 tmp[i] = cpu_to_le32(buf[i]); 710 } 711 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 712 } 713 714 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 715 { 716 int index; 717 718 if (!uport->dev) { 719 return NULL; 720 } 721 switch (uport->dev->speed) { 722 case USB_SPEED_LOW: 723 case USB_SPEED_FULL: 724 case USB_SPEED_HIGH: 725 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 726 index = uport->index + xhci->numports_3; 727 } else { 728 index = uport->index; 729 } 730 break; 731 case USB_SPEED_SUPER: 732 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 733 index = uport->index; 734 } else { 735 index = uport->index + xhci->numports_2; 736 } 737 break; 738 default: 739 return NULL; 740 } 741 return &xhci->ports[index]; 742 } 743 744 static void xhci_intx_update(XHCIState *xhci) 745 { 746 PCIDevice *pci_dev = PCI_DEVICE(xhci); 747 int level = 0; 748 749 if (msix_enabled(pci_dev) || 750 msi_enabled(pci_dev)) { 751 return; 752 } 753 754 if (xhci->intr[0].iman & IMAN_IP && 755 xhci->intr[0].iman & IMAN_IE && 756 xhci->usbcmd & USBCMD_INTE) { 757 level = 1; 758 } 759 760 trace_usb_xhci_irq_intx(level); 761 pci_set_irq(pci_dev, level); 762 } 763 764 static void xhci_msix_update(XHCIState *xhci, int v) 765 { 766 PCIDevice *pci_dev = PCI_DEVICE(xhci); 767 bool enabled; 768 769 if (!msix_enabled(pci_dev)) { 770 return; 771 } 772 773 enabled = xhci->intr[v].iman & IMAN_IE; 774 if (enabled == xhci->intr[v].msix_used) { 775 return; 776 } 777 778 if (enabled) { 779 trace_usb_xhci_irq_msix_use(v); 780 msix_vector_use(pci_dev, v); 781 xhci->intr[v].msix_used = true; 782 } else { 783 trace_usb_xhci_irq_msix_unuse(v); 784 msix_vector_unuse(pci_dev, v); 785 xhci->intr[v].msix_used = false; 786 } 787 } 788 789 static void xhci_intr_raise(XHCIState *xhci, int v) 790 { 791 PCIDevice *pci_dev = PCI_DEVICE(xhci); 792 793 xhci->intr[v].erdp_low |= ERDP_EHB; 794 xhci->intr[v].iman |= IMAN_IP; 795 xhci->usbsts |= USBSTS_EINT; 796 797 if (!(xhci->intr[v].iman & IMAN_IE)) { 798 return; 799 } 800 801 if (!(xhci->usbcmd & USBCMD_INTE)) { 802 return; 803 } 804 805 if (msix_enabled(pci_dev)) { 806 trace_usb_xhci_irq_msix(v); 807 msix_notify(pci_dev, v); 808 return; 809 } 810 811 if (msi_enabled(pci_dev)) { 812 trace_usb_xhci_irq_msi(v); 813 msi_notify(pci_dev, v); 814 return; 815 } 816 817 if (v == 0) { 818 trace_usb_xhci_irq_intx(1); 819 pci_irq_assert(pci_dev); 820 } 821 } 822 823 static inline int xhci_running(XHCIState *xhci) 824 { 825 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 826 } 827 828 static void xhci_die(XHCIState *xhci) 829 { 830 xhci->usbsts |= USBSTS_HCE; 831 DPRINTF("xhci: asserted controller error\n"); 832 } 833 834 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 835 { 836 PCIDevice *pci_dev = PCI_DEVICE(xhci); 837 XHCIInterrupter *intr = &xhci->intr[v]; 838 XHCITRB ev_trb; 839 dma_addr_t addr; 840 841 ev_trb.parameter = cpu_to_le64(event->ptr); 842 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 843 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 844 event->flags | (event->type << TRB_TYPE_SHIFT); 845 if (intr->er_pcs) { 846 ev_trb.control |= TRB_C; 847 } 848 ev_trb.control = cpu_to_le32(ev_trb.control); 849 850 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 851 event_name(event), ev_trb.parameter, 852 ev_trb.status, ev_trb.control); 853 854 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 855 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 856 857 intr->er_ep_idx++; 858 if (intr->er_ep_idx >= intr->er_size) { 859 intr->er_ep_idx = 0; 860 intr->er_pcs = !intr->er_pcs; 861 } 862 } 863 864 static void xhci_events_update(XHCIState *xhci, int v) 865 { 866 XHCIInterrupter *intr = &xhci->intr[v]; 867 dma_addr_t erdp; 868 unsigned int dp_idx; 869 bool do_irq = 0; 870 871 if (xhci->usbsts & USBSTS_HCH) { 872 return; 873 } 874 875 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 876 if (erdp < intr->er_start || 877 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 878 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 879 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 880 v, intr->er_start, intr->er_size); 881 xhci_die(xhci); 882 return; 883 } 884 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 885 assert(dp_idx < intr->er_size); 886 887 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 888 * deadlocks when the ER is full. Hack it by holding off events until 889 * the driver decides to free at least half of the ring */ 890 if (intr->er_full) { 891 int er_free = dp_idx - intr->er_ep_idx; 892 if (er_free <= 0) { 893 er_free += intr->er_size; 894 } 895 if (er_free < (intr->er_size/2)) { 896 DPRINTF("xhci_events_update(): event ring still " 897 "more than half full (hack)\n"); 898 return; 899 } 900 } 901 902 while (intr->ev_buffer_put != intr->ev_buffer_get) { 903 assert(intr->er_full); 904 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 905 DPRINTF("xhci_events_update(): event ring full again\n"); 906 #ifndef ER_FULL_HACK 907 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 908 xhci_write_event(xhci, &full, v); 909 #endif 910 do_irq = 1; 911 break; 912 } 913 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 914 xhci_write_event(xhci, event, v); 915 intr->ev_buffer_get++; 916 do_irq = 1; 917 if (intr->ev_buffer_get == EV_QUEUE) { 918 intr->ev_buffer_get = 0; 919 } 920 } 921 922 if (do_irq) { 923 xhci_intr_raise(xhci, v); 924 } 925 926 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 927 DPRINTF("xhci_events_update(): event ring no longer full\n"); 928 intr->er_full = 0; 929 } 930 } 931 932 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 933 { 934 XHCIInterrupter *intr; 935 dma_addr_t erdp; 936 unsigned int dp_idx; 937 938 if (v >= xhci->numintrs) { 939 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 940 return; 941 } 942 intr = &xhci->intr[v]; 943 944 if (intr->er_full) { 945 DPRINTF("xhci_event(): ER full, queueing\n"); 946 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 947 DPRINTF("xhci: event queue full, dropping event!\n"); 948 return; 949 } 950 intr->ev_buffer[intr->ev_buffer_put++] = *event; 951 if (intr->ev_buffer_put == EV_QUEUE) { 952 intr->ev_buffer_put = 0; 953 } 954 return; 955 } 956 957 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 958 if (erdp < intr->er_start || 959 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 960 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 961 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 962 v, intr->er_start, intr->er_size); 963 xhci_die(xhci); 964 return; 965 } 966 967 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 968 assert(dp_idx < intr->er_size); 969 970 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 971 DPRINTF("xhci_event(): ER full, queueing\n"); 972 #ifndef ER_FULL_HACK 973 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 974 xhci_write_event(xhci, &full); 975 #endif 976 intr->er_full = 1; 977 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 978 DPRINTF("xhci: event queue full, dropping event!\n"); 979 return; 980 } 981 intr->ev_buffer[intr->ev_buffer_put++] = *event; 982 if (intr->ev_buffer_put == EV_QUEUE) { 983 intr->ev_buffer_put = 0; 984 } 985 } else { 986 xhci_write_event(xhci, event, v); 987 } 988 989 xhci_intr_raise(xhci, v); 990 } 991 992 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 993 dma_addr_t base) 994 { 995 ring->dequeue = base; 996 ring->ccs = 1; 997 } 998 999 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 1000 dma_addr_t *addr) 1001 { 1002 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1003 1004 while (1) { 1005 TRBType type; 1006 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 1007 trb->addr = ring->dequeue; 1008 trb->ccs = ring->ccs; 1009 le64_to_cpus(&trb->parameter); 1010 le32_to_cpus(&trb->status); 1011 le32_to_cpus(&trb->control); 1012 1013 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 1014 trb->parameter, trb->status, trb->control); 1015 1016 if ((trb->control & TRB_C) != ring->ccs) { 1017 return 0; 1018 } 1019 1020 type = TRB_TYPE(*trb); 1021 1022 if (type != TR_LINK) { 1023 if (addr) { 1024 *addr = ring->dequeue; 1025 } 1026 ring->dequeue += TRB_SIZE; 1027 return type; 1028 } else { 1029 ring->dequeue = xhci_mask64(trb->parameter); 1030 if (trb->control & TRB_LK_TC) { 1031 ring->ccs = !ring->ccs; 1032 } 1033 } 1034 } 1035 } 1036 1037 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 1038 { 1039 PCIDevice *pci_dev = PCI_DEVICE(xhci); 1040 XHCITRB trb; 1041 int length = 0; 1042 dma_addr_t dequeue = ring->dequeue; 1043 bool ccs = ring->ccs; 1044 /* hack to bundle together the two/three TDs that make a setup transfer */ 1045 bool control_td_set = 0; 1046 1047 while (1) { 1048 TRBType type; 1049 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 1050 le64_to_cpus(&trb.parameter); 1051 le32_to_cpus(&trb.status); 1052 le32_to_cpus(&trb.control); 1053 1054 if ((trb.control & TRB_C) != ccs) { 1055 return -length; 1056 } 1057 1058 type = TRB_TYPE(trb); 1059 1060 if (type == TR_LINK) { 1061 dequeue = xhci_mask64(trb.parameter); 1062 if (trb.control & TRB_LK_TC) { 1063 ccs = !ccs; 1064 } 1065 continue; 1066 } 1067 1068 length += 1; 1069 dequeue += TRB_SIZE; 1070 1071 if (type == TR_SETUP) { 1072 control_td_set = 1; 1073 } else if (type == TR_STATUS) { 1074 control_td_set = 0; 1075 } 1076 1077 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1078 return length; 1079 } 1080 } 1081 } 1082 1083 static void xhci_er_reset(XHCIState *xhci, int v) 1084 { 1085 XHCIInterrupter *intr = &xhci->intr[v]; 1086 XHCIEvRingSeg seg; 1087 1088 if (intr->erstsz == 0) { 1089 /* disabled */ 1090 intr->er_start = 0; 1091 intr->er_size = 0; 1092 return; 1093 } 1094 /* cache the (sole) event ring segment location */ 1095 if (intr->erstsz != 1) { 1096 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1097 xhci_die(xhci); 1098 return; 1099 } 1100 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1101 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1102 le32_to_cpus(&seg.addr_low); 1103 le32_to_cpus(&seg.addr_high); 1104 le32_to_cpus(&seg.size); 1105 if (seg.size < 16 || seg.size > 4096) { 1106 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 1107 xhci_die(xhci); 1108 return; 1109 } 1110 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1111 intr->er_size = seg.size; 1112 1113 intr->er_ep_idx = 0; 1114 intr->er_pcs = 1; 1115 intr->er_full = 0; 1116 1117 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1118 v, intr->er_start, intr->er_size); 1119 } 1120 1121 static void xhci_run(XHCIState *xhci) 1122 { 1123 trace_usb_xhci_run(); 1124 xhci->usbsts &= ~USBSTS_HCH; 1125 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1126 } 1127 1128 static void xhci_stop(XHCIState *xhci) 1129 { 1130 trace_usb_xhci_stop(); 1131 xhci->usbsts |= USBSTS_HCH; 1132 xhci->crcr_low &= ~CRCR_CRR; 1133 } 1134 1135 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1136 dma_addr_t base) 1137 { 1138 XHCIStreamContext *stctx; 1139 unsigned int i; 1140 1141 stctx = g_new0(XHCIStreamContext, count); 1142 for (i = 0; i < count; i++) { 1143 stctx[i].pctx = base + i * 16; 1144 stctx[i].sct = -1; 1145 } 1146 return stctx; 1147 } 1148 1149 static void xhci_reset_streams(XHCIEPContext *epctx) 1150 { 1151 unsigned int i; 1152 1153 for (i = 0; i < epctx->nr_pstreams; i++) { 1154 epctx->pstreams[i].sct = -1; 1155 } 1156 } 1157 1158 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1159 { 1160 assert(epctx->pstreams == NULL); 1161 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1162 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1163 } 1164 1165 static void xhci_free_streams(XHCIEPContext *epctx) 1166 { 1167 assert(epctx->pstreams != NULL); 1168 1169 g_free(epctx->pstreams); 1170 epctx->pstreams = NULL; 1171 epctx->nr_pstreams = 0; 1172 } 1173 1174 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 1175 unsigned int slotid, 1176 uint32_t epmask, 1177 XHCIEPContext **epctxs, 1178 USBEndpoint **eps) 1179 { 1180 XHCISlot *slot; 1181 XHCIEPContext *epctx; 1182 USBEndpoint *ep; 1183 int i, j; 1184 1185 assert(slotid >= 1 && slotid <= xhci->numslots); 1186 1187 slot = &xhci->slots[slotid - 1]; 1188 1189 for (i = 2, j = 0; i <= 31; i++) { 1190 if (!(epmask & (1u << i))) { 1191 continue; 1192 } 1193 1194 epctx = slot->eps[i - 1]; 1195 ep = xhci_epid_to_usbep(xhci, slotid, i); 1196 if (!epctx || !epctx->nr_pstreams || !ep) { 1197 continue; 1198 } 1199 1200 if (epctxs) { 1201 epctxs[j] = epctx; 1202 } 1203 eps[j++] = ep; 1204 } 1205 return j; 1206 } 1207 1208 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 1209 uint32_t epmask) 1210 { 1211 USBEndpoint *eps[30]; 1212 int nr_eps; 1213 1214 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 1215 if (nr_eps) { 1216 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 1217 } 1218 } 1219 1220 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 1221 uint32_t epmask) 1222 { 1223 XHCIEPContext *epctxs[30]; 1224 USBEndpoint *eps[30]; 1225 int i, r, nr_eps, req_nr_streams, dev_max_streams; 1226 1227 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 1228 eps); 1229 if (nr_eps == 0) { 1230 return CC_SUCCESS; 1231 } 1232 1233 req_nr_streams = epctxs[0]->nr_pstreams; 1234 dev_max_streams = eps[0]->max_streams; 1235 1236 for (i = 1; i < nr_eps; i++) { 1237 /* 1238 * HdG: I don't expect these to ever trigger, but if they do we need 1239 * to come up with another solution, ie group identical endpoints 1240 * together and make an usb_device_alloc_streams call per group. 1241 */ 1242 if (epctxs[i]->nr_pstreams != req_nr_streams) { 1243 FIXME("guest streams config not identical for all eps"); 1244 return CC_RESOURCE_ERROR; 1245 } 1246 if (eps[i]->max_streams != dev_max_streams) { 1247 FIXME("device streams config not identical for all eps"); 1248 return CC_RESOURCE_ERROR; 1249 } 1250 } 1251 1252 /* 1253 * max-streams in both the device descriptor and in the controller is a 1254 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 1255 * streams the guest will ask for 5 rounded up to the next power of 2 which 1256 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 1257 * 1258 * For redirected devices however this is an issue, as there we must ask 1259 * the real xhci controller to alloc streams, and the host driver for the 1260 * real xhci controller will likely disallow allocating more streams then 1261 * the device can handle. 1262 * 1263 * So we limit the requested nr_streams to the maximum number the device 1264 * can handle. 1265 */ 1266 if (req_nr_streams > dev_max_streams) { 1267 req_nr_streams = dev_max_streams; 1268 } 1269 1270 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 1271 if (r != 0) { 1272 DPRINTF("xhci: alloc streams failed\n"); 1273 return CC_RESOURCE_ERROR; 1274 } 1275 1276 return CC_SUCCESS; 1277 } 1278 1279 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1280 unsigned int streamid, 1281 uint32_t *cc_error) 1282 { 1283 XHCIStreamContext *sctx; 1284 dma_addr_t base; 1285 uint32_t ctx[2], sct; 1286 1287 assert(streamid != 0); 1288 if (epctx->lsa) { 1289 if (streamid >= epctx->nr_pstreams) { 1290 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1291 return NULL; 1292 } 1293 sctx = epctx->pstreams + streamid; 1294 } else { 1295 FIXME("secondary streams not implemented yet"); 1296 } 1297 1298 if (sctx->sct == -1) { 1299 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1300 sct = (ctx[0] >> 1) & 0x07; 1301 if (epctx->lsa && sct != 1) { 1302 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1303 return NULL; 1304 } 1305 sctx->sct = sct; 1306 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1307 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1308 } 1309 return sctx; 1310 } 1311 1312 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1313 XHCIStreamContext *sctx, uint32_t state) 1314 { 1315 XHCIRing *ring = NULL; 1316 uint32_t ctx[5]; 1317 uint32_t ctx2[2]; 1318 1319 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1320 ctx[0] &= ~EP_STATE_MASK; 1321 ctx[0] |= state; 1322 1323 /* update ring dequeue ptr */ 1324 if (epctx->nr_pstreams) { 1325 if (sctx != NULL) { 1326 ring = &sctx->ring; 1327 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1328 ctx2[0] &= 0xe; 1329 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1330 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1331 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1332 } 1333 } else { 1334 ring = &epctx->ring; 1335 } 1336 if (ring) { 1337 ctx[2] = ring->dequeue | ring->ccs; 1338 ctx[3] = (ring->dequeue >> 16) >> 16; 1339 1340 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1341 epctx->pctx, state, ctx[3], ctx[2]); 1342 } 1343 1344 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1345 if (epctx->state != state) { 1346 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1347 ep_state_name(epctx->state), 1348 ep_state_name(state)); 1349 } 1350 epctx->state = state; 1351 } 1352 1353 static void xhci_ep_kick_timer(void *opaque) 1354 { 1355 XHCIEPContext *epctx = opaque; 1356 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); 1357 } 1358 1359 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1360 unsigned int slotid, 1361 unsigned int epid) 1362 { 1363 XHCIEPContext *epctx; 1364 int i; 1365 1366 epctx = g_new0(XHCIEPContext, 1); 1367 epctx->xhci = xhci; 1368 epctx->slotid = slotid; 1369 epctx->epid = epid; 1370 1371 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1372 epctx->transfers[i].xhci = xhci; 1373 epctx->transfers[i].slotid = slotid; 1374 epctx->transfers[i].epid = epid; 1375 usb_packet_init(&epctx->transfers[i].packet); 1376 } 1377 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1378 1379 return epctx; 1380 } 1381 1382 static void xhci_init_epctx(XHCIEPContext *epctx, 1383 dma_addr_t pctx, uint32_t *ctx) 1384 { 1385 dma_addr_t dequeue; 1386 1387 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1388 1389 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1390 epctx->pctx = pctx; 1391 epctx->max_psize = ctx[1]>>16; 1392 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1393 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1394 epctx->lsa = (ctx[0] >> 15) & 1; 1395 if (epctx->max_pstreams) { 1396 xhci_alloc_streams(epctx, dequeue); 1397 } else { 1398 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1399 epctx->ring.ccs = ctx[2] & 1; 1400 } 1401 1402 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1403 } 1404 1405 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1406 unsigned int epid, dma_addr_t pctx, 1407 uint32_t *ctx) 1408 { 1409 XHCISlot *slot; 1410 XHCIEPContext *epctx; 1411 1412 trace_usb_xhci_ep_enable(slotid, epid); 1413 assert(slotid >= 1 && slotid <= xhci->numslots); 1414 assert(epid >= 1 && epid <= 31); 1415 1416 slot = &xhci->slots[slotid-1]; 1417 if (slot->eps[epid-1]) { 1418 xhci_disable_ep(xhci, slotid, epid); 1419 } 1420 1421 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1422 slot->eps[epid-1] = epctx; 1423 xhci_init_epctx(epctx, pctx, ctx); 1424 1425 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1426 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1427 1428 epctx->mfindex_last = 0; 1429 1430 epctx->state = EP_RUNNING; 1431 ctx[0] &= ~EP_STATE_MASK; 1432 ctx[0] |= EP_RUNNING; 1433 1434 return CC_SUCCESS; 1435 } 1436 1437 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1438 { 1439 int killed = 0; 1440 1441 if (report && (t->running_async || t->running_retry)) { 1442 t->status = report; 1443 xhci_xfer_report(t); 1444 } 1445 1446 if (t->running_async) { 1447 usb_cancel_packet(&t->packet); 1448 t->running_async = 0; 1449 killed = 1; 1450 } 1451 if (t->running_retry) { 1452 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1453 if (epctx) { 1454 epctx->retry = NULL; 1455 timer_del(epctx->kick_timer); 1456 } 1457 t->running_retry = 0; 1458 killed = 1; 1459 } 1460 g_free(t->trbs); 1461 1462 t->trbs = NULL; 1463 t->trb_count = t->trb_alloced = 0; 1464 1465 return killed; 1466 } 1467 1468 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1469 unsigned int epid, TRBCCode report) 1470 { 1471 XHCISlot *slot; 1472 XHCIEPContext *epctx; 1473 int i, xferi, killed = 0; 1474 USBEndpoint *ep = NULL; 1475 assert(slotid >= 1 && slotid <= xhci->numslots); 1476 assert(epid >= 1 && epid <= 31); 1477 1478 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1479 1480 slot = &xhci->slots[slotid-1]; 1481 1482 if (!slot->eps[epid-1]) { 1483 return 0; 1484 } 1485 1486 epctx = slot->eps[epid-1]; 1487 1488 xferi = epctx->next_xfer; 1489 for (i = 0; i < TD_QUEUE; i++) { 1490 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report); 1491 if (killed) { 1492 report = 0; /* Only report once */ 1493 } 1494 epctx->transfers[xferi].packet.ep = NULL; 1495 xferi = (xferi + 1) % TD_QUEUE; 1496 } 1497 1498 ep = xhci_epid_to_usbep(xhci, slotid, epid); 1499 if (ep) { 1500 usb_device_ep_stopped(ep->dev, ep); 1501 } 1502 return killed; 1503 } 1504 1505 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1506 unsigned int epid) 1507 { 1508 XHCISlot *slot; 1509 XHCIEPContext *epctx; 1510 int i; 1511 1512 trace_usb_xhci_ep_disable(slotid, epid); 1513 assert(slotid >= 1 && slotid <= xhci->numslots); 1514 assert(epid >= 1 && epid <= 31); 1515 1516 slot = &xhci->slots[slotid-1]; 1517 1518 if (!slot->eps[epid-1]) { 1519 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1520 return CC_SUCCESS; 1521 } 1522 1523 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1524 1525 epctx = slot->eps[epid-1]; 1526 1527 if (epctx->nr_pstreams) { 1528 xhci_free_streams(epctx); 1529 } 1530 1531 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1532 usb_packet_cleanup(&epctx->transfers[i].packet); 1533 } 1534 1535 /* only touch guest RAM if we're not resetting the HC */ 1536 if (xhci->dcbaap_low || xhci->dcbaap_high) { 1537 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1538 } 1539 1540 timer_free(epctx->kick_timer); 1541 g_free(epctx); 1542 slot->eps[epid-1] = NULL; 1543 1544 return CC_SUCCESS; 1545 } 1546 1547 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1548 unsigned int epid) 1549 { 1550 XHCISlot *slot; 1551 XHCIEPContext *epctx; 1552 1553 trace_usb_xhci_ep_stop(slotid, epid); 1554 assert(slotid >= 1 && slotid <= xhci->numslots); 1555 1556 if (epid < 1 || epid > 31) { 1557 DPRINTF("xhci: bad ep %d\n", epid); 1558 return CC_TRB_ERROR; 1559 } 1560 1561 slot = &xhci->slots[slotid-1]; 1562 1563 if (!slot->eps[epid-1]) { 1564 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1565 return CC_EP_NOT_ENABLED_ERROR; 1566 } 1567 1568 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1569 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1570 "data might be lost\n"); 1571 } 1572 1573 epctx = slot->eps[epid-1]; 1574 1575 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1576 1577 if (epctx->nr_pstreams) { 1578 xhci_reset_streams(epctx); 1579 } 1580 1581 return CC_SUCCESS; 1582 } 1583 1584 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1585 unsigned int epid) 1586 { 1587 XHCISlot *slot; 1588 XHCIEPContext *epctx; 1589 1590 trace_usb_xhci_ep_reset(slotid, epid); 1591 assert(slotid >= 1 && slotid <= xhci->numslots); 1592 1593 if (epid < 1 || epid > 31) { 1594 DPRINTF("xhci: bad ep %d\n", epid); 1595 return CC_TRB_ERROR; 1596 } 1597 1598 slot = &xhci->slots[slotid-1]; 1599 1600 if (!slot->eps[epid-1]) { 1601 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1602 return CC_EP_NOT_ENABLED_ERROR; 1603 } 1604 1605 epctx = slot->eps[epid-1]; 1606 1607 if (epctx->state != EP_HALTED) { 1608 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1609 epid, epctx->state); 1610 return CC_CONTEXT_STATE_ERROR; 1611 } 1612 1613 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1614 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1615 "data might be lost\n"); 1616 } 1617 1618 if (!xhci->slots[slotid-1].uport || 1619 !xhci->slots[slotid-1].uport->dev || 1620 !xhci->slots[slotid-1].uport->dev->attached) { 1621 return CC_USB_TRANSACTION_ERROR; 1622 } 1623 1624 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1625 1626 if (epctx->nr_pstreams) { 1627 xhci_reset_streams(epctx); 1628 } 1629 1630 return CC_SUCCESS; 1631 } 1632 1633 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1634 unsigned int epid, unsigned int streamid, 1635 uint64_t pdequeue) 1636 { 1637 XHCISlot *slot; 1638 XHCIEPContext *epctx; 1639 XHCIStreamContext *sctx; 1640 dma_addr_t dequeue; 1641 1642 assert(slotid >= 1 && slotid <= xhci->numslots); 1643 1644 if (epid < 1 || epid > 31) { 1645 DPRINTF("xhci: bad ep %d\n", epid); 1646 return CC_TRB_ERROR; 1647 } 1648 1649 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1650 dequeue = xhci_mask64(pdequeue); 1651 1652 slot = &xhci->slots[slotid-1]; 1653 1654 if (!slot->eps[epid-1]) { 1655 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1656 return CC_EP_NOT_ENABLED_ERROR; 1657 } 1658 1659 epctx = slot->eps[epid-1]; 1660 1661 if (epctx->state != EP_STOPPED) { 1662 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1663 return CC_CONTEXT_STATE_ERROR; 1664 } 1665 1666 if (epctx->nr_pstreams) { 1667 uint32_t err; 1668 sctx = xhci_find_stream(epctx, streamid, &err); 1669 if (sctx == NULL) { 1670 return err; 1671 } 1672 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1673 sctx->ring.ccs = dequeue & 1; 1674 } else { 1675 sctx = NULL; 1676 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1677 epctx->ring.ccs = dequeue & 1; 1678 } 1679 1680 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1681 1682 return CC_SUCCESS; 1683 } 1684 1685 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1686 { 1687 XHCIState *xhci = xfer->xhci; 1688 int i; 1689 1690 xfer->int_req = false; 1691 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1692 for (i = 0; i < xfer->trb_count; i++) { 1693 XHCITRB *trb = &xfer->trbs[i]; 1694 dma_addr_t addr; 1695 unsigned int chunk = 0; 1696 1697 if (trb->control & TRB_TR_IOC) { 1698 xfer->int_req = true; 1699 } 1700 1701 switch (TRB_TYPE(*trb)) { 1702 case TR_DATA: 1703 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1704 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1705 goto err; 1706 } 1707 /* fallthrough */ 1708 case TR_NORMAL: 1709 case TR_ISOCH: 1710 addr = xhci_mask64(trb->parameter); 1711 chunk = trb->status & 0x1ffff; 1712 if (trb->control & TRB_TR_IDT) { 1713 if (chunk > 8 || in_xfer) { 1714 DPRINTF("xhci: invalid immediate data TRB\n"); 1715 goto err; 1716 } 1717 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1718 } else { 1719 qemu_sglist_add(&xfer->sgl, addr, chunk); 1720 } 1721 break; 1722 } 1723 } 1724 1725 return 0; 1726 1727 err: 1728 qemu_sglist_destroy(&xfer->sgl); 1729 xhci_die(xhci); 1730 return -1; 1731 } 1732 1733 static void xhci_xfer_unmap(XHCITransfer *xfer) 1734 { 1735 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1736 qemu_sglist_destroy(&xfer->sgl); 1737 } 1738 1739 static void xhci_xfer_report(XHCITransfer *xfer) 1740 { 1741 uint32_t edtla = 0; 1742 unsigned int left; 1743 bool reported = 0; 1744 bool shortpkt = 0; 1745 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1746 XHCIState *xhci = xfer->xhci; 1747 int i; 1748 1749 left = xfer->packet.actual_length; 1750 1751 for (i = 0; i < xfer->trb_count; i++) { 1752 XHCITRB *trb = &xfer->trbs[i]; 1753 unsigned int chunk = 0; 1754 1755 switch (TRB_TYPE(*trb)) { 1756 case TR_DATA: 1757 case TR_NORMAL: 1758 case TR_ISOCH: 1759 chunk = trb->status & 0x1ffff; 1760 if (chunk > left) { 1761 chunk = left; 1762 if (xfer->status == CC_SUCCESS) { 1763 shortpkt = 1; 1764 } 1765 } 1766 left -= chunk; 1767 edtla += chunk; 1768 break; 1769 case TR_STATUS: 1770 reported = 0; 1771 shortpkt = 0; 1772 break; 1773 } 1774 1775 if (!reported && ((trb->control & TRB_TR_IOC) || 1776 (shortpkt && (trb->control & TRB_TR_ISP)) || 1777 (xfer->status != CC_SUCCESS && left == 0))) { 1778 event.slotid = xfer->slotid; 1779 event.epid = xfer->epid; 1780 event.length = (trb->status & 0x1ffff) - chunk; 1781 event.flags = 0; 1782 event.ptr = trb->addr; 1783 if (xfer->status == CC_SUCCESS) { 1784 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1785 } else { 1786 event.ccode = xfer->status; 1787 } 1788 if (TRB_TYPE(*trb) == TR_EVDATA) { 1789 event.ptr = trb->parameter; 1790 event.flags |= TRB_EV_ED; 1791 event.length = edtla & 0xffffff; 1792 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1793 edtla = 0; 1794 } 1795 xhci_event(xhci, &event, TRB_INTR(*trb)); 1796 reported = 1; 1797 if (xfer->status != CC_SUCCESS) { 1798 return; 1799 } 1800 } 1801 1802 switch (TRB_TYPE(*trb)) { 1803 case TR_SETUP: 1804 reported = 0; 1805 shortpkt = 0; 1806 break; 1807 } 1808 1809 } 1810 } 1811 1812 static void xhci_stall_ep(XHCITransfer *xfer) 1813 { 1814 XHCIState *xhci = xfer->xhci; 1815 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1816 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1817 uint32_t err; 1818 XHCIStreamContext *sctx; 1819 1820 if (epctx->nr_pstreams) { 1821 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1822 if (sctx == NULL) { 1823 return; 1824 } 1825 sctx->ring.dequeue = xfer->trbs[0].addr; 1826 sctx->ring.ccs = xfer->trbs[0].ccs; 1827 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1828 } else { 1829 epctx->ring.dequeue = xfer->trbs[0].addr; 1830 epctx->ring.ccs = xfer->trbs[0].ccs; 1831 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1832 } 1833 } 1834 1835 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1836 XHCIEPContext *epctx); 1837 1838 static int xhci_setup_packet(XHCITransfer *xfer) 1839 { 1840 XHCIState *xhci = xfer->xhci; 1841 USBEndpoint *ep; 1842 int dir; 1843 1844 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1845 1846 if (xfer->packet.ep) { 1847 ep = xfer->packet.ep; 1848 } else { 1849 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid); 1850 if (!ep) { 1851 DPRINTF("xhci: slot %d has no device\n", 1852 xfer->slotid); 1853 return -1; 1854 } 1855 } 1856 1857 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1858 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1859 xfer->trbs[0].addr, false, xfer->int_req); 1860 usb_packet_map(&xfer->packet, &xfer->sgl); 1861 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1862 xfer->packet.pid, ep->dev->addr, ep->nr); 1863 return 0; 1864 } 1865 1866 static int xhci_complete_packet(XHCITransfer *xfer) 1867 { 1868 if (xfer->packet.status == USB_RET_ASYNC) { 1869 trace_usb_xhci_xfer_async(xfer); 1870 xfer->running_async = 1; 1871 xfer->running_retry = 0; 1872 xfer->complete = 0; 1873 return 0; 1874 } else if (xfer->packet.status == USB_RET_NAK) { 1875 trace_usb_xhci_xfer_nak(xfer); 1876 xfer->running_async = 0; 1877 xfer->running_retry = 1; 1878 xfer->complete = 0; 1879 return 0; 1880 } else { 1881 xfer->running_async = 0; 1882 xfer->running_retry = 0; 1883 xfer->complete = 1; 1884 xhci_xfer_unmap(xfer); 1885 } 1886 1887 if (xfer->packet.status == USB_RET_SUCCESS) { 1888 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1889 xfer->status = CC_SUCCESS; 1890 xhci_xfer_report(xfer); 1891 return 0; 1892 } 1893 1894 /* error */ 1895 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1896 switch (xfer->packet.status) { 1897 case USB_RET_NODEV: 1898 case USB_RET_IOERROR: 1899 xfer->status = CC_USB_TRANSACTION_ERROR; 1900 xhci_xfer_report(xfer); 1901 xhci_stall_ep(xfer); 1902 break; 1903 case USB_RET_STALL: 1904 xfer->status = CC_STALL_ERROR; 1905 xhci_xfer_report(xfer); 1906 xhci_stall_ep(xfer); 1907 break; 1908 case USB_RET_BABBLE: 1909 xfer->status = CC_BABBLE_DETECTED; 1910 xhci_xfer_report(xfer); 1911 xhci_stall_ep(xfer); 1912 break; 1913 default: 1914 DPRINTF("%s: FIXME: status = %d\n", __func__, 1915 xfer->packet.status); 1916 FIXME("unhandled USB_RET_*"); 1917 } 1918 return 0; 1919 } 1920 1921 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1922 { 1923 XHCITRB *trb_setup, *trb_status; 1924 uint8_t bmRequestType; 1925 1926 trb_setup = &xfer->trbs[0]; 1927 trb_status = &xfer->trbs[xfer->trb_count-1]; 1928 1929 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 1930 1931 /* at most one Event Data TRB allowed after STATUS */ 1932 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1933 trb_status--; 1934 } 1935 1936 /* do some sanity checks */ 1937 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1938 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1939 TRB_TYPE(*trb_setup)); 1940 return -1; 1941 } 1942 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1943 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1944 TRB_TYPE(*trb_status)); 1945 return -1; 1946 } 1947 if (!(trb_setup->control & TRB_TR_IDT)) { 1948 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1949 return -1; 1950 } 1951 if ((trb_setup->status & 0x1ffff) != 8) { 1952 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1953 (trb_setup->status & 0x1ffff)); 1954 return -1; 1955 } 1956 1957 bmRequestType = trb_setup->parameter; 1958 1959 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1960 xfer->iso_xfer = false; 1961 xfer->timed_xfer = false; 1962 1963 if (xhci_setup_packet(xfer) < 0) { 1964 return -1; 1965 } 1966 xfer->packet.parameter = trb_setup->parameter; 1967 1968 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1969 1970 xhci_complete_packet(xfer); 1971 if (!xfer->running_async && !xfer->running_retry) { 1972 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); 1973 } 1974 return 0; 1975 } 1976 1977 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1978 XHCIEPContext *epctx, uint64_t mfindex) 1979 { 1980 uint64_t asap = ((mfindex + epctx->interval - 1) & 1981 ~(epctx->interval-1)); 1982 uint64_t kick = epctx->mfindex_last + epctx->interval; 1983 1984 assert(epctx->interval != 0); 1985 xfer->mfindex_kick = MAX(asap, kick); 1986 } 1987 1988 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1989 XHCIEPContext *epctx, uint64_t mfindex) 1990 { 1991 if (xfer->trbs[0].control & TRB_TR_SIA) { 1992 uint64_t asap = ((mfindex + epctx->interval - 1) & 1993 ~(epctx->interval-1)); 1994 if (asap >= epctx->mfindex_last && 1995 asap <= epctx->mfindex_last + epctx->interval * 4) { 1996 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1997 } else { 1998 xfer->mfindex_kick = asap; 1999 } 2000 } else { 2001 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 2002 & TRB_TR_FRAMEID_MASK) << 3; 2003 xfer->mfindex_kick |= mfindex & ~0x3fff; 2004 if (xfer->mfindex_kick + 0x100 < mfindex) { 2005 xfer->mfindex_kick += 0x4000; 2006 } 2007 } 2008 } 2009 2010 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 2011 XHCIEPContext *epctx, uint64_t mfindex) 2012 { 2013 if (xfer->mfindex_kick > mfindex) { 2014 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 2015 (xfer->mfindex_kick - mfindex) * 125000); 2016 xfer->running_retry = 1; 2017 } else { 2018 epctx->mfindex_last = xfer->mfindex_kick; 2019 timer_del(epctx->kick_timer); 2020 xfer->running_retry = 0; 2021 } 2022 } 2023 2024 2025 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2026 { 2027 uint64_t mfindex; 2028 2029 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 2030 2031 xfer->in_xfer = epctx->type>>2; 2032 2033 switch(epctx->type) { 2034 case ET_INTR_OUT: 2035 case ET_INTR_IN: 2036 xfer->pkts = 0; 2037 xfer->iso_xfer = false; 2038 xfer->timed_xfer = true; 2039 mfindex = xhci_mfindex_get(xhci); 2040 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 2041 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2042 if (xfer->running_retry) { 2043 return -1; 2044 } 2045 break; 2046 case ET_BULK_OUT: 2047 case ET_BULK_IN: 2048 xfer->pkts = 0; 2049 xfer->iso_xfer = false; 2050 xfer->timed_xfer = false; 2051 break; 2052 case ET_ISO_OUT: 2053 case ET_ISO_IN: 2054 xfer->pkts = 1; 2055 xfer->iso_xfer = true; 2056 xfer->timed_xfer = true; 2057 mfindex = xhci_mfindex_get(xhci); 2058 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 2059 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2060 if (xfer->running_retry) { 2061 return -1; 2062 } 2063 break; 2064 default: 2065 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 2066 return -1; 2067 } 2068 2069 if (xhci_setup_packet(xfer) < 0) { 2070 return -1; 2071 } 2072 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2073 2074 xhci_complete_packet(xfer); 2075 if (!xfer->running_async && !xfer->running_retry) { 2076 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); 2077 } 2078 return 0; 2079 } 2080 2081 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2082 { 2083 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); 2084 return xhci_submit(xhci, xfer, epctx); 2085 } 2086 2087 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 2088 unsigned int epid, unsigned int streamid) 2089 { 2090 XHCIStreamContext *stctx; 2091 XHCIEPContext *epctx; 2092 XHCIRing *ring; 2093 USBEndpoint *ep = NULL; 2094 uint64_t mfindex; 2095 int length; 2096 int i; 2097 2098 trace_usb_xhci_ep_kick(slotid, epid, streamid); 2099 assert(slotid >= 1 && slotid <= xhci->numslots); 2100 assert(epid >= 1 && epid <= 31); 2101 2102 if (!xhci->slots[slotid-1].enabled) { 2103 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 2104 return; 2105 } 2106 epctx = xhci->slots[slotid-1].eps[epid-1]; 2107 if (!epctx) { 2108 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 2109 epid, slotid); 2110 return; 2111 } 2112 2113 /* If the device has been detached, but the guest has not noticed this 2114 yet the 2 above checks will succeed, but we must NOT continue */ 2115 if (!xhci->slots[slotid - 1].uport || 2116 !xhci->slots[slotid - 1].uport->dev || 2117 !xhci->slots[slotid - 1].uport->dev->attached) { 2118 return; 2119 } 2120 2121 if (epctx->retry) { 2122 XHCITransfer *xfer = epctx->retry; 2123 2124 trace_usb_xhci_xfer_retry(xfer); 2125 assert(xfer->running_retry); 2126 if (xfer->timed_xfer) { 2127 /* time to kick the transfer? */ 2128 mfindex = xhci_mfindex_get(xhci); 2129 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2130 if (xfer->running_retry) { 2131 return; 2132 } 2133 xfer->timed_xfer = 0; 2134 xfer->running_retry = 1; 2135 } 2136 if (xfer->iso_xfer) { 2137 /* retry iso transfer */ 2138 if (xhci_setup_packet(xfer) < 0) { 2139 return; 2140 } 2141 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2142 assert(xfer->packet.status != USB_RET_NAK); 2143 xhci_complete_packet(xfer); 2144 } else { 2145 /* retry nak'ed transfer */ 2146 if (xhci_setup_packet(xfer) < 0) { 2147 return; 2148 } 2149 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2150 if (xfer->packet.status == USB_RET_NAK) { 2151 return; 2152 } 2153 xhci_complete_packet(xfer); 2154 } 2155 assert(!xfer->running_retry); 2156 epctx->retry = NULL; 2157 } 2158 2159 if (epctx->state == EP_HALTED) { 2160 DPRINTF("xhci: ep halted, not running schedule\n"); 2161 return; 2162 } 2163 2164 2165 if (epctx->nr_pstreams) { 2166 uint32_t err; 2167 stctx = xhci_find_stream(epctx, streamid, &err); 2168 if (stctx == NULL) { 2169 return; 2170 } 2171 ring = &stctx->ring; 2172 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2173 } else { 2174 ring = &epctx->ring; 2175 streamid = 0; 2176 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2177 } 2178 assert(ring->dequeue != 0); 2179 2180 while (1) { 2181 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 2182 if (xfer->running_async || xfer->running_retry) { 2183 break; 2184 } 2185 length = xhci_ring_chain_length(xhci, ring); 2186 if (length < 0) { 2187 break; 2188 } else if (length == 0) { 2189 break; 2190 } 2191 if (xfer->trbs && xfer->trb_alloced < length) { 2192 xfer->trb_count = 0; 2193 xfer->trb_alloced = 0; 2194 g_free(xfer->trbs); 2195 xfer->trbs = NULL; 2196 } 2197 if (!xfer->trbs) { 2198 xfer->trbs = g_new(XHCITRB, length); 2199 xfer->trb_alloced = length; 2200 } 2201 xfer->trb_count = length; 2202 2203 for (i = 0; i < length; i++) { 2204 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); 2205 } 2206 xfer->streamid = streamid; 2207 2208 if (epid == 1) { 2209 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 2210 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2211 } else { 2212 DPRINTF("xhci: error firing CTL transfer\n"); 2213 } 2214 } else { 2215 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 2216 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 2217 } else { 2218 if (!xfer->timed_xfer) { 2219 DPRINTF("xhci: error firing data transfer\n"); 2220 } 2221 } 2222 } 2223 2224 if (epctx->state == EP_HALTED) { 2225 break; 2226 } 2227 if (xfer->running_retry) { 2228 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2229 epctx->retry = xfer; 2230 break; 2231 } 2232 } 2233 2234 ep = xhci_epid_to_usbep(xhci, slotid, epid); 2235 if (ep) { 2236 usb_device_flush_ep_queue(ep->dev, ep); 2237 } 2238 } 2239 2240 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2241 { 2242 trace_usb_xhci_slot_enable(slotid); 2243 assert(slotid >= 1 && slotid <= xhci->numslots); 2244 xhci->slots[slotid-1].enabled = 1; 2245 xhci->slots[slotid-1].uport = NULL; 2246 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2247 2248 return CC_SUCCESS; 2249 } 2250 2251 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2252 { 2253 int i; 2254 2255 trace_usb_xhci_slot_disable(slotid); 2256 assert(slotid >= 1 && slotid <= xhci->numslots); 2257 2258 for (i = 1; i <= 31; i++) { 2259 if (xhci->slots[slotid-1].eps[i-1]) { 2260 xhci_disable_ep(xhci, slotid, i); 2261 } 2262 } 2263 2264 xhci->slots[slotid-1].enabled = 0; 2265 xhci->slots[slotid-1].addressed = 0; 2266 xhci->slots[slotid-1].uport = NULL; 2267 return CC_SUCCESS; 2268 } 2269 2270 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2271 { 2272 USBPort *uport; 2273 char path[32]; 2274 int i, pos, port; 2275 2276 port = (slot_ctx[1]>>16) & 0xFF; 2277 if (port < 1 || port > xhci->numports) { 2278 return NULL; 2279 } 2280 port = xhci->ports[port-1].uport->index+1; 2281 pos = snprintf(path, sizeof(path), "%d", port); 2282 for (i = 0; i < 5; i++) { 2283 port = (slot_ctx[0] >> 4*i) & 0x0f; 2284 if (!port) { 2285 break; 2286 } 2287 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2288 } 2289 2290 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2291 if (strcmp(uport->path, path) == 0) { 2292 return uport; 2293 } 2294 } 2295 return NULL; 2296 } 2297 2298 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2299 uint64_t pictx, bool bsr) 2300 { 2301 XHCISlot *slot; 2302 USBPort *uport; 2303 USBDevice *dev; 2304 dma_addr_t ictx, octx, dcbaap; 2305 uint64_t poctx; 2306 uint32_t ictl_ctx[2]; 2307 uint32_t slot_ctx[4]; 2308 uint32_t ep0_ctx[5]; 2309 int i; 2310 TRBCCode res; 2311 2312 assert(slotid >= 1 && slotid <= xhci->numslots); 2313 2314 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2315 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2316 ictx = xhci_mask64(pictx); 2317 octx = xhci_mask64(poctx); 2318 2319 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2320 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2321 2322 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2323 2324 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2325 DPRINTF("xhci: invalid input context control %08x %08x\n", 2326 ictl_ctx[0], ictl_ctx[1]); 2327 return CC_TRB_ERROR; 2328 } 2329 2330 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2331 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2332 2333 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2334 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2335 2336 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2337 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2338 2339 uport = xhci_lookup_uport(xhci, slot_ctx); 2340 if (uport == NULL) { 2341 DPRINTF("xhci: port not found\n"); 2342 return CC_TRB_ERROR; 2343 } 2344 trace_usb_xhci_slot_address(slotid, uport->path); 2345 2346 dev = uport->dev; 2347 if (!dev || !dev->attached) { 2348 DPRINTF("xhci: port %s not connected\n", uport->path); 2349 return CC_USB_TRANSACTION_ERROR; 2350 } 2351 2352 for (i = 0; i < xhci->numslots; i++) { 2353 if (i == slotid-1) { 2354 continue; 2355 } 2356 if (xhci->slots[i].uport == uport) { 2357 DPRINTF("xhci: port %s already assigned to slot %d\n", 2358 uport->path, i+1); 2359 return CC_TRB_ERROR; 2360 } 2361 } 2362 2363 slot = &xhci->slots[slotid-1]; 2364 slot->uport = uport; 2365 slot->ctx = octx; 2366 2367 /* Make sure device is in USB_STATE_DEFAULT state */ 2368 usb_device_reset(dev); 2369 if (bsr) { 2370 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2371 } else { 2372 USBPacket p; 2373 uint8_t buf[1]; 2374 2375 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2376 memset(&p, 0, sizeof(p)); 2377 usb_packet_addbuf(&p, buf, sizeof(buf)); 2378 usb_packet_setup(&p, USB_TOKEN_OUT, 2379 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2380 0, false, false); 2381 usb_device_handle_control(dev, &p, 2382 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2383 slotid, 0, 0, NULL); 2384 assert(p.status != USB_RET_ASYNC); 2385 } 2386 2387 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2388 2389 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2390 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2391 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2392 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2393 2394 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2395 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2396 2397 xhci->slots[slotid-1].addressed = 1; 2398 return res; 2399 } 2400 2401 2402 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2403 uint64_t pictx, bool dc) 2404 { 2405 dma_addr_t ictx, octx; 2406 uint32_t ictl_ctx[2]; 2407 uint32_t slot_ctx[4]; 2408 uint32_t islot_ctx[4]; 2409 uint32_t ep_ctx[5]; 2410 int i; 2411 TRBCCode res; 2412 2413 trace_usb_xhci_slot_configure(slotid); 2414 assert(slotid >= 1 && slotid <= xhci->numslots); 2415 2416 ictx = xhci_mask64(pictx); 2417 octx = xhci->slots[slotid-1].ctx; 2418 2419 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2420 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2421 2422 if (dc) { 2423 for (i = 2; i <= 31; i++) { 2424 if (xhci->slots[slotid-1].eps[i-1]) { 2425 xhci_disable_ep(xhci, slotid, i); 2426 } 2427 } 2428 2429 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2430 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2431 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2432 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2433 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2434 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2435 2436 return CC_SUCCESS; 2437 } 2438 2439 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2440 2441 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2442 DPRINTF("xhci: invalid input context control %08x %08x\n", 2443 ictl_ctx[0], ictl_ctx[1]); 2444 return CC_TRB_ERROR; 2445 } 2446 2447 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2448 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2449 2450 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2451 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2452 return CC_CONTEXT_STATE_ERROR; 2453 } 2454 2455 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2456 2457 for (i = 2; i <= 31; i++) { 2458 if (ictl_ctx[0] & (1<<i)) { 2459 xhci_disable_ep(xhci, slotid, i); 2460 } 2461 if (ictl_ctx[1] & (1<<i)) { 2462 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2463 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2464 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2465 ep_ctx[3], ep_ctx[4]); 2466 xhci_disable_ep(xhci, slotid, i); 2467 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2468 if (res != CC_SUCCESS) { 2469 return res; 2470 } 2471 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2472 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2473 ep_ctx[3], ep_ctx[4]); 2474 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2475 } 2476 } 2477 2478 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2479 if (res != CC_SUCCESS) { 2480 for (i = 2; i <= 31; i++) { 2481 if (ictl_ctx[1] & (1u << i)) { 2482 xhci_disable_ep(xhci, slotid, i); 2483 } 2484 } 2485 return res; 2486 } 2487 2488 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2489 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2490 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2491 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2492 SLOT_CONTEXT_ENTRIES_SHIFT); 2493 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2494 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2495 2496 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2497 2498 return CC_SUCCESS; 2499 } 2500 2501 2502 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2503 uint64_t pictx) 2504 { 2505 dma_addr_t ictx, octx; 2506 uint32_t ictl_ctx[2]; 2507 uint32_t iep0_ctx[5]; 2508 uint32_t ep0_ctx[5]; 2509 uint32_t islot_ctx[4]; 2510 uint32_t slot_ctx[4]; 2511 2512 trace_usb_xhci_slot_evaluate(slotid); 2513 assert(slotid >= 1 && slotid <= xhci->numslots); 2514 2515 ictx = xhci_mask64(pictx); 2516 octx = xhci->slots[slotid-1].ctx; 2517 2518 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2519 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2520 2521 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2522 2523 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2524 DPRINTF("xhci: invalid input context control %08x %08x\n", 2525 ictl_ctx[0], ictl_ctx[1]); 2526 return CC_TRB_ERROR; 2527 } 2528 2529 if (ictl_ctx[1] & 0x1) { 2530 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2531 2532 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2533 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2534 2535 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2536 2537 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2538 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2539 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2540 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2541 2542 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2543 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2544 2545 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2546 } 2547 2548 if (ictl_ctx[1] & 0x2) { 2549 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2550 2551 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2552 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2553 iep0_ctx[3], iep0_ctx[4]); 2554 2555 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2556 2557 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2558 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2559 2560 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2561 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2562 2563 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2564 } 2565 2566 return CC_SUCCESS; 2567 } 2568 2569 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2570 { 2571 uint32_t slot_ctx[4]; 2572 dma_addr_t octx; 2573 int i; 2574 2575 trace_usb_xhci_slot_reset(slotid); 2576 assert(slotid >= 1 && slotid <= xhci->numslots); 2577 2578 octx = xhci->slots[slotid-1].ctx; 2579 2580 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2581 2582 for (i = 2; i <= 31; i++) { 2583 if (xhci->slots[slotid-1].eps[i-1]) { 2584 xhci_disable_ep(xhci, slotid, i); 2585 } 2586 } 2587 2588 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2589 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2590 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2591 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2592 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2593 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2594 2595 return CC_SUCCESS; 2596 } 2597 2598 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2599 { 2600 unsigned int slotid; 2601 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2602 if (slotid < 1 || slotid > xhci->numslots) { 2603 DPRINTF("xhci: bad slot id %d\n", slotid); 2604 event->ccode = CC_TRB_ERROR; 2605 return 0; 2606 } else if (!xhci->slots[slotid-1].enabled) { 2607 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2608 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2609 return 0; 2610 } 2611 return slotid; 2612 } 2613 2614 /* cleanup slot state on usb device detach */ 2615 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2616 { 2617 int slot, ep; 2618 2619 for (slot = 0; slot < xhci->numslots; slot++) { 2620 if (xhci->slots[slot].uport == uport) { 2621 break; 2622 } 2623 } 2624 if (slot == xhci->numslots) { 2625 return; 2626 } 2627 2628 for (ep = 0; ep < 31; ep++) { 2629 if (xhci->slots[slot].eps[ep]) { 2630 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2631 } 2632 } 2633 xhci->slots[slot].uport = NULL; 2634 } 2635 2636 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2637 { 2638 dma_addr_t ctx; 2639 uint8_t bw_ctx[xhci->numports+1]; 2640 2641 DPRINTF("xhci_get_port_bandwidth()\n"); 2642 2643 ctx = xhci_mask64(pctx); 2644 2645 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2646 2647 /* TODO: actually implement real values here */ 2648 bw_ctx[0] = 0; 2649 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2650 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2651 2652 return CC_SUCCESS; 2653 } 2654 2655 static uint32_t rotl(uint32_t v, unsigned count) 2656 { 2657 count &= 31; 2658 return (v << count) | (v >> (32 - count)); 2659 } 2660 2661 2662 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2663 { 2664 uint32_t val; 2665 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2666 val += rotl(lo + 0x49434878, hi & 0x1F); 2667 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2668 return ~val; 2669 } 2670 2671 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2672 { 2673 PCIDevice *pci_dev = PCI_DEVICE(xhci); 2674 uint32_t buf[8]; 2675 uint32_t obuf[8]; 2676 dma_addr_t paddr = xhci_mask64(addr); 2677 2678 pci_dma_read(pci_dev, paddr, &buf, 32); 2679 2680 memcpy(obuf, buf, sizeof(obuf)); 2681 2682 if ((buf[0] & 0xff) == 2) { 2683 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2684 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2685 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2686 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2687 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2688 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2689 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2690 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2691 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2692 } 2693 2694 pci_dma_write(pci_dev, paddr, &obuf, 32); 2695 } 2696 2697 static void xhci_process_commands(XHCIState *xhci) 2698 { 2699 XHCITRB trb; 2700 TRBType type; 2701 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2702 dma_addr_t addr; 2703 unsigned int i, slotid = 0; 2704 2705 DPRINTF("xhci_process_commands()\n"); 2706 if (!xhci_running(xhci)) { 2707 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2708 return; 2709 } 2710 2711 xhci->crcr_low |= CRCR_CRR; 2712 2713 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2714 event.ptr = addr; 2715 switch (type) { 2716 case CR_ENABLE_SLOT: 2717 for (i = 0; i < xhci->numslots; i++) { 2718 if (!xhci->slots[i].enabled) { 2719 break; 2720 } 2721 } 2722 if (i >= xhci->numslots) { 2723 DPRINTF("xhci: no device slots available\n"); 2724 event.ccode = CC_NO_SLOTS_ERROR; 2725 } else { 2726 slotid = i+1; 2727 event.ccode = xhci_enable_slot(xhci, slotid); 2728 } 2729 break; 2730 case CR_DISABLE_SLOT: 2731 slotid = xhci_get_slot(xhci, &event, &trb); 2732 if (slotid) { 2733 event.ccode = xhci_disable_slot(xhci, slotid); 2734 } 2735 break; 2736 case CR_ADDRESS_DEVICE: 2737 slotid = xhci_get_slot(xhci, &event, &trb); 2738 if (slotid) { 2739 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2740 trb.control & TRB_CR_BSR); 2741 } 2742 break; 2743 case CR_CONFIGURE_ENDPOINT: 2744 slotid = xhci_get_slot(xhci, &event, &trb); 2745 if (slotid) { 2746 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2747 trb.control & TRB_CR_DC); 2748 } 2749 break; 2750 case CR_EVALUATE_CONTEXT: 2751 slotid = xhci_get_slot(xhci, &event, &trb); 2752 if (slotid) { 2753 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2754 } 2755 break; 2756 case CR_STOP_ENDPOINT: 2757 slotid = xhci_get_slot(xhci, &event, &trb); 2758 if (slotid) { 2759 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2760 & TRB_CR_EPID_MASK; 2761 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2762 } 2763 break; 2764 case CR_RESET_ENDPOINT: 2765 slotid = xhci_get_slot(xhci, &event, &trb); 2766 if (slotid) { 2767 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2768 & TRB_CR_EPID_MASK; 2769 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2770 } 2771 break; 2772 case CR_SET_TR_DEQUEUE: 2773 slotid = xhci_get_slot(xhci, &event, &trb); 2774 if (slotid) { 2775 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2776 & TRB_CR_EPID_MASK; 2777 unsigned int streamid = (trb.status >> 16) & 0xffff; 2778 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2779 epid, streamid, 2780 trb.parameter); 2781 } 2782 break; 2783 case CR_RESET_DEVICE: 2784 slotid = xhci_get_slot(xhci, &event, &trb); 2785 if (slotid) { 2786 event.ccode = xhci_reset_slot(xhci, slotid); 2787 } 2788 break; 2789 case CR_GET_PORT_BANDWIDTH: 2790 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2791 break; 2792 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2793 xhci_via_challenge(xhci, trb.parameter); 2794 break; 2795 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2796 event.type = 48; /* NEC reply */ 2797 event.length = 0x3025; 2798 break; 2799 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2800 { 2801 uint32_t chi = trb.parameter >> 32; 2802 uint32_t clo = trb.parameter; 2803 uint32_t val = xhci_nec_challenge(chi, clo); 2804 event.length = val & 0xFFFF; 2805 event.epid = val >> 16; 2806 slotid = val >> 24; 2807 event.type = 48; /* NEC reply */ 2808 } 2809 break; 2810 default: 2811 trace_usb_xhci_unimplemented("command", type); 2812 event.ccode = CC_TRB_ERROR; 2813 break; 2814 } 2815 event.slotid = slotid; 2816 xhci_event(xhci, &event, 0); 2817 } 2818 } 2819 2820 static bool xhci_port_have_device(XHCIPort *port) 2821 { 2822 if (!port->uport->dev || !port->uport->dev->attached) { 2823 return false; /* no device present */ 2824 } 2825 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2826 return false; /* speed mismatch */ 2827 } 2828 return true; 2829 } 2830 2831 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2832 { 2833 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2834 port->portnr << 24 }; 2835 2836 if ((port->portsc & bits) == bits) { 2837 return; 2838 } 2839 trace_usb_xhci_port_notify(port->portnr, bits); 2840 port->portsc |= bits; 2841 if (!xhci_running(port->xhci)) { 2842 return; 2843 } 2844 xhci_event(port->xhci, &ev, 0); 2845 } 2846 2847 static void xhci_port_update(XHCIPort *port, int is_detach) 2848 { 2849 uint32_t pls = PLS_RX_DETECT; 2850 2851 port->portsc = PORTSC_PP; 2852 if (!is_detach && xhci_port_have_device(port)) { 2853 port->portsc |= PORTSC_CCS; 2854 switch (port->uport->dev->speed) { 2855 case USB_SPEED_LOW: 2856 port->portsc |= PORTSC_SPEED_LOW; 2857 pls = PLS_POLLING; 2858 break; 2859 case USB_SPEED_FULL: 2860 port->portsc |= PORTSC_SPEED_FULL; 2861 pls = PLS_POLLING; 2862 break; 2863 case USB_SPEED_HIGH: 2864 port->portsc |= PORTSC_SPEED_HIGH; 2865 pls = PLS_POLLING; 2866 break; 2867 case USB_SPEED_SUPER: 2868 port->portsc |= PORTSC_SPEED_SUPER; 2869 port->portsc |= PORTSC_PED; 2870 pls = PLS_U0; 2871 break; 2872 } 2873 } 2874 set_field(&port->portsc, pls, PORTSC_PLS); 2875 trace_usb_xhci_port_link(port->portnr, pls); 2876 xhci_port_notify(port, PORTSC_CSC); 2877 } 2878 2879 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2880 { 2881 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2882 2883 if (!xhci_port_have_device(port)) { 2884 return; 2885 } 2886 2887 usb_device_reset(port->uport->dev); 2888 2889 switch (port->uport->dev->speed) { 2890 case USB_SPEED_SUPER: 2891 if (warm_reset) { 2892 port->portsc |= PORTSC_WRC; 2893 } 2894 /* fall through */ 2895 case USB_SPEED_LOW: 2896 case USB_SPEED_FULL: 2897 case USB_SPEED_HIGH: 2898 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2899 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2900 port->portsc |= PORTSC_PED; 2901 break; 2902 } 2903 2904 port->portsc &= ~PORTSC_PR; 2905 xhci_port_notify(port, PORTSC_PRC); 2906 } 2907 2908 static void xhci_reset(DeviceState *dev) 2909 { 2910 XHCIState *xhci = XHCI(dev); 2911 int i; 2912 2913 trace_usb_xhci_reset(); 2914 if (!(xhci->usbsts & USBSTS_HCH)) { 2915 DPRINTF("xhci: reset while running!\n"); 2916 } 2917 2918 xhci->usbcmd = 0; 2919 xhci->usbsts = USBSTS_HCH; 2920 xhci->dnctrl = 0; 2921 xhci->crcr_low = 0; 2922 xhci->crcr_high = 0; 2923 xhci->dcbaap_low = 0; 2924 xhci->dcbaap_high = 0; 2925 xhci->config = 0; 2926 2927 for (i = 0; i < xhci->numslots; i++) { 2928 xhci_disable_slot(xhci, i+1); 2929 } 2930 2931 for (i = 0; i < xhci->numports; i++) { 2932 xhci_port_update(xhci->ports + i, 0); 2933 } 2934 2935 for (i = 0; i < xhci->numintrs; i++) { 2936 xhci->intr[i].iman = 0; 2937 xhci->intr[i].imod = 0; 2938 xhci->intr[i].erstsz = 0; 2939 xhci->intr[i].erstba_low = 0; 2940 xhci->intr[i].erstba_high = 0; 2941 xhci->intr[i].erdp_low = 0; 2942 xhci->intr[i].erdp_high = 0; 2943 xhci->intr[i].msix_used = 0; 2944 2945 xhci->intr[i].er_ep_idx = 0; 2946 xhci->intr[i].er_pcs = 1; 2947 xhci->intr[i].er_full = 0; 2948 xhci->intr[i].ev_buffer_put = 0; 2949 xhci->intr[i].ev_buffer_get = 0; 2950 } 2951 2952 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2953 xhci_mfwrap_update(xhci); 2954 } 2955 2956 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2957 { 2958 XHCIState *xhci = ptr; 2959 uint32_t ret; 2960 2961 switch (reg) { 2962 case 0x00: /* HCIVERSION, CAPLENGTH */ 2963 ret = 0x01000000 | LEN_CAP; 2964 break; 2965 case 0x04: /* HCSPARAMS 1 */ 2966 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2967 | (xhci->numintrs<<8) | xhci->numslots; 2968 break; 2969 case 0x08: /* HCSPARAMS 2 */ 2970 ret = 0x0000000f; 2971 break; 2972 case 0x0c: /* HCSPARAMS 3 */ 2973 ret = 0x00000000; 2974 break; 2975 case 0x10: /* HCCPARAMS */ 2976 if (sizeof(dma_addr_t) == 4) { 2977 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 2978 } else { 2979 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 2980 } 2981 break; 2982 case 0x14: /* DBOFF */ 2983 ret = OFF_DOORBELL; 2984 break; 2985 case 0x18: /* RTSOFF */ 2986 ret = OFF_RUNTIME; 2987 break; 2988 2989 /* extended capabilities */ 2990 case 0x20: /* Supported Protocol:00 */ 2991 ret = 0x02000402; /* USB 2.0 */ 2992 break; 2993 case 0x24: /* Supported Protocol:04 */ 2994 ret = 0x20425355; /* "USB " */ 2995 break; 2996 case 0x28: /* Supported Protocol:08 */ 2997 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2998 ret = (xhci->numports_2<<8) | (xhci->numports_3+1); 2999 } else { 3000 ret = (xhci->numports_2<<8) | 1; 3001 } 3002 break; 3003 case 0x2c: /* Supported Protocol:0c */ 3004 ret = 0x00000000; /* reserved */ 3005 break; 3006 case 0x30: /* Supported Protocol:00 */ 3007 ret = 0x03000002; /* USB 3.0 */ 3008 break; 3009 case 0x34: /* Supported Protocol:04 */ 3010 ret = 0x20425355; /* "USB " */ 3011 break; 3012 case 0x38: /* Supported Protocol:08 */ 3013 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3014 ret = (xhci->numports_3<<8) | 1; 3015 } else { 3016 ret = (xhci->numports_3<<8) | (xhci->numports_2+1); 3017 } 3018 break; 3019 case 0x3c: /* Supported Protocol:0c */ 3020 ret = 0x00000000; /* reserved */ 3021 break; 3022 default: 3023 trace_usb_xhci_unimplemented("cap read", reg); 3024 ret = 0; 3025 } 3026 3027 trace_usb_xhci_cap_read(reg, ret); 3028 return ret; 3029 } 3030 3031 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 3032 { 3033 XHCIPort *port = ptr; 3034 uint32_t ret; 3035 3036 switch (reg) { 3037 case 0x00: /* PORTSC */ 3038 ret = port->portsc; 3039 break; 3040 case 0x04: /* PORTPMSC */ 3041 case 0x08: /* PORTLI */ 3042 ret = 0; 3043 break; 3044 case 0x0c: /* reserved */ 3045 default: 3046 trace_usb_xhci_unimplemented("port read", reg); 3047 ret = 0; 3048 } 3049 3050 trace_usb_xhci_port_read(port->portnr, reg, ret); 3051 return ret; 3052 } 3053 3054 static void xhci_port_write(void *ptr, hwaddr reg, 3055 uint64_t val, unsigned size) 3056 { 3057 XHCIPort *port = ptr; 3058 uint32_t portsc, notify; 3059 3060 trace_usb_xhci_port_write(port->portnr, reg, val); 3061 3062 switch (reg) { 3063 case 0x00: /* PORTSC */ 3064 /* write-1-to-start bits */ 3065 if (val & PORTSC_WPR) { 3066 xhci_port_reset(port, true); 3067 break; 3068 } 3069 if (val & PORTSC_PR) { 3070 xhci_port_reset(port, false); 3071 break; 3072 } 3073 3074 portsc = port->portsc; 3075 notify = 0; 3076 /* write-1-to-clear bits*/ 3077 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 3078 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 3079 if (val & PORTSC_LWS) { 3080 /* overwrite PLS only when LWS=1 */ 3081 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 3082 uint32_t new_pls = get_field(val, PORTSC_PLS); 3083 switch (new_pls) { 3084 case PLS_U0: 3085 if (old_pls != PLS_U0) { 3086 set_field(&portsc, new_pls, PORTSC_PLS); 3087 trace_usb_xhci_port_link(port->portnr, new_pls); 3088 notify = PORTSC_PLC; 3089 } 3090 break; 3091 case PLS_U3: 3092 if (old_pls < PLS_U3) { 3093 set_field(&portsc, new_pls, PORTSC_PLS); 3094 trace_usb_xhci_port_link(port->portnr, new_pls); 3095 } 3096 break; 3097 case PLS_RESUME: 3098 /* windows does this for some reason, don't spam stderr */ 3099 break; 3100 default: 3101 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 3102 __func__, old_pls, new_pls); 3103 break; 3104 } 3105 } 3106 /* read/write bits */ 3107 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 3108 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 3109 port->portsc = portsc; 3110 if (notify) { 3111 xhci_port_notify(port, notify); 3112 } 3113 break; 3114 case 0x04: /* PORTPMSC */ 3115 case 0x08: /* PORTLI */ 3116 default: 3117 trace_usb_xhci_unimplemented("port write", reg); 3118 } 3119 } 3120 3121 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 3122 { 3123 XHCIState *xhci = ptr; 3124 uint32_t ret; 3125 3126 switch (reg) { 3127 case 0x00: /* USBCMD */ 3128 ret = xhci->usbcmd; 3129 break; 3130 case 0x04: /* USBSTS */ 3131 ret = xhci->usbsts; 3132 break; 3133 case 0x08: /* PAGESIZE */ 3134 ret = 1; /* 4KiB */ 3135 break; 3136 case 0x14: /* DNCTRL */ 3137 ret = xhci->dnctrl; 3138 break; 3139 case 0x18: /* CRCR low */ 3140 ret = xhci->crcr_low & ~0xe; 3141 break; 3142 case 0x1c: /* CRCR high */ 3143 ret = xhci->crcr_high; 3144 break; 3145 case 0x30: /* DCBAAP low */ 3146 ret = xhci->dcbaap_low; 3147 break; 3148 case 0x34: /* DCBAAP high */ 3149 ret = xhci->dcbaap_high; 3150 break; 3151 case 0x38: /* CONFIG */ 3152 ret = xhci->config; 3153 break; 3154 default: 3155 trace_usb_xhci_unimplemented("oper read", reg); 3156 ret = 0; 3157 } 3158 3159 trace_usb_xhci_oper_read(reg, ret); 3160 return ret; 3161 } 3162 3163 static void xhci_oper_write(void *ptr, hwaddr reg, 3164 uint64_t val, unsigned size) 3165 { 3166 XHCIState *xhci = ptr; 3167 DeviceState *d = DEVICE(ptr); 3168 3169 trace_usb_xhci_oper_write(reg, val); 3170 3171 switch (reg) { 3172 case 0x00: /* USBCMD */ 3173 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3174 xhci_run(xhci); 3175 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3176 xhci_stop(xhci); 3177 } 3178 if (val & USBCMD_CSS) { 3179 /* save state */ 3180 xhci->usbsts &= ~USBSTS_SRE; 3181 } 3182 if (val & USBCMD_CRS) { 3183 /* restore state */ 3184 xhci->usbsts |= USBSTS_SRE; 3185 } 3186 xhci->usbcmd = val & 0xc0f; 3187 xhci_mfwrap_update(xhci); 3188 if (val & USBCMD_HCRST) { 3189 xhci_reset(d); 3190 } 3191 xhci_intx_update(xhci); 3192 break; 3193 3194 case 0x04: /* USBSTS */ 3195 /* these bits are write-1-to-clear */ 3196 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3197 xhci_intx_update(xhci); 3198 break; 3199 3200 case 0x14: /* DNCTRL */ 3201 xhci->dnctrl = val & 0xffff; 3202 break; 3203 case 0x18: /* CRCR low */ 3204 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3205 break; 3206 case 0x1c: /* CRCR high */ 3207 xhci->crcr_high = val; 3208 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3209 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3210 xhci->crcr_low &= ~CRCR_CRR; 3211 xhci_event(xhci, &event, 0); 3212 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3213 } else { 3214 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3215 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3216 } 3217 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3218 break; 3219 case 0x30: /* DCBAAP low */ 3220 xhci->dcbaap_low = val & 0xffffffc0; 3221 break; 3222 case 0x34: /* DCBAAP high */ 3223 xhci->dcbaap_high = val; 3224 break; 3225 case 0x38: /* CONFIG */ 3226 xhci->config = val & 0xff; 3227 break; 3228 default: 3229 trace_usb_xhci_unimplemented("oper write", reg); 3230 } 3231 } 3232 3233 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3234 unsigned size) 3235 { 3236 XHCIState *xhci = ptr; 3237 uint32_t ret = 0; 3238 3239 if (reg < 0x20) { 3240 switch (reg) { 3241 case 0x00: /* MFINDEX */ 3242 ret = xhci_mfindex_get(xhci) & 0x3fff; 3243 break; 3244 default: 3245 trace_usb_xhci_unimplemented("runtime read", reg); 3246 break; 3247 } 3248 } else { 3249 int v = (reg - 0x20) / 0x20; 3250 XHCIInterrupter *intr = &xhci->intr[v]; 3251 switch (reg & 0x1f) { 3252 case 0x00: /* IMAN */ 3253 ret = intr->iman; 3254 break; 3255 case 0x04: /* IMOD */ 3256 ret = intr->imod; 3257 break; 3258 case 0x08: /* ERSTSZ */ 3259 ret = intr->erstsz; 3260 break; 3261 case 0x10: /* ERSTBA low */ 3262 ret = intr->erstba_low; 3263 break; 3264 case 0x14: /* ERSTBA high */ 3265 ret = intr->erstba_high; 3266 break; 3267 case 0x18: /* ERDP low */ 3268 ret = intr->erdp_low; 3269 break; 3270 case 0x1c: /* ERDP high */ 3271 ret = intr->erdp_high; 3272 break; 3273 } 3274 } 3275 3276 trace_usb_xhci_runtime_read(reg, ret); 3277 return ret; 3278 } 3279 3280 static void xhci_runtime_write(void *ptr, hwaddr reg, 3281 uint64_t val, unsigned size) 3282 { 3283 XHCIState *xhci = ptr; 3284 int v = (reg - 0x20) / 0x20; 3285 XHCIInterrupter *intr = &xhci->intr[v]; 3286 trace_usb_xhci_runtime_write(reg, val); 3287 3288 if (reg < 0x20) { 3289 trace_usb_xhci_unimplemented("runtime write", reg); 3290 return; 3291 } 3292 3293 switch (reg & 0x1f) { 3294 case 0x00: /* IMAN */ 3295 if (val & IMAN_IP) { 3296 intr->iman &= ~IMAN_IP; 3297 } 3298 intr->iman &= ~IMAN_IE; 3299 intr->iman |= val & IMAN_IE; 3300 if (v == 0) { 3301 xhci_intx_update(xhci); 3302 } 3303 xhci_msix_update(xhci, v); 3304 break; 3305 case 0x04: /* IMOD */ 3306 intr->imod = val; 3307 break; 3308 case 0x08: /* ERSTSZ */ 3309 intr->erstsz = val & 0xffff; 3310 break; 3311 case 0x10: /* ERSTBA low */ 3312 /* XXX NEC driver bug: it doesn't align this to 64 bytes 3313 intr->erstba_low = val & 0xffffffc0; */ 3314 intr->erstba_low = val & 0xfffffff0; 3315 break; 3316 case 0x14: /* ERSTBA high */ 3317 intr->erstba_high = val; 3318 xhci_er_reset(xhci, v); 3319 break; 3320 case 0x18: /* ERDP low */ 3321 if (val & ERDP_EHB) { 3322 intr->erdp_low &= ~ERDP_EHB; 3323 } 3324 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3325 break; 3326 case 0x1c: /* ERDP high */ 3327 intr->erdp_high = val; 3328 xhci_events_update(xhci, v); 3329 break; 3330 default: 3331 trace_usb_xhci_unimplemented("oper write", reg); 3332 } 3333 } 3334 3335 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3336 unsigned size) 3337 { 3338 /* doorbells always read as 0 */ 3339 trace_usb_xhci_doorbell_read(reg, 0); 3340 return 0; 3341 } 3342 3343 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3344 uint64_t val, unsigned size) 3345 { 3346 XHCIState *xhci = ptr; 3347 unsigned int epid, streamid; 3348 3349 trace_usb_xhci_doorbell_write(reg, val); 3350 3351 if (!xhci_running(xhci)) { 3352 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3353 return; 3354 } 3355 3356 reg >>= 2; 3357 3358 if (reg == 0) { 3359 if (val == 0) { 3360 xhci_process_commands(xhci); 3361 } else { 3362 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3363 (uint32_t)val); 3364 } 3365 } else { 3366 epid = val & 0xff; 3367 streamid = (val >> 16) & 0xffff; 3368 if (reg > xhci->numslots) { 3369 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3370 } else if (epid > 31) { 3371 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3372 (int)reg, (uint32_t)val); 3373 } else { 3374 xhci_kick_ep(xhci, reg, epid, streamid); 3375 } 3376 } 3377 } 3378 3379 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3380 unsigned width) 3381 { 3382 /* nothing */ 3383 } 3384 3385 static const MemoryRegionOps xhci_cap_ops = { 3386 .read = xhci_cap_read, 3387 .write = xhci_cap_write, 3388 .valid.min_access_size = 1, 3389 .valid.max_access_size = 4, 3390 .impl.min_access_size = 4, 3391 .impl.max_access_size = 4, 3392 .endianness = DEVICE_LITTLE_ENDIAN, 3393 }; 3394 3395 static const MemoryRegionOps xhci_oper_ops = { 3396 .read = xhci_oper_read, 3397 .write = xhci_oper_write, 3398 .valid.min_access_size = 4, 3399 .valid.max_access_size = 4, 3400 .endianness = DEVICE_LITTLE_ENDIAN, 3401 }; 3402 3403 static const MemoryRegionOps xhci_port_ops = { 3404 .read = xhci_port_read, 3405 .write = xhci_port_write, 3406 .valid.min_access_size = 4, 3407 .valid.max_access_size = 4, 3408 .endianness = DEVICE_LITTLE_ENDIAN, 3409 }; 3410 3411 static const MemoryRegionOps xhci_runtime_ops = { 3412 .read = xhci_runtime_read, 3413 .write = xhci_runtime_write, 3414 .valid.min_access_size = 4, 3415 .valid.max_access_size = 4, 3416 .endianness = DEVICE_LITTLE_ENDIAN, 3417 }; 3418 3419 static const MemoryRegionOps xhci_doorbell_ops = { 3420 .read = xhci_doorbell_read, 3421 .write = xhci_doorbell_write, 3422 .valid.min_access_size = 4, 3423 .valid.max_access_size = 4, 3424 .endianness = DEVICE_LITTLE_ENDIAN, 3425 }; 3426 3427 static void xhci_attach(USBPort *usbport) 3428 { 3429 XHCIState *xhci = usbport->opaque; 3430 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3431 3432 xhci_port_update(port, 0); 3433 } 3434 3435 static void xhci_detach(USBPort *usbport) 3436 { 3437 XHCIState *xhci = usbport->opaque; 3438 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3439 3440 xhci_detach_slot(xhci, usbport); 3441 xhci_port_update(port, 1); 3442 } 3443 3444 static void xhci_wakeup(USBPort *usbport) 3445 { 3446 XHCIState *xhci = usbport->opaque; 3447 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3448 3449 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3450 return; 3451 } 3452 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3453 xhci_port_notify(port, PORTSC_PLC); 3454 } 3455 3456 static void xhci_complete(USBPort *port, USBPacket *packet) 3457 { 3458 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3459 3460 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3461 xhci_ep_nuke_one_xfer(xfer, 0); 3462 return; 3463 } 3464 xhci_complete_packet(xfer); 3465 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); 3466 } 3467 3468 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3469 { 3470 USBBus *bus = usb_bus_from_device(child); 3471 XHCIState *xhci = container_of(bus, XHCIState, bus); 3472 3473 xhci_detach_slot(xhci, child->port); 3474 } 3475 3476 static USBPortOps xhci_uport_ops = { 3477 .attach = xhci_attach, 3478 .detach = xhci_detach, 3479 .wakeup = xhci_wakeup, 3480 .complete = xhci_complete, 3481 .child_detach = xhci_child_detach, 3482 }; 3483 3484 static int xhci_find_epid(USBEndpoint *ep) 3485 { 3486 if (ep->nr == 0) { 3487 return 1; 3488 } 3489 if (ep->pid == USB_TOKEN_IN) { 3490 return ep->nr * 2 + 1; 3491 } else { 3492 return ep->nr * 2; 3493 } 3494 } 3495 3496 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci, 3497 unsigned int slotid, unsigned int epid) 3498 { 3499 assert(slotid >= 1 && slotid <= xhci->numslots); 3500 3501 if (!xhci->slots[slotid - 1].uport) { 3502 return NULL; 3503 } 3504 3505 return usb_ep_get(xhci->slots[slotid - 1].uport->dev, 3506 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1); 3507 } 3508 3509 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3510 unsigned int stream) 3511 { 3512 XHCIState *xhci = container_of(bus, XHCIState, bus); 3513 int slotid; 3514 3515 DPRINTF("%s\n", __func__); 3516 slotid = ep->dev->addr; 3517 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3518 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3519 return; 3520 } 3521 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3522 } 3523 3524 static USBBusOps xhci_bus_ops = { 3525 .wakeup_endpoint = xhci_wakeup_endpoint, 3526 }; 3527 3528 static void usb_xhci_init(XHCIState *xhci) 3529 { 3530 DeviceState *dev = DEVICE(xhci); 3531 XHCIPort *port; 3532 int i, usbports, speedmask; 3533 3534 xhci->usbsts = USBSTS_HCH; 3535 3536 if (xhci->numports_2 > MAXPORTS_2) { 3537 xhci->numports_2 = MAXPORTS_2; 3538 } 3539 if (xhci->numports_3 > MAXPORTS_3) { 3540 xhci->numports_3 = MAXPORTS_3; 3541 } 3542 usbports = MAX(xhci->numports_2, xhci->numports_3); 3543 xhci->numports = xhci->numports_2 + xhci->numports_3; 3544 3545 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3546 3547 for (i = 0; i < usbports; i++) { 3548 speedmask = 0; 3549 if (i < xhci->numports_2) { 3550 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3551 port = &xhci->ports[i + xhci->numports_3]; 3552 port->portnr = i + 1 + xhci->numports_3; 3553 } else { 3554 port = &xhci->ports[i]; 3555 port->portnr = i + 1; 3556 } 3557 port->uport = &xhci->uports[i]; 3558 port->speedmask = 3559 USB_SPEED_MASK_LOW | 3560 USB_SPEED_MASK_FULL | 3561 USB_SPEED_MASK_HIGH; 3562 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3563 speedmask |= port->speedmask; 3564 } 3565 if (i < xhci->numports_3) { 3566 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3567 port = &xhci->ports[i]; 3568 port->portnr = i + 1; 3569 } else { 3570 port = &xhci->ports[i + xhci->numports_2]; 3571 port->portnr = i + 1 + xhci->numports_2; 3572 } 3573 port->uport = &xhci->uports[i]; 3574 port->speedmask = USB_SPEED_MASK_SUPER; 3575 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3576 speedmask |= port->speedmask; 3577 } 3578 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3579 &xhci_uport_ops, speedmask); 3580 } 3581 } 3582 3583 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) 3584 { 3585 int i, ret; 3586 Error *err = NULL; 3587 3588 XHCIState *xhci = XHCI(dev); 3589 3590 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3591 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3592 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3593 dev->config[0x60] = 0x30; /* release number */ 3594 3595 usb_xhci_init(xhci); 3596 3597 if (xhci->msi != ON_OFF_AUTO_OFF) { 3598 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); 3599 /* Any error other than -ENOTSUP(board's MSI support is broken) 3600 * is a programming error */ 3601 assert(!ret || ret == -ENOTSUP); 3602 if (ret && xhci->msi == ON_OFF_AUTO_ON) { 3603 /* Can't satisfy user's explicit msi=on request, fail */ 3604 error_append_hint(&err, "You have to use msi=auto (default) or " 3605 "msi=off with this machine type.\n"); 3606 error_propagate(errp, err); 3607 return; 3608 } 3609 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); 3610 /* With msi=auto, we fall back to MSI off silently */ 3611 error_free(err); 3612 } 3613 3614 if (xhci->numintrs > MAXINTRS) { 3615 xhci->numintrs = MAXINTRS; 3616 } 3617 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3618 xhci->numintrs++; 3619 } 3620 if (xhci->numintrs < 1) { 3621 xhci->numintrs = 1; 3622 } 3623 if (xhci->numslots > MAXSLOTS) { 3624 xhci->numslots = MAXSLOTS; 3625 } 3626 if (xhci->numslots < 1) { 3627 xhci->numslots = 1; 3628 } 3629 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3630 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3631 } else { 3632 xhci->max_pstreams_mask = 0; 3633 } 3634 3635 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3636 3637 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3638 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3639 "capabilities", LEN_CAP); 3640 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3641 "operational", 0x400); 3642 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3643 "runtime", LEN_RUNTIME); 3644 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3645 "doorbell", LEN_DOORBELL); 3646 3647 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3648 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3649 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3650 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3651 3652 for (i = 0; i < xhci->numports; i++) { 3653 XHCIPort *port = &xhci->ports[i]; 3654 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3655 port->xhci = xhci; 3656 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3657 port->name, 0x10); 3658 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3659 } 3660 3661 pci_register_bar(dev, 0, 3662 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3663 &xhci->mem); 3664 3665 if (pci_bus_is_express(dev->bus) || 3666 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 3667 ret = pcie_endpoint_cap_init(dev, 0xa0); 3668 assert(ret >= 0); 3669 } 3670 3671 if (xhci->msix != ON_OFF_AUTO_OFF) { 3672 /* TODO check for errors */ 3673 msix_init(dev, xhci->numintrs, 3674 &xhci->mem, 0, OFF_MSIX_TABLE, 3675 &xhci->mem, 0, OFF_MSIX_PBA, 3676 0x90); 3677 } 3678 } 3679 3680 static void usb_xhci_exit(PCIDevice *dev) 3681 { 3682 int i; 3683 XHCIState *xhci = XHCI(dev); 3684 3685 trace_usb_xhci_exit(); 3686 3687 for (i = 0; i < xhci->numslots; i++) { 3688 xhci_disable_slot(xhci, i + 1); 3689 } 3690 3691 if (xhci->mfwrap_timer) { 3692 timer_del(xhci->mfwrap_timer); 3693 timer_free(xhci->mfwrap_timer); 3694 xhci->mfwrap_timer = NULL; 3695 } 3696 3697 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3698 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3699 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3700 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3701 3702 for (i = 0; i < xhci->numports; i++) { 3703 XHCIPort *port = &xhci->ports[i]; 3704 memory_region_del_subregion(&xhci->mem, &port->mem); 3705 } 3706 3707 /* destroy msix memory region */ 3708 if (dev->msix_table && dev->msix_pba 3709 && dev->msix_entry_used) { 3710 memory_region_del_subregion(&xhci->mem, &dev->msix_table_mmio); 3711 memory_region_del_subregion(&xhci->mem, &dev->msix_pba_mmio); 3712 } 3713 3714 usb_bus_release(&xhci->bus); 3715 } 3716 3717 static int usb_xhci_post_load(void *opaque, int version_id) 3718 { 3719 XHCIState *xhci = opaque; 3720 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3721 XHCISlot *slot; 3722 XHCIEPContext *epctx; 3723 dma_addr_t dcbaap, pctx; 3724 uint32_t slot_ctx[4]; 3725 uint32_t ep_ctx[5]; 3726 int slotid, epid, state, intr; 3727 3728 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3729 3730 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3731 slot = &xhci->slots[slotid-1]; 3732 if (!slot->addressed) { 3733 continue; 3734 } 3735 slot->ctx = 3736 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3737 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3738 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3739 if (!slot->uport) { 3740 /* should not happen, but may trigger on guest bugs */ 3741 slot->enabled = 0; 3742 slot->addressed = 0; 3743 continue; 3744 } 3745 assert(slot->uport && slot->uport->dev); 3746 3747 for (epid = 1; epid <= 31; epid++) { 3748 pctx = slot->ctx + 32 * epid; 3749 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3750 state = ep_ctx[0] & EP_STATE_MASK; 3751 if (state == EP_DISABLED) { 3752 continue; 3753 } 3754 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3755 slot->eps[epid-1] = epctx; 3756 xhci_init_epctx(epctx, pctx, ep_ctx); 3757 epctx->state = state; 3758 if (state == EP_RUNNING) { 3759 /* kick endpoint after vmload is finished */ 3760 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3761 } 3762 } 3763 } 3764 3765 for (intr = 0; intr < xhci->numintrs; intr++) { 3766 if (xhci->intr[intr].msix_used) { 3767 msix_vector_use(pci_dev, intr); 3768 } else { 3769 msix_vector_unuse(pci_dev, intr); 3770 } 3771 } 3772 3773 return 0; 3774 } 3775 3776 static const VMStateDescription vmstate_xhci_ring = { 3777 .name = "xhci-ring", 3778 .version_id = 1, 3779 .fields = (VMStateField[]) { 3780 VMSTATE_UINT64(dequeue, XHCIRing), 3781 VMSTATE_BOOL(ccs, XHCIRing), 3782 VMSTATE_END_OF_LIST() 3783 } 3784 }; 3785 3786 static const VMStateDescription vmstate_xhci_port = { 3787 .name = "xhci-port", 3788 .version_id = 1, 3789 .fields = (VMStateField[]) { 3790 VMSTATE_UINT32(portsc, XHCIPort), 3791 VMSTATE_END_OF_LIST() 3792 } 3793 }; 3794 3795 static const VMStateDescription vmstate_xhci_slot = { 3796 .name = "xhci-slot", 3797 .version_id = 1, 3798 .fields = (VMStateField[]) { 3799 VMSTATE_BOOL(enabled, XHCISlot), 3800 VMSTATE_BOOL(addressed, XHCISlot), 3801 VMSTATE_END_OF_LIST() 3802 } 3803 }; 3804 3805 static const VMStateDescription vmstate_xhci_event = { 3806 .name = "xhci-event", 3807 .version_id = 1, 3808 .fields = (VMStateField[]) { 3809 VMSTATE_UINT32(type, XHCIEvent), 3810 VMSTATE_UINT32(ccode, XHCIEvent), 3811 VMSTATE_UINT64(ptr, XHCIEvent), 3812 VMSTATE_UINT32(length, XHCIEvent), 3813 VMSTATE_UINT32(flags, XHCIEvent), 3814 VMSTATE_UINT8(slotid, XHCIEvent), 3815 VMSTATE_UINT8(epid, XHCIEvent), 3816 VMSTATE_END_OF_LIST() 3817 } 3818 }; 3819 3820 static bool xhci_er_full(void *opaque, int version_id) 3821 { 3822 struct XHCIInterrupter *intr = opaque; 3823 return intr->er_full; 3824 } 3825 3826 static const VMStateDescription vmstate_xhci_intr = { 3827 .name = "xhci-intr", 3828 .version_id = 1, 3829 .fields = (VMStateField[]) { 3830 /* registers */ 3831 VMSTATE_UINT32(iman, XHCIInterrupter), 3832 VMSTATE_UINT32(imod, XHCIInterrupter), 3833 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3834 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3835 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3836 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3837 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3838 3839 /* state */ 3840 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3841 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3842 VMSTATE_UINT64(er_start, XHCIInterrupter), 3843 VMSTATE_UINT32(er_size, XHCIInterrupter), 3844 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3845 3846 /* event queue (used if ring is full) */ 3847 VMSTATE_BOOL(er_full, XHCIInterrupter), 3848 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3849 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3850 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3851 xhci_er_full, 1, 3852 vmstate_xhci_event, XHCIEvent), 3853 3854 VMSTATE_END_OF_LIST() 3855 } 3856 }; 3857 3858 static const VMStateDescription vmstate_xhci = { 3859 .name = "xhci", 3860 .version_id = 1, 3861 .post_load = usb_xhci_post_load, 3862 .fields = (VMStateField[]) { 3863 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState), 3864 VMSTATE_MSIX(parent_obj, XHCIState), 3865 3866 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3867 vmstate_xhci_port, XHCIPort), 3868 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3869 vmstate_xhci_slot, XHCISlot), 3870 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3871 vmstate_xhci_intr, XHCIInterrupter), 3872 3873 /* Operational Registers */ 3874 VMSTATE_UINT32(usbcmd, XHCIState), 3875 VMSTATE_UINT32(usbsts, XHCIState), 3876 VMSTATE_UINT32(dnctrl, XHCIState), 3877 VMSTATE_UINT32(crcr_low, XHCIState), 3878 VMSTATE_UINT32(crcr_high, XHCIState), 3879 VMSTATE_UINT32(dcbaap_low, XHCIState), 3880 VMSTATE_UINT32(dcbaap_high, XHCIState), 3881 VMSTATE_UINT32(config, XHCIState), 3882 3883 /* Runtime Registers & state */ 3884 VMSTATE_INT64(mfindex_start, XHCIState), 3885 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3886 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3887 3888 VMSTATE_END_OF_LIST() 3889 } 3890 }; 3891 3892 static Property xhci_properties[] = { 3893 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO), 3894 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO), 3895 DEFINE_PROP_BIT("superspeed-ports-first", 3896 XHCIState, flags, XHCI_FLAG_SS_FIRST, true), 3897 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, 3898 XHCI_FLAG_FORCE_PCIE_ENDCAP, false), 3899 DEFINE_PROP_BIT("streams", XHCIState, flags, 3900 XHCI_FLAG_ENABLE_STREAMS, true), 3901 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3902 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3903 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3904 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3905 DEFINE_PROP_END_OF_LIST(), 3906 }; 3907 3908 static void xhci_class_init(ObjectClass *klass, void *data) 3909 { 3910 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3911 DeviceClass *dc = DEVICE_CLASS(klass); 3912 3913 dc->vmsd = &vmstate_xhci; 3914 dc->props = xhci_properties; 3915 dc->reset = xhci_reset; 3916 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3917 k->realize = usb_xhci_realize; 3918 k->exit = usb_xhci_exit; 3919 k->vendor_id = PCI_VENDOR_ID_NEC; 3920 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3921 k->class_id = PCI_CLASS_SERIAL_USB; 3922 k->revision = 0x03; 3923 k->is_express = 1; 3924 } 3925 3926 static const TypeInfo xhci_info = { 3927 .name = TYPE_XHCI, 3928 .parent = TYPE_PCI_DEVICE, 3929 .instance_size = sizeof(XHCIState), 3930 .class_init = xhci_class_init, 3931 }; 3932 3933 static void xhci_register_types(void) 3934 { 3935 type_register_static(&xhci_info); 3936 } 3937 3938 type_init(xhci_register_types) 3939