1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "qemu/queue.h" 25 #include "hw/usb.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/msix.h" 29 #include "trace.h" 30 #include "qapi/error.h" 31 32 //#define DEBUG_XHCI 33 //#define DEBUG_DATA 34 35 #ifdef DEBUG_XHCI 36 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 37 #else 38 #define DPRINTF(...) do {} while (0) 39 #endif 40 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 41 __func__, __LINE__, _msg); abort(); } while (0) 42 43 #define MAXPORTS_2 15 44 #define MAXPORTS_3 15 45 46 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 47 #define MAXSLOTS 64 48 #define MAXINTRS 16 49 50 /* Very pessimistic, let's hope it's enough for all cases */ 51 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 52 53 #define TRB_LINK_LIMIT 4 54 #define COMMAND_LIMIT 256 55 #define TRANSFER_LIMIT 256 56 57 #define LEN_CAP 0x40 58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 59 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 60 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 61 62 #define OFF_OPER LEN_CAP 63 #define OFF_RUNTIME 0x1000 64 #define OFF_DOORBELL 0x2000 65 #define OFF_MSIX_TABLE 0x3000 66 #define OFF_MSIX_PBA 0x3800 67 /* must be power of 2 */ 68 #define LEN_REGS 0x4000 69 70 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 71 #error Increase OFF_RUNTIME 72 #endif 73 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 74 #error Increase OFF_DOORBELL 75 #endif 76 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 77 # error Increase LEN_REGS 78 #endif 79 80 /* bit definitions */ 81 #define USBCMD_RS (1<<0) 82 #define USBCMD_HCRST (1<<1) 83 #define USBCMD_INTE (1<<2) 84 #define USBCMD_HSEE (1<<3) 85 #define USBCMD_LHCRST (1<<7) 86 #define USBCMD_CSS (1<<8) 87 #define USBCMD_CRS (1<<9) 88 #define USBCMD_EWE (1<<10) 89 #define USBCMD_EU3S (1<<11) 90 91 #define USBSTS_HCH (1<<0) 92 #define USBSTS_HSE (1<<2) 93 #define USBSTS_EINT (1<<3) 94 #define USBSTS_PCD (1<<4) 95 #define USBSTS_SSS (1<<8) 96 #define USBSTS_RSS (1<<9) 97 #define USBSTS_SRE (1<<10) 98 #define USBSTS_CNR (1<<11) 99 #define USBSTS_HCE (1<<12) 100 101 102 #define PORTSC_CCS (1<<0) 103 #define PORTSC_PED (1<<1) 104 #define PORTSC_OCA (1<<3) 105 #define PORTSC_PR (1<<4) 106 #define PORTSC_PLS_SHIFT 5 107 #define PORTSC_PLS_MASK 0xf 108 #define PORTSC_PP (1<<9) 109 #define PORTSC_SPEED_SHIFT 10 110 #define PORTSC_SPEED_MASK 0xf 111 #define PORTSC_SPEED_FULL (1<<10) 112 #define PORTSC_SPEED_LOW (2<<10) 113 #define PORTSC_SPEED_HIGH (3<<10) 114 #define PORTSC_SPEED_SUPER (4<<10) 115 #define PORTSC_PIC_SHIFT 14 116 #define PORTSC_PIC_MASK 0x3 117 #define PORTSC_LWS (1<<16) 118 #define PORTSC_CSC (1<<17) 119 #define PORTSC_PEC (1<<18) 120 #define PORTSC_WRC (1<<19) 121 #define PORTSC_OCC (1<<20) 122 #define PORTSC_PRC (1<<21) 123 #define PORTSC_PLC (1<<22) 124 #define PORTSC_CEC (1<<23) 125 #define PORTSC_CAS (1<<24) 126 #define PORTSC_WCE (1<<25) 127 #define PORTSC_WDE (1<<26) 128 #define PORTSC_WOE (1<<27) 129 #define PORTSC_DR (1<<30) 130 #define PORTSC_WPR (1<<31) 131 132 #define CRCR_RCS (1<<0) 133 #define CRCR_CS (1<<1) 134 #define CRCR_CA (1<<2) 135 #define CRCR_CRR (1<<3) 136 137 #define IMAN_IP (1<<0) 138 #define IMAN_IE (1<<1) 139 140 #define ERDP_EHB (1<<3) 141 142 #define TRB_SIZE 16 143 typedef struct XHCITRB { 144 uint64_t parameter; 145 uint32_t status; 146 uint32_t control; 147 dma_addr_t addr; 148 bool ccs; 149 } XHCITRB; 150 151 enum { 152 PLS_U0 = 0, 153 PLS_U1 = 1, 154 PLS_U2 = 2, 155 PLS_U3 = 3, 156 PLS_DISABLED = 4, 157 PLS_RX_DETECT = 5, 158 PLS_INACTIVE = 6, 159 PLS_POLLING = 7, 160 PLS_RECOVERY = 8, 161 PLS_HOT_RESET = 9, 162 PLS_COMPILANCE_MODE = 10, 163 PLS_TEST_MODE = 11, 164 PLS_RESUME = 15, 165 }; 166 167 typedef enum TRBType { 168 TRB_RESERVED = 0, 169 TR_NORMAL, 170 TR_SETUP, 171 TR_DATA, 172 TR_STATUS, 173 TR_ISOCH, 174 TR_LINK, 175 TR_EVDATA, 176 TR_NOOP, 177 CR_ENABLE_SLOT, 178 CR_DISABLE_SLOT, 179 CR_ADDRESS_DEVICE, 180 CR_CONFIGURE_ENDPOINT, 181 CR_EVALUATE_CONTEXT, 182 CR_RESET_ENDPOINT, 183 CR_STOP_ENDPOINT, 184 CR_SET_TR_DEQUEUE, 185 CR_RESET_DEVICE, 186 CR_FORCE_EVENT, 187 CR_NEGOTIATE_BW, 188 CR_SET_LATENCY_TOLERANCE, 189 CR_GET_PORT_BANDWIDTH, 190 CR_FORCE_HEADER, 191 CR_NOOP, 192 ER_TRANSFER = 32, 193 ER_COMMAND_COMPLETE, 194 ER_PORT_STATUS_CHANGE, 195 ER_BANDWIDTH_REQUEST, 196 ER_DOORBELL, 197 ER_HOST_CONTROLLER, 198 ER_DEVICE_NOTIFICATION, 199 ER_MFINDEX_WRAP, 200 /* vendor specific bits */ 201 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 202 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 203 } TRBType; 204 205 #define CR_LINK TR_LINK 206 207 typedef enum TRBCCode { 208 CC_INVALID = 0, 209 CC_SUCCESS, 210 CC_DATA_BUFFER_ERROR, 211 CC_BABBLE_DETECTED, 212 CC_USB_TRANSACTION_ERROR, 213 CC_TRB_ERROR, 214 CC_STALL_ERROR, 215 CC_RESOURCE_ERROR, 216 CC_BANDWIDTH_ERROR, 217 CC_NO_SLOTS_ERROR, 218 CC_INVALID_STREAM_TYPE_ERROR, 219 CC_SLOT_NOT_ENABLED_ERROR, 220 CC_EP_NOT_ENABLED_ERROR, 221 CC_SHORT_PACKET, 222 CC_RING_UNDERRUN, 223 CC_RING_OVERRUN, 224 CC_VF_ER_FULL, 225 CC_PARAMETER_ERROR, 226 CC_BANDWIDTH_OVERRUN, 227 CC_CONTEXT_STATE_ERROR, 228 CC_NO_PING_RESPONSE_ERROR, 229 CC_EVENT_RING_FULL_ERROR, 230 CC_INCOMPATIBLE_DEVICE_ERROR, 231 CC_MISSED_SERVICE_ERROR, 232 CC_COMMAND_RING_STOPPED, 233 CC_COMMAND_ABORTED, 234 CC_STOPPED, 235 CC_STOPPED_LENGTH_INVALID, 236 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 237 CC_ISOCH_BUFFER_OVERRUN = 31, 238 CC_EVENT_LOST_ERROR, 239 CC_UNDEFINED_ERROR, 240 CC_INVALID_STREAM_ID_ERROR, 241 CC_SECONDARY_BANDWIDTH_ERROR, 242 CC_SPLIT_TRANSACTION_ERROR 243 } TRBCCode; 244 245 #define TRB_C (1<<0) 246 #define TRB_TYPE_SHIFT 10 247 #define TRB_TYPE_MASK 0x3f 248 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 249 250 #define TRB_EV_ED (1<<2) 251 252 #define TRB_TR_ENT (1<<1) 253 #define TRB_TR_ISP (1<<2) 254 #define TRB_TR_NS (1<<3) 255 #define TRB_TR_CH (1<<4) 256 #define TRB_TR_IOC (1<<5) 257 #define TRB_TR_IDT (1<<6) 258 #define TRB_TR_TBC_SHIFT 7 259 #define TRB_TR_TBC_MASK 0x3 260 #define TRB_TR_BEI (1<<9) 261 #define TRB_TR_TLBPC_SHIFT 16 262 #define TRB_TR_TLBPC_MASK 0xf 263 #define TRB_TR_FRAMEID_SHIFT 20 264 #define TRB_TR_FRAMEID_MASK 0x7ff 265 #define TRB_TR_SIA (1<<31) 266 267 #define TRB_TR_DIR (1<<16) 268 269 #define TRB_CR_SLOTID_SHIFT 24 270 #define TRB_CR_SLOTID_MASK 0xff 271 #define TRB_CR_EPID_SHIFT 16 272 #define TRB_CR_EPID_MASK 0x1f 273 274 #define TRB_CR_BSR (1<<9) 275 #define TRB_CR_DC (1<<9) 276 277 #define TRB_LK_TC (1<<1) 278 279 #define TRB_INTR_SHIFT 22 280 #define TRB_INTR_MASK 0x3ff 281 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 282 283 #define EP_TYPE_MASK 0x7 284 #define EP_TYPE_SHIFT 3 285 286 #define EP_STATE_MASK 0x7 287 #define EP_DISABLED (0<<0) 288 #define EP_RUNNING (1<<0) 289 #define EP_HALTED (2<<0) 290 #define EP_STOPPED (3<<0) 291 #define EP_ERROR (4<<0) 292 293 #define SLOT_STATE_MASK 0x1f 294 #define SLOT_STATE_SHIFT 27 295 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 296 #define SLOT_ENABLED 0 297 #define SLOT_DEFAULT 1 298 #define SLOT_ADDRESSED 2 299 #define SLOT_CONFIGURED 3 300 301 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 302 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 303 304 typedef struct XHCIState XHCIState; 305 typedef struct XHCIStreamContext XHCIStreamContext; 306 typedef struct XHCIEPContext XHCIEPContext; 307 308 #define get_field(data, field) \ 309 (((data) >> field##_SHIFT) & field##_MASK) 310 311 #define set_field(data, newval, field) do { \ 312 uint32_t val = *data; \ 313 val &= ~(field##_MASK << field##_SHIFT); \ 314 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 315 *data = val; \ 316 } while (0) 317 318 typedef enum EPType { 319 ET_INVALID = 0, 320 ET_ISO_OUT, 321 ET_BULK_OUT, 322 ET_INTR_OUT, 323 ET_CONTROL, 324 ET_ISO_IN, 325 ET_BULK_IN, 326 ET_INTR_IN, 327 } EPType; 328 329 typedef struct XHCIRing { 330 dma_addr_t dequeue; 331 bool ccs; 332 } XHCIRing; 333 334 typedef struct XHCIPort { 335 XHCIState *xhci; 336 uint32_t portsc; 337 uint32_t portnr; 338 USBPort *uport; 339 uint32_t speedmask; 340 char name[16]; 341 MemoryRegion mem; 342 } XHCIPort; 343 344 typedef struct XHCITransfer { 345 XHCIEPContext *epctx; 346 USBPacket packet; 347 QEMUSGList sgl; 348 bool running_async; 349 bool running_retry; 350 bool complete; 351 bool int_req; 352 unsigned int iso_pkts; 353 unsigned int streamid; 354 bool in_xfer; 355 bool iso_xfer; 356 bool timed_xfer; 357 358 unsigned int trb_count; 359 XHCITRB *trbs; 360 361 TRBCCode status; 362 363 unsigned int pkts; 364 unsigned int pktsize; 365 unsigned int cur_pkt; 366 367 uint64_t mfindex_kick; 368 369 QTAILQ_ENTRY(XHCITransfer) next; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 uint32_t xfer_count; 385 QTAILQ_HEAD(, XHCITransfer) transfers; 386 XHCITransfer *retry; 387 EPType type; 388 dma_addr_t pctx; 389 unsigned int max_psize; 390 uint32_t state; 391 uint32_t kick_active; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 /* kept for live migration compat only */ 439 bool er_full_unused; 440 XHCIEvent ev_buffer[EV_QUEUE]; 441 unsigned int ev_buffer_put; 442 unsigned int ev_buffer_get; 443 444 } XHCIInterrupter; 445 446 struct XHCIState { 447 /*< private >*/ 448 PCIDevice parent_obj; 449 /*< public >*/ 450 451 USBBus bus; 452 MemoryRegion mem; 453 MemoryRegion mem_cap; 454 MemoryRegion mem_oper; 455 MemoryRegion mem_runtime; 456 MemoryRegion mem_doorbell; 457 458 /* properties */ 459 uint32_t numports_2; 460 uint32_t numports_3; 461 uint32_t numintrs; 462 uint32_t numslots; 463 uint32_t flags; 464 uint32_t max_pstreams_mask; 465 OnOffAuto msi; 466 OnOffAuto msix; 467 468 /* Operational Registers */ 469 uint32_t usbcmd; 470 uint32_t usbsts; 471 uint32_t dnctrl; 472 uint32_t crcr_low; 473 uint32_t crcr_high; 474 uint32_t dcbaap_low; 475 uint32_t dcbaap_high; 476 uint32_t config; 477 478 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 479 XHCIPort ports[MAXPORTS]; 480 XHCISlot slots[MAXSLOTS]; 481 uint32_t numports; 482 483 /* Runtime Registers */ 484 int64_t mfindex_start; 485 QEMUTimer *mfwrap_timer; 486 XHCIInterrupter intr[MAXINTRS]; 487 488 XHCIRing cmd_ring; 489 490 bool nec_quirks; 491 }; 492 493 #define TYPE_XHCI "base-xhci" 494 #define TYPE_NEC_XHCI "nec-usb-xhci" 495 #define TYPE_QEMU_XHCI "qemu-xhci" 496 497 #define XHCI(obj) \ 498 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 499 500 typedef struct XHCIEvRingSeg { 501 uint32_t addr_low; 502 uint32_t addr_high; 503 uint32_t size; 504 uint32_t rsvd; 505 } XHCIEvRingSeg; 506 507 enum xhci_flags { 508 XHCI_FLAG_SS_FIRST = 1, 509 XHCI_FLAG_FORCE_PCIE_ENDCAP, 510 XHCI_FLAG_ENABLE_STREAMS, 511 }; 512 513 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 514 unsigned int epid, unsigned int streamid); 515 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid); 516 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 517 unsigned int epid); 518 static void xhci_xfer_report(XHCITransfer *xfer); 519 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 520 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 521 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx); 522 523 static const char *TRBType_names[] = { 524 [TRB_RESERVED] = "TRB_RESERVED", 525 [TR_NORMAL] = "TR_NORMAL", 526 [TR_SETUP] = "TR_SETUP", 527 [TR_DATA] = "TR_DATA", 528 [TR_STATUS] = "TR_STATUS", 529 [TR_ISOCH] = "TR_ISOCH", 530 [TR_LINK] = "TR_LINK", 531 [TR_EVDATA] = "TR_EVDATA", 532 [TR_NOOP] = "TR_NOOP", 533 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 534 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 535 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 536 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 537 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 538 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 539 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 540 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 541 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 542 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 543 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 544 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 545 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 546 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 547 [CR_NOOP] = "CR_NOOP", 548 [ER_TRANSFER] = "ER_TRANSFER", 549 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 550 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 551 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 552 [ER_DOORBELL] = "ER_DOORBELL", 553 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 554 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 555 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 556 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 557 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 558 }; 559 560 static const char *TRBCCode_names[] = { 561 [CC_INVALID] = "CC_INVALID", 562 [CC_SUCCESS] = "CC_SUCCESS", 563 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 564 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 565 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 566 [CC_TRB_ERROR] = "CC_TRB_ERROR", 567 [CC_STALL_ERROR] = "CC_STALL_ERROR", 568 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 569 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 570 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 571 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 572 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 573 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 574 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 575 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 576 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 577 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 578 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 579 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 580 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 581 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 582 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 583 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 584 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 585 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 586 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 587 [CC_STOPPED] = "CC_STOPPED", 588 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 589 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 590 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 591 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 592 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 593 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 594 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 595 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 596 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 597 }; 598 599 static const char *ep_state_names[] = { 600 [EP_DISABLED] = "disabled", 601 [EP_RUNNING] = "running", 602 [EP_HALTED] = "halted", 603 [EP_STOPPED] = "stopped", 604 [EP_ERROR] = "error", 605 }; 606 607 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 608 { 609 if (index >= llen || list[index] == NULL) { 610 return "???"; 611 } 612 return list[index]; 613 } 614 615 static const char *trb_name(XHCITRB *trb) 616 { 617 return lookup_name(TRB_TYPE(*trb), TRBType_names, 618 ARRAY_SIZE(TRBType_names)); 619 } 620 621 static const char *event_name(XHCIEvent *event) 622 { 623 return lookup_name(event->ccode, TRBCCode_names, 624 ARRAY_SIZE(TRBCCode_names)); 625 } 626 627 static const char *ep_state_name(uint32_t state) 628 { 629 return lookup_name(state, ep_state_names, 630 ARRAY_SIZE(ep_state_names)); 631 } 632 633 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 634 { 635 return xhci->flags & (1 << bit); 636 } 637 638 static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) 639 { 640 xhci->flags |= (1 << bit); 641 } 642 643 static uint64_t xhci_mfindex_get(XHCIState *xhci) 644 { 645 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 646 return (now - xhci->mfindex_start) / 125000; 647 } 648 649 static void xhci_mfwrap_update(XHCIState *xhci) 650 { 651 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 652 uint32_t mfindex, left; 653 int64_t now; 654 655 if ((xhci->usbcmd & bits) == bits) { 656 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 657 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 658 left = 0x4000 - mfindex; 659 timer_mod(xhci->mfwrap_timer, now + left * 125000); 660 } else { 661 timer_del(xhci->mfwrap_timer); 662 } 663 } 664 665 static void xhci_mfwrap_timer(void *opaque) 666 { 667 XHCIState *xhci = opaque; 668 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 669 670 xhci_event(xhci, &wrap, 0); 671 xhci_mfwrap_update(xhci); 672 } 673 674 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 675 { 676 if (sizeof(dma_addr_t) == 4) { 677 return low; 678 } else { 679 return low | (((dma_addr_t)high << 16) << 16); 680 } 681 } 682 683 static inline dma_addr_t xhci_mask64(uint64_t addr) 684 { 685 if (sizeof(dma_addr_t) == 4) { 686 return addr & 0xffffffff; 687 } else { 688 return addr; 689 } 690 } 691 692 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 693 uint32_t *buf, size_t len) 694 { 695 int i; 696 697 assert((len % sizeof(uint32_t)) == 0); 698 699 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 700 701 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 702 buf[i] = le32_to_cpu(buf[i]); 703 } 704 } 705 706 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 707 uint32_t *buf, size_t len) 708 { 709 int i; 710 uint32_t tmp[5]; 711 uint32_t n = len / sizeof(uint32_t); 712 713 assert((len % sizeof(uint32_t)) == 0); 714 assert(n <= ARRAY_SIZE(tmp)); 715 716 for (i = 0; i < n; i++) { 717 tmp[i] = cpu_to_le32(buf[i]); 718 } 719 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 720 } 721 722 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 723 { 724 int index; 725 726 if (!uport->dev) { 727 return NULL; 728 } 729 switch (uport->dev->speed) { 730 case USB_SPEED_LOW: 731 case USB_SPEED_FULL: 732 case USB_SPEED_HIGH: 733 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 734 index = uport->index + xhci->numports_3; 735 } else { 736 index = uport->index; 737 } 738 break; 739 case USB_SPEED_SUPER: 740 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 741 index = uport->index; 742 } else { 743 index = uport->index + xhci->numports_2; 744 } 745 break; 746 default: 747 return NULL; 748 } 749 return &xhci->ports[index]; 750 } 751 752 static void xhci_intx_update(XHCIState *xhci) 753 { 754 PCIDevice *pci_dev = PCI_DEVICE(xhci); 755 int level = 0; 756 757 if (msix_enabled(pci_dev) || 758 msi_enabled(pci_dev)) { 759 return; 760 } 761 762 if (xhci->intr[0].iman & IMAN_IP && 763 xhci->intr[0].iman & IMAN_IE && 764 xhci->usbcmd & USBCMD_INTE) { 765 level = 1; 766 } 767 768 trace_usb_xhci_irq_intx(level); 769 pci_set_irq(pci_dev, level); 770 } 771 772 static void xhci_msix_update(XHCIState *xhci, int v) 773 { 774 PCIDevice *pci_dev = PCI_DEVICE(xhci); 775 bool enabled; 776 777 if (!msix_enabled(pci_dev)) { 778 return; 779 } 780 781 enabled = xhci->intr[v].iman & IMAN_IE; 782 if (enabled == xhci->intr[v].msix_used) { 783 return; 784 } 785 786 if (enabled) { 787 trace_usb_xhci_irq_msix_use(v); 788 msix_vector_use(pci_dev, v); 789 xhci->intr[v].msix_used = true; 790 } else { 791 trace_usb_xhci_irq_msix_unuse(v); 792 msix_vector_unuse(pci_dev, v); 793 xhci->intr[v].msix_used = false; 794 } 795 } 796 797 static void xhci_intr_raise(XHCIState *xhci, int v) 798 { 799 PCIDevice *pci_dev = PCI_DEVICE(xhci); 800 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB); 801 802 xhci->intr[v].erdp_low |= ERDP_EHB; 803 xhci->intr[v].iman |= IMAN_IP; 804 xhci->usbsts |= USBSTS_EINT; 805 806 if (pending) { 807 return; 808 } 809 if (!(xhci->intr[v].iman & IMAN_IE)) { 810 return; 811 } 812 813 if (!(xhci->usbcmd & USBCMD_INTE)) { 814 return; 815 } 816 817 if (msix_enabled(pci_dev)) { 818 trace_usb_xhci_irq_msix(v); 819 msix_notify(pci_dev, v); 820 return; 821 } 822 823 if (msi_enabled(pci_dev)) { 824 trace_usb_xhci_irq_msi(v); 825 msi_notify(pci_dev, v); 826 return; 827 } 828 829 if (v == 0) { 830 trace_usb_xhci_irq_intx(1); 831 pci_irq_assert(pci_dev); 832 } 833 } 834 835 static inline int xhci_running(XHCIState *xhci) 836 { 837 return !(xhci->usbsts & USBSTS_HCH); 838 } 839 840 static void xhci_die(XHCIState *xhci) 841 { 842 xhci->usbsts |= USBSTS_HCE; 843 DPRINTF("xhci: asserted controller error\n"); 844 } 845 846 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 847 { 848 PCIDevice *pci_dev = PCI_DEVICE(xhci); 849 XHCIInterrupter *intr = &xhci->intr[v]; 850 XHCITRB ev_trb; 851 dma_addr_t addr; 852 853 ev_trb.parameter = cpu_to_le64(event->ptr); 854 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 855 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 856 event->flags | (event->type << TRB_TYPE_SHIFT); 857 if (intr->er_pcs) { 858 ev_trb.control |= TRB_C; 859 } 860 ev_trb.control = cpu_to_le32(ev_trb.control); 861 862 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 863 event_name(event), ev_trb.parameter, 864 ev_trb.status, ev_trb.control); 865 866 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 867 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 868 869 intr->er_ep_idx++; 870 if (intr->er_ep_idx >= intr->er_size) { 871 intr->er_ep_idx = 0; 872 intr->er_pcs = !intr->er_pcs; 873 } 874 } 875 876 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 877 { 878 XHCIInterrupter *intr; 879 dma_addr_t erdp; 880 unsigned int dp_idx; 881 882 if (v >= xhci->numintrs) { 883 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 884 return; 885 } 886 intr = &xhci->intr[v]; 887 888 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 889 if (erdp < intr->er_start || 890 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 891 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 892 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 893 v, intr->er_start, intr->er_size); 894 xhci_die(xhci); 895 return; 896 } 897 898 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 899 assert(dp_idx < intr->er_size); 900 901 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) { 902 DPRINTF("xhci: ER %d full, send ring full error\n", v); 903 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 904 xhci_write_event(xhci, &full, v); 905 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) { 906 DPRINTF("xhci: ER %d full, drop event\n", v); 907 } else { 908 xhci_write_event(xhci, event, v); 909 } 910 911 xhci_intr_raise(xhci, v); 912 } 913 914 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 915 dma_addr_t base) 916 { 917 ring->dequeue = base; 918 ring->ccs = 1; 919 } 920 921 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 922 dma_addr_t *addr) 923 { 924 PCIDevice *pci_dev = PCI_DEVICE(xhci); 925 uint32_t link_cnt = 0; 926 927 while (1) { 928 TRBType type; 929 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 930 trb->addr = ring->dequeue; 931 trb->ccs = ring->ccs; 932 le64_to_cpus(&trb->parameter); 933 le32_to_cpus(&trb->status); 934 le32_to_cpus(&trb->control); 935 936 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 937 trb->parameter, trb->status, trb->control); 938 939 if ((trb->control & TRB_C) != ring->ccs) { 940 return 0; 941 } 942 943 type = TRB_TYPE(*trb); 944 945 if (type != TR_LINK) { 946 if (addr) { 947 *addr = ring->dequeue; 948 } 949 ring->dequeue += TRB_SIZE; 950 return type; 951 } else { 952 if (++link_cnt > TRB_LINK_LIMIT) { 953 trace_usb_xhci_enforced_limit("trb-link"); 954 return 0; 955 } 956 ring->dequeue = xhci_mask64(trb->parameter); 957 if (trb->control & TRB_LK_TC) { 958 ring->ccs = !ring->ccs; 959 } 960 } 961 } 962 } 963 964 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 965 { 966 PCIDevice *pci_dev = PCI_DEVICE(xhci); 967 XHCITRB trb; 968 int length = 0; 969 dma_addr_t dequeue = ring->dequeue; 970 bool ccs = ring->ccs; 971 /* hack to bundle together the two/three TDs that make a setup transfer */ 972 bool control_td_set = 0; 973 uint32_t link_cnt = 0; 974 975 while (1) { 976 TRBType type; 977 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 978 le64_to_cpus(&trb.parameter); 979 le32_to_cpus(&trb.status); 980 le32_to_cpus(&trb.control); 981 982 if ((trb.control & TRB_C) != ccs) { 983 return -length; 984 } 985 986 type = TRB_TYPE(trb); 987 988 if (type == TR_LINK) { 989 if (++link_cnt > TRB_LINK_LIMIT) { 990 return -length; 991 } 992 dequeue = xhci_mask64(trb.parameter); 993 if (trb.control & TRB_LK_TC) { 994 ccs = !ccs; 995 } 996 continue; 997 } 998 999 length += 1; 1000 dequeue += TRB_SIZE; 1001 1002 if (type == TR_SETUP) { 1003 control_td_set = 1; 1004 } else if (type == TR_STATUS) { 1005 control_td_set = 0; 1006 } 1007 1008 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1009 return length; 1010 } 1011 } 1012 } 1013 1014 static void xhci_er_reset(XHCIState *xhci, int v) 1015 { 1016 XHCIInterrupter *intr = &xhci->intr[v]; 1017 XHCIEvRingSeg seg; 1018 1019 if (intr->erstsz == 0) { 1020 /* disabled */ 1021 intr->er_start = 0; 1022 intr->er_size = 0; 1023 return; 1024 } 1025 /* cache the (sole) event ring segment location */ 1026 if (intr->erstsz != 1) { 1027 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1028 xhci_die(xhci); 1029 return; 1030 } 1031 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1032 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1033 le32_to_cpus(&seg.addr_low); 1034 le32_to_cpus(&seg.addr_high); 1035 le32_to_cpus(&seg.size); 1036 if (seg.size < 16 || seg.size > 4096) { 1037 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 1038 xhci_die(xhci); 1039 return; 1040 } 1041 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1042 intr->er_size = seg.size; 1043 1044 intr->er_ep_idx = 0; 1045 intr->er_pcs = 1; 1046 1047 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1048 v, intr->er_start, intr->er_size); 1049 } 1050 1051 static void xhci_run(XHCIState *xhci) 1052 { 1053 trace_usb_xhci_run(); 1054 xhci->usbsts &= ~USBSTS_HCH; 1055 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1056 } 1057 1058 static void xhci_stop(XHCIState *xhci) 1059 { 1060 trace_usb_xhci_stop(); 1061 xhci->usbsts |= USBSTS_HCH; 1062 xhci->crcr_low &= ~CRCR_CRR; 1063 } 1064 1065 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1066 dma_addr_t base) 1067 { 1068 XHCIStreamContext *stctx; 1069 unsigned int i; 1070 1071 stctx = g_new0(XHCIStreamContext, count); 1072 for (i = 0; i < count; i++) { 1073 stctx[i].pctx = base + i * 16; 1074 stctx[i].sct = -1; 1075 } 1076 return stctx; 1077 } 1078 1079 static void xhci_reset_streams(XHCIEPContext *epctx) 1080 { 1081 unsigned int i; 1082 1083 for (i = 0; i < epctx->nr_pstreams; i++) { 1084 epctx->pstreams[i].sct = -1; 1085 } 1086 } 1087 1088 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1089 { 1090 assert(epctx->pstreams == NULL); 1091 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1092 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1093 } 1094 1095 static void xhci_free_streams(XHCIEPContext *epctx) 1096 { 1097 assert(epctx->pstreams != NULL); 1098 1099 g_free(epctx->pstreams); 1100 epctx->pstreams = NULL; 1101 epctx->nr_pstreams = 0; 1102 } 1103 1104 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 1105 unsigned int slotid, 1106 uint32_t epmask, 1107 XHCIEPContext **epctxs, 1108 USBEndpoint **eps) 1109 { 1110 XHCISlot *slot; 1111 XHCIEPContext *epctx; 1112 USBEndpoint *ep; 1113 int i, j; 1114 1115 assert(slotid >= 1 && slotid <= xhci->numslots); 1116 1117 slot = &xhci->slots[slotid - 1]; 1118 1119 for (i = 2, j = 0; i <= 31; i++) { 1120 if (!(epmask & (1u << i))) { 1121 continue; 1122 } 1123 1124 epctx = slot->eps[i - 1]; 1125 ep = xhci_epid_to_usbep(epctx); 1126 if (!epctx || !epctx->nr_pstreams || !ep) { 1127 continue; 1128 } 1129 1130 if (epctxs) { 1131 epctxs[j] = epctx; 1132 } 1133 eps[j++] = ep; 1134 } 1135 return j; 1136 } 1137 1138 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 1139 uint32_t epmask) 1140 { 1141 USBEndpoint *eps[30]; 1142 int nr_eps; 1143 1144 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 1145 if (nr_eps) { 1146 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 1147 } 1148 } 1149 1150 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 1151 uint32_t epmask) 1152 { 1153 XHCIEPContext *epctxs[30]; 1154 USBEndpoint *eps[30]; 1155 int i, r, nr_eps, req_nr_streams, dev_max_streams; 1156 1157 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 1158 eps); 1159 if (nr_eps == 0) { 1160 return CC_SUCCESS; 1161 } 1162 1163 req_nr_streams = epctxs[0]->nr_pstreams; 1164 dev_max_streams = eps[0]->max_streams; 1165 1166 for (i = 1; i < nr_eps; i++) { 1167 /* 1168 * HdG: I don't expect these to ever trigger, but if they do we need 1169 * to come up with another solution, ie group identical endpoints 1170 * together and make an usb_device_alloc_streams call per group. 1171 */ 1172 if (epctxs[i]->nr_pstreams != req_nr_streams) { 1173 FIXME("guest streams config not identical for all eps"); 1174 return CC_RESOURCE_ERROR; 1175 } 1176 if (eps[i]->max_streams != dev_max_streams) { 1177 FIXME("device streams config not identical for all eps"); 1178 return CC_RESOURCE_ERROR; 1179 } 1180 } 1181 1182 /* 1183 * max-streams in both the device descriptor and in the controller is a 1184 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 1185 * streams the guest will ask for 5 rounded up to the next power of 2 which 1186 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 1187 * 1188 * For redirected devices however this is an issue, as there we must ask 1189 * the real xhci controller to alloc streams, and the host driver for the 1190 * real xhci controller will likely disallow allocating more streams then 1191 * the device can handle. 1192 * 1193 * So we limit the requested nr_streams to the maximum number the device 1194 * can handle. 1195 */ 1196 if (req_nr_streams > dev_max_streams) { 1197 req_nr_streams = dev_max_streams; 1198 } 1199 1200 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 1201 if (r != 0) { 1202 DPRINTF("xhci: alloc streams failed\n"); 1203 return CC_RESOURCE_ERROR; 1204 } 1205 1206 return CC_SUCCESS; 1207 } 1208 1209 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1210 unsigned int streamid, 1211 uint32_t *cc_error) 1212 { 1213 XHCIStreamContext *sctx; 1214 dma_addr_t base; 1215 uint32_t ctx[2], sct; 1216 1217 assert(streamid != 0); 1218 if (epctx->lsa) { 1219 if (streamid >= epctx->nr_pstreams) { 1220 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1221 return NULL; 1222 } 1223 sctx = epctx->pstreams + streamid; 1224 } else { 1225 FIXME("secondary streams not implemented yet"); 1226 } 1227 1228 if (sctx->sct == -1) { 1229 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1230 sct = (ctx[0] >> 1) & 0x07; 1231 if (epctx->lsa && sct != 1) { 1232 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1233 return NULL; 1234 } 1235 sctx->sct = sct; 1236 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1237 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1238 } 1239 return sctx; 1240 } 1241 1242 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1243 XHCIStreamContext *sctx, uint32_t state) 1244 { 1245 XHCIRing *ring = NULL; 1246 uint32_t ctx[5]; 1247 uint32_t ctx2[2]; 1248 1249 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1250 ctx[0] &= ~EP_STATE_MASK; 1251 ctx[0] |= state; 1252 1253 /* update ring dequeue ptr */ 1254 if (epctx->nr_pstreams) { 1255 if (sctx != NULL) { 1256 ring = &sctx->ring; 1257 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1258 ctx2[0] &= 0xe; 1259 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1260 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1261 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1262 } 1263 } else { 1264 ring = &epctx->ring; 1265 } 1266 if (ring) { 1267 ctx[2] = ring->dequeue | ring->ccs; 1268 ctx[3] = (ring->dequeue >> 16) >> 16; 1269 1270 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1271 epctx->pctx, state, ctx[3], ctx[2]); 1272 } 1273 1274 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1275 if (epctx->state != state) { 1276 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1277 ep_state_name(epctx->state), 1278 ep_state_name(state)); 1279 } 1280 epctx->state = state; 1281 } 1282 1283 static void xhci_ep_kick_timer(void *opaque) 1284 { 1285 XHCIEPContext *epctx = opaque; 1286 xhci_kick_epctx(epctx, 0); 1287 } 1288 1289 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1290 unsigned int slotid, 1291 unsigned int epid) 1292 { 1293 XHCIEPContext *epctx; 1294 1295 epctx = g_new0(XHCIEPContext, 1); 1296 epctx->xhci = xhci; 1297 epctx->slotid = slotid; 1298 epctx->epid = epid; 1299 1300 QTAILQ_INIT(&epctx->transfers); 1301 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1302 1303 return epctx; 1304 } 1305 1306 static void xhci_init_epctx(XHCIEPContext *epctx, 1307 dma_addr_t pctx, uint32_t *ctx) 1308 { 1309 dma_addr_t dequeue; 1310 1311 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1312 1313 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1314 epctx->pctx = pctx; 1315 epctx->max_psize = ctx[1]>>16; 1316 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1317 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1318 epctx->lsa = (ctx[0] >> 15) & 1; 1319 if (epctx->max_pstreams) { 1320 xhci_alloc_streams(epctx, dequeue); 1321 } else { 1322 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1323 epctx->ring.ccs = ctx[2] & 1; 1324 } 1325 1326 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1327 } 1328 1329 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1330 unsigned int epid, dma_addr_t pctx, 1331 uint32_t *ctx) 1332 { 1333 XHCISlot *slot; 1334 XHCIEPContext *epctx; 1335 1336 trace_usb_xhci_ep_enable(slotid, epid); 1337 assert(slotid >= 1 && slotid <= xhci->numslots); 1338 assert(epid >= 1 && epid <= 31); 1339 1340 slot = &xhci->slots[slotid-1]; 1341 if (slot->eps[epid-1]) { 1342 xhci_disable_ep(xhci, slotid, epid); 1343 } 1344 1345 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1346 slot->eps[epid-1] = epctx; 1347 xhci_init_epctx(epctx, pctx, ctx); 1348 1349 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1350 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1351 1352 epctx->mfindex_last = 0; 1353 1354 epctx->state = EP_RUNNING; 1355 ctx[0] &= ~EP_STATE_MASK; 1356 ctx[0] |= EP_RUNNING; 1357 1358 return CC_SUCCESS; 1359 } 1360 1361 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx, 1362 uint32_t length) 1363 { 1364 uint32_t limit = epctx->nr_pstreams + 16; 1365 XHCITransfer *xfer; 1366 1367 if (epctx->xfer_count >= limit) { 1368 return NULL; 1369 } 1370 1371 xfer = g_new0(XHCITransfer, 1); 1372 xfer->epctx = epctx; 1373 xfer->trbs = g_new(XHCITRB, length); 1374 xfer->trb_count = length; 1375 usb_packet_init(&xfer->packet); 1376 1377 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next); 1378 epctx->xfer_count++; 1379 1380 return xfer; 1381 } 1382 1383 static void xhci_ep_free_xfer(XHCITransfer *xfer) 1384 { 1385 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next); 1386 xfer->epctx->xfer_count--; 1387 1388 usb_packet_cleanup(&xfer->packet); 1389 g_free(xfer->trbs); 1390 g_free(xfer); 1391 } 1392 1393 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1394 { 1395 int killed = 0; 1396 1397 if (report && (t->running_async || t->running_retry)) { 1398 t->status = report; 1399 xhci_xfer_report(t); 1400 } 1401 1402 if (t->running_async) { 1403 usb_cancel_packet(&t->packet); 1404 t->running_async = 0; 1405 killed = 1; 1406 } 1407 if (t->running_retry) { 1408 if (t->epctx) { 1409 t->epctx->retry = NULL; 1410 timer_del(t->epctx->kick_timer); 1411 } 1412 t->running_retry = 0; 1413 killed = 1; 1414 } 1415 g_free(t->trbs); 1416 1417 t->trbs = NULL; 1418 t->trb_count = 0; 1419 1420 return killed; 1421 } 1422 1423 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1424 unsigned int epid, TRBCCode report) 1425 { 1426 XHCISlot *slot; 1427 XHCIEPContext *epctx; 1428 XHCITransfer *xfer; 1429 int killed = 0; 1430 USBEndpoint *ep = NULL; 1431 assert(slotid >= 1 && slotid <= xhci->numslots); 1432 assert(epid >= 1 && epid <= 31); 1433 1434 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1435 1436 slot = &xhci->slots[slotid-1]; 1437 1438 if (!slot->eps[epid-1]) { 1439 return 0; 1440 } 1441 1442 epctx = slot->eps[epid-1]; 1443 1444 for (;;) { 1445 xfer = QTAILQ_FIRST(&epctx->transfers); 1446 if (xfer == NULL) { 1447 break; 1448 } 1449 killed += xhci_ep_nuke_one_xfer(xfer, report); 1450 if (killed) { 1451 report = 0; /* Only report once */ 1452 } 1453 xhci_ep_free_xfer(xfer); 1454 } 1455 1456 ep = xhci_epid_to_usbep(epctx); 1457 if (ep) { 1458 usb_device_ep_stopped(ep->dev, ep); 1459 } 1460 return killed; 1461 } 1462 1463 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1464 unsigned int epid) 1465 { 1466 XHCISlot *slot; 1467 XHCIEPContext *epctx; 1468 1469 trace_usb_xhci_ep_disable(slotid, epid); 1470 assert(slotid >= 1 && slotid <= xhci->numslots); 1471 assert(epid >= 1 && epid <= 31); 1472 1473 slot = &xhci->slots[slotid-1]; 1474 1475 if (!slot->eps[epid-1]) { 1476 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1477 return CC_SUCCESS; 1478 } 1479 1480 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1481 1482 epctx = slot->eps[epid-1]; 1483 1484 if (epctx->nr_pstreams) { 1485 xhci_free_streams(epctx); 1486 } 1487 1488 /* only touch guest RAM if we're not resetting the HC */ 1489 if (xhci->dcbaap_low || xhci->dcbaap_high) { 1490 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1491 } 1492 1493 timer_free(epctx->kick_timer); 1494 g_free(epctx); 1495 slot->eps[epid-1] = NULL; 1496 1497 return CC_SUCCESS; 1498 } 1499 1500 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1501 unsigned int epid) 1502 { 1503 XHCISlot *slot; 1504 XHCIEPContext *epctx; 1505 1506 trace_usb_xhci_ep_stop(slotid, epid); 1507 assert(slotid >= 1 && slotid <= xhci->numslots); 1508 1509 if (epid < 1 || epid > 31) { 1510 DPRINTF("xhci: bad ep %d\n", epid); 1511 return CC_TRB_ERROR; 1512 } 1513 1514 slot = &xhci->slots[slotid-1]; 1515 1516 if (!slot->eps[epid-1]) { 1517 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1518 return CC_EP_NOT_ENABLED_ERROR; 1519 } 1520 1521 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1522 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1523 "data might be lost\n"); 1524 } 1525 1526 epctx = slot->eps[epid-1]; 1527 1528 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1529 1530 if (epctx->nr_pstreams) { 1531 xhci_reset_streams(epctx); 1532 } 1533 1534 return CC_SUCCESS; 1535 } 1536 1537 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1538 unsigned int epid) 1539 { 1540 XHCISlot *slot; 1541 XHCIEPContext *epctx; 1542 1543 trace_usb_xhci_ep_reset(slotid, epid); 1544 assert(slotid >= 1 && slotid <= xhci->numslots); 1545 1546 if (epid < 1 || epid > 31) { 1547 DPRINTF("xhci: bad ep %d\n", epid); 1548 return CC_TRB_ERROR; 1549 } 1550 1551 slot = &xhci->slots[slotid-1]; 1552 1553 if (!slot->eps[epid-1]) { 1554 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1555 return CC_EP_NOT_ENABLED_ERROR; 1556 } 1557 1558 epctx = slot->eps[epid-1]; 1559 1560 if (epctx->state != EP_HALTED) { 1561 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1562 epid, epctx->state); 1563 return CC_CONTEXT_STATE_ERROR; 1564 } 1565 1566 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1567 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1568 "data might be lost\n"); 1569 } 1570 1571 if (!xhci->slots[slotid-1].uport || 1572 !xhci->slots[slotid-1].uport->dev || 1573 !xhci->slots[slotid-1].uport->dev->attached) { 1574 return CC_USB_TRANSACTION_ERROR; 1575 } 1576 1577 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1578 1579 if (epctx->nr_pstreams) { 1580 xhci_reset_streams(epctx); 1581 } 1582 1583 return CC_SUCCESS; 1584 } 1585 1586 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1587 unsigned int epid, unsigned int streamid, 1588 uint64_t pdequeue) 1589 { 1590 XHCISlot *slot; 1591 XHCIEPContext *epctx; 1592 XHCIStreamContext *sctx; 1593 dma_addr_t dequeue; 1594 1595 assert(slotid >= 1 && slotid <= xhci->numslots); 1596 1597 if (epid < 1 || epid > 31) { 1598 DPRINTF("xhci: bad ep %d\n", epid); 1599 return CC_TRB_ERROR; 1600 } 1601 1602 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1603 dequeue = xhci_mask64(pdequeue); 1604 1605 slot = &xhci->slots[slotid-1]; 1606 1607 if (!slot->eps[epid-1]) { 1608 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1609 return CC_EP_NOT_ENABLED_ERROR; 1610 } 1611 1612 epctx = slot->eps[epid-1]; 1613 1614 if (epctx->state != EP_STOPPED) { 1615 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1616 return CC_CONTEXT_STATE_ERROR; 1617 } 1618 1619 if (epctx->nr_pstreams) { 1620 uint32_t err; 1621 sctx = xhci_find_stream(epctx, streamid, &err); 1622 if (sctx == NULL) { 1623 return err; 1624 } 1625 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1626 sctx->ring.ccs = dequeue & 1; 1627 } else { 1628 sctx = NULL; 1629 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1630 epctx->ring.ccs = dequeue & 1; 1631 } 1632 1633 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1634 1635 return CC_SUCCESS; 1636 } 1637 1638 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1639 { 1640 XHCIState *xhci = xfer->epctx->xhci; 1641 int i; 1642 1643 xfer->int_req = false; 1644 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1645 for (i = 0; i < xfer->trb_count; i++) { 1646 XHCITRB *trb = &xfer->trbs[i]; 1647 dma_addr_t addr; 1648 unsigned int chunk = 0; 1649 1650 if (trb->control & TRB_TR_IOC) { 1651 xfer->int_req = true; 1652 } 1653 1654 switch (TRB_TYPE(*trb)) { 1655 case TR_DATA: 1656 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1657 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1658 goto err; 1659 } 1660 /* fallthrough */ 1661 case TR_NORMAL: 1662 case TR_ISOCH: 1663 addr = xhci_mask64(trb->parameter); 1664 chunk = trb->status & 0x1ffff; 1665 if (trb->control & TRB_TR_IDT) { 1666 if (chunk > 8 || in_xfer) { 1667 DPRINTF("xhci: invalid immediate data TRB\n"); 1668 goto err; 1669 } 1670 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1671 } else { 1672 qemu_sglist_add(&xfer->sgl, addr, chunk); 1673 } 1674 break; 1675 } 1676 } 1677 1678 return 0; 1679 1680 err: 1681 qemu_sglist_destroy(&xfer->sgl); 1682 xhci_die(xhci); 1683 return -1; 1684 } 1685 1686 static void xhci_xfer_unmap(XHCITransfer *xfer) 1687 { 1688 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1689 qemu_sglist_destroy(&xfer->sgl); 1690 } 1691 1692 static void xhci_xfer_report(XHCITransfer *xfer) 1693 { 1694 uint32_t edtla = 0; 1695 unsigned int left; 1696 bool reported = 0; 1697 bool shortpkt = 0; 1698 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1699 XHCIState *xhci = xfer->epctx->xhci; 1700 int i; 1701 1702 left = xfer->packet.actual_length; 1703 1704 for (i = 0; i < xfer->trb_count; i++) { 1705 XHCITRB *trb = &xfer->trbs[i]; 1706 unsigned int chunk = 0; 1707 1708 switch (TRB_TYPE(*trb)) { 1709 case TR_SETUP: 1710 chunk = trb->status & 0x1ffff; 1711 if (chunk > 8) { 1712 chunk = 8; 1713 } 1714 break; 1715 case TR_DATA: 1716 case TR_NORMAL: 1717 case TR_ISOCH: 1718 chunk = trb->status & 0x1ffff; 1719 if (chunk > left) { 1720 chunk = left; 1721 if (xfer->status == CC_SUCCESS) { 1722 shortpkt = 1; 1723 } 1724 } 1725 left -= chunk; 1726 edtla += chunk; 1727 break; 1728 case TR_STATUS: 1729 reported = 0; 1730 shortpkt = 0; 1731 break; 1732 } 1733 1734 if (!reported && ((trb->control & TRB_TR_IOC) || 1735 (shortpkt && (trb->control & TRB_TR_ISP)) || 1736 (xfer->status != CC_SUCCESS && left == 0))) { 1737 event.slotid = xfer->epctx->slotid; 1738 event.epid = xfer->epctx->epid; 1739 event.length = (trb->status & 0x1ffff) - chunk; 1740 event.flags = 0; 1741 event.ptr = trb->addr; 1742 if (xfer->status == CC_SUCCESS) { 1743 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1744 } else { 1745 event.ccode = xfer->status; 1746 } 1747 if (TRB_TYPE(*trb) == TR_EVDATA) { 1748 event.ptr = trb->parameter; 1749 event.flags |= TRB_EV_ED; 1750 event.length = edtla & 0xffffff; 1751 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1752 edtla = 0; 1753 } 1754 xhci_event(xhci, &event, TRB_INTR(*trb)); 1755 reported = 1; 1756 if (xfer->status != CC_SUCCESS) { 1757 return; 1758 } 1759 } 1760 1761 switch (TRB_TYPE(*trb)) { 1762 case TR_SETUP: 1763 reported = 0; 1764 shortpkt = 0; 1765 break; 1766 } 1767 1768 } 1769 } 1770 1771 static void xhci_stall_ep(XHCITransfer *xfer) 1772 { 1773 XHCIEPContext *epctx = xfer->epctx; 1774 XHCIState *xhci = epctx->xhci; 1775 uint32_t err; 1776 XHCIStreamContext *sctx; 1777 1778 if (epctx->nr_pstreams) { 1779 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1780 if (sctx == NULL) { 1781 return; 1782 } 1783 sctx->ring.dequeue = xfer->trbs[0].addr; 1784 sctx->ring.ccs = xfer->trbs[0].ccs; 1785 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1786 } else { 1787 epctx->ring.dequeue = xfer->trbs[0].addr; 1788 epctx->ring.ccs = xfer->trbs[0].ccs; 1789 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1790 } 1791 } 1792 1793 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1794 XHCIEPContext *epctx); 1795 1796 static int xhci_setup_packet(XHCITransfer *xfer) 1797 { 1798 USBEndpoint *ep; 1799 int dir; 1800 1801 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1802 1803 if (xfer->packet.ep) { 1804 ep = xfer->packet.ep; 1805 } else { 1806 ep = xhci_epid_to_usbep(xfer->epctx); 1807 if (!ep) { 1808 DPRINTF("xhci: slot %d has no device\n", 1809 xfer->slotid); 1810 return -1; 1811 } 1812 } 1813 1814 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1815 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1816 xfer->trbs[0].addr, false, xfer->int_req); 1817 usb_packet_map(&xfer->packet, &xfer->sgl); 1818 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1819 xfer->packet.pid, ep->dev->addr, ep->nr); 1820 return 0; 1821 } 1822 1823 static int xhci_try_complete_packet(XHCITransfer *xfer) 1824 { 1825 if (xfer->packet.status == USB_RET_ASYNC) { 1826 trace_usb_xhci_xfer_async(xfer); 1827 xfer->running_async = 1; 1828 xfer->running_retry = 0; 1829 xfer->complete = 0; 1830 return 0; 1831 } else if (xfer->packet.status == USB_RET_NAK) { 1832 trace_usb_xhci_xfer_nak(xfer); 1833 xfer->running_async = 0; 1834 xfer->running_retry = 1; 1835 xfer->complete = 0; 1836 return 0; 1837 } else { 1838 xfer->running_async = 0; 1839 xfer->running_retry = 0; 1840 xfer->complete = 1; 1841 xhci_xfer_unmap(xfer); 1842 } 1843 1844 if (xfer->packet.status == USB_RET_SUCCESS) { 1845 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1846 xfer->status = CC_SUCCESS; 1847 xhci_xfer_report(xfer); 1848 return 0; 1849 } 1850 1851 /* error */ 1852 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1853 switch (xfer->packet.status) { 1854 case USB_RET_NODEV: 1855 case USB_RET_IOERROR: 1856 xfer->status = CC_USB_TRANSACTION_ERROR; 1857 xhci_xfer_report(xfer); 1858 xhci_stall_ep(xfer); 1859 break; 1860 case USB_RET_STALL: 1861 xfer->status = CC_STALL_ERROR; 1862 xhci_xfer_report(xfer); 1863 xhci_stall_ep(xfer); 1864 break; 1865 case USB_RET_BABBLE: 1866 xfer->status = CC_BABBLE_DETECTED; 1867 xhci_xfer_report(xfer); 1868 xhci_stall_ep(xfer); 1869 break; 1870 default: 1871 DPRINTF("%s: FIXME: status = %d\n", __func__, 1872 xfer->packet.status); 1873 FIXME("unhandled USB_RET_*"); 1874 } 1875 return 0; 1876 } 1877 1878 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1879 { 1880 XHCITRB *trb_setup, *trb_status; 1881 uint8_t bmRequestType; 1882 1883 trb_setup = &xfer->trbs[0]; 1884 trb_status = &xfer->trbs[xfer->trb_count-1]; 1885 1886 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 1887 xfer->epctx->epid, xfer->streamid); 1888 1889 /* at most one Event Data TRB allowed after STATUS */ 1890 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1891 trb_status--; 1892 } 1893 1894 /* do some sanity checks */ 1895 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1896 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1897 TRB_TYPE(*trb_setup)); 1898 return -1; 1899 } 1900 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1901 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1902 TRB_TYPE(*trb_status)); 1903 return -1; 1904 } 1905 if (!(trb_setup->control & TRB_TR_IDT)) { 1906 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1907 return -1; 1908 } 1909 if ((trb_setup->status & 0x1ffff) != 8) { 1910 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1911 (trb_setup->status & 0x1ffff)); 1912 return -1; 1913 } 1914 1915 bmRequestType = trb_setup->parameter; 1916 1917 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1918 xfer->iso_xfer = false; 1919 xfer->timed_xfer = false; 1920 1921 if (xhci_setup_packet(xfer) < 0) { 1922 return -1; 1923 } 1924 xfer->packet.parameter = trb_setup->parameter; 1925 1926 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1927 xhci_try_complete_packet(xfer); 1928 return 0; 1929 } 1930 1931 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1932 XHCIEPContext *epctx, uint64_t mfindex) 1933 { 1934 uint64_t asap = ((mfindex + epctx->interval - 1) & 1935 ~(epctx->interval-1)); 1936 uint64_t kick = epctx->mfindex_last + epctx->interval; 1937 1938 assert(epctx->interval != 0); 1939 xfer->mfindex_kick = MAX(asap, kick); 1940 } 1941 1942 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1943 XHCIEPContext *epctx, uint64_t mfindex) 1944 { 1945 if (xfer->trbs[0].control & TRB_TR_SIA) { 1946 uint64_t asap = ((mfindex + epctx->interval - 1) & 1947 ~(epctx->interval-1)); 1948 if (asap >= epctx->mfindex_last && 1949 asap <= epctx->mfindex_last + epctx->interval * 4) { 1950 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1951 } else { 1952 xfer->mfindex_kick = asap; 1953 } 1954 } else { 1955 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1956 & TRB_TR_FRAMEID_MASK) << 3; 1957 xfer->mfindex_kick |= mfindex & ~0x3fff; 1958 if (xfer->mfindex_kick + 0x100 < mfindex) { 1959 xfer->mfindex_kick += 0x4000; 1960 } 1961 } 1962 } 1963 1964 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1965 XHCIEPContext *epctx, uint64_t mfindex) 1966 { 1967 if (xfer->mfindex_kick > mfindex) { 1968 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1969 (xfer->mfindex_kick - mfindex) * 125000); 1970 xfer->running_retry = 1; 1971 } else { 1972 epctx->mfindex_last = xfer->mfindex_kick; 1973 timer_del(epctx->kick_timer); 1974 xfer->running_retry = 0; 1975 } 1976 } 1977 1978 1979 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1980 { 1981 uint64_t mfindex; 1982 1983 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1984 1985 xfer->in_xfer = epctx->type>>2; 1986 1987 switch(epctx->type) { 1988 case ET_INTR_OUT: 1989 case ET_INTR_IN: 1990 xfer->pkts = 0; 1991 xfer->iso_xfer = false; 1992 xfer->timed_xfer = true; 1993 mfindex = xhci_mfindex_get(xhci); 1994 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1995 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1996 if (xfer->running_retry) { 1997 return -1; 1998 } 1999 break; 2000 case ET_BULK_OUT: 2001 case ET_BULK_IN: 2002 xfer->pkts = 0; 2003 xfer->iso_xfer = false; 2004 xfer->timed_xfer = false; 2005 break; 2006 case ET_ISO_OUT: 2007 case ET_ISO_IN: 2008 xfer->pkts = 1; 2009 xfer->iso_xfer = true; 2010 xfer->timed_xfer = true; 2011 mfindex = xhci_mfindex_get(xhci); 2012 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 2013 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2014 if (xfer->running_retry) { 2015 return -1; 2016 } 2017 break; 2018 default: 2019 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 2020 return -1; 2021 } 2022 2023 if (xhci_setup_packet(xfer) < 0) { 2024 return -1; 2025 } 2026 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2027 xhci_try_complete_packet(xfer); 2028 return 0; 2029 } 2030 2031 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2032 { 2033 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 2034 xfer->epctx->epid, xfer->streamid); 2035 return xhci_submit(xhci, xfer, epctx); 2036 } 2037 2038 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 2039 unsigned int epid, unsigned int streamid) 2040 { 2041 XHCIEPContext *epctx; 2042 2043 assert(slotid >= 1 && slotid <= xhci->numslots); 2044 assert(epid >= 1 && epid <= 31); 2045 2046 if (!xhci->slots[slotid-1].enabled) { 2047 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 2048 return; 2049 } 2050 epctx = xhci->slots[slotid-1].eps[epid-1]; 2051 if (!epctx) { 2052 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 2053 epid, slotid); 2054 return; 2055 } 2056 2057 if (epctx->kick_active) { 2058 return; 2059 } 2060 xhci_kick_epctx(epctx, streamid); 2061 } 2062 2063 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid) 2064 { 2065 XHCIState *xhci = epctx->xhci; 2066 XHCIStreamContext *stctx; 2067 XHCITransfer *xfer; 2068 XHCIRing *ring; 2069 USBEndpoint *ep = NULL; 2070 uint64_t mfindex; 2071 unsigned int count = 0; 2072 int length; 2073 int i; 2074 2075 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid); 2076 assert(!epctx->kick_active); 2077 2078 /* If the device has been detached, but the guest has not noticed this 2079 yet the 2 above checks will succeed, but we must NOT continue */ 2080 if (!xhci->slots[epctx->slotid - 1].uport || 2081 !xhci->slots[epctx->slotid - 1].uport->dev || 2082 !xhci->slots[epctx->slotid - 1].uport->dev->attached) { 2083 return; 2084 } 2085 2086 if (epctx->retry) { 2087 XHCITransfer *xfer = epctx->retry; 2088 2089 trace_usb_xhci_xfer_retry(xfer); 2090 assert(xfer->running_retry); 2091 if (xfer->timed_xfer) { 2092 /* time to kick the transfer? */ 2093 mfindex = xhci_mfindex_get(xhci); 2094 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2095 if (xfer->running_retry) { 2096 return; 2097 } 2098 xfer->timed_xfer = 0; 2099 xfer->running_retry = 1; 2100 } 2101 if (xfer->iso_xfer) { 2102 /* retry iso transfer */ 2103 if (xhci_setup_packet(xfer) < 0) { 2104 return; 2105 } 2106 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2107 assert(xfer->packet.status != USB_RET_NAK); 2108 xhci_try_complete_packet(xfer); 2109 } else { 2110 /* retry nak'ed transfer */ 2111 if (xhci_setup_packet(xfer) < 0) { 2112 return; 2113 } 2114 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2115 if (xfer->packet.status == USB_RET_NAK) { 2116 return; 2117 } 2118 xhci_try_complete_packet(xfer); 2119 } 2120 assert(!xfer->running_retry); 2121 if (xfer->complete) { 2122 xhci_ep_free_xfer(epctx->retry); 2123 } 2124 epctx->retry = NULL; 2125 } 2126 2127 if (epctx->state == EP_HALTED) { 2128 DPRINTF("xhci: ep halted, not running schedule\n"); 2129 return; 2130 } 2131 2132 2133 if (epctx->nr_pstreams) { 2134 uint32_t err; 2135 stctx = xhci_find_stream(epctx, streamid, &err); 2136 if (stctx == NULL) { 2137 return; 2138 } 2139 ring = &stctx->ring; 2140 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2141 } else { 2142 ring = &epctx->ring; 2143 streamid = 0; 2144 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2145 } 2146 assert(ring->dequeue != 0); 2147 2148 epctx->kick_active++; 2149 while (1) { 2150 length = xhci_ring_chain_length(xhci, ring); 2151 if (length <= 0) { 2152 break; 2153 } 2154 xfer = xhci_ep_alloc_xfer(epctx, length); 2155 if (xfer == NULL) { 2156 break; 2157 } 2158 2159 for (i = 0; i < length; i++) { 2160 TRBType type; 2161 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL); 2162 assert(type); 2163 } 2164 xfer->streamid = streamid; 2165 2166 if (epctx->epid == 1) { 2167 xhci_fire_ctl_transfer(xhci, xfer); 2168 } else { 2169 xhci_fire_transfer(xhci, xfer, epctx); 2170 } 2171 if (xfer->complete) { 2172 xhci_ep_free_xfer(xfer); 2173 xfer = NULL; 2174 } 2175 2176 if (epctx->state == EP_HALTED) { 2177 break; 2178 } 2179 if (xfer != NULL && xfer->running_retry) { 2180 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2181 epctx->retry = xfer; 2182 break; 2183 } 2184 if (count++ > TRANSFER_LIMIT) { 2185 trace_usb_xhci_enforced_limit("transfers"); 2186 break; 2187 } 2188 } 2189 epctx->kick_active--; 2190 2191 ep = xhci_epid_to_usbep(epctx); 2192 if (ep) { 2193 usb_device_flush_ep_queue(ep->dev, ep); 2194 } 2195 } 2196 2197 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2198 { 2199 trace_usb_xhci_slot_enable(slotid); 2200 assert(slotid >= 1 && slotid <= xhci->numslots); 2201 xhci->slots[slotid-1].enabled = 1; 2202 xhci->slots[slotid-1].uport = NULL; 2203 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2204 2205 return CC_SUCCESS; 2206 } 2207 2208 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2209 { 2210 int i; 2211 2212 trace_usb_xhci_slot_disable(slotid); 2213 assert(slotid >= 1 && slotid <= xhci->numslots); 2214 2215 for (i = 1; i <= 31; i++) { 2216 if (xhci->slots[slotid-1].eps[i-1]) { 2217 xhci_disable_ep(xhci, slotid, i); 2218 } 2219 } 2220 2221 xhci->slots[slotid-1].enabled = 0; 2222 xhci->slots[slotid-1].addressed = 0; 2223 xhci->slots[slotid-1].uport = NULL; 2224 return CC_SUCCESS; 2225 } 2226 2227 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2228 { 2229 USBPort *uport; 2230 char path[32]; 2231 int i, pos, port; 2232 2233 port = (slot_ctx[1]>>16) & 0xFF; 2234 if (port < 1 || port > xhci->numports) { 2235 return NULL; 2236 } 2237 port = xhci->ports[port-1].uport->index+1; 2238 pos = snprintf(path, sizeof(path), "%d", port); 2239 for (i = 0; i < 5; i++) { 2240 port = (slot_ctx[0] >> 4*i) & 0x0f; 2241 if (!port) { 2242 break; 2243 } 2244 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2245 } 2246 2247 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2248 if (strcmp(uport->path, path) == 0) { 2249 return uport; 2250 } 2251 } 2252 return NULL; 2253 } 2254 2255 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2256 uint64_t pictx, bool bsr) 2257 { 2258 XHCISlot *slot; 2259 USBPort *uport; 2260 USBDevice *dev; 2261 dma_addr_t ictx, octx, dcbaap; 2262 uint64_t poctx; 2263 uint32_t ictl_ctx[2]; 2264 uint32_t slot_ctx[4]; 2265 uint32_t ep0_ctx[5]; 2266 int i; 2267 TRBCCode res; 2268 2269 assert(slotid >= 1 && slotid <= xhci->numslots); 2270 2271 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2272 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2273 ictx = xhci_mask64(pictx); 2274 octx = xhci_mask64(poctx); 2275 2276 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2277 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2278 2279 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2280 2281 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2282 DPRINTF("xhci: invalid input context control %08x %08x\n", 2283 ictl_ctx[0], ictl_ctx[1]); 2284 return CC_TRB_ERROR; 2285 } 2286 2287 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2288 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2289 2290 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2291 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2292 2293 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2294 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2295 2296 uport = xhci_lookup_uport(xhci, slot_ctx); 2297 if (uport == NULL) { 2298 DPRINTF("xhci: port not found\n"); 2299 return CC_TRB_ERROR; 2300 } 2301 trace_usb_xhci_slot_address(slotid, uport->path); 2302 2303 dev = uport->dev; 2304 if (!dev || !dev->attached) { 2305 DPRINTF("xhci: port %s not connected\n", uport->path); 2306 return CC_USB_TRANSACTION_ERROR; 2307 } 2308 2309 for (i = 0; i < xhci->numslots; i++) { 2310 if (i == slotid-1) { 2311 continue; 2312 } 2313 if (xhci->slots[i].uport == uport) { 2314 DPRINTF("xhci: port %s already assigned to slot %d\n", 2315 uport->path, i+1); 2316 return CC_TRB_ERROR; 2317 } 2318 } 2319 2320 slot = &xhci->slots[slotid-1]; 2321 slot->uport = uport; 2322 slot->ctx = octx; 2323 2324 /* Make sure device is in USB_STATE_DEFAULT state */ 2325 usb_device_reset(dev); 2326 if (bsr) { 2327 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2328 } else { 2329 USBPacket p; 2330 uint8_t buf[1]; 2331 2332 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2333 memset(&p, 0, sizeof(p)); 2334 usb_packet_addbuf(&p, buf, sizeof(buf)); 2335 usb_packet_setup(&p, USB_TOKEN_OUT, 2336 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2337 0, false, false); 2338 usb_device_handle_control(dev, &p, 2339 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2340 slotid, 0, 0, NULL); 2341 assert(p.status != USB_RET_ASYNC); 2342 } 2343 2344 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2345 2346 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2347 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2348 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2349 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2350 2351 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2352 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2353 2354 xhci->slots[slotid-1].addressed = 1; 2355 return res; 2356 } 2357 2358 2359 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2360 uint64_t pictx, bool dc) 2361 { 2362 dma_addr_t ictx, octx; 2363 uint32_t ictl_ctx[2]; 2364 uint32_t slot_ctx[4]; 2365 uint32_t islot_ctx[4]; 2366 uint32_t ep_ctx[5]; 2367 int i; 2368 TRBCCode res; 2369 2370 trace_usb_xhci_slot_configure(slotid); 2371 assert(slotid >= 1 && slotid <= xhci->numslots); 2372 2373 ictx = xhci_mask64(pictx); 2374 octx = xhci->slots[slotid-1].ctx; 2375 2376 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2377 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2378 2379 if (dc) { 2380 for (i = 2; i <= 31; i++) { 2381 if (xhci->slots[slotid-1].eps[i-1]) { 2382 xhci_disable_ep(xhci, slotid, i); 2383 } 2384 } 2385 2386 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2387 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2388 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2389 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2390 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2391 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2392 2393 return CC_SUCCESS; 2394 } 2395 2396 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2397 2398 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2399 DPRINTF("xhci: invalid input context control %08x %08x\n", 2400 ictl_ctx[0], ictl_ctx[1]); 2401 return CC_TRB_ERROR; 2402 } 2403 2404 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2405 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2406 2407 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2408 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2409 return CC_CONTEXT_STATE_ERROR; 2410 } 2411 2412 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2413 2414 for (i = 2; i <= 31; i++) { 2415 if (ictl_ctx[0] & (1<<i)) { 2416 xhci_disable_ep(xhci, slotid, i); 2417 } 2418 if (ictl_ctx[1] & (1<<i)) { 2419 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2420 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2421 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2422 ep_ctx[3], ep_ctx[4]); 2423 xhci_disable_ep(xhci, slotid, i); 2424 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2425 if (res != CC_SUCCESS) { 2426 return res; 2427 } 2428 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2429 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2430 ep_ctx[3], ep_ctx[4]); 2431 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2432 } 2433 } 2434 2435 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2436 if (res != CC_SUCCESS) { 2437 for (i = 2; i <= 31; i++) { 2438 if (ictl_ctx[1] & (1u << i)) { 2439 xhci_disable_ep(xhci, slotid, i); 2440 } 2441 } 2442 return res; 2443 } 2444 2445 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2446 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2447 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2448 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2449 SLOT_CONTEXT_ENTRIES_SHIFT); 2450 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2451 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2452 2453 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2454 2455 return CC_SUCCESS; 2456 } 2457 2458 2459 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2460 uint64_t pictx) 2461 { 2462 dma_addr_t ictx, octx; 2463 uint32_t ictl_ctx[2]; 2464 uint32_t iep0_ctx[5]; 2465 uint32_t ep0_ctx[5]; 2466 uint32_t islot_ctx[4]; 2467 uint32_t slot_ctx[4]; 2468 2469 trace_usb_xhci_slot_evaluate(slotid); 2470 assert(slotid >= 1 && slotid <= xhci->numslots); 2471 2472 ictx = xhci_mask64(pictx); 2473 octx = xhci->slots[slotid-1].ctx; 2474 2475 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2476 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2477 2478 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2479 2480 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2481 DPRINTF("xhci: invalid input context control %08x %08x\n", 2482 ictl_ctx[0], ictl_ctx[1]); 2483 return CC_TRB_ERROR; 2484 } 2485 2486 if (ictl_ctx[1] & 0x1) { 2487 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2488 2489 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2490 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2491 2492 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2493 2494 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2495 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2496 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2497 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2498 2499 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2500 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2501 2502 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2503 } 2504 2505 if (ictl_ctx[1] & 0x2) { 2506 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2507 2508 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2509 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2510 iep0_ctx[3], iep0_ctx[4]); 2511 2512 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2513 2514 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2515 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2516 2517 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2518 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2519 2520 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2521 } 2522 2523 return CC_SUCCESS; 2524 } 2525 2526 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2527 { 2528 uint32_t slot_ctx[4]; 2529 dma_addr_t octx; 2530 int i; 2531 2532 trace_usb_xhci_slot_reset(slotid); 2533 assert(slotid >= 1 && slotid <= xhci->numslots); 2534 2535 octx = xhci->slots[slotid-1].ctx; 2536 2537 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2538 2539 for (i = 2; i <= 31; i++) { 2540 if (xhci->slots[slotid-1].eps[i-1]) { 2541 xhci_disable_ep(xhci, slotid, i); 2542 } 2543 } 2544 2545 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2546 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2547 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2548 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2549 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2550 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2551 2552 return CC_SUCCESS; 2553 } 2554 2555 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2556 { 2557 unsigned int slotid; 2558 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2559 if (slotid < 1 || slotid > xhci->numslots) { 2560 DPRINTF("xhci: bad slot id %d\n", slotid); 2561 event->ccode = CC_TRB_ERROR; 2562 return 0; 2563 } else if (!xhci->slots[slotid-1].enabled) { 2564 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2565 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2566 return 0; 2567 } 2568 return slotid; 2569 } 2570 2571 /* cleanup slot state on usb device detach */ 2572 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2573 { 2574 int slot, ep; 2575 2576 for (slot = 0; slot < xhci->numslots; slot++) { 2577 if (xhci->slots[slot].uport == uport) { 2578 break; 2579 } 2580 } 2581 if (slot == xhci->numslots) { 2582 return; 2583 } 2584 2585 for (ep = 0; ep < 31; ep++) { 2586 if (xhci->slots[slot].eps[ep]) { 2587 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2588 } 2589 } 2590 xhci->slots[slot].uport = NULL; 2591 } 2592 2593 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2594 { 2595 dma_addr_t ctx; 2596 uint8_t bw_ctx[xhci->numports+1]; 2597 2598 DPRINTF("xhci_get_port_bandwidth()\n"); 2599 2600 ctx = xhci_mask64(pctx); 2601 2602 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2603 2604 /* TODO: actually implement real values here */ 2605 bw_ctx[0] = 0; 2606 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2607 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2608 2609 return CC_SUCCESS; 2610 } 2611 2612 static uint32_t rotl(uint32_t v, unsigned count) 2613 { 2614 count &= 31; 2615 return (v << count) | (v >> (32 - count)); 2616 } 2617 2618 2619 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2620 { 2621 uint32_t val; 2622 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2623 val += rotl(lo + 0x49434878, hi & 0x1F); 2624 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2625 return ~val; 2626 } 2627 2628 static void xhci_process_commands(XHCIState *xhci) 2629 { 2630 XHCITRB trb; 2631 TRBType type; 2632 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2633 dma_addr_t addr; 2634 unsigned int i, slotid = 0, count = 0; 2635 2636 DPRINTF("xhci_process_commands()\n"); 2637 if (!xhci_running(xhci)) { 2638 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2639 return; 2640 } 2641 2642 xhci->crcr_low |= CRCR_CRR; 2643 2644 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2645 event.ptr = addr; 2646 switch (type) { 2647 case CR_ENABLE_SLOT: 2648 for (i = 0; i < xhci->numslots; i++) { 2649 if (!xhci->slots[i].enabled) { 2650 break; 2651 } 2652 } 2653 if (i >= xhci->numslots) { 2654 DPRINTF("xhci: no device slots available\n"); 2655 event.ccode = CC_NO_SLOTS_ERROR; 2656 } else { 2657 slotid = i+1; 2658 event.ccode = xhci_enable_slot(xhci, slotid); 2659 } 2660 break; 2661 case CR_DISABLE_SLOT: 2662 slotid = xhci_get_slot(xhci, &event, &trb); 2663 if (slotid) { 2664 event.ccode = xhci_disable_slot(xhci, slotid); 2665 } 2666 break; 2667 case CR_ADDRESS_DEVICE: 2668 slotid = xhci_get_slot(xhci, &event, &trb); 2669 if (slotid) { 2670 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2671 trb.control & TRB_CR_BSR); 2672 } 2673 break; 2674 case CR_CONFIGURE_ENDPOINT: 2675 slotid = xhci_get_slot(xhci, &event, &trb); 2676 if (slotid) { 2677 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2678 trb.control & TRB_CR_DC); 2679 } 2680 break; 2681 case CR_EVALUATE_CONTEXT: 2682 slotid = xhci_get_slot(xhci, &event, &trb); 2683 if (slotid) { 2684 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2685 } 2686 break; 2687 case CR_STOP_ENDPOINT: 2688 slotid = xhci_get_slot(xhci, &event, &trb); 2689 if (slotid) { 2690 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2691 & TRB_CR_EPID_MASK; 2692 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2693 } 2694 break; 2695 case CR_RESET_ENDPOINT: 2696 slotid = xhci_get_slot(xhci, &event, &trb); 2697 if (slotid) { 2698 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2699 & TRB_CR_EPID_MASK; 2700 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2701 } 2702 break; 2703 case CR_SET_TR_DEQUEUE: 2704 slotid = xhci_get_slot(xhci, &event, &trb); 2705 if (slotid) { 2706 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2707 & TRB_CR_EPID_MASK; 2708 unsigned int streamid = (trb.status >> 16) & 0xffff; 2709 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2710 epid, streamid, 2711 trb.parameter); 2712 } 2713 break; 2714 case CR_RESET_DEVICE: 2715 slotid = xhci_get_slot(xhci, &event, &trb); 2716 if (slotid) { 2717 event.ccode = xhci_reset_slot(xhci, slotid); 2718 } 2719 break; 2720 case CR_GET_PORT_BANDWIDTH: 2721 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2722 break; 2723 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2724 if (xhci->nec_quirks) { 2725 event.type = 48; /* NEC reply */ 2726 event.length = 0x3025; 2727 } else { 2728 event.ccode = CC_TRB_ERROR; 2729 } 2730 break; 2731 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2732 if (xhci->nec_quirks) { 2733 uint32_t chi = trb.parameter >> 32; 2734 uint32_t clo = trb.parameter; 2735 uint32_t val = xhci_nec_challenge(chi, clo); 2736 event.length = val & 0xFFFF; 2737 event.epid = val >> 16; 2738 slotid = val >> 24; 2739 event.type = 48; /* NEC reply */ 2740 } else { 2741 event.ccode = CC_TRB_ERROR; 2742 } 2743 break; 2744 default: 2745 trace_usb_xhci_unimplemented("command", type); 2746 event.ccode = CC_TRB_ERROR; 2747 break; 2748 } 2749 event.slotid = slotid; 2750 xhci_event(xhci, &event, 0); 2751 2752 if (count++ > COMMAND_LIMIT) { 2753 trace_usb_xhci_enforced_limit("commands"); 2754 return; 2755 } 2756 } 2757 } 2758 2759 static bool xhci_port_have_device(XHCIPort *port) 2760 { 2761 if (!port->uport->dev || !port->uport->dev->attached) { 2762 return false; /* no device present */ 2763 } 2764 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2765 return false; /* speed mismatch */ 2766 } 2767 return true; 2768 } 2769 2770 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2771 { 2772 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2773 port->portnr << 24 }; 2774 2775 if ((port->portsc & bits) == bits) { 2776 return; 2777 } 2778 trace_usb_xhci_port_notify(port->portnr, bits); 2779 port->portsc |= bits; 2780 if (!xhci_running(port->xhci)) { 2781 return; 2782 } 2783 xhci_event(port->xhci, &ev, 0); 2784 } 2785 2786 static void xhci_port_update(XHCIPort *port, int is_detach) 2787 { 2788 uint32_t pls = PLS_RX_DETECT; 2789 2790 port->portsc = PORTSC_PP; 2791 if (!is_detach && xhci_port_have_device(port)) { 2792 port->portsc |= PORTSC_CCS; 2793 switch (port->uport->dev->speed) { 2794 case USB_SPEED_LOW: 2795 port->portsc |= PORTSC_SPEED_LOW; 2796 pls = PLS_POLLING; 2797 break; 2798 case USB_SPEED_FULL: 2799 port->portsc |= PORTSC_SPEED_FULL; 2800 pls = PLS_POLLING; 2801 break; 2802 case USB_SPEED_HIGH: 2803 port->portsc |= PORTSC_SPEED_HIGH; 2804 pls = PLS_POLLING; 2805 break; 2806 case USB_SPEED_SUPER: 2807 port->portsc |= PORTSC_SPEED_SUPER; 2808 port->portsc |= PORTSC_PED; 2809 pls = PLS_U0; 2810 break; 2811 } 2812 } 2813 set_field(&port->portsc, pls, PORTSC_PLS); 2814 trace_usb_xhci_port_link(port->portnr, pls); 2815 xhci_port_notify(port, PORTSC_CSC); 2816 } 2817 2818 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2819 { 2820 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2821 2822 if (!xhci_port_have_device(port)) { 2823 return; 2824 } 2825 2826 usb_device_reset(port->uport->dev); 2827 2828 switch (port->uport->dev->speed) { 2829 case USB_SPEED_SUPER: 2830 if (warm_reset) { 2831 port->portsc |= PORTSC_WRC; 2832 } 2833 /* fall through */ 2834 case USB_SPEED_LOW: 2835 case USB_SPEED_FULL: 2836 case USB_SPEED_HIGH: 2837 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2838 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2839 port->portsc |= PORTSC_PED; 2840 break; 2841 } 2842 2843 port->portsc &= ~PORTSC_PR; 2844 xhci_port_notify(port, PORTSC_PRC); 2845 } 2846 2847 static void xhci_reset(DeviceState *dev) 2848 { 2849 XHCIState *xhci = XHCI(dev); 2850 int i; 2851 2852 trace_usb_xhci_reset(); 2853 if (!(xhci->usbsts & USBSTS_HCH)) { 2854 DPRINTF("xhci: reset while running!\n"); 2855 } 2856 2857 xhci->usbcmd = 0; 2858 xhci->usbsts = USBSTS_HCH; 2859 xhci->dnctrl = 0; 2860 xhci->crcr_low = 0; 2861 xhci->crcr_high = 0; 2862 xhci->dcbaap_low = 0; 2863 xhci->dcbaap_high = 0; 2864 xhci->config = 0; 2865 2866 for (i = 0; i < xhci->numslots; i++) { 2867 xhci_disable_slot(xhci, i+1); 2868 } 2869 2870 for (i = 0; i < xhci->numports; i++) { 2871 xhci_port_update(xhci->ports + i, 0); 2872 } 2873 2874 for (i = 0; i < xhci->numintrs; i++) { 2875 xhci->intr[i].iman = 0; 2876 xhci->intr[i].imod = 0; 2877 xhci->intr[i].erstsz = 0; 2878 xhci->intr[i].erstba_low = 0; 2879 xhci->intr[i].erstba_high = 0; 2880 xhci->intr[i].erdp_low = 0; 2881 xhci->intr[i].erdp_high = 0; 2882 xhci->intr[i].msix_used = 0; 2883 2884 xhci->intr[i].er_ep_idx = 0; 2885 xhci->intr[i].er_pcs = 1; 2886 xhci->intr[i].ev_buffer_put = 0; 2887 xhci->intr[i].ev_buffer_get = 0; 2888 } 2889 2890 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2891 xhci_mfwrap_update(xhci); 2892 } 2893 2894 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2895 { 2896 XHCIState *xhci = ptr; 2897 uint32_t ret; 2898 2899 switch (reg) { 2900 case 0x00: /* HCIVERSION, CAPLENGTH */ 2901 ret = 0x01000000 | LEN_CAP; 2902 break; 2903 case 0x04: /* HCSPARAMS 1 */ 2904 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2905 | (xhci->numintrs<<8) | xhci->numslots; 2906 break; 2907 case 0x08: /* HCSPARAMS 2 */ 2908 ret = 0x0000000f; 2909 break; 2910 case 0x0c: /* HCSPARAMS 3 */ 2911 ret = 0x00000000; 2912 break; 2913 case 0x10: /* HCCPARAMS */ 2914 if (sizeof(dma_addr_t) == 4) { 2915 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 2916 } else { 2917 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 2918 } 2919 break; 2920 case 0x14: /* DBOFF */ 2921 ret = OFF_DOORBELL; 2922 break; 2923 case 0x18: /* RTSOFF */ 2924 ret = OFF_RUNTIME; 2925 break; 2926 2927 /* extended capabilities */ 2928 case 0x20: /* Supported Protocol:00 */ 2929 ret = 0x02000402; /* USB 2.0 */ 2930 break; 2931 case 0x24: /* Supported Protocol:04 */ 2932 ret = 0x20425355; /* "USB " */ 2933 break; 2934 case 0x28: /* Supported Protocol:08 */ 2935 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2936 ret = (xhci->numports_2<<8) | (xhci->numports_3+1); 2937 } else { 2938 ret = (xhci->numports_2<<8) | 1; 2939 } 2940 break; 2941 case 0x2c: /* Supported Protocol:0c */ 2942 ret = 0x00000000; /* reserved */ 2943 break; 2944 case 0x30: /* Supported Protocol:00 */ 2945 ret = 0x03000002; /* USB 3.0 */ 2946 break; 2947 case 0x34: /* Supported Protocol:04 */ 2948 ret = 0x20425355; /* "USB " */ 2949 break; 2950 case 0x38: /* Supported Protocol:08 */ 2951 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2952 ret = (xhci->numports_3<<8) | 1; 2953 } else { 2954 ret = (xhci->numports_3<<8) | (xhci->numports_2+1); 2955 } 2956 break; 2957 case 0x3c: /* Supported Protocol:0c */ 2958 ret = 0x00000000; /* reserved */ 2959 break; 2960 default: 2961 trace_usb_xhci_unimplemented("cap read", reg); 2962 ret = 0; 2963 } 2964 2965 trace_usb_xhci_cap_read(reg, ret); 2966 return ret; 2967 } 2968 2969 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2970 { 2971 XHCIPort *port = ptr; 2972 uint32_t ret; 2973 2974 switch (reg) { 2975 case 0x00: /* PORTSC */ 2976 ret = port->portsc; 2977 break; 2978 case 0x04: /* PORTPMSC */ 2979 case 0x08: /* PORTLI */ 2980 ret = 0; 2981 break; 2982 case 0x0c: /* reserved */ 2983 default: 2984 trace_usb_xhci_unimplemented("port read", reg); 2985 ret = 0; 2986 } 2987 2988 trace_usb_xhci_port_read(port->portnr, reg, ret); 2989 return ret; 2990 } 2991 2992 static void xhci_port_write(void *ptr, hwaddr reg, 2993 uint64_t val, unsigned size) 2994 { 2995 XHCIPort *port = ptr; 2996 uint32_t portsc, notify; 2997 2998 trace_usb_xhci_port_write(port->portnr, reg, val); 2999 3000 switch (reg) { 3001 case 0x00: /* PORTSC */ 3002 /* write-1-to-start bits */ 3003 if (val & PORTSC_WPR) { 3004 xhci_port_reset(port, true); 3005 break; 3006 } 3007 if (val & PORTSC_PR) { 3008 xhci_port_reset(port, false); 3009 break; 3010 } 3011 3012 portsc = port->portsc; 3013 notify = 0; 3014 /* write-1-to-clear bits*/ 3015 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 3016 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 3017 if (val & PORTSC_LWS) { 3018 /* overwrite PLS only when LWS=1 */ 3019 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 3020 uint32_t new_pls = get_field(val, PORTSC_PLS); 3021 switch (new_pls) { 3022 case PLS_U0: 3023 if (old_pls != PLS_U0) { 3024 set_field(&portsc, new_pls, PORTSC_PLS); 3025 trace_usb_xhci_port_link(port->portnr, new_pls); 3026 notify = PORTSC_PLC; 3027 } 3028 break; 3029 case PLS_U3: 3030 if (old_pls < PLS_U3) { 3031 set_field(&portsc, new_pls, PORTSC_PLS); 3032 trace_usb_xhci_port_link(port->portnr, new_pls); 3033 } 3034 break; 3035 case PLS_RESUME: 3036 /* windows does this for some reason, don't spam stderr */ 3037 break; 3038 default: 3039 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 3040 __func__, old_pls, new_pls); 3041 break; 3042 } 3043 } 3044 /* read/write bits */ 3045 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 3046 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 3047 port->portsc = portsc; 3048 if (notify) { 3049 xhci_port_notify(port, notify); 3050 } 3051 break; 3052 case 0x04: /* PORTPMSC */ 3053 case 0x08: /* PORTLI */ 3054 default: 3055 trace_usb_xhci_unimplemented("port write", reg); 3056 } 3057 } 3058 3059 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 3060 { 3061 XHCIState *xhci = ptr; 3062 uint32_t ret; 3063 3064 switch (reg) { 3065 case 0x00: /* USBCMD */ 3066 ret = xhci->usbcmd; 3067 break; 3068 case 0x04: /* USBSTS */ 3069 ret = xhci->usbsts; 3070 break; 3071 case 0x08: /* PAGESIZE */ 3072 ret = 1; /* 4KiB */ 3073 break; 3074 case 0x14: /* DNCTRL */ 3075 ret = xhci->dnctrl; 3076 break; 3077 case 0x18: /* CRCR low */ 3078 ret = xhci->crcr_low & ~0xe; 3079 break; 3080 case 0x1c: /* CRCR high */ 3081 ret = xhci->crcr_high; 3082 break; 3083 case 0x30: /* DCBAAP low */ 3084 ret = xhci->dcbaap_low; 3085 break; 3086 case 0x34: /* DCBAAP high */ 3087 ret = xhci->dcbaap_high; 3088 break; 3089 case 0x38: /* CONFIG */ 3090 ret = xhci->config; 3091 break; 3092 default: 3093 trace_usb_xhci_unimplemented("oper read", reg); 3094 ret = 0; 3095 } 3096 3097 trace_usb_xhci_oper_read(reg, ret); 3098 return ret; 3099 } 3100 3101 static void xhci_oper_write(void *ptr, hwaddr reg, 3102 uint64_t val, unsigned size) 3103 { 3104 XHCIState *xhci = ptr; 3105 DeviceState *d = DEVICE(ptr); 3106 3107 trace_usb_xhci_oper_write(reg, val); 3108 3109 switch (reg) { 3110 case 0x00: /* USBCMD */ 3111 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3112 xhci_run(xhci); 3113 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3114 xhci_stop(xhci); 3115 } 3116 if (val & USBCMD_CSS) { 3117 /* save state */ 3118 xhci->usbsts &= ~USBSTS_SRE; 3119 } 3120 if (val & USBCMD_CRS) { 3121 /* restore state */ 3122 xhci->usbsts |= USBSTS_SRE; 3123 } 3124 xhci->usbcmd = val & 0xc0f; 3125 xhci_mfwrap_update(xhci); 3126 if (val & USBCMD_HCRST) { 3127 xhci_reset(d); 3128 } 3129 xhci_intx_update(xhci); 3130 break; 3131 3132 case 0x04: /* USBSTS */ 3133 /* these bits are write-1-to-clear */ 3134 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3135 xhci_intx_update(xhci); 3136 break; 3137 3138 case 0x14: /* DNCTRL */ 3139 xhci->dnctrl = val & 0xffff; 3140 break; 3141 case 0x18: /* CRCR low */ 3142 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3143 break; 3144 case 0x1c: /* CRCR high */ 3145 xhci->crcr_high = val; 3146 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3147 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3148 xhci->crcr_low &= ~CRCR_CRR; 3149 xhci_event(xhci, &event, 0); 3150 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3151 } else { 3152 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3153 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3154 } 3155 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3156 break; 3157 case 0x30: /* DCBAAP low */ 3158 xhci->dcbaap_low = val & 0xffffffc0; 3159 break; 3160 case 0x34: /* DCBAAP high */ 3161 xhci->dcbaap_high = val; 3162 break; 3163 case 0x38: /* CONFIG */ 3164 xhci->config = val & 0xff; 3165 break; 3166 default: 3167 trace_usb_xhci_unimplemented("oper write", reg); 3168 } 3169 } 3170 3171 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3172 unsigned size) 3173 { 3174 XHCIState *xhci = ptr; 3175 uint32_t ret = 0; 3176 3177 if (reg < 0x20) { 3178 switch (reg) { 3179 case 0x00: /* MFINDEX */ 3180 ret = xhci_mfindex_get(xhci) & 0x3fff; 3181 break; 3182 default: 3183 trace_usb_xhci_unimplemented("runtime read", reg); 3184 break; 3185 } 3186 } else { 3187 int v = (reg - 0x20) / 0x20; 3188 XHCIInterrupter *intr = &xhci->intr[v]; 3189 switch (reg & 0x1f) { 3190 case 0x00: /* IMAN */ 3191 ret = intr->iman; 3192 break; 3193 case 0x04: /* IMOD */ 3194 ret = intr->imod; 3195 break; 3196 case 0x08: /* ERSTSZ */ 3197 ret = intr->erstsz; 3198 break; 3199 case 0x10: /* ERSTBA low */ 3200 ret = intr->erstba_low; 3201 break; 3202 case 0x14: /* ERSTBA high */ 3203 ret = intr->erstba_high; 3204 break; 3205 case 0x18: /* ERDP low */ 3206 ret = intr->erdp_low; 3207 break; 3208 case 0x1c: /* ERDP high */ 3209 ret = intr->erdp_high; 3210 break; 3211 } 3212 } 3213 3214 trace_usb_xhci_runtime_read(reg, ret); 3215 return ret; 3216 } 3217 3218 static void xhci_runtime_write(void *ptr, hwaddr reg, 3219 uint64_t val, unsigned size) 3220 { 3221 XHCIState *xhci = ptr; 3222 int v = (reg - 0x20) / 0x20; 3223 XHCIInterrupter *intr = &xhci->intr[v]; 3224 trace_usb_xhci_runtime_write(reg, val); 3225 3226 if (reg < 0x20) { 3227 trace_usb_xhci_unimplemented("runtime write", reg); 3228 return; 3229 } 3230 3231 switch (reg & 0x1f) { 3232 case 0x00: /* IMAN */ 3233 if (val & IMAN_IP) { 3234 intr->iman &= ~IMAN_IP; 3235 } 3236 intr->iman &= ~IMAN_IE; 3237 intr->iman |= val & IMAN_IE; 3238 if (v == 0) { 3239 xhci_intx_update(xhci); 3240 } 3241 xhci_msix_update(xhci, v); 3242 break; 3243 case 0x04: /* IMOD */ 3244 intr->imod = val; 3245 break; 3246 case 0x08: /* ERSTSZ */ 3247 intr->erstsz = val & 0xffff; 3248 break; 3249 case 0x10: /* ERSTBA low */ 3250 if (xhci->nec_quirks) { 3251 /* NEC driver bug: it doesn't align this to 64 bytes */ 3252 intr->erstba_low = val & 0xfffffff0; 3253 } else { 3254 intr->erstba_low = val & 0xffffffc0; 3255 } 3256 break; 3257 case 0x14: /* ERSTBA high */ 3258 intr->erstba_high = val; 3259 xhci_er_reset(xhci, v); 3260 break; 3261 case 0x18: /* ERDP low */ 3262 if (val & ERDP_EHB) { 3263 intr->erdp_low &= ~ERDP_EHB; 3264 } 3265 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3266 if (val & ERDP_EHB) { 3267 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 3268 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE; 3269 if (erdp >= intr->er_start && 3270 erdp < (intr->er_start + TRB_SIZE * intr->er_size) && 3271 dp_idx != intr->er_ep_idx) { 3272 xhci_intr_raise(xhci, v); 3273 } 3274 } 3275 break; 3276 case 0x1c: /* ERDP high */ 3277 intr->erdp_high = val; 3278 break; 3279 default: 3280 trace_usb_xhci_unimplemented("oper write", reg); 3281 } 3282 } 3283 3284 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3285 unsigned size) 3286 { 3287 /* doorbells always read as 0 */ 3288 trace_usb_xhci_doorbell_read(reg, 0); 3289 return 0; 3290 } 3291 3292 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3293 uint64_t val, unsigned size) 3294 { 3295 XHCIState *xhci = ptr; 3296 unsigned int epid, streamid; 3297 3298 trace_usb_xhci_doorbell_write(reg, val); 3299 3300 if (!xhci_running(xhci)) { 3301 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3302 return; 3303 } 3304 3305 reg >>= 2; 3306 3307 if (reg == 0) { 3308 if (val == 0) { 3309 xhci_process_commands(xhci); 3310 } else { 3311 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3312 (uint32_t)val); 3313 } 3314 } else { 3315 epid = val & 0xff; 3316 streamid = (val >> 16) & 0xffff; 3317 if (reg > xhci->numslots) { 3318 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3319 } else if (epid > 31) { 3320 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3321 (int)reg, (uint32_t)val); 3322 } else { 3323 xhci_kick_ep(xhci, reg, epid, streamid); 3324 } 3325 } 3326 } 3327 3328 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3329 unsigned width) 3330 { 3331 /* nothing */ 3332 } 3333 3334 static const MemoryRegionOps xhci_cap_ops = { 3335 .read = xhci_cap_read, 3336 .write = xhci_cap_write, 3337 .valid.min_access_size = 1, 3338 .valid.max_access_size = 4, 3339 .impl.min_access_size = 4, 3340 .impl.max_access_size = 4, 3341 .endianness = DEVICE_LITTLE_ENDIAN, 3342 }; 3343 3344 static const MemoryRegionOps xhci_oper_ops = { 3345 .read = xhci_oper_read, 3346 .write = xhci_oper_write, 3347 .valid.min_access_size = 4, 3348 .valid.max_access_size = 4, 3349 .endianness = DEVICE_LITTLE_ENDIAN, 3350 }; 3351 3352 static const MemoryRegionOps xhci_port_ops = { 3353 .read = xhci_port_read, 3354 .write = xhci_port_write, 3355 .valid.min_access_size = 4, 3356 .valid.max_access_size = 4, 3357 .endianness = DEVICE_LITTLE_ENDIAN, 3358 }; 3359 3360 static const MemoryRegionOps xhci_runtime_ops = { 3361 .read = xhci_runtime_read, 3362 .write = xhci_runtime_write, 3363 .valid.min_access_size = 4, 3364 .valid.max_access_size = 4, 3365 .endianness = DEVICE_LITTLE_ENDIAN, 3366 }; 3367 3368 static const MemoryRegionOps xhci_doorbell_ops = { 3369 .read = xhci_doorbell_read, 3370 .write = xhci_doorbell_write, 3371 .valid.min_access_size = 4, 3372 .valid.max_access_size = 4, 3373 .endianness = DEVICE_LITTLE_ENDIAN, 3374 }; 3375 3376 static void xhci_attach(USBPort *usbport) 3377 { 3378 XHCIState *xhci = usbport->opaque; 3379 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3380 3381 xhci_port_update(port, 0); 3382 } 3383 3384 static void xhci_detach(USBPort *usbport) 3385 { 3386 XHCIState *xhci = usbport->opaque; 3387 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3388 3389 xhci_detach_slot(xhci, usbport); 3390 xhci_port_update(port, 1); 3391 } 3392 3393 static void xhci_wakeup(USBPort *usbport) 3394 { 3395 XHCIState *xhci = usbport->opaque; 3396 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3397 3398 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3399 return; 3400 } 3401 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3402 xhci_port_notify(port, PORTSC_PLC); 3403 } 3404 3405 static void xhci_complete(USBPort *port, USBPacket *packet) 3406 { 3407 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3408 3409 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3410 xhci_ep_nuke_one_xfer(xfer, 0); 3411 return; 3412 } 3413 xhci_try_complete_packet(xfer); 3414 xhci_kick_epctx(xfer->epctx, xfer->streamid); 3415 if (xfer->complete) { 3416 xhci_ep_free_xfer(xfer); 3417 } 3418 } 3419 3420 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3421 { 3422 USBBus *bus = usb_bus_from_device(child); 3423 XHCIState *xhci = container_of(bus, XHCIState, bus); 3424 3425 xhci_detach_slot(xhci, child->port); 3426 } 3427 3428 static USBPortOps xhci_uport_ops = { 3429 .attach = xhci_attach, 3430 .detach = xhci_detach, 3431 .wakeup = xhci_wakeup, 3432 .complete = xhci_complete, 3433 .child_detach = xhci_child_detach, 3434 }; 3435 3436 static int xhci_find_epid(USBEndpoint *ep) 3437 { 3438 if (ep->nr == 0) { 3439 return 1; 3440 } 3441 if (ep->pid == USB_TOKEN_IN) { 3442 return ep->nr * 2 + 1; 3443 } else { 3444 return ep->nr * 2; 3445 } 3446 } 3447 3448 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx) 3449 { 3450 USBPort *uport; 3451 uint32_t token; 3452 3453 if (!epctx) { 3454 return NULL; 3455 } 3456 uport = epctx->xhci->slots[epctx->slotid - 1].uport; 3457 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; 3458 if (!uport) { 3459 return NULL; 3460 } 3461 return usb_ep_get(uport->dev, token, epctx->epid >> 1); 3462 } 3463 3464 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3465 unsigned int stream) 3466 { 3467 XHCIState *xhci = container_of(bus, XHCIState, bus); 3468 int slotid; 3469 3470 DPRINTF("%s\n", __func__); 3471 slotid = ep->dev->addr; 3472 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3473 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3474 return; 3475 } 3476 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3477 } 3478 3479 static USBBusOps xhci_bus_ops = { 3480 .wakeup_endpoint = xhci_wakeup_endpoint, 3481 }; 3482 3483 static void usb_xhci_init(XHCIState *xhci) 3484 { 3485 DeviceState *dev = DEVICE(xhci); 3486 XHCIPort *port; 3487 int i, usbports, speedmask; 3488 3489 xhci->usbsts = USBSTS_HCH; 3490 3491 if (xhci->numports_2 > MAXPORTS_2) { 3492 xhci->numports_2 = MAXPORTS_2; 3493 } 3494 if (xhci->numports_3 > MAXPORTS_3) { 3495 xhci->numports_3 = MAXPORTS_3; 3496 } 3497 usbports = MAX(xhci->numports_2, xhci->numports_3); 3498 xhci->numports = xhci->numports_2 + xhci->numports_3; 3499 3500 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3501 3502 for (i = 0; i < usbports; i++) { 3503 speedmask = 0; 3504 if (i < xhci->numports_2) { 3505 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3506 port = &xhci->ports[i + xhci->numports_3]; 3507 port->portnr = i + 1 + xhci->numports_3; 3508 } else { 3509 port = &xhci->ports[i]; 3510 port->portnr = i + 1; 3511 } 3512 port->uport = &xhci->uports[i]; 3513 port->speedmask = 3514 USB_SPEED_MASK_LOW | 3515 USB_SPEED_MASK_FULL | 3516 USB_SPEED_MASK_HIGH; 3517 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3518 speedmask |= port->speedmask; 3519 } 3520 if (i < xhci->numports_3) { 3521 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3522 port = &xhci->ports[i]; 3523 port->portnr = i + 1; 3524 } else { 3525 port = &xhci->ports[i + xhci->numports_2]; 3526 port->portnr = i + 1 + xhci->numports_2; 3527 } 3528 port->uport = &xhci->uports[i]; 3529 port->speedmask = USB_SPEED_MASK_SUPER; 3530 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3531 speedmask |= port->speedmask; 3532 } 3533 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3534 &xhci_uport_ops, speedmask); 3535 } 3536 } 3537 3538 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) 3539 { 3540 int i, ret; 3541 Error *err = NULL; 3542 3543 XHCIState *xhci = XHCI(dev); 3544 3545 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3546 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3547 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3548 dev->config[0x60] = 0x30; /* release number */ 3549 3550 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { 3551 xhci->nec_quirks = true; 3552 } 3553 if (xhci->numintrs > MAXINTRS) { 3554 xhci->numintrs = MAXINTRS; 3555 } 3556 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3557 xhci->numintrs++; 3558 } 3559 if (xhci->numintrs < 1) { 3560 xhci->numintrs = 1; 3561 } 3562 if (xhci->numslots > MAXSLOTS) { 3563 xhci->numslots = MAXSLOTS; 3564 } 3565 if (xhci->numslots < 1) { 3566 xhci->numslots = 1; 3567 } 3568 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3569 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3570 } else { 3571 xhci->max_pstreams_mask = 0; 3572 } 3573 3574 if (xhci->msi != ON_OFF_AUTO_OFF) { 3575 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); 3576 /* Any error other than -ENOTSUP(board's MSI support is broken) 3577 * is a programming error */ 3578 assert(!ret || ret == -ENOTSUP); 3579 if (ret && xhci->msi == ON_OFF_AUTO_ON) { 3580 /* Can't satisfy user's explicit msi=on request, fail */ 3581 error_append_hint(&err, "You have to use msi=auto (default) or " 3582 "msi=off with this machine type.\n"); 3583 error_propagate(errp, err); 3584 return; 3585 } 3586 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); 3587 /* With msi=auto, we fall back to MSI off silently */ 3588 error_free(err); 3589 } 3590 3591 usb_xhci_init(xhci); 3592 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3593 3594 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3595 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3596 "capabilities", LEN_CAP); 3597 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3598 "operational", 0x400); 3599 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3600 "runtime", LEN_RUNTIME); 3601 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3602 "doorbell", LEN_DOORBELL); 3603 3604 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3605 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3606 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3607 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3608 3609 for (i = 0; i < xhci->numports; i++) { 3610 XHCIPort *port = &xhci->ports[i]; 3611 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3612 port->xhci = xhci; 3613 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3614 port->name, 0x10); 3615 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3616 } 3617 3618 pci_register_bar(dev, 0, 3619 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3620 &xhci->mem); 3621 3622 if (pci_bus_is_express(dev->bus) || 3623 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 3624 ret = pcie_endpoint_cap_init(dev, 0xa0); 3625 assert(ret >= 0); 3626 } 3627 3628 if (xhci->msix != ON_OFF_AUTO_OFF) { 3629 /* TODO check for errors, and should fail when msix=on */ 3630 msix_init(dev, xhci->numintrs, 3631 &xhci->mem, 0, OFF_MSIX_TABLE, 3632 &xhci->mem, 0, OFF_MSIX_PBA, 3633 0x90, NULL); 3634 } 3635 } 3636 3637 static void usb_xhci_exit(PCIDevice *dev) 3638 { 3639 int i; 3640 XHCIState *xhci = XHCI(dev); 3641 3642 trace_usb_xhci_exit(); 3643 3644 for (i = 0; i < xhci->numslots; i++) { 3645 xhci_disable_slot(xhci, i + 1); 3646 } 3647 3648 if (xhci->mfwrap_timer) { 3649 timer_del(xhci->mfwrap_timer); 3650 timer_free(xhci->mfwrap_timer); 3651 xhci->mfwrap_timer = NULL; 3652 } 3653 3654 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3655 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3656 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3657 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3658 3659 for (i = 0; i < xhci->numports; i++) { 3660 XHCIPort *port = &xhci->ports[i]; 3661 memory_region_del_subregion(&xhci->mem, &port->mem); 3662 } 3663 3664 /* destroy msix memory region */ 3665 if (dev->msix_table && dev->msix_pba 3666 && dev->msix_entry_used) { 3667 msix_uninit(dev, &xhci->mem, &xhci->mem); 3668 } 3669 3670 usb_bus_release(&xhci->bus); 3671 } 3672 3673 static int usb_xhci_post_load(void *opaque, int version_id) 3674 { 3675 XHCIState *xhci = opaque; 3676 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3677 XHCISlot *slot; 3678 XHCIEPContext *epctx; 3679 dma_addr_t dcbaap, pctx; 3680 uint32_t slot_ctx[4]; 3681 uint32_t ep_ctx[5]; 3682 int slotid, epid, state, intr; 3683 3684 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3685 3686 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3687 slot = &xhci->slots[slotid-1]; 3688 if (!slot->addressed) { 3689 continue; 3690 } 3691 slot->ctx = 3692 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3693 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3694 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3695 if (!slot->uport) { 3696 /* should not happen, but may trigger on guest bugs */ 3697 slot->enabled = 0; 3698 slot->addressed = 0; 3699 continue; 3700 } 3701 assert(slot->uport && slot->uport->dev); 3702 3703 for (epid = 1; epid <= 31; epid++) { 3704 pctx = slot->ctx + 32 * epid; 3705 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3706 state = ep_ctx[0] & EP_STATE_MASK; 3707 if (state == EP_DISABLED) { 3708 continue; 3709 } 3710 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3711 slot->eps[epid-1] = epctx; 3712 xhci_init_epctx(epctx, pctx, ep_ctx); 3713 epctx->state = state; 3714 if (state == EP_RUNNING) { 3715 /* kick endpoint after vmload is finished */ 3716 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3717 } 3718 } 3719 } 3720 3721 for (intr = 0; intr < xhci->numintrs; intr++) { 3722 if (xhci->intr[intr].msix_used) { 3723 msix_vector_use(pci_dev, intr); 3724 } else { 3725 msix_vector_unuse(pci_dev, intr); 3726 } 3727 } 3728 3729 return 0; 3730 } 3731 3732 static const VMStateDescription vmstate_xhci_ring = { 3733 .name = "xhci-ring", 3734 .version_id = 1, 3735 .fields = (VMStateField[]) { 3736 VMSTATE_UINT64(dequeue, XHCIRing), 3737 VMSTATE_BOOL(ccs, XHCIRing), 3738 VMSTATE_END_OF_LIST() 3739 } 3740 }; 3741 3742 static const VMStateDescription vmstate_xhci_port = { 3743 .name = "xhci-port", 3744 .version_id = 1, 3745 .fields = (VMStateField[]) { 3746 VMSTATE_UINT32(portsc, XHCIPort), 3747 VMSTATE_END_OF_LIST() 3748 } 3749 }; 3750 3751 static const VMStateDescription vmstate_xhci_slot = { 3752 .name = "xhci-slot", 3753 .version_id = 1, 3754 .fields = (VMStateField[]) { 3755 VMSTATE_BOOL(enabled, XHCISlot), 3756 VMSTATE_BOOL(addressed, XHCISlot), 3757 VMSTATE_END_OF_LIST() 3758 } 3759 }; 3760 3761 static const VMStateDescription vmstate_xhci_event = { 3762 .name = "xhci-event", 3763 .version_id = 1, 3764 .fields = (VMStateField[]) { 3765 VMSTATE_UINT32(type, XHCIEvent), 3766 VMSTATE_UINT32(ccode, XHCIEvent), 3767 VMSTATE_UINT64(ptr, XHCIEvent), 3768 VMSTATE_UINT32(length, XHCIEvent), 3769 VMSTATE_UINT32(flags, XHCIEvent), 3770 VMSTATE_UINT8(slotid, XHCIEvent), 3771 VMSTATE_UINT8(epid, XHCIEvent), 3772 VMSTATE_END_OF_LIST() 3773 } 3774 }; 3775 3776 static bool xhci_er_full(void *opaque, int version_id) 3777 { 3778 return false; 3779 } 3780 3781 static const VMStateDescription vmstate_xhci_intr = { 3782 .name = "xhci-intr", 3783 .version_id = 1, 3784 .fields = (VMStateField[]) { 3785 /* registers */ 3786 VMSTATE_UINT32(iman, XHCIInterrupter), 3787 VMSTATE_UINT32(imod, XHCIInterrupter), 3788 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3789 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3790 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3791 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3792 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3793 3794 /* state */ 3795 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3796 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3797 VMSTATE_UINT64(er_start, XHCIInterrupter), 3798 VMSTATE_UINT32(er_size, XHCIInterrupter), 3799 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3800 3801 /* event queue (used if ring is full) */ 3802 VMSTATE_BOOL(er_full_unused, XHCIInterrupter), 3803 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3804 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3805 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3806 xhci_er_full, 1, 3807 vmstate_xhci_event, XHCIEvent), 3808 3809 VMSTATE_END_OF_LIST() 3810 } 3811 }; 3812 3813 static const VMStateDescription vmstate_xhci = { 3814 .name = "xhci", 3815 .version_id = 1, 3816 .post_load = usb_xhci_post_load, 3817 .fields = (VMStateField[]) { 3818 VMSTATE_PCI_DEVICE(parent_obj, XHCIState), 3819 VMSTATE_MSIX(parent_obj, XHCIState), 3820 3821 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3822 vmstate_xhci_port, XHCIPort), 3823 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3824 vmstate_xhci_slot, XHCISlot), 3825 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3826 vmstate_xhci_intr, XHCIInterrupter), 3827 3828 /* Operational Registers */ 3829 VMSTATE_UINT32(usbcmd, XHCIState), 3830 VMSTATE_UINT32(usbsts, XHCIState), 3831 VMSTATE_UINT32(dnctrl, XHCIState), 3832 VMSTATE_UINT32(crcr_low, XHCIState), 3833 VMSTATE_UINT32(crcr_high, XHCIState), 3834 VMSTATE_UINT32(dcbaap_low, XHCIState), 3835 VMSTATE_UINT32(dcbaap_high, XHCIState), 3836 VMSTATE_UINT32(config, XHCIState), 3837 3838 /* Runtime Registers & state */ 3839 VMSTATE_INT64(mfindex_start, XHCIState), 3840 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3841 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3842 3843 VMSTATE_END_OF_LIST() 3844 } 3845 }; 3846 3847 static Property nec_xhci_properties[] = { 3848 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO), 3849 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO), 3850 DEFINE_PROP_BIT("superspeed-ports-first", 3851 XHCIState, flags, XHCI_FLAG_SS_FIRST, true), 3852 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, 3853 XHCI_FLAG_FORCE_PCIE_ENDCAP, false), 3854 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3855 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3856 DEFINE_PROP_END_OF_LIST(), 3857 }; 3858 3859 static Property xhci_properties[] = { 3860 DEFINE_PROP_BIT("streams", XHCIState, flags, 3861 XHCI_FLAG_ENABLE_STREAMS, true), 3862 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3863 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3864 DEFINE_PROP_END_OF_LIST(), 3865 }; 3866 3867 static void xhci_class_init(ObjectClass *klass, void *data) 3868 { 3869 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3870 DeviceClass *dc = DEVICE_CLASS(klass); 3871 3872 dc->vmsd = &vmstate_xhci; 3873 dc->props = xhci_properties; 3874 dc->reset = xhci_reset; 3875 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3876 k->realize = usb_xhci_realize; 3877 k->exit = usb_xhci_exit; 3878 k->class_id = PCI_CLASS_SERIAL_USB; 3879 k->is_express = 1; 3880 } 3881 3882 static const TypeInfo xhci_info = { 3883 .name = TYPE_XHCI, 3884 .parent = TYPE_PCI_DEVICE, 3885 .instance_size = sizeof(XHCIState), 3886 .class_init = xhci_class_init, 3887 .abstract = true, 3888 }; 3889 3890 static void nec_xhci_class_init(ObjectClass *klass, void *data) 3891 { 3892 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3893 DeviceClass *dc = DEVICE_CLASS(klass); 3894 3895 dc->props = nec_xhci_properties; 3896 k->vendor_id = PCI_VENDOR_ID_NEC; 3897 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3898 k->revision = 0x03; 3899 } 3900 3901 static const TypeInfo nec_xhci_info = { 3902 .name = TYPE_NEC_XHCI, 3903 .parent = TYPE_XHCI, 3904 .class_init = nec_xhci_class_init, 3905 }; 3906 3907 static void qemu_xhci_class_init(ObjectClass *klass, void *data) 3908 { 3909 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3910 3911 k->vendor_id = PCI_VENDOR_ID_REDHAT; 3912 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; 3913 k->revision = 0x01; 3914 } 3915 3916 static void qemu_xhci_instance_init(Object *obj) 3917 { 3918 XHCIState *xhci = XHCI(obj); 3919 3920 xhci->msi = ON_OFF_AUTO_OFF; 3921 xhci->msix = ON_OFF_AUTO_AUTO; 3922 xhci->numintrs = MAXINTRS; 3923 xhci->numslots = MAXSLOTS; 3924 xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); 3925 } 3926 3927 static const TypeInfo qemu_xhci_info = { 3928 .name = TYPE_QEMU_XHCI, 3929 .parent = TYPE_XHCI, 3930 .class_init = qemu_xhci_class_init, 3931 .instance_init = qemu_xhci_instance_init, 3932 }; 3933 3934 static void xhci_register_types(void) 3935 { 3936 type_register_static(&xhci_info); 3937 type_register_static(&nec_xhci_info); 3938 type_register_static(&qemu_xhci_info); 3939 } 3940 3941 type_init(xhci_register_types) 3942