1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 8 41 #define MAXPORTS_3 8 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS MAXPORTS 45 #define MAXINTRS 1 /* MAXPORTS */ 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 #if MAXINTRS > 1 79 # error TODO: only one interrupter supported 80 #endif 81 82 /* bit definitions */ 83 #define USBCMD_RS (1<<0) 84 #define USBCMD_HCRST (1<<1) 85 #define USBCMD_INTE (1<<2) 86 #define USBCMD_HSEE (1<<3) 87 #define USBCMD_LHCRST (1<<7) 88 #define USBCMD_CSS (1<<8) 89 #define USBCMD_CRS (1<<9) 90 #define USBCMD_EWE (1<<10) 91 #define USBCMD_EU3S (1<<11) 92 93 #define USBSTS_HCH (1<<0) 94 #define USBSTS_HSE (1<<2) 95 #define USBSTS_EINT (1<<3) 96 #define USBSTS_PCD (1<<4) 97 #define USBSTS_SSS (1<<8) 98 #define USBSTS_RSS (1<<9) 99 #define USBSTS_SRE (1<<10) 100 #define USBSTS_CNR (1<<11) 101 #define USBSTS_HCE (1<<12) 102 103 104 #define PORTSC_CCS (1<<0) 105 #define PORTSC_PED (1<<1) 106 #define PORTSC_OCA (1<<3) 107 #define PORTSC_PR (1<<4) 108 #define PORTSC_PLS_SHIFT 5 109 #define PORTSC_PLS_MASK 0xf 110 #define PORTSC_PP (1<<9) 111 #define PORTSC_SPEED_SHIFT 10 112 #define PORTSC_SPEED_MASK 0xf 113 #define PORTSC_SPEED_FULL (1<<10) 114 #define PORTSC_SPEED_LOW (2<<10) 115 #define PORTSC_SPEED_HIGH (3<<10) 116 #define PORTSC_SPEED_SUPER (4<<10) 117 #define PORTSC_PIC_SHIFT 14 118 #define PORTSC_PIC_MASK 0x3 119 #define PORTSC_LWS (1<<16) 120 #define PORTSC_CSC (1<<17) 121 #define PORTSC_PEC (1<<18) 122 #define PORTSC_WRC (1<<19) 123 #define PORTSC_OCC (1<<20) 124 #define PORTSC_PRC (1<<21) 125 #define PORTSC_PLC (1<<22) 126 #define PORTSC_CEC (1<<23) 127 #define PORTSC_CAS (1<<24) 128 #define PORTSC_WCE (1<<25) 129 #define PORTSC_WDE (1<<26) 130 #define PORTSC_WOE (1<<27) 131 #define PORTSC_DR (1<<30) 132 #define PORTSC_WPR (1<<31) 133 134 #define CRCR_RCS (1<<0) 135 #define CRCR_CS (1<<1) 136 #define CRCR_CA (1<<2) 137 #define CRCR_CRR (1<<3) 138 139 #define IMAN_IP (1<<0) 140 #define IMAN_IE (1<<1) 141 142 #define ERDP_EHB (1<<3) 143 144 #define TRB_SIZE 16 145 typedef struct XHCITRB { 146 uint64_t parameter; 147 uint32_t status; 148 uint32_t control; 149 dma_addr_t addr; 150 bool ccs; 151 } XHCITRB; 152 153 154 typedef enum TRBType { 155 TRB_RESERVED = 0, 156 TR_NORMAL, 157 TR_SETUP, 158 TR_DATA, 159 TR_STATUS, 160 TR_ISOCH, 161 TR_LINK, 162 TR_EVDATA, 163 TR_NOOP, 164 CR_ENABLE_SLOT, 165 CR_DISABLE_SLOT, 166 CR_ADDRESS_DEVICE, 167 CR_CONFIGURE_ENDPOINT, 168 CR_EVALUATE_CONTEXT, 169 CR_RESET_ENDPOINT, 170 CR_STOP_ENDPOINT, 171 CR_SET_TR_DEQUEUE, 172 CR_RESET_DEVICE, 173 CR_FORCE_EVENT, 174 CR_NEGOTIATE_BW, 175 CR_SET_LATENCY_TOLERANCE, 176 CR_GET_PORT_BANDWIDTH, 177 CR_FORCE_HEADER, 178 CR_NOOP, 179 ER_TRANSFER = 32, 180 ER_COMMAND_COMPLETE, 181 ER_PORT_STATUS_CHANGE, 182 ER_BANDWIDTH_REQUEST, 183 ER_DOORBELL, 184 ER_HOST_CONTROLLER, 185 ER_DEVICE_NOTIFICATION, 186 ER_MFINDEX_WRAP, 187 /* vendor specific bits */ 188 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 189 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 190 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 191 } TRBType; 192 193 #define CR_LINK TR_LINK 194 195 typedef enum TRBCCode { 196 CC_INVALID = 0, 197 CC_SUCCESS, 198 CC_DATA_BUFFER_ERROR, 199 CC_BABBLE_DETECTED, 200 CC_USB_TRANSACTION_ERROR, 201 CC_TRB_ERROR, 202 CC_STALL_ERROR, 203 CC_RESOURCE_ERROR, 204 CC_BANDWIDTH_ERROR, 205 CC_NO_SLOTS_ERROR, 206 CC_INVALID_STREAM_TYPE_ERROR, 207 CC_SLOT_NOT_ENABLED_ERROR, 208 CC_EP_NOT_ENABLED_ERROR, 209 CC_SHORT_PACKET, 210 CC_RING_UNDERRUN, 211 CC_RING_OVERRUN, 212 CC_VF_ER_FULL, 213 CC_PARAMETER_ERROR, 214 CC_BANDWIDTH_OVERRUN, 215 CC_CONTEXT_STATE_ERROR, 216 CC_NO_PING_RESPONSE_ERROR, 217 CC_EVENT_RING_FULL_ERROR, 218 CC_INCOMPATIBLE_DEVICE_ERROR, 219 CC_MISSED_SERVICE_ERROR, 220 CC_COMMAND_RING_STOPPED, 221 CC_COMMAND_ABORTED, 222 CC_STOPPED, 223 CC_STOPPED_LENGTH_INVALID, 224 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 225 CC_ISOCH_BUFFER_OVERRUN = 31, 226 CC_EVENT_LOST_ERROR, 227 CC_UNDEFINED_ERROR, 228 CC_INVALID_STREAM_ID_ERROR, 229 CC_SECONDARY_BANDWIDTH_ERROR, 230 CC_SPLIT_TRANSACTION_ERROR 231 } TRBCCode; 232 233 #define TRB_C (1<<0) 234 #define TRB_TYPE_SHIFT 10 235 #define TRB_TYPE_MASK 0x3f 236 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 237 238 #define TRB_EV_ED (1<<2) 239 240 #define TRB_TR_ENT (1<<1) 241 #define TRB_TR_ISP (1<<2) 242 #define TRB_TR_NS (1<<3) 243 #define TRB_TR_CH (1<<4) 244 #define TRB_TR_IOC (1<<5) 245 #define TRB_TR_IDT (1<<6) 246 #define TRB_TR_TBC_SHIFT 7 247 #define TRB_TR_TBC_MASK 0x3 248 #define TRB_TR_BEI (1<<9) 249 #define TRB_TR_TLBPC_SHIFT 16 250 #define TRB_TR_TLBPC_MASK 0xf 251 #define TRB_TR_FRAMEID_SHIFT 20 252 #define TRB_TR_FRAMEID_MASK 0x7ff 253 #define TRB_TR_SIA (1<<31) 254 255 #define TRB_TR_DIR (1<<16) 256 257 #define TRB_CR_SLOTID_SHIFT 24 258 #define TRB_CR_SLOTID_MASK 0xff 259 #define TRB_CR_EPID_SHIFT 16 260 #define TRB_CR_EPID_MASK 0x1f 261 262 #define TRB_CR_BSR (1<<9) 263 #define TRB_CR_DC (1<<9) 264 265 #define TRB_LK_TC (1<<1) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef enum EPType { 289 ET_INVALID = 0, 290 ET_ISO_OUT, 291 ET_BULK_OUT, 292 ET_INTR_OUT, 293 ET_CONTROL, 294 ET_ISO_IN, 295 ET_BULK_IN, 296 ET_INTR_IN, 297 } EPType; 298 299 typedef struct XHCIRing { 300 dma_addr_t base; 301 dma_addr_t dequeue; 302 bool ccs; 303 } XHCIRing; 304 305 typedef struct XHCIPort { 306 uint32_t portsc; 307 uint32_t portnr; 308 USBPort *uport; 309 uint32_t speedmask; 310 } XHCIPort; 311 312 struct XHCIState; 313 typedef struct XHCIState XHCIState; 314 315 typedef struct XHCITransfer { 316 XHCIState *xhci; 317 USBPacket packet; 318 QEMUSGList sgl; 319 bool running_async; 320 bool running_retry; 321 bool cancelled; 322 bool complete; 323 unsigned int iso_pkts; 324 unsigned int slotid; 325 unsigned int epid; 326 bool in_xfer; 327 bool iso_xfer; 328 329 unsigned int trb_count; 330 unsigned int trb_alloced; 331 XHCITRB *trbs; 332 333 TRBCCode status; 334 335 unsigned int pkts; 336 unsigned int pktsize; 337 unsigned int cur_pkt; 338 339 uint64_t mfindex_kick; 340 } XHCITransfer; 341 342 typedef struct XHCIEPContext { 343 XHCIState *xhci; 344 unsigned int slotid; 345 unsigned int epid; 346 347 XHCIRing ring; 348 unsigned int next_xfer; 349 unsigned int comp_xfer; 350 XHCITransfer transfers[TD_QUEUE]; 351 XHCITransfer *retry; 352 EPType type; 353 dma_addr_t pctx; 354 unsigned int max_psize; 355 uint32_t state; 356 357 /* iso xfer scheduling */ 358 unsigned int interval; 359 int64_t mfindex_last; 360 QEMUTimer *kick_timer; 361 } XHCIEPContext; 362 363 typedef struct XHCISlot { 364 bool enabled; 365 dma_addr_t ctx; 366 unsigned int port; 367 unsigned int devaddr; 368 XHCIEPContext * eps[31]; 369 } XHCISlot; 370 371 typedef struct XHCIEvent { 372 TRBType type; 373 TRBCCode ccode; 374 uint64_t ptr; 375 uint32_t length; 376 uint32_t flags; 377 uint8_t slotid; 378 uint8_t epid; 379 } XHCIEvent; 380 381 struct XHCIState { 382 PCIDevice pci_dev; 383 USBBus bus; 384 qemu_irq irq; 385 MemoryRegion mem; 386 const char *name; 387 unsigned int devaddr; 388 389 /* properties */ 390 uint32_t numports_2; 391 uint32_t numports_3; 392 uint32_t flags; 393 394 /* Operational Registers */ 395 uint32_t usbcmd; 396 uint32_t usbsts; 397 uint32_t dnctrl; 398 uint32_t crcr_low; 399 uint32_t crcr_high; 400 uint32_t dcbaap_low; 401 uint32_t dcbaap_high; 402 uint32_t config; 403 404 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 405 XHCIPort ports[MAXPORTS]; 406 XHCISlot slots[MAXSLOTS]; 407 uint32_t numports; 408 409 /* Runtime Registers */ 410 uint32_t iman; 411 uint32_t imod; 412 uint32_t erstsz; 413 uint32_t erstba_low; 414 uint32_t erstba_high; 415 uint32_t erdp_low; 416 uint32_t erdp_high; 417 bool msix_used; 418 419 int64_t mfindex_start; 420 QEMUTimer *mfwrap_timer; 421 422 dma_addr_t er_start; 423 uint32_t er_size; 424 bool er_pcs; 425 unsigned int er_ep_idx; 426 bool er_full; 427 428 XHCIEvent ev_buffer[EV_QUEUE]; 429 unsigned int ev_buffer_put; 430 unsigned int ev_buffer_get; 431 432 XHCIRing cmd_ring; 433 }; 434 435 typedef struct XHCIEvRingSeg { 436 uint32_t addr_low; 437 uint32_t addr_high; 438 uint32_t size; 439 uint32_t rsvd; 440 } XHCIEvRingSeg; 441 442 enum xhci_flags { 443 XHCI_FLAG_USE_MSI = 1, 444 XHCI_FLAG_USE_MSI_X, 445 }; 446 447 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 448 unsigned int epid); 449 static void xhci_event(XHCIState *xhci, XHCIEvent *event); 450 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event); 451 452 static const char *TRBType_names[] = { 453 [TRB_RESERVED] = "TRB_RESERVED", 454 [TR_NORMAL] = "TR_NORMAL", 455 [TR_SETUP] = "TR_SETUP", 456 [TR_DATA] = "TR_DATA", 457 [TR_STATUS] = "TR_STATUS", 458 [TR_ISOCH] = "TR_ISOCH", 459 [TR_LINK] = "TR_LINK", 460 [TR_EVDATA] = "TR_EVDATA", 461 [TR_NOOP] = "TR_NOOP", 462 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 463 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 464 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 465 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 466 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 467 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 468 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 469 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 470 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 471 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 472 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 473 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 474 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 475 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 476 [CR_NOOP] = "CR_NOOP", 477 [ER_TRANSFER] = "ER_TRANSFER", 478 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 479 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 480 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 481 [ER_DOORBELL] = "ER_DOORBELL", 482 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 483 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 484 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 485 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 486 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 487 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 488 }; 489 490 static const char *TRBCCode_names[] = { 491 [CC_INVALID] = "CC_INVALID", 492 [CC_SUCCESS] = "CC_SUCCESS", 493 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 494 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 495 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 496 [CC_TRB_ERROR] = "CC_TRB_ERROR", 497 [CC_STALL_ERROR] = "CC_STALL_ERROR", 498 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 499 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 500 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 501 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 502 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 503 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 504 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 505 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 506 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 507 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 508 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 509 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 510 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 511 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 512 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 513 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 514 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 515 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 516 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 517 [CC_STOPPED] = "CC_STOPPED", 518 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 519 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 520 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 521 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 522 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 523 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 524 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 525 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 526 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 527 }; 528 529 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 530 { 531 if (index >= llen || list[index] == NULL) { 532 return "???"; 533 } 534 return list[index]; 535 } 536 537 static const char *trb_name(XHCITRB *trb) 538 { 539 return lookup_name(TRB_TYPE(*trb), TRBType_names, 540 ARRAY_SIZE(TRBType_names)); 541 } 542 543 static const char *event_name(XHCIEvent *event) 544 { 545 return lookup_name(event->ccode, TRBCCode_names, 546 ARRAY_SIZE(TRBCCode_names)); 547 } 548 549 static uint64_t xhci_mfindex_get(XHCIState *xhci) 550 { 551 int64_t now = qemu_get_clock_ns(vm_clock); 552 return (now - xhci->mfindex_start) / 125000; 553 } 554 555 static void xhci_mfwrap_update(XHCIState *xhci) 556 { 557 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 558 uint32_t mfindex, left; 559 int64_t now; 560 561 if ((xhci->usbcmd & bits) == bits) { 562 now = qemu_get_clock_ns(vm_clock); 563 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 564 left = 0x4000 - mfindex; 565 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 566 } else { 567 qemu_del_timer(xhci->mfwrap_timer); 568 } 569 } 570 571 static void xhci_mfwrap_timer(void *opaque) 572 { 573 XHCIState *xhci = opaque; 574 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 575 576 xhci_event(xhci, &wrap); 577 xhci_mfwrap_update(xhci); 578 } 579 580 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 581 { 582 if (sizeof(dma_addr_t) == 4) { 583 return low; 584 } else { 585 return low | (((dma_addr_t)high << 16) << 16); 586 } 587 } 588 589 static inline dma_addr_t xhci_mask64(uint64_t addr) 590 { 591 if (sizeof(dma_addr_t) == 4) { 592 return addr & 0xffffffff; 593 } else { 594 return addr; 595 } 596 } 597 598 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 599 { 600 int index; 601 602 if (!uport->dev) { 603 return NULL; 604 } 605 switch (uport->dev->speed) { 606 case USB_SPEED_LOW: 607 case USB_SPEED_FULL: 608 case USB_SPEED_HIGH: 609 index = uport->index; 610 break; 611 case USB_SPEED_SUPER: 612 index = uport->index + xhci->numports_2; 613 break; 614 default: 615 return NULL; 616 } 617 return &xhci->ports[index]; 618 } 619 620 static void xhci_intx_update(XHCIState *xhci) 621 { 622 int level = 0; 623 624 if (msix_enabled(&xhci->pci_dev) || 625 msi_enabled(&xhci->pci_dev)) { 626 return; 627 } 628 629 if (xhci->iman & IMAN_IP && 630 xhci->iman & IMAN_IE && 631 xhci->usbcmd & USBCMD_INTE) { 632 level = 1; 633 } 634 635 trace_usb_xhci_irq_intx(level); 636 qemu_set_irq(xhci->irq, level); 637 } 638 639 static void xhci_msix_update(XHCIState *xhci) 640 { 641 bool enabled; 642 643 if (!msix_enabled(&xhci->pci_dev)) { 644 return; 645 } 646 647 enabled = xhci->iman & IMAN_IE; 648 if (enabled == xhci->msix_used) { 649 return; 650 } 651 652 if (enabled) { 653 trace_usb_xhci_irq_msix_use(0); 654 msix_vector_use(&xhci->pci_dev, 0); 655 xhci->msix_used = true; 656 } else { 657 trace_usb_xhci_irq_msix_unuse(0); 658 msix_vector_unuse(&xhci->pci_dev, 0); 659 xhci->msix_used = false; 660 } 661 } 662 663 static void xhci_intr_raise(XHCIState *xhci) 664 { 665 xhci->erdp_low |= ERDP_EHB; 666 xhci->iman |= IMAN_IP; 667 xhci->usbsts |= USBSTS_EINT; 668 669 if (!(xhci->iman & IMAN_IE)) { 670 return; 671 } 672 673 if (!(xhci->usbcmd & USBCMD_INTE)) { 674 return; 675 } 676 677 if (msix_enabled(&xhci->pci_dev)) { 678 trace_usb_xhci_irq_msix(0); 679 msix_notify(&xhci->pci_dev, 0); 680 return; 681 } 682 683 if (msi_enabled(&xhci->pci_dev)) { 684 trace_usb_xhci_irq_msi(0); 685 msi_notify(&xhci->pci_dev, 0); 686 return; 687 } 688 689 trace_usb_xhci_irq_intx(1); 690 qemu_set_irq(xhci->irq, 1); 691 } 692 693 static inline int xhci_running(XHCIState *xhci) 694 { 695 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full; 696 } 697 698 static void xhci_die(XHCIState *xhci) 699 { 700 xhci->usbsts |= USBSTS_HCE; 701 fprintf(stderr, "xhci: asserted controller error\n"); 702 } 703 704 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event) 705 { 706 XHCITRB ev_trb; 707 dma_addr_t addr; 708 709 ev_trb.parameter = cpu_to_le64(event->ptr); 710 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 711 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 712 event->flags | (event->type << TRB_TYPE_SHIFT); 713 if (xhci->er_pcs) { 714 ev_trb.control |= TRB_C; 715 } 716 ev_trb.control = cpu_to_le32(ev_trb.control); 717 718 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb), 719 event_name(event), ev_trb.parameter, 720 ev_trb.status, ev_trb.control); 721 722 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx; 723 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 724 725 xhci->er_ep_idx++; 726 if (xhci->er_ep_idx >= xhci->er_size) { 727 xhci->er_ep_idx = 0; 728 xhci->er_pcs = !xhci->er_pcs; 729 } 730 } 731 732 static void xhci_events_update(XHCIState *xhci) 733 { 734 dma_addr_t erdp; 735 unsigned int dp_idx; 736 bool do_irq = 0; 737 738 if (xhci->usbsts & USBSTS_HCH) { 739 return; 740 } 741 742 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); 743 if (erdp < xhci->er_start || 744 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { 745 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 746 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n", 747 xhci->er_start, xhci->er_size); 748 xhci_die(xhci); 749 return; 750 } 751 dp_idx = (erdp - xhci->er_start) / TRB_SIZE; 752 assert(dp_idx < xhci->er_size); 753 754 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 755 * deadlocks when the ER is full. Hack it by holding off events until 756 * the driver decides to free at least half of the ring */ 757 if (xhci->er_full) { 758 int er_free = dp_idx - xhci->er_ep_idx; 759 if (er_free <= 0) { 760 er_free += xhci->er_size; 761 } 762 if (er_free < (xhci->er_size/2)) { 763 DPRINTF("xhci_events_update(): event ring still " 764 "more than half full (hack)\n"); 765 return; 766 } 767 } 768 769 while (xhci->ev_buffer_put != xhci->ev_buffer_get) { 770 assert(xhci->er_full); 771 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) { 772 DPRINTF("xhci_events_update(): event ring full again\n"); 773 #ifndef ER_FULL_HACK 774 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 775 xhci_write_event(xhci, &full); 776 #endif 777 do_irq = 1; 778 break; 779 } 780 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get]; 781 xhci_write_event(xhci, event); 782 xhci->ev_buffer_get++; 783 do_irq = 1; 784 if (xhci->ev_buffer_get == EV_QUEUE) { 785 xhci->ev_buffer_get = 0; 786 } 787 } 788 789 if (do_irq) { 790 xhci_intr_raise(xhci); 791 } 792 793 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) { 794 DPRINTF("xhci_events_update(): event ring no longer full\n"); 795 xhci->er_full = 0; 796 } 797 return; 798 } 799 800 static void xhci_event(XHCIState *xhci, XHCIEvent *event) 801 { 802 dma_addr_t erdp; 803 unsigned int dp_idx; 804 805 if (xhci->er_full) { 806 DPRINTF("xhci_event(): ER full, queueing\n"); 807 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { 808 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 809 return; 810 } 811 xhci->ev_buffer[xhci->ev_buffer_put++] = *event; 812 if (xhci->ev_buffer_put == EV_QUEUE) { 813 xhci->ev_buffer_put = 0; 814 } 815 return; 816 } 817 818 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high); 819 if (erdp < xhci->er_start || 820 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) { 821 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 822 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n", 823 xhci->er_start, xhci->er_size); 824 xhci_die(xhci); 825 return; 826 } 827 828 dp_idx = (erdp - xhci->er_start) / TRB_SIZE; 829 assert(dp_idx < xhci->er_size); 830 831 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) { 832 DPRINTF("xhci_event(): ER full, queueing\n"); 833 #ifndef ER_FULL_HACK 834 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 835 xhci_write_event(xhci, &full); 836 #endif 837 xhci->er_full = 1; 838 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) { 839 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 840 return; 841 } 842 xhci->ev_buffer[xhci->ev_buffer_put++] = *event; 843 if (xhci->ev_buffer_put == EV_QUEUE) { 844 xhci->ev_buffer_put = 0; 845 } 846 } else { 847 xhci_write_event(xhci, event); 848 } 849 850 xhci_intr_raise(xhci); 851 } 852 853 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 854 dma_addr_t base) 855 { 856 ring->base = base; 857 ring->dequeue = base; 858 ring->ccs = 1; 859 } 860 861 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 862 dma_addr_t *addr) 863 { 864 while (1) { 865 TRBType type; 866 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 867 trb->addr = ring->dequeue; 868 trb->ccs = ring->ccs; 869 le64_to_cpus(&trb->parameter); 870 le32_to_cpus(&trb->status); 871 le32_to_cpus(&trb->control); 872 873 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 874 trb->parameter, trb->status, trb->control); 875 876 if ((trb->control & TRB_C) != ring->ccs) { 877 return 0; 878 } 879 880 type = TRB_TYPE(*trb); 881 882 if (type != TR_LINK) { 883 if (addr) { 884 *addr = ring->dequeue; 885 } 886 ring->dequeue += TRB_SIZE; 887 return type; 888 } else { 889 ring->dequeue = xhci_mask64(trb->parameter); 890 if (trb->control & TRB_LK_TC) { 891 ring->ccs = !ring->ccs; 892 } 893 } 894 } 895 } 896 897 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 898 { 899 XHCITRB trb; 900 int length = 0; 901 dma_addr_t dequeue = ring->dequeue; 902 bool ccs = ring->ccs; 903 /* hack to bundle together the two/three TDs that make a setup transfer */ 904 bool control_td_set = 0; 905 906 while (1) { 907 TRBType type; 908 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 909 le64_to_cpus(&trb.parameter); 910 le32_to_cpus(&trb.status); 911 le32_to_cpus(&trb.control); 912 913 if ((trb.control & TRB_C) != ccs) { 914 return -length; 915 } 916 917 type = TRB_TYPE(trb); 918 919 if (type == TR_LINK) { 920 dequeue = xhci_mask64(trb.parameter); 921 if (trb.control & TRB_LK_TC) { 922 ccs = !ccs; 923 } 924 continue; 925 } 926 927 length += 1; 928 dequeue += TRB_SIZE; 929 930 if (type == TR_SETUP) { 931 control_td_set = 1; 932 } else if (type == TR_STATUS) { 933 control_td_set = 0; 934 } 935 936 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 937 return length; 938 } 939 } 940 } 941 942 static void xhci_er_reset(XHCIState *xhci) 943 { 944 XHCIEvRingSeg seg; 945 946 /* cache the (sole) event ring segment location */ 947 if (xhci->erstsz != 1) { 948 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz); 949 xhci_die(xhci); 950 return; 951 } 952 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high); 953 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 954 le32_to_cpus(&seg.addr_low); 955 le32_to_cpus(&seg.addr_high); 956 le32_to_cpus(&seg.size); 957 if (seg.size < 16 || seg.size > 4096) { 958 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 959 xhci_die(xhci); 960 return; 961 } 962 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 963 xhci->er_size = seg.size; 964 965 xhci->er_ep_idx = 0; 966 xhci->er_pcs = 1; 967 xhci->er_full = 0; 968 969 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n", 970 xhci->er_start, xhci->er_size); 971 } 972 973 static void xhci_run(XHCIState *xhci) 974 { 975 trace_usb_xhci_run(); 976 xhci->usbsts &= ~USBSTS_HCH; 977 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 978 } 979 980 static void xhci_stop(XHCIState *xhci) 981 { 982 trace_usb_xhci_stop(); 983 xhci->usbsts |= USBSTS_HCH; 984 xhci->crcr_low &= ~CRCR_CRR; 985 } 986 987 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 988 uint32_t state) 989 { 990 uint32_t ctx[5]; 991 if (epctx->state == state) { 992 return; 993 } 994 995 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 996 ctx[0] &= ~EP_STATE_MASK; 997 ctx[0] |= state; 998 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 999 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1000 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1001 epctx->pctx, state, ctx[3], ctx[2]); 1002 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1003 epctx->state = state; 1004 } 1005 1006 static void xhci_ep_kick_timer(void *opaque) 1007 { 1008 XHCIEPContext *epctx = opaque; 1009 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1010 } 1011 1012 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1013 unsigned int epid, dma_addr_t pctx, 1014 uint32_t *ctx) 1015 { 1016 XHCISlot *slot; 1017 XHCIEPContext *epctx; 1018 dma_addr_t dequeue; 1019 int i; 1020 1021 trace_usb_xhci_ep_enable(slotid, epid); 1022 assert(slotid >= 1 && slotid <= MAXSLOTS); 1023 assert(epid >= 1 && epid <= 31); 1024 1025 slot = &xhci->slots[slotid-1]; 1026 if (slot->eps[epid-1]) { 1027 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1028 return CC_TRB_ERROR; 1029 } 1030 1031 epctx = g_malloc(sizeof(XHCIEPContext)); 1032 memset(epctx, 0, sizeof(XHCIEPContext)); 1033 epctx->xhci = xhci; 1034 epctx->slotid = slotid; 1035 epctx->epid = epid; 1036 1037 slot->eps[epid-1] = epctx; 1038 1039 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1040 xhci_ring_init(xhci, &epctx->ring, dequeue); 1041 epctx->ring.ccs = ctx[2] & 1; 1042 1043 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1044 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1045 epctx->pctx = pctx; 1046 epctx->max_psize = ctx[1]>>16; 1047 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1048 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1049 epid/2, epid%2, epctx->max_psize); 1050 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1051 usb_packet_init(&epctx->transfers[i].packet); 1052 } 1053 1054 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1055 epctx->mfindex_last = 0; 1056 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1057 1058 epctx->state = EP_RUNNING; 1059 ctx[0] &= ~EP_STATE_MASK; 1060 ctx[0] |= EP_RUNNING; 1061 1062 return CC_SUCCESS; 1063 } 1064 1065 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1066 unsigned int epid) 1067 { 1068 XHCISlot *slot; 1069 XHCIEPContext *epctx; 1070 int i, xferi, killed = 0; 1071 assert(slotid >= 1 && slotid <= MAXSLOTS); 1072 assert(epid >= 1 && epid <= 31); 1073 1074 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1075 1076 slot = &xhci->slots[slotid-1]; 1077 1078 if (!slot->eps[epid-1]) { 1079 return 0; 1080 } 1081 1082 epctx = slot->eps[epid-1]; 1083 1084 xferi = epctx->next_xfer; 1085 for (i = 0; i < TD_QUEUE; i++) { 1086 XHCITransfer *t = &epctx->transfers[xferi]; 1087 if (t->running_async) { 1088 usb_cancel_packet(&t->packet); 1089 t->running_async = 0; 1090 t->cancelled = 1; 1091 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i); 1092 killed++; 1093 } 1094 if (t->running_retry) { 1095 t->running_retry = 0; 1096 epctx->retry = NULL; 1097 qemu_del_timer(epctx->kick_timer); 1098 } 1099 if (t->trbs) { 1100 g_free(t->trbs); 1101 } 1102 1103 t->trbs = NULL; 1104 t->trb_count = t->trb_alloced = 0; 1105 xferi = (xferi + 1) % TD_QUEUE; 1106 } 1107 return killed; 1108 } 1109 1110 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1111 unsigned int epid) 1112 { 1113 XHCISlot *slot; 1114 XHCIEPContext *epctx; 1115 1116 trace_usb_xhci_ep_disable(slotid, epid); 1117 assert(slotid >= 1 && slotid <= MAXSLOTS); 1118 assert(epid >= 1 && epid <= 31); 1119 1120 slot = &xhci->slots[slotid-1]; 1121 1122 if (!slot->eps[epid-1]) { 1123 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1124 return CC_SUCCESS; 1125 } 1126 1127 xhci_ep_nuke_xfers(xhci, slotid, epid); 1128 1129 epctx = slot->eps[epid-1]; 1130 1131 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1132 1133 qemu_free_timer(epctx->kick_timer); 1134 g_free(epctx); 1135 slot->eps[epid-1] = NULL; 1136 1137 return CC_SUCCESS; 1138 } 1139 1140 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1141 unsigned int epid) 1142 { 1143 XHCISlot *slot; 1144 XHCIEPContext *epctx; 1145 1146 trace_usb_xhci_ep_stop(slotid, epid); 1147 assert(slotid >= 1 && slotid <= MAXSLOTS); 1148 1149 if (epid < 1 || epid > 31) { 1150 fprintf(stderr, "xhci: bad ep %d\n", epid); 1151 return CC_TRB_ERROR; 1152 } 1153 1154 slot = &xhci->slots[slotid-1]; 1155 1156 if (!slot->eps[epid-1]) { 1157 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1158 return CC_EP_NOT_ENABLED_ERROR; 1159 } 1160 1161 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1162 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1163 "data might be lost\n"); 1164 } 1165 1166 epctx = slot->eps[epid-1]; 1167 1168 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1169 1170 return CC_SUCCESS; 1171 } 1172 1173 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1174 unsigned int epid) 1175 { 1176 XHCISlot *slot; 1177 XHCIEPContext *epctx; 1178 USBDevice *dev; 1179 1180 trace_usb_xhci_ep_reset(slotid, epid); 1181 assert(slotid >= 1 && slotid <= MAXSLOTS); 1182 1183 if (epid < 1 || epid > 31) { 1184 fprintf(stderr, "xhci: bad ep %d\n", epid); 1185 return CC_TRB_ERROR; 1186 } 1187 1188 slot = &xhci->slots[slotid-1]; 1189 1190 if (!slot->eps[epid-1]) { 1191 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1192 return CC_EP_NOT_ENABLED_ERROR; 1193 } 1194 1195 epctx = slot->eps[epid-1]; 1196 1197 if (epctx->state != EP_HALTED) { 1198 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1199 epid, epctx->state); 1200 return CC_CONTEXT_STATE_ERROR; 1201 } 1202 1203 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1204 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1205 "data might be lost\n"); 1206 } 1207 1208 uint8_t ep = epid>>1; 1209 1210 if (epid & 1) { 1211 ep |= 0x80; 1212 } 1213 1214 dev = xhci->ports[xhci->slots[slotid-1].port-1].uport->dev; 1215 if (!dev) { 1216 return CC_USB_TRANSACTION_ERROR; 1217 } 1218 1219 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1220 1221 return CC_SUCCESS; 1222 } 1223 1224 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1225 unsigned int epid, uint64_t pdequeue) 1226 { 1227 XHCISlot *slot; 1228 XHCIEPContext *epctx; 1229 dma_addr_t dequeue; 1230 1231 assert(slotid >= 1 && slotid <= MAXSLOTS); 1232 1233 if (epid < 1 || epid > 31) { 1234 fprintf(stderr, "xhci: bad ep %d\n", epid); 1235 return CC_TRB_ERROR; 1236 } 1237 1238 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1239 dequeue = xhci_mask64(pdequeue); 1240 1241 slot = &xhci->slots[slotid-1]; 1242 1243 if (!slot->eps[epid-1]) { 1244 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1245 return CC_EP_NOT_ENABLED_ERROR; 1246 } 1247 1248 epctx = slot->eps[epid-1]; 1249 1250 1251 if (epctx->state != EP_STOPPED) { 1252 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1253 return CC_CONTEXT_STATE_ERROR; 1254 } 1255 1256 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1257 epctx->ring.ccs = dequeue & 1; 1258 1259 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1260 1261 return CC_SUCCESS; 1262 } 1263 1264 static int xhci_xfer_map(XHCITransfer *xfer) 1265 { 1266 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN); 1267 XHCIState *xhci = xfer->xhci; 1268 int i; 1269 1270 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1271 for (i = 0; i < xfer->trb_count; i++) { 1272 XHCITRB *trb = &xfer->trbs[i]; 1273 dma_addr_t addr; 1274 unsigned int chunk = 0; 1275 1276 switch (TRB_TYPE(*trb)) { 1277 case TR_DATA: 1278 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1279 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1280 goto err; 1281 } 1282 /* fallthrough */ 1283 case TR_NORMAL: 1284 case TR_ISOCH: 1285 addr = xhci_mask64(trb->parameter); 1286 chunk = trb->status & 0x1ffff; 1287 if (trb->control & TRB_TR_IDT) { 1288 if (chunk > 8 || in_xfer) { 1289 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1290 goto err; 1291 } 1292 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1293 } else { 1294 qemu_sglist_add(&xfer->sgl, addr, chunk); 1295 } 1296 break; 1297 } 1298 } 1299 1300 usb_packet_map(&xfer->packet, &xfer->sgl); 1301 return 0; 1302 1303 err: 1304 qemu_sglist_destroy(&xfer->sgl); 1305 xhci_die(xhci); 1306 return -1; 1307 } 1308 1309 static void xhci_xfer_unmap(XHCITransfer *xfer) 1310 { 1311 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1312 qemu_sglist_destroy(&xfer->sgl); 1313 } 1314 1315 static void xhci_xfer_report(XHCITransfer *xfer) 1316 { 1317 uint32_t edtla = 0; 1318 unsigned int left; 1319 bool reported = 0; 1320 bool shortpkt = 0; 1321 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1322 XHCIState *xhci = xfer->xhci; 1323 int i; 1324 1325 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1326 1327 for (i = 0; i < xfer->trb_count; i++) { 1328 XHCITRB *trb = &xfer->trbs[i]; 1329 unsigned int chunk = 0; 1330 1331 switch (TRB_TYPE(*trb)) { 1332 case TR_DATA: 1333 case TR_NORMAL: 1334 case TR_ISOCH: 1335 chunk = trb->status & 0x1ffff; 1336 if (chunk > left) { 1337 chunk = left; 1338 if (xfer->status == CC_SUCCESS) { 1339 shortpkt = 1; 1340 } 1341 } 1342 left -= chunk; 1343 edtla += chunk; 1344 break; 1345 case TR_STATUS: 1346 reported = 0; 1347 shortpkt = 0; 1348 break; 1349 } 1350 1351 if (!reported && ((trb->control & TRB_TR_IOC) || 1352 (shortpkt && (trb->control & TRB_TR_ISP)) || 1353 (xfer->status != CC_SUCCESS))) { 1354 event.slotid = xfer->slotid; 1355 event.epid = xfer->epid; 1356 event.length = (trb->status & 0x1ffff) - chunk; 1357 event.flags = 0; 1358 event.ptr = trb->addr; 1359 if (xfer->status == CC_SUCCESS) { 1360 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1361 } else { 1362 event.ccode = xfer->status; 1363 } 1364 if (TRB_TYPE(*trb) == TR_EVDATA) { 1365 event.ptr = trb->parameter; 1366 event.flags |= TRB_EV_ED; 1367 event.length = edtla & 0xffffff; 1368 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1369 edtla = 0; 1370 } 1371 xhci_event(xhci, &event); 1372 reported = 1; 1373 if (xfer->status != CC_SUCCESS) { 1374 return; 1375 } 1376 } 1377 } 1378 } 1379 1380 static void xhci_stall_ep(XHCITransfer *xfer) 1381 { 1382 XHCIState *xhci = xfer->xhci; 1383 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1384 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1385 1386 epctx->ring.dequeue = xfer->trbs[0].addr; 1387 epctx->ring.ccs = xfer->trbs[0].ccs; 1388 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1389 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1390 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1391 } 1392 1393 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1394 XHCIEPContext *epctx); 1395 1396 static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr) 1397 { 1398 if (!(port->portsc & PORTSC_PED)) { 1399 return NULL; 1400 } 1401 return usb_find_device(port->uport, addr); 1402 } 1403 1404 static int xhci_setup_packet(XHCITransfer *xfer) 1405 { 1406 XHCIState *xhci = xfer->xhci; 1407 XHCIPort *port; 1408 USBDevice *dev; 1409 USBEndpoint *ep; 1410 int dir; 1411 1412 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1413 1414 if (xfer->packet.ep) { 1415 ep = xfer->packet.ep; 1416 dev = ep->dev; 1417 } else { 1418 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1]; 1419 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr); 1420 if (!dev) { 1421 fprintf(stderr, "xhci: slot %d port %d has no device\n", 1422 xfer->slotid, xhci->slots[xfer->slotid-1].port); 1423 return -1; 1424 } 1425 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1426 } 1427 1428 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr); 1429 xhci_xfer_map(xfer); 1430 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1431 xfer->packet.pid, dev->addr, ep->nr); 1432 return 0; 1433 } 1434 1435 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1436 { 1437 if (ret == USB_RET_ASYNC) { 1438 trace_usb_xhci_xfer_async(xfer); 1439 xfer->running_async = 1; 1440 xfer->running_retry = 0; 1441 xfer->complete = 0; 1442 xfer->cancelled = 0; 1443 return 0; 1444 } else if (ret == USB_RET_NAK) { 1445 trace_usb_xhci_xfer_nak(xfer); 1446 xfer->running_async = 0; 1447 xfer->running_retry = 1; 1448 xfer->complete = 0; 1449 xfer->cancelled = 0; 1450 return 0; 1451 } else { 1452 xfer->running_async = 0; 1453 xfer->running_retry = 0; 1454 xfer->complete = 1; 1455 xhci_xfer_unmap(xfer); 1456 } 1457 1458 if (ret >= 0) { 1459 trace_usb_xhci_xfer_success(xfer, ret); 1460 xfer->status = CC_SUCCESS; 1461 xhci_xfer_report(xfer); 1462 return 0; 1463 } 1464 1465 /* error */ 1466 trace_usb_xhci_xfer_error(xfer, ret); 1467 switch (ret) { 1468 case USB_RET_NODEV: 1469 xfer->status = CC_USB_TRANSACTION_ERROR; 1470 xhci_xfer_report(xfer); 1471 xhci_stall_ep(xfer); 1472 break; 1473 case USB_RET_STALL: 1474 xfer->status = CC_STALL_ERROR; 1475 xhci_xfer_report(xfer); 1476 xhci_stall_ep(xfer); 1477 break; 1478 default: 1479 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1480 FIXME(); 1481 } 1482 return 0; 1483 } 1484 1485 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1486 { 1487 XHCITRB *trb_setup, *trb_status; 1488 uint8_t bmRequestType; 1489 int ret; 1490 1491 trb_setup = &xfer->trbs[0]; 1492 trb_status = &xfer->trbs[xfer->trb_count-1]; 1493 1494 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1495 1496 /* at most one Event Data TRB allowed after STATUS */ 1497 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1498 trb_status--; 1499 } 1500 1501 /* do some sanity checks */ 1502 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1503 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1504 TRB_TYPE(*trb_setup)); 1505 return -1; 1506 } 1507 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1508 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1509 TRB_TYPE(*trb_status)); 1510 return -1; 1511 } 1512 if (!(trb_setup->control & TRB_TR_IDT)) { 1513 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1514 return -1; 1515 } 1516 if ((trb_setup->status & 0x1ffff) != 8) { 1517 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1518 (trb_setup->status & 0x1ffff)); 1519 return -1; 1520 } 1521 1522 bmRequestType = trb_setup->parameter; 1523 1524 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1525 xfer->iso_xfer = false; 1526 1527 if (xhci_setup_packet(xfer) < 0) { 1528 return -1; 1529 } 1530 xfer->packet.parameter = trb_setup->parameter; 1531 1532 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1533 1534 xhci_complete_packet(xfer, ret); 1535 if (!xfer->running_async && !xfer->running_retry) { 1536 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1537 } 1538 return 0; 1539 } 1540 1541 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1542 XHCIEPContext *epctx, uint64_t mfindex) 1543 { 1544 if (xfer->trbs[0].control & TRB_TR_SIA) { 1545 uint64_t asap = ((mfindex + epctx->interval - 1) & 1546 ~(epctx->interval-1)); 1547 if (asap >= epctx->mfindex_last && 1548 asap <= epctx->mfindex_last + epctx->interval * 4) { 1549 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1550 } else { 1551 xfer->mfindex_kick = asap; 1552 } 1553 } else { 1554 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1555 & TRB_TR_FRAMEID_MASK; 1556 xfer->mfindex_kick |= mfindex & ~0x3fff; 1557 if (xfer->mfindex_kick < mfindex) { 1558 xfer->mfindex_kick += 0x4000; 1559 } 1560 } 1561 } 1562 1563 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1564 XHCIEPContext *epctx, uint64_t mfindex) 1565 { 1566 if (xfer->mfindex_kick > mfindex) { 1567 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1568 (xfer->mfindex_kick - mfindex) * 125000); 1569 xfer->running_retry = 1; 1570 } else { 1571 epctx->mfindex_last = xfer->mfindex_kick; 1572 qemu_del_timer(epctx->kick_timer); 1573 xfer->running_retry = 0; 1574 } 1575 } 1576 1577 1578 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1579 { 1580 uint64_t mfindex; 1581 int ret; 1582 1583 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1584 1585 xfer->in_xfer = epctx->type>>2; 1586 1587 switch(epctx->type) { 1588 case ET_INTR_OUT: 1589 case ET_INTR_IN: 1590 case ET_BULK_OUT: 1591 case ET_BULK_IN: 1592 xfer->pkts = 0; 1593 xfer->iso_xfer = false; 1594 break; 1595 case ET_ISO_OUT: 1596 case ET_ISO_IN: 1597 xfer->pkts = 1; 1598 xfer->iso_xfer = true; 1599 mfindex = xhci_mfindex_get(xhci); 1600 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1601 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1602 if (xfer->running_retry) { 1603 return -1; 1604 } 1605 break; 1606 default: 1607 fprintf(stderr, "xhci: unknown or unhandled EP " 1608 "(type %d, in %d, ep %02x)\n", 1609 epctx->type, xfer->in_xfer, xfer->epid); 1610 return -1; 1611 } 1612 1613 if (xhci_setup_packet(xfer) < 0) { 1614 return -1; 1615 } 1616 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1617 1618 xhci_complete_packet(xfer, ret); 1619 if (!xfer->running_async && !xfer->running_retry) { 1620 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1621 } 1622 return 0; 1623 } 1624 1625 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1626 { 1627 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1628 return xhci_submit(xhci, xfer, epctx); 1629 } 1630 1631 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1632 { 1633 XHCIEPContext *epctx; 1634 uint64_t mfindex; 1635 int length; 1636 int i; 1637 1638 trace_usb_xhci_ep_kick(slotid, epid); 1639 assert(slotid >= 1 && slotid <= MAXSLOTS); 1640 assert(epid >= 1 && epid <= 31); 1641 1642 if (!xhci->slots[slotid-1].enabled) { 1643 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1644 return; 1645 } 1646 epctx = xhci->slots[slotid-1].eps[epid-1]; 1647 if (!epctx) { 1648 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1649 epid, slotid); 1650 return; 1651 } 1652 1653 if (epctx->retry) { 1654 XHCITransfer *xfer = epctx->retry; 1655 int result; 1656 1657 trace_usb_xhci_xfer_retry(xfer); 1658 assert(xfer->running_retry); 1659 if (xfer->iso_xfer) { 1660 /* retry delayed iso transfer */ 1661 mfindex = xhci_mfindex_get(xhci); 1662 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1663 if (xfer->running_retry) { 1664 return; 1665 } 1666 if (xhci_setup_packet(xfer) < 0) { 1667 return; 1668 } 1669 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1670 assert(result != USB_RET_NAK); 1671 xhci_complete_packet(xfer, result); 1672 } else { 1673 /* retry nak'ed transfer */ 1674 if (xhci_setup_packet(xfer) < 0) { 1675 return; 1676 } 1677 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1678 if (result == USB_RET_NAK) { 1679 return; 1680 } 1681 xhci_complete_packet(xfer, result); 1682 } 1683 assert(!xfer->running_retry); 1684 epctx->retry = NULL; 1685 } 1686 1687 if (epctx->state == EP_HALTED) { 1688 DPRINTF("xhci: ep halted, not running schedule\n"); 1689 return; 1690 } 1691 1692 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1693 1694 while (1) { 1695 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1696 if (xfer->running_async || xfer->running_retry) { 1697 break; 1698 } 1699 length = xhci_ring_chain_length(xhci, &epctx->ring); 1700 if (length < 0) { 1701 break; 1702 } else if (length == 0) { 1703 break; 1704 } 1705 if (xfer->trbs && xfer->trb_alloced < length) { 1706 xfer->trb_count = 0; 1707 xfer->trb_alloced = 0; 1708 g_free(xfer->trbs); 1709 xfer->trbs = NULL; 1710 } 1711 if (!xfer->trbs) { 1712 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1713 xfer->trb_alloced = length; 1714 } 1715 xfer->trb_count = length; 1716 1717 for (i = 0; i < length; i++) { 1718 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1719 } 1720 xfer->xhci = xhci; 1721 xfer->epid = epid; 1722 xfer->slotid = slotid; 1723 1724 if (epid == 1) { 1725 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1726 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1727 } else { 1728 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1729 } 1730 } else { 1731 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1732 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1733 } else { 1734 if (!xfer->iso_xfer) { 1735 fprintf(stderr, "xhci: error firing data transfer\n"); 1736 } 1737 } 1738 } 1739 1740 if (epctx->state == EP_HALTED) { 1741 break; 1742 } 1743 if (xfer->running_retry) { 1744 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1745 epctx->retry = xfer; 1746 break; 1747 } 1748 } 1749 } 1750 1751 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1752 { 1753 trace_usb_xhci_slot_enable(slotid); 1754 assert(slotid >= 1 && slotid <= MAXSLOTS); 1755 xhci->slots[slotid-1].enabled = 1; 1756 xhci->slots[slotid-1].port = 0; 1757 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1758 1759 return CC_SUCCESS; 1760 } 1761 1762 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1763 { 1764 int i; 1765 1766 trace_usb_xhci_slot_disable(slotid); 1767 assert(slotid >= 1 && slotid <= MAXSLOTS); 1768 1769 for (i = 1; i <= 31; i++) { 1770 if (xhci->slots[slotid-1].eps[i-1]) { 1771 xhci_disable_ep(xhci, slotid, i); 1772 } 1773 } 1774 1775 xhci->slots[slotid-1].enabled = 0; 1776 return CC_SUCCESS; 1777 } 1778 1779 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1780 uint64_t pictx, bool bsr) 1781 { 1782 XHCISlot *slot; 1783 USBDevice *dev; 1784 dma_addr_t ictx, octx, dcbaap; 1785 uint64_t poctx; 1786 uint32_t ictl_ctx[2]; 1787 uint32_t slot_ctx[4]; 1788 uint32_t ep0_ctx[5]; 1789 unsigned int port; 1790 int i; 1791 TRBCCode res; 1792 1793 trace_usb_xhci_slot_address(slotid); 1794 assert(slotid >= 1 && slotid <= MAXSLOTS); 1795 1796 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1797 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1798 ictx = xhci_mask64(pictx); 1799 octx = xhci_mask64(le64_to_cpu(poctx)); 1800 1801 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1802 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1803 1804 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1805 1806 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1807 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1808 ictl_ctx[0], ictl_ctx[1]); 1809 return CC_TRB_ERROR; 1810 } 1811 1812 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1813 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1814 1815 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1816 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1817 1818 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1819 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1820 1821 port = (slot_ctx[1]>>16) & 0xFF; 1822 dev = xhci->ports[port-1].uport->dev; 1823 1824 if (port < 1 || port > xhci->numports) { 1825 fprintf(stderr, "xhci: bad port %d\n", port); 1826 return CC_TRB_ERROR; 1827 } else if (!dev) { 1828 fprintf(stderr, "xhci: port %d not connected\n", port); 1829 return CC_USB_TRANSACTION_ERROR; 1830 } 1831 1832 for (i = 0; i < MAXSLOTS; i++) { 1833 if (xhci->slots[i].port == port) { 1834 fprintf(stderr, "xhci: port %d already assigned to slot %d\n", 1835 port, i+1); 1836 return CC_TRB_ERROR; 1837 } 1838 } 1839 1840 slot = &xhci->slots[slotid-1]; 1841 slot->port = port; 1842 slot->ctx = octx; 1843 1844 if (bsr) { 1845 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1846 } else { 1847 slot->devaddr = xhci->devaddr++; 1848 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1849 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1850 usb_device_handle_control(dev, NULL, 1851 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1852 slot->devaddr, 0, 0, NULL); 1853 } 1854 1855 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1856 1857 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1858 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1859 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1860 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1861 1862 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1863 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1864 1865 return res; 1866 } 1867 1868 1869 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1870 uint64_t pictx, bool dc) 1871 { 1872 dma_addr_t ictx, octx; 1873 uint32_t ictl_ctx[2]; 1874 uint32_t slot_ctx[4]; 1875 uint32_t islot_ctx[4]; 1876 uint32_t ep_ctx[5]; 1877 int i; 1878 TRBCCode res; 1879 1880 trace_usb_xhci_slot_configure(slotid); 1881 assert(slotid >= 1 && slotid <= MAXSLOTS); 1882 1883 ictx = xhci_mask64(pictx); 1884 octx = xhci->slots[slotid-1].ctx; 1885 1886 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1887 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1888 1889 if (dc) { 1890 for (i = 2; i <= 31; i++) { 1891 if (xhci->slots[slotid-1].eps[i-1]) { 1892 xhci_disable_ep(xhci, slotid, i); 1893 } 1894 } 1895 1896 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1897 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1898 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1899 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1900 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1901 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1902 1903 return CC_SUCCESS; 1904 } 1905 1906 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1907 1908 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1909 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1910 ictl_ctx[0], ictl_ctx[1]); 1911 return CC_TRB_ERROR; 1912 } 1913 1914 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1915 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1916 1917 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1918 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1919 return CC_CONTEXT_STATE_ERROR; 1920 } 1921 1922 for (i = 2; i <= 31; i++) { 1923 if (ictl_ctx[0] & (1<<i)) { 1924 xhci_disable_ep(xhci, slotid, i); 1925 } 1926 if (ictl_ctx[1] & (1<<i)) { 1927 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1928 sizeof(ep_ctx)); 1929 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1930 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1931 ep_ctx[3], ep_ctx[4]); 1932 xhci_disable_ep(xhci, slotid, i); 1933 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1934 if (res != CC_SUCCESS) { 1935 return res; 1936 } 1937 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 1938 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1939 ep_ctx[3], ep_ctx[4]); 1940 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 1941 } 1942 } 1943 1944 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1945 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 1946 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 1947 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 1948 SLOT_CONTEXT_ENTRIES_SHIFT); 1949 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1950 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1951 1952 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1953 1954 return CC_SUCCESS; 1955 } 1956 1957 1958 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 1959 uint64_t pictx) 1960 { 1961 dma_addr_t ictx, octx; 1962 uint32_t ictl_ctx[2]; 1963 uint32_t iep0_ctx[5]; 1964 uint32_t ep0_ctx[5]; 1965 uint32_t islot_ctx[4]; 1966 uint32_t slot_ctx[4]; 1967 1968 trace_usb_xhci_slot_evaluate(slotid); 1969 assert(slotid >= 1 && slotid <= MAXSLOTS); 1970 1971 ictx = xhci_mask64(pictx); 1972 octx = xhci->slots[slotid-1].ctx; 1973 1974 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1975 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1976 1977 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1978 1979 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 1980 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1981 ictl_ctx[0], ictl_ctx[1]); 1982 return CC_TRB_ERROR; 1983 } 1984 1985 if (ictl_ctx[1] & 0x1) { 1986 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1987 1988 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1989 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 1990 1991 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1992 1993 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 1994 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 1995 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 1996 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 1997 1998 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1999 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2000 2001 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2002 } 2003 2004 if (ictl_ctx[1] & 0x2) { 2005 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2006 2007 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2008 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2009 iep0_ctx[3], iep0_ctx[4]); 2010 2011 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2012 2013 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2014 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2015 2016 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2017 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2018 2019 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2020 } 2021 2022 return CC_SUCCESS; 2023 } 2024 2025 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2026 { 2027 uint32_t slot_ctx[4]; 2028 dma_addr_t octx; 2029 int i; 2030 2031 trace_usb_xhci_slot_reset(slotid); 2032 assert(slotid >= 1 && slotid <= MAXSLOTS); 2033 2034 octx = xhci->slots[slotid-1].ctx; 2035 2036 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2037 2038 for (i = 2; i <= 31; i++) { 2039 if (xhci->slots[slotid-1].eps[i-1]) { 2040 xhci_disable_ep(xhci, slotid, i); 2041 } 2042 } 2043 2044 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2045 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2046 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2047 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2048 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2049 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2050 2051 return CC_SUCCESS; 2052 } 2053 2054 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2055 { 2056 unsigned int slotid; 2057 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2058 if (slotid < 1 || slotid > MAXSLOTS) { 2059 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2060 event->ccode = CC_TRB_ERROR; 2061 return 0; 2062 } else if (!xhci->slots[slotid-1].enabled) { 2063 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2064 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2065 return 0; 2066 } 2067 return slotid; 2068 } 2069 2070 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2071 { 2072 dma_addr_t ctx; 2073 uint8_t bw_ctx[xhci->numports+1]; 2074 2075 DPRINTF("xhci_get_port_bandwidth()\n"); 2076 2077 ctx = xhci_mask64(pctx); 2078 2079 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2080 2081 /* TODO: actually implement real values here */ 2082 bw_ctx[0] = 0; 2083 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2084 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2085 2086 return CC_SUCCESS; 2087 } 2088 2089 static uint32_t rotl(uint32_t v, unsigned count) 2090 { 2091 count &= 31; 2092 return (v << count) | (v >> (32 - count)); 2093 } 2094 2095 2096 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2097 { 2098 uint32_t val; 2099 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2100 val += rotl(lo + 0x49434878, hi & 0x1F); 2101 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2102 return ~val; 2103 } 2104 2105 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2106 { 2107 uint32_t buf[8]; 2108 uint32_t obuf[8]; 2109 dma_addr_t paddr = xhci_mask64(addr); 2110 2111 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2112 2113 memcpy(obuf, buf, sizeof(obuf)); 2114 2115 if ((buf[0] & 0xff) == 2) { 2116 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2117 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2118 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2119 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2120 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2121 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2122 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2123 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2124 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2125 } 2126 2127 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2128 } 2129 2130 static void xhci_process_commands(XHCIState *xhci) 2131 { 2132 XHCITRB trb; 2133 TRBType type; 2134 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2135 dma_addr_t addr; 2136 unsigned int i, slotid = 0; 2137 2138 DPRINTF("xhci_process_commands()\n"); 2139 if (!xhci_running(xhci)) { 2140 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2141 return; 2142 } 2143 2144 xhci->crcr_low |= CRCR_CRR; 2145 2146 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2147 event.ptr = addr; 2148 switch (type) { 2149 case CR_ENABLE_SLOT: 2150 for (i = 0; i < MAXSLOTS; i++) { 2151 if (!xhci->slots[i].enabled) { 2152 break; 2153 } 2154 } 2155 if (i >= MAXSLOTS) { 2156 fprintf(stderr, "xhci: no device slots available\n"); 2157 event.ccode = CC_NO_SLOTS_ERROR; 2158 } else { 2159 slotid = i+1; 2160 event.ccode = xhci_enable_slot(xhci, slotid); 2161 } 2162 break; 2163 case CR_DISABLE_SLOT: 2164 slotid = xhci_get_slot(xhci, &event, &trb); 2165 if (slotid) { 2166 event.ccode = xhci_disable_slot(xhci, slotid); 2167 } 2168 break; 2169 case CR_ADDRESS_DEVICE: 2170 slotid = xhci_get_slot(xhci, &event, &trb); 2171 if (slotid) { 2172 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2173 trb.control & TRB_CR_BSR); 2174 } 2175 break; 2176 case CR_CONFIGURE_ENDPOINT: 2177 slotid = xhci_get_slot(xhci, &event, &trb); 2178 if (slotid) { 2179 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2180 trb.control & TRB_CR_DC); 2181 } 2182 break; 2183 case CR_EVALUATE_CONTEXT: 2184 slotid = xhci_get_slot(xhci, &event, &trb); 2185 if (slotid) { 2186 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2187 } 2188 break; 2189 case CR_STOP_ENDPOINT: 2190 slotid = xhci_get_slot(xhci, &event, &trb); 2191 if (slotid) { 2192 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2193 & TRB_CR_EPID_MASK; 2194 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2195 } 2196 break; 2197 case CR_RESET_ENDPOINT: 2198 slotid = xhci_get_slot(xhci, &event, &trb); 2199 if (slotid) { 2200 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2201 & TRB_CR_EPID_MASK; 2202 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2203 } 2204 break; 2205 case CR_SET_TR_DEQUEUE: 2206 slotid = xhci_get_slot(xhci, &event, &trb); 2207 if (slotid) { 2208 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2209 & TRB_CR_EPID_MASK; 2210 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2211 trb.parameter); 2212 } 2213 break; 2214 case CR_RESET_DEVICE: 2215 slotid = xhci_get_slot(xhci, &event, &trb); 2216 if (slotid) { 2217 event.ccode = xhci_reset_slot(xhci, slotid); 2218 } 2219 break; 2220 case CR_GET_PORT_BANDWIDTH: 2221 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2222 break; 2223 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2224 xhci_via_challenge(xhci, trb.parameter); 2225 break; 2226 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2227 event.type = 48; /* NEC reply */ 2228 event.length = 0x3025; 2229 break; 2230 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2231 { 2232 uint32_t chi = trb.parameter >> 32; 2233 uint32_t clo = trb.parameter; 2234 uint32_t val = xhci_nec_challenge(chi, clo); 2235 event.length = val & 0xFFFF; 2236 event.epid = val >> 16; 2237 slotid = val >> 24; 2238 event.type = 48; /* NEC reply */ 2239 } 2240 break; 2241 default: 2242 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2243 event.ccode = CC_TRB_ERROR; 2244 break; 2245 } 2246 event.slotid = slotid; 2247 xhci_event(xhci, &event); 2248 } 2249 } 2250 2251 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2252 { 2253 port->portsc = PORTSC_PP; 2254 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2255 (1 << port->uport->dev->speed) & port->speedmask) { 2256 port->portsc |= PORTSC_CCS; 2257 switch (port->uport->dev->speed) { 2258 case USB_SPEED_LOW: 2259 port->portsc |= PORTSC_SPEED_LOW; 2260 break; 2261 case USB_SPEED_FULL: 2262 port->portsc |= PORTSC_SPEED_FULL; 2263 break; 2264 case USB_SPEED_HIGH: 2265 port->portsc |= PORTSC_SPEED_HIGH; 2266 break; 2267 case USB_SPEED_SUPER: 2268 port->portsc |= PORTSC_SPEED_SUPER; 2269 break; 2270 } 2271 } 2272 2273 if (xhci_running(xhci)) { 2274 port->portsc |= PORTSC_CSC; 2275 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2276 port->portnr << 24}; 2277 xhci_event(xhci, &ev); 2278 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2279 } 2280 } 2281 2282 static void xhci_reset(DeviceState *dev) 2283 { 2284 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2285 int i; 2286 2287 trace_usb_xhci_reset(); 2288 if (!(xhci->usbsts & USBSTS_HCH)) { 2289 fprintf(stderr, "xhci: reset while running!\n"); 2290 } 2291 2292 xhci->usbcmd = 0; 2293 xhci->usbsts = USBSTS_HCH; 2294 xhci->dnctrl = 0; 2295 xhci->crcr_low = 0; 2296 xhci->crcr_high = 0; 2297 xhci->dcbaap_low = 0; 2298 xhci->dcbaap_high = 0; 2299 xhci->config = 0; 2300 xhci->devaddr = 2; 2301 2302 for (i = 0; i < MAXSLOTS; i++) { 2303 xhci_disable_slot(xhci, i+1); 2304 } 2305 2306 for (i = 0; i < xhci->numports; i++) { 2307 xhci_update_port(xhci, xhci->ports + i, 0); 2308 } 2309 2310 xhci->iman = 0; 2311 xhci->imod = 0; 2312 xhci->erstsz = 0; 2313 xhci->erstba_low = 0; 2314 xhci->erstba_high = 0; 2315 xhci->erdp_low = 0; 2316 xhci->erdp_high = 0; 2317 xhci->msix_used = 0; 2318 2319 xhci->er_ep_idx = 0; 2320 xhci->er_pcs = 1; 2321 xhci->er_full = 0; 2322 xhci->ev_buffer_put = 0; 2323 xhci->ev_buffer_get = 0; 2324 2325 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2326 xhci_mfwrap_update(xhci); 2327 } 2328 2329 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg) 2330 { 2331 uint32_t ret; 2332 2333 switch (reg) { 2334 case 0x00: /* HCIVERSION, CAPLENGTH */ 2335 ret = 0x01000000 | LEN_CAP; 2336 break; 2337 case 0x04: /* HCSPARAMS 1 */ 2338 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2339 | (MAXINTRS<<8) | MAXSLOTS; 2340 break; 2341 case 0x08: /* HCSPARAMS 2 */ 2342 ret = 0x0000000f; 2343 break; 2344 case 0x0c: /* HCSPARAMS 3 */ 2345 ret = 0x00000000; 2346 break; 2347 case 0x10: /* HCCPARAMS */ 2348 if (sizeof(dma_addr_t) == 4) { 2349 ret = 0x00081000; 2350 } else { 2351 ret = 0x00081001; 2352 } 2353 break; 2354 case 0x14: /* DBOFF */ 2355 ret = OFF_DOORBELL; 2356 break; 2357 case 0x18: /* RTSOFF */ 2358 ret = OFF_RUNTIME; 2359 break; 2360 2361 /* extended capabilities */ 2362 case 0x20: /* Supported Protocol:00 */ 2363 ret = 0x02000402; /* USB 2.0 */ 2364 break; 2365 case 0x24: /* Supported Protocol:04 */ 2366 ret = 0x20425455; /* "USB " */ 2367 break; 2368 case 0x28: /* Supported Protocol:08 */ 2369 ret = 0x00000001 | (xhci->numports_2<<8); 2370 break; 2371 case 0x2c: /* Supported Protocol:0c */ 2372 ret = 0x00000000; /* reserved */ 2373 break; 2374 case 0x30: /* Supported Protocol:00 */ 2375 ret = 0x03000002; /* USB 3.0 */ 2376 break; 2377 case 0x34: /* Supported Protocol:04 */ 2378 ret = 0x20425455; /* "USB " */ 2379 break; 2380 case 0x38: /* Supported Protocol:08 */ 2381 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2382 break; 2383 case 0x3c: /* Supported Protocol:0c */ 2384 ret = 0x00000000; /* reserved */ 2385 break; 2386 default: 2387 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg); 2388 ret = 0; 2389 } 2390 2391 trace_usb_xhci_cap_read(reg, ret); 2392 return ret; 2393 } 2394 2395 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg) 2396 { 2397 uint32_t port = reg >> 4; 2398 uint32_t ret; 2399 2400 if (port >= xhci->numports) { 2401 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2402 ret = 0; 2403 goto out; 2404 } 2405 2406 switch (reg & 0xf) { 2407 case 0x00: /* PORTSC */ 2408 ret = xhci->ports[port].portsc; 2409 break; 2410 case 0x04: /* PORTPMSC */ 2411 case 0x08: /* PORTLI */ 2412 ret = 0; 2413 break; 2414 case 0x0c: /* reserved */ 2415 default: 2416 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2417 port, reg); 2418 ret = 0; 2419 } 2420 2421 out: 2422 trace_usb_xhci_port_read(port, reg & 0x0f, ret); 2423 return ret; 2424 } 2425 2426 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2427 { 2428 uint32_t port = reg >> 4; 2429 uint32_t portsc; 2430 2431 trace_usb_xhci_port_write(port, reg & 0x0f, val); 2432 2433 if (port >= xhci->numports) { 2434 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port); 2435 return; 2436 } 2437 2438 switch (reg & 0xf) { 2439 case 0x00: /* PORTSC */ 2440 portsc = xhci->ports[port].portsc; 2441 /* write-1-to-clear bits*/ 2442 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2443 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2444 if (val & PORTSC_LWS) { 2445 /* overwrite PLS only when LWS=1 */ 2446 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2447 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2448 } 2449 /* read/write bits */ 2450 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2451 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2452 /* write-1-to-start bits */ 2453 if (val & PORTSC_PR) { 2454 DPRINTF("xhci: port %d reset\n", port); 2455 usb_device_reset(xhci->ports[port].uport->dev); 2456 portsc |= PORTSC_PRC | PORTSC_PED; 2457 } 2458 xhci->ports[port].portsc = portsc; 2459 break; 2460 case 0x04: /* PORTPMSC */ 2461 case 0x08: /* PORTLI */ 2462 default: 2463 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2464 port, reg); 2465 } 2466 } 2467 2468 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg) 2469 { 2470 uint32_t ret; 2471 2472 if (reg >= 0x400) { 2473 return xhci_port_read(xhci, reg - 0x400); 2474 } 2475 2476 switch (reg) { 2477 case 0x00: /* USBCMD */ 2478 ret = xhci->usbcmd; 2479 break; 2480 case 0x04: /* USBSTS */ 2481 ret = xhci->usbsts; 2482 break; 2483 case 0x08: /* PAGESIZE */ 2484 ret = 1; /* 4KiB */ 2485 break; 2486 case 0x14: /* DNCTRL */ 2487 ret = xhci->dnctrl; 2488 break; 2489 case 0x18: /* CRCR low */ 2490 ret = xhci->crcr_low & ~0xe; 2491 break; 2492 case 0x1c: /* CRCR high */ 2493 ret = xhci->crcr_high; 2494 break; 2495 case 0x30: /* DCBAAP low */ 2496 ret = xhci->dcbaap_low; 2497 break; 2498 case 0x34: /* DCBAAP high */ 2499 ret = xhci->dcbaap_high; 2500 break; 2501 case 0x38: /* CONFIG */ 2502 ret = xhci->config; 2503 break; 2504 default: 2505 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg); 2506 ret = 0; 2507 } 2508 2509 trace_usb_xhci_oper_read(reg, ret); 2510 return ret; 2511 } 2512 2513 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2514 { 2515 if (reg >= 0x400) { 2516 xhci_port_write(xhci, reg - 0x400, val); 2517 return; 2518 } 2519 2520 trace_usb_xhci_oper_write(reg, val); 2521 2522 switch (reg) { 2523 case 0x00: /* USBCMD */ 2524 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2525 xhci_run(xhci); 2526 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2527 xhci_stop(xhci); 2528 } 2529 xhci->usbcmd = val & 0xc0f; 2530 xhci_mfwrap_update(xhci); 2531 if (val & USBCMD_HCRST) { 2532 xhci_reset(&xhci->pci_dev.qdev); 2533 } 2534 xhci_intx_update(xhci); 2535 break; 2536 2537 case 0x04: /* USBSTS */ 2538 /* these bits are write-1-to-clear */ 2539 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2540 xhci_intx_update(xhci); 2541 break; 2542 2543 case 0x14: /* DNCTRL */ 2544 xhci->dnctrl = val & 0xffff; 2545 break; 2546 case 0x18: /* CRCR low */ 2547 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2548 break; 2549 case 0x1c: /* CRCR high */ 2550 xhci->crcr_high = val; 2551 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2552 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2553 xhci->crcr_low &= ~CRCR_CRR; 2554 xhci_event(xhci, &event); 2555 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2556 } else { 2557 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2558 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2559 } 2560 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2561 break; 2562 case 0x30: /* DCBAAP low */ 2563 xhci->dcbaap_low = val & 0xffffffc0; 2564 break; 2565 case 0x34: /* DCBAAP high */ 2566 xhci->dcbaap_high = val; 2567 break; 2568 case 0x38: /* CONFIG */ 2569 xhci->config = val & 0xff; 2570 break; 2571 default: 2572 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg); 2573 } 2574 } 2575 2576 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg) 2577 { 2578 uint32_t ret; 2579 2580 switch (reg) { 2581 case 0x00: /* MFINDEX */ 2582 ret = xhci_mfindex_get(xhci) & 0x3fff; 2583 break; 2584 case 0x20: /* IMAN */ 2585 ret = xhci->iman; 2586 break; 2587 case 0x24: /* IMOD */ 2588 ret = xhci->imod; 2589 break; 2590 case 0x28: /* ERSTSZ */ 2591 ret = xhci->erstsz; 2592 break; 2593 case 0x30: /* ERSTBA low */ 2594 ret = xhci->erstba_low; 2595 break; 2596 case 0x34: /* ERSTBA high */ 2597 ret = xhci->erstba_high; 2598 break; 2599 case 0x38: /* ERDP low */ 2600 ret = xhci->erdp_low; 2601 break; 2602 case 0x3c: /* ERDP high */ 2603 ret = xhci->erdp_high; 2604 break; 2605 default: 2606 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg); 2607 ret = 0; 2608 } 2609 2610 trace_usb_xhci_runtime_read(reg, ret); 2611 return ret; 2612 } 2613 2614 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2615 { 2616 trace_usb_xhci_runtime_write(reg, val); 2617 2618 switch (reg) { 2619 case 0x20: /* IMAN */ 2620 if (val & IMAN_IP) { 2621 xhci->iman &= ~IMAN_IP; 2622 } 2623 xhci->iman &= ~IMAN_IE; 2624 xhci->iman |= val & IMAN_IE; 2625 xhci_intx_update(xhci); 2626 xhci_msix_update(xhci); 2627 break; 2628 case 0x24: /* IMOD */ 2629 xhci->imod = val; 2630 break; 2631 case 0x28: /* ERSTSZ */ 2632 xhci->erstsz = val & 0xffff; 2633 break; 2634 case 0x30: /* ERSTBA low */ 2635 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2636 xhci->erstba_low = val & 0xffffffc0; */ 2637 xhci->erstba_low = val & 0xfffffff0; 2638 break; 2639 case 0x34: /* ERSTBA high */ 2640 xhci->erstba_high = val; 2641 xhci_er_reset(xhci); 2642 break; 2643 case 0x38: /* ERDP low */ 2644 if (val & ERDP_EHB) { 2645 xhci->erdp_low &= ~ERDP_EHB; 2646 } 2647 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB); 2648 break; 2649 case 0x3c: /* ERDP high */ 2650 xhci->erdp_high = val; 2651 xhci_events_update(xhci); 2652 break; 2653 default: 2654 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg); 2655 } 2656 } 2657 2658 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg) 2659 { 2660 /* doorbells always read as 0 */ 2661 trace_usb_xhci_doorbell_read(reg, 0); 2662 return 0; 2663 } 2664 2665 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val) 2666 { 2667 trace_usb_xhci_doorbell_write(reg, val); 2668 2669 if (!xhci_running(xhci)) { 2670 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2671 return; 2672 } 2673 2674 reg >>= 2; 2675 2676 if (reg == 0) { 2677 if (val == 0) { 2678 xhci_process_commands(xhci); 2679 } else { 2680 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val); 2681 } 2682 } else { 2683 if (reg > MAXSLOTS) { 2684 fprintf(stderr, "xhci: bad doorbell %d\n", reg); 2685 } else if (val > 31) { 2686 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val); 2687 } else { 2688 xhci_kick_ep(xhci, reg, val); 2689 } 2690 } 2691 } 2692 2693 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr, 2694 unsigned size) 2695 { 2696 XHCIState *xhci = ptr; 2697 2698 /* Only aligned reads are allowed on xHCI */ 2699 if (addr & 3) { 2700 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n"); 2701 return 0; 2702 } 2703 2704 if (addr < LEN_CAP) { 2705 return xhci_cap_read(xhci, addr); 2706 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { 2707 return xhci_oper_read(xhci, addr - OFF_OPER); 2708 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { 2709 return xhci_runtime_read(xhci, addr - OFF_RUNTIME); 2710 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { 2711 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL); 2712 } else { 2713 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr); 2714 return 0; 2715 } 2716 } 2717 2718 static void xhci_mem_write(void *ptr, target_phys_addr_t addr, 2719 uint64_t val, unsigned size) 2720 { 2721 XHCIState *xhci = ptr; 2722 2723 /* Only aligned writes are allowed on xHCI */ 2724 if (addr & 3) { 2725 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n"); 2726 return; 2727 } 2728 2729 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) { 2730 xhci_oper_write(xhci, addr - OFF_OPER, val); 2731 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) { 2732 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val); 2733 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) { 2734 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val); 2735 } else { 2736 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr); 2737 } 2738 } 2739 2740 static const MemoryRegionOps xhci_mem_ops = { 2741 .read = xhci_mem_read, 2742 .write = xhci_mem_write, 2743 .valid.min_access_size = 4, 2744 .valid.max_access_size = 4, 2745 .endianness = DEVICE_LITTLE_ENDIAN, 2746 }; 2747 2748 static void xhci_attach(USBPort *usbport) 2749 { 2750 XHCIState *xhci = usbport->opaque; 2751 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2752 2753 xhci_update_port(xhci, port, 0); 2754 } 2755 2756 static void xhci_detach(USBPort *usbport) 2757 { 2758 XHCIState *xhci = usbport->opaque; 2759 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2760 2761 xhci_update_port(xhci, port, 1); 2762 } 2763 2764 static void xhci_wakeup(USBPort *usbport) 2765 { 2766 XHCIState *xhci = usbport->opaque; 2767 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2768 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2769 port->portnr << 24}; 2770 uint32_t pls; 2771 2772 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2773 if (pls != 3) { 2774 return; 2775 } 2776 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2777 if (port->portsc & PORTSC_PLC) { 2778 return; 2779 } 2780 port->portsc |= PORTSC_PLC; 2781 xhci_event(xhci, &ev); 2782 } 2783 2784 static void xhci_complete(USBPort *port, USBPacket *packet) 2785 { 2786 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2787 2788 xhci_complete_packet(xfer, packet->result); 2789 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2790 } 2791 2792 static void xhci_child_detach(USBPort *port, USBDevice *child) 2793 { 2794 FIXME(); 2795 } 2796 2797 static USBPortOps xhci_port_ops = { 2798 .attach = xhci_attach, 2799 .detach = xhci_detach, 2800 .wakeup = xhci_wakeup, 2801 .complete = xhci_complete, 2802 .child_detach = xhci_child_detach, 2803 }; 2804 2805 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2806 { 2807 XHCISlot *slot; 2808 int slotid; 2809 2810 for (slotid = 1; slotid <= MAXSLOTS; slotid++) { 2811 slot = &xhci->slots[slotid-1]; 2812 if (slot->devaddr == dev->addr) { 2813 return slotid; 2814 } 2815 } 2816 return 0; 2817 } 2818 2819 static int xhci_find_epid(USBEndpoint *ep) 2820 { 2821 if (ep->nr == 0) { 2822 return 1; 2823 } 2824 if (ep->pid == USB_TOKEN_IN) { 2825 return ep->nr * 2 + 1; 2826 } else { 2827 return ep->nr * 2; 2828 } 2829 } 2830 2831 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2832 { 2833 XHCIState *xhci = container_of(bus, XHCIState, bus); 2834 int slotid; 2835 2836 DPRINTF("%s\n", __func__); 2837 slotid = xhci_find_slotid(xhci, ep->dev); 2838 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2839 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2840 return; 2841 } 2842 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2843 } 2844 2845 static USBBusOps xhci_bus_ops = { 2846 .wakeup_endpoint = xhci_wakeup_endpoint, 2847 }; 2848 2849 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2850 { 2851 XHCIPort *port; 2852 int i, usbports, speedmask; 2853 2854 xhci->usbsts = USBSTS_HCH; 2855 2856 if (xhci->numports_2 > MAXPORTS_2) { 2857 xhci->numports_2 = MAXPORTS_2; 2858 } 2859 if (xhci->numports_3 > MAXPORTS_3) { 2860 xhci->numports_3 = MAXPORTS_3; 2861 } 2862 usbports = MAX(xhci->numports_2, xhci->numports_3); 2863 xhci->numports = xhci->numports_2 + xhci->numports_3; 2864 2865 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2866 2867 for (i = 0; i < usbports; i++) { 2868 speedmask = 0; 2869 if (i < xhci->numports_2) { 2870 port = &xhci->ports[i]; 2871 port->portnr = i + 1; 2872 port->uport = &xhci->uports[i]; 2873 port->speedmask = 2874 USB_SPEED_MASK_LOW | 2875 USB_SPEED_MASK_FULL | 2876 USB_SPEED_MASK_HIGH; 2877 speedmask |= port->speedmask; 2878 } 2879 if (i < xhci->numports_3) { 2880 port = &xhci->ports[i + xhci->numports_2]; 2881 port->portnr = i + 1 + xhci->numports_2; 2882 port->uport = &xhci->uports[i]; 2883 port->speedmask = USB_SPEED_MASK_SUPER; 2884 speedmask |= port->speedmask; 2885 } 2886 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2887 &xhci_port_ops, speedmask); 2888 } 2889 } 2890 2891 static int usb_xhci_initfn(struct PCIDevice *dev) 2892 { 2893 int ret; 2894 2895 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2896 2897 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2898 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2899 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2900 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2901 2902 usb_xhci_init(xhci, &dev->qdev); 2903 2904 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2905 2906 xhci->irq = xhci->pci_dev.irq[0]; 2907 2908 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci, 2909 "xhci", LEN_REGS); 2910 pci_register_bar(&xhci->pci_dev, 0, 2911 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 2912 &xhci->mem); 2913 2914 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 2915 assert(ret >= 0); 2916 2917 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 2918 msi_init(&xhci->pci_dev, 0x70, MAXINTRS, true, false); 2919 } 2920 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 2921 msix_init(&xhci->pci_dev, MAXINTRS, 2922 &xhci->mem, 0, OFF_MSIX_TABLE, 2923 &xhci->mem, 0, OFF_MSIX_PBA, 2924 0x90); 2925 } 2926 2927 return 0; 2928 } 2929 2930 static const VMStateDescription vmstate_xhci = { 2931 .name = "xhci", 2932 .unmigratable = 1, 2933 }; 2934 2935 static Property xhci_properties[] = { 2936 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 2937 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 2938 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 2939 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 2940 DEFINE_PROP_END_OF_LIST(), 2941 }; 2942 2943 static void xhci_class_init(ObjectClass *klass, void *data) 2944 { 2945 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2946 DeviceClass *dc = DEVICE_CLASS(klass); 2947 2948 dc->vmsd = &vmstate_xhci; 2949 dc->props = xhci_properties; 2950 dc->reset = xhci_reset; 2951 k->init = usb_xhci_initfn; 2952 k->vendor_id = PCI_VENDOR_ID_NEC; 2953 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 2954 k->class_id = PCI_CLASS_SERIAL_USB; 2955 k->revision = 0x03; 2956 k->is_express = 1; 2957 } 2958 2959 static TypeInfo xhci_info = { 2960 .name = "nec-usb-xhci", 2961 .parent = TYPE_PCI_DEVICE, 2962 .instance_size = sizeof(XHCIState), 2963 .class_init = xhci_class_init, 2964 }; 2965 2966 static void xhci_register_types(void) 2967 { 2968 type_register_static(&xhci_info); 2969 } 2970 2971 type_init(xhci_register_types) 2972