1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 150 typedef enum TRBType { 151 TRB_RESERVED = 0, 152 TR_NORMAL, 153 TR_SETUP, 154 TR_DATA, 155 TR_STATUS, 156 TR_ISOCH, 157 TR_LINK, 158 TR_EVDATA, 159 TR_NOOP, 160 CR_ENABLE_SLOT, 161 CR_DISABLE_SLOT, 162 CR_ADDRESS_DEVICE, 163 CR_CONFIGURE_ENDPOINT, 164 CR_EVALUATE_CONTEXT, 165 CR_RESET_ENDPOINT, 166 CR_STOP_ENDPOINT, 167 CR_SET_TR_DEQUEUE, 168 CR_RESET_DEVICE, 169 CR_FORCE_EVENT, 170 CR_NEGOTIATE_BW, 171 CR_SET_LATENCY_TOLERANCE, 172 CR_GET_PORT_BANDWIDTH, 173 CR_FORCE_HEADER, 174 CR_NOOP, 175 ER_TRANSFER = 32, 176 ER_COMMAND_COMPLETE, 177 ER_PORT_STATUS_CHANGE, 178 ER_BANDWIDTH_REQUEST, 179 ER_DOORBELL, 180 ER_HOST_CONTROLLER, 181 ER_DEVICE_NOTIFICATION, 182 ER_MFINDEX_WRAP, 183 /* vendor specific bits */ 184 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 185 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 186 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 187 } TRBType; 188 189 #define CR_LINK TR_LINK 190 191 typedef enum TRBCCode { 192 CC_INVALID = 0, 193 CC_SUCCESS, 194 CC_DATA_BUFFER_ERROR, 195 CC_BABBLE_DETECTED, 196 CC_USB_TRANSACTION_ERROR, 197 CC_TRB_ERROR, 198 CC_STALL_ERROR, 199 CC_RESOURCE_ERROR, 200 CC_BANDWIDTH_ERROR, 201 CC_NO_SLOTS_ERROR, 202 CC_INVALID_STREAM_TYPE_ERROR, 203 CC_SLOT_NOT_ENABLED_ERROR, 204 CC_EP_NOT_ENABLED_ERROR, 205 CC_SHORT_PACKET, 206 CC_RING_UNDERRUN, 207 CC_RING_OVERRUN, 208 CC_VF_ER_FULL, 209 CC_PARAMETER_ERROR, 210 CC_BANDWIDTH_OVERRUN, 211 CC_CONTEXT_STATE_ERROR, 212 CC_NO_PING_RESPONSE_ERROR, 213 CC_EVENT_RING_FULL_ERROR, 214 CC_INCOMPATIBLE_DEVICE_ERROR, 215 CC_MISSED_SERVICE_ERROR, 216 CC_COMMAND_RING_STOPPED, 217 CC_COMMAND_ABORTED, 218 CC_STOPPED, 219 CC_STOPPED_LENGTH_INVALID, 220 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 221 CC_ISOCH_BUFFER_OVERRUN = 31, 222 CC_EVENT_LOST_ERROR, 223 CC_UNDEFINED_ERROR, 224 CC_INVALID_STREAM_ID_ERROR, 225 CC_SECONDARY_BANDWIDTH_ERROR, 226 CC_SPLIT_TRANSACTION_ERROR 227 } TRBCCode; 228 229 #define TRB_C (1<<0) 230 #define TRB_TYPE_SHIFT 10 231 #define TRB_TYPE_MASK 0x3f 232 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 233 234 #define TRB_EV_ED (1<<2) 235 236 #define TRB_TR_ENT (1<<1) 237 #define TRB_TR_ISP (1<<2) 238 #define TRB_TR_NS (1<<3) 239 #define TRB_TR_CH (1<<4) 240 #define TRB_TR_IOC (1<<5) 241 #define TRB_TR_IDT (1<<6) 242 #define TRB_TR_TBC_SHIFT 7 243 #define TRB_TR_TBC_MASK 0x3 244 #define TRB_TR_BEI (1<<9) 245 #define TRB_TR_TLBPC_SHIFT 16 246 #define TRB_TR_TLBPC_MASK 0xf 247 #define TRB_TR_FRAMEID_SHIFT 20 248 #define TRB_TR_FRAMEID_MASK 0x7ff 249 #define TRB_TR_SIA (1<<31) 250 251 #define TRB_TR_DIR (1<<16) 252 253 #define TRB_CR_SLOTID_SHIFT 24 254 #define TRB_CR_SLOTID_MASK 0xff 255 #define TRB_CR_EPID_SHIFT 16 256 #define TRB_CR_EPID_MASK 0x1f 257 258 #define TRB_CR_BSR (1<<9) 259 #define TRB_CR_DC (1<<9) 260 261 #define TRB_LK_TC (1<<1) 262 263 #define TRB_INTR_SHIFT 22 264 #define TRB_INTR_MASK 0x3ff 265 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 266 267 #define EP_TYPE_MASK 0x7 268 #define EP_TYPE_SHIFT 3 269 270 #define EP_STATE_MASK 0x7 271 #define EP_DISABLED (0<<0) 272 #define EP_RUNNING (1<<0) 273 #define EP_HALTED (2<<0) 274 #define EP_STOPPED (3<<0) 275 #define EP_ERROR (4<<0) 276 277 #define SLOT_STATE_MASK 0x1f 278 #define SLOT_STATE_SHIFT 27 279 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 280 #define SLOT_ENABLED 0 281 #define SLOT_DEFAULT 1 282 #define SLOT_ADDRESSED 2 283 #define SLOT_CONFIGURED 3 284 285 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 286 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 287 288 typedef struct XHCIState XHCIState; 289 290 typedef enum EPType { 291 ET_INVALID = 0, 292 ET_ISO_OUT, 293 ET_BULK_OUT, 294 ET_INTR_OUT, 295 ET_CONTROL, 296 ET_ISO_IN, 297 ET_BULK_IN, 298 ET_INTR_IN, 299 } EPType; 300 301 typedef struct XHCIRing { 302 dma_addr_t base; 303 dma_addr_t dequeue; 304 bool ccs; 305 } XHCIRing; 306 307 typedef struct XHCIPort { 308 XHCIState *xhci; 309 uint32_t portsc; 310 uint32_t portnr; 311 USBPort *uport; 312 uint32_t speedmask; 313 char name[16]; 314 MemoryRegion mem; 315 } XHCIPort; 316 317 typedef struct XHCITransfer { 318 XHCIState *xhci; 319 USBPacket packet; 320 QEMUSGList sgl; 321 bool running_async; 322 bool running_retry; 323 bool cancelled; 324 bool complete; 325 bool int_req; 326 unsigned int iso_pkts; 327 unsigned int slotid; 328 unsigned int epid; 329 bool in_xfer; 330 bool iso_xfer; 331 332 unsigned int trb_count; 333 unsigned int trb_alloced; 334 XHCITRB *trbs; 335 336 TRBCCode status; 337 338 unsigned int pkts; 339 unsigned int pktsize; 340 unsigned int cur_pkt; 341 342 uint64_t mfindex_kick; 343 } XHCITransfer; 344 345 typedef struct XHCIEPContext { 346 XHCIState *xhci; 347 unsigned int slotid; 348 unsigned int epid; 349 350 XHCIRing ring; 351 unsigned int next_xfer; 352 unsigned int comp_xfer; 353 XHCITransfer transfers[TD_QUEUE]; 354 XHCITransfer *retry; 355 EPType type; 356 dma_addr_t pctx; 357 unsigned int max_psize; 358 uint32_t state; 359 360 /* iso xfer scheduling */ 361 unsigned int interval; 362 int64_t mfindex_last; 363 QEMUTimer *kick_timer; 364 } XHCIEPContext; 365 366 typedef struct XHCISlot { 367 bool enabled; 368 dma_addr_t ctx; 369 USBPort *uport; 370 unsigned int devaddr; 371 XHCIEPContext * eps[31]; 372 } XHCISlot; 373 374 typedef struct XHCIEvent { 375 TRBType type; 376 TRBCCode ccode; 377 uint64_t ptr; 378 uint32_t length; 379 uint32_t flags; 380 uint8_t slotid; 381 uint8_t epid; 382 } XHCIEvent; 383 384 typedef struct XHCIInterrupter { 385 uint32_t iman; 386 uint32_t imod; 387 uint32_t erstsz; 388 uint32_t erstba_low; 389 uint32_t erstba_high; 390 uint32_t erdp_low; 391 uint32_t erdp_high; 392 393 bool msix_used, er_pcs, er_full; 394 395 dma_addr_t er_start; 396 uint32_t er_size; 397 unsigned int er_ep_idx; 398 399 XHCIEvent ev_buffer[EV_QUEUE]; 400 unsigned int ev_buffer_put; 401 unsigned int ev_buffer_get; 402 403 } XHCIInterrupter; 404 405 struct XHCIState { 406 PCIDevice pci_dev; 407 USBBus bus; 408 qemu_irq irq; 409 MemoryRegion mem; 410 MemoryRegion mem_cap; 411 MemoryRegion mem_oper; 412 MemoryRegion mem_runtime; 413 MemoryRegion mem_doorbell; 414 const char *name; 415 unsigned int devaddr; 416 417 /* properties */ 418 uint32_t numports_2; 419 uint32_t numports_3; 420 uint32_t numintrs; 421 uint32_t numslots; 422 uint32_t flags; 423 424 /* Operational Registers */ 425 uint32_t usbcmd; 426 uint32_t usbsts; 427 uint32_t dnctrl; 428 uint32_t crcr_low; 429 uint32_t crcr_high; 430 uint32_t dcbaap_low; 431 uint32_t dcbaap_high; 432 uint32_t config; 433 434 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 435 XHCIPort ports[MAXPORTS]; 436 XHCISlot slots[MAXSLOTS]; 437 uint32_t numports; 438 439 /* Runtime Registers */ 440 int64_t mfindex_start; 441 QEMUTimer *mfwrap_timer; 442 XHCIInterrupter intr[MAXINTRS]; 443 444 XHCIRing cmd_ring; 445 }; 446 447 typedef struct XHCIEvRingSeg { 448 uint32_t addr_low; 449 uint32_t addr_high; 450 uint32_t size; 451 uint32_t rsvd; 452 } XHCIEvRingSeg; 453 454 enum xhci_flags { 455 XHCI_FLAG_USE_MSI = 1, 456 XHCI_FLAG_USE_MSI_X, 457 }; 458 459 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 460 unsigned int epid); 461 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 462 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 463 464 static const char *TRBType_names[] = { 465 [TRB_RESERVED] = "TRB_RESERVED", 466 [TR_NORMAL] = "TR_NORMAL", 467 [TR_SETUP] = "TR_SETUP", 468 [TR_DATA] = "TR_DATA", 469 [TR_STATUS] = "TR_STATUS", 470 [TR_ISOCH] = "TR_ISOCH", 471 [TR_LINK] = "TR_LINK", 472 [TR_EVDATA] = "TR_EVDATA", 473 [TR_NOOP] = "TR_NOOP", 474 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 475 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 476 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 477 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 478 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 479 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 480 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 481 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 482 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 483 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 484 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 485 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 486 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 487 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 488 [CR_NOOP] = "CR_NOOP", 489 [ER_TRANSFER] = "ER_TRANSFER", 490 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 491 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 492 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 493 [ER_DOORBELL] = "ER_DOORBELL", 494 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 495 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 496 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 497 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 498 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 499 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 500 }; 501 502 static const char *TRBCCode_names[] = { 503 [CC_INVALID] = "CC_INVALID", 504 [CC_SUCCESS] = "CC_SUCCESS", 505 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 506 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 507 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 508 [CC_TRB_ERROR] = "CC_TRB_ERROR", 509 [CC_STALL_ERROR] = "CC_STALL_ERROR", 510 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 511 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 512 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 513 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 514 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 515 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 516 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 517 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 518 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 519 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 520 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 521 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 522 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 523 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 524 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 525 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 526 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 527 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 528 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 529 [CC_STOPPED] = "CC_STOPPED", 530 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 531 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 532 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 533 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 534 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 535 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 536 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 537 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 538 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 539 }; 540 541 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 542 { 543 if (index >= llen || list[index] == NULL) { 544 return "???"; 545 } 546 return list[index]; 547 } 548 549 static const char *trb_name(XHCITRB *trb) 550 { 551 return lookup_name(TRB_TYPE(*trb), TRBType_names, 552 ARRAY_SIZE(TRBType_names)); 553 } 554 555 static const char *event_name(XHCIEvent *event) 556 { 557 return lookup_name(event->ccode, TRBCCode_names, 558 ARRAY_SIZE(TRBCCode_names)); 559 } 560 561 static uint64_t xhci_mfindex_get(XHCIState *xhci) 562 { 563 int64_t now = qemu_get_clock_ns(vm_clock); 564 return (now - xhci->mfindex_start) / 125000; 565 } 566 567 static void xhci_mfwrap_update(XHCIState *xhci) 568 { 569 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 570 uint32_t mfindex, left; 571 int64_t now; 572 573 if ((xhci->usbcmd & bits) == bits) { 574 now = qemu_get_clock_ns(vm_clock); 575 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 576 left = 0x4000 - mfindex; 577 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 578 } else { 579 qemu_del_timer(xhci->mfwrap_timer); 580 } 581 } 582 583 static void xhci_mfwrap_timer(void *opaque) 584 { 585 XHCIState *xhci = opaque; 586 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 587 588 xhci_event(xhci, &wrap, 0); 589 xhci_mfwrap_update(xhci); 590 } 591 592 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 593 { 594 if (sizeof(dma_addr_t) == 4) { 595 return low; 596 } else { 597 return low | (((dma_addr_t)high << 16) << 16); 598 } 599 } 600 601 static inline dma_addr_t xhci_mask64(uint64_t addr) 602 { 603 if (sizeof(dma_addr_t) == 4) { 604 return addr & 0xffffffff; 605 } else { 606 return addr; 607 } 608 } 609 610 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 611 { 612 int index; 613 614 if (!uport->dev) { 615 return NULL; 616 } 617 switch (uport->dev->speed) { 618 case USB_SPEED_LOW: 619 case USB_SPEED_FULL: 620 case USB_SPEED_HIGH: 621 index = uport->index; 622 break; 623 case USB_SPEED_SUPER: 624 index = uport->index + xhci->numports_2; 625 break; 626 default: 627 return NULL; 628 } 629 return &xhci->ports[index]; 630 } 631 632 static void xhci_intx_update(XHCIState *xhci) 633 { 634 int level = 0; 635 636 if (msix_enabled(&xhci->pci_dev) || 637 msi_enabled(&xhci->pci_dev)) { 638 return; 639 } 640 641 if (xhci->intr[0].iman & IMAN_IP && 642 xhci->intr[0].iman & IMAN_IE && 643 xhci->usbcmd & USBCMD_INTE) { 644 level = 1; 645 } 646 647 trace_usb_xhci_irq_intx(level); 648 qemu_set_irq(xhci->irq, level); 649 } 650 651 static void xhci_msix_update(XHCIState *xhci, int v) 652 { 653 bool enabled; 654 655 if (!msix_enabled(&xhci->pci_dev)) { 656 return; 657 } 658 659 enabled = xhci->intr[v].iman & IMAN_IE; 660 if (enabled == xhci->intr[v].msix_used) { 661 return; 662 } 663 664 if (enabled) { 665 trace_usb_xhci_irq_msix_use(v); 666 msix_vector_use(&xhci->pci_dev, v); 667 xhci->intr[v].msix_used = true; 668 } else { 669 trace_usb_xhci_irq_msix_unuse(v); 670 msix_vector_unuse(&xhci->pci_dev, v); 671 xhci->intr[v].msix_used = false; 672 } 673 } 674 675 static void xhci_intr_raise(XHCIState *xhci, int v) 676 { 677 xhci->intr[v].erdp_low |= ERDP_EHB; 678 xhci->intr[v].iman |= IMAN_IP; 679 xhci->usbsts |= USBSTS_EINT; 680 681 if (!(xhci->intr[v].iman & IMAN_IE)) { 682 return; 683 } 684 685 if (!(xhci->usbcmd & USBCMD_INTE)) { 686 return; 687 } 688 689 if (msix_enabled(&xhci->pci_dev)) { 690 trace_usb_xhci_irq_msix(v); 691 msix_notify(&xhci->pci_dev, v); 692 return; 693 } 694 695 if (msi_enabled(&xhci->pci_dev)) { 696 trace_usb_xhci_irq_msi(v); 697 msi_notify(&xhci->pci_dev, v); 698 return; 699 } 700 701 if (v == 0) { 702 trace_usb_xhci_irq_intx(1); 703 qemu_set_irq(xhci->irq, 1); 704 } 705 } 706 707 static inline int xhci_running(XHCIState *xhci) 708 { 709 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 710 } 711 712 static void xhci_die(XHCIState *xhci) 713 { 714 xhci->usbsts |= USBSTS_HCE; 715 fprintf(stderr, "xhci: asserted controller error\n"); 716 } 717 718 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 719 { 720 XHCIInterrupter *intr = &xhci->intr[v]; 721 XHCITRB ev_trb; 722 dma_addr_t addr; 723 724 ev_trb.parameter = cpu_to_le64(event->ptr); 725 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 726 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 727 event->flags | (event->type << TRB_TYPE_SHIFT); 728 if (intr->er_pcs) { 729 ev_trb.control |= TRB_C; 730 } 731 ev_trb.control = cpu_to_le32(ev_trb.control); 732 733 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 734 event_name(event), ev_trb.parameter, 735 ev_trb.status, ev_trb.control); 736 737 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 738 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 739 740 intr->er_ep_idx++; 741 if (intr->er_ep_idx >= intr->er_size) { 742 intr->er_ep_idx = 0; 743 intr->er_pcs = !intr->er_pcs; 744 } 745 } 746 747 static void xhci_events_update(XHCIState *xhci, int v) 748 { 749 XHCIInterrupter *intr = &xhci->intr[v]; 750 dma_addr_t erdp; 751 unsigned int dp_idx; 752 bool do_irq = 0; 753 754 if (xhci->usbsts & USBSTS_HCH) { 755 return; 756 } 757 758 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 759 if (erdp < intr->er_start || 760 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 761 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 762 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 763 v, intr->er_start, intr->er_size); 764 xhci_die(xhci); 765 return; 766 } 767 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 768 assert(dp_idx < intr->er_size); 769 770 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 771 * deadlocks when the ER is full. Hack it by holding off events until 772 * the driver decides to free at least half of the ring */ 773 if (intr->er_full) { 774 int er_free = dp_idx - intr->er_ep_idx; 775 if (er_free <= 0) { 776 er_free += intr->er_size; 777 } 778 if (er_free < (intr->er_size/2)) { 779 DPRINTF("xhci_events_update(): event ring still " 780 "more than half full (hack)\n"); 781 return; 782 } 783 } 784 785 while (intr->ev_buffer_put != intr->ev_buffer_get) { 786 assert(intr->er_full); 787 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 788 DPRINTF("xhci_events_update(): event ring full again\n"); 789 #ifndef ER_FULL_HACK 790 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 791 xhci_write_event(xhci, &full, v); 792 #endif 793 do_irq = 1; 794 break; 795 } 796 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 797 xhci_write_event(xhci, event, v); 798 intr->ev_buffer_get++; 799 do_irq = 1; 800 if (intr->ev_buffer_get == EV_QUEUE) { 801 intr->ev_buffer_get = 0; 802 } 803 } 804 805 if (do_irq) { 806 xhci_intr_raise(xhci, v); 807 } 808 809 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 810 DPRINTF("xhci_events_update(): event ring no longer full\n"); 811 intr->er_full = 0; 812 } 813 } 814 815 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 816 { 817 XHCIInterrupter *intr; 818 dma_addr_t erdp; 819 unsigned int dp_idx; 820 821 if (v >= xhci->numintrs) { 822 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 823 return; 824 } 825 intr = &xhci->intr[v]; 826 827 if (intr->er_full) { 828 DPRINTF("xhci_event(): ER full, queueing\n"); 829 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 830 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 831 return; 832 } 833 intr->ev_buffer[intr->ev_buffer_put++] = *event; 834 if (intr->ev_buffer_put == EV_QUEUE) { 835 intr->ev_buffer_put = 0; 836 } 837 return; 838 } 839 840 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 841 if (erdp < intr->er_start || 842 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 843 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 844 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 845 v, intr->er_start, intr->er_size); 846 xhci_die(xhci); 847 return; 848 } 849 850 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 851 assert(dp_idx < intr->er_size); 852 853 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 854 DPRINTF("xhci_event(): ER full, queueing\n"); 855 #ifndef ER_FULL_HACK 856 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 857 xhci_write_event(xhci, &full); 858 #endif 859 intr->er_full = 1; 860 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 861 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 862 return; 863 } 864 intr->ev_buffer[intr->ev_buffer_put++] = *event; 865 if (intr->ev_buffer_put == EV_QUEUE) { 866 intr->ev_buffer_put = 0; 867 } 868 } else { 869 xhci_write_event(xhci, event, v); 870 } 871 872 xhci_intr_raise(xhci, v); 873 } 874 875 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 876 dma_addr_t base) 877 { 878 ring->base = base; 879 ring->dequeue = base; 880 ring->ccs = 1; 881 } 882 883 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 884 dma_addr_t *addr) 885 { 886 while (1) { 887 TRBType type; 888 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 889 trb->addr = ring->dequeue; 890 trb->ccs = ring->ccs; 891 le64_to_cpus(&trb->parameter); 892 le32_to_cpus(&trb->status); 893 le32_to_cpus(&trb->control); 894 895 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 896 trb->parameter, trb->status, trb->control); 897 898 if ((trb->control & TRB_C) != ring->ccs) { 899 return 0; 900 } 901 902 type = TRB_TYPE(*trb); 903 904 if (type != TR_LINK) { 905 if (addr) { 906 *addr = ring->dequeue; 907 } 908 ring->dequeue += TRB_SIZE; 909 return type; 910 } else { 911 ring->dequeue = xhci_mask64(trb->parameter); 912 if (trb->control & TRB_LK_TC) { 913 ring->ccs = !ring->ccs; 914 } 915 } 916 } 917 } 918 919 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 920 { 921 XHCITRB trb; 922 int length = 0; 923 dma_addr_t dequeue = ring->dequeue; 924 bool ccs = ring->ccs; 925 /* hack to bundle together the two/three TDs that make a setup transfer */ 926 bool control_td_set = 0; 927 928 while (1) { 929 TRBType type; 930 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 931 le64_to_cpus(&trb.parameter); 932 le32_to_cpus(&trb.status); 933 le32_to_cpus(&trb.control); 934 935 if ((trb.control & TRB_C) != ccs) { 936 return -length; 937 } 938 939 type = TRB_TYPE(trb); 940 941 if (type == TR_LINK) { 942 dequeue = xhci_mask64(trb.parameter); 943 if (trb.control & TRB_LK_TC) { 944 ccs = !ccs; 945 } 946 continue; 947 } 948 949 length += 1; 950 dequeue += TRB_SIZE; 951 952 if (type == TR_SETUP) { 953 control_td_set = 1; 954 } else if (type == TR_STATUS) { 955 control_td_set = 0; 956 } 957 958 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 959 return length; 960 } 961 } 962 } 963 964 static void xhci_er_reset(XHCIState *xhci, int v) 965 { 966 XHCIInterrupter *intr = &xhci->intr[v]; 967 XHCIEvRingSeg seg; 968 969 if (intr->erstsz == 0) { 970 /* disabled */ 971 intr->er_start = 0; 972 intr->er_size = 0; 973 return; 974 } 975 /* cache the (sole) event ring segment location */ 976 if (intr->erstsz != 1) { 977 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 978 xhci_die(xhci); 979 return; 980 } 981 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 982 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 983 le32_to_cpus(&seg.addr_low); 984 le32_to_cpus(&seg.addr_high); 985 le32_to_cpus(&seg.size); 986 if (seg.size < 16 || seg.size > 4096) { 987 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 988 xhci_die(xhci); 989 return; 990 } 991 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 992 intr->er_size = seg.size; 993 994 intr->er_ep_idx = 0; 995 intr->er_pcs = 1; 996 intr->er_full = 0; 997 998 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 999 v, intr->er_start, intr->er_size); 1000 } 1001 1002 static void xhci_run(XHCIState *xhci) 1003 { 1004 trace_usb_xhci_run(); 1005 xhci->usbsts &= ~USBSTS_HCH; 1006 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1007 } 1008 1009 static void xhci_stop(XHCIState *xhci) 1010 { 1011 trace_usb_xhci_stop(); 1012 xhci->usbsts |= USBSTS_HCH; 1013 xhci->crcr_low &= ~CRCR_CRR; 1014 } 1015 1016 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1017 uint32_t state) 1018 { 1019 uint32_t ctx[5]; 1020 1021 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1022 ctx[0] &= ~EP_STATE_MASK; 1023 ctx[0] |= state; 1024 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1025 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1026 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1027 epctx->pctx, state, ctx[3], ctx[2]); 1028 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx)); 1029 epctx->state = state; 1030 } 1031 1032 static void xhci_ep_kick_timer(void *opaque) 1033 { 1034 XHCIEPContext *epctx = opaque; 1035 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1036 } 1037 1038 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1039 unsigned int epid, dma_addr_t pctx, 1040 uint32_t *ctx) 1041 { 1042 XHCISlot *slot; 1043 XHCIEPContext *epctx; 1044 dma_addr_t dequeue; 1045 int i; 1046 1047 trace_usb_xhci_ep_enable(slotid, epid); 1048 assert(slotid >= 1 && slotid <= xhci->numslots); 1049 assert(epid >= 1 && epid <= 31); 1050 1051 slot = &xhci->slots[slotid-1]; 1052 if (slot->eps[epid-1]) { 1053 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); 1054 return CC_TRB_ERROR; 1055 } 1056 1057 epctx = g_malloc(sizeof(XHCIEPContext)); 1058 memset(epctx, 0, sizeof(XHCIEPContext)); 1059 epctx->xhci = xhci; 1060 epctx->slotid = slotid; 1061 epctx->epid = epid; 1062 1063 slot->eps[epid-1] = epctx; 1064 1065 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1066 xhci_ring_init(xhci, &epctx->ring, dequeue); 1067 epctx->ring.ccs = ctx[2] & 1; 1068 1069 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1070 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1071 epctx->pctx = pctx; 1072 epctx->max_psize = ctx[1]>>16; 1073 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1074 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1075 epid/2, epid%2, epctx->max_psize); 1076 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1077 usb_packet_init(&epctx->transfers[i].packet); 1078 } 1079 1080 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1081 epctx->mfindex_last = 0; 1082 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1083 1084 epctx->state = EP_RUNNING; 1085 ctx[0] &= ~EP_STATE_MASK; 1086 ctx[0] |= EP_RUNNING; 1087 1088 return CC_SUCCESS; 1089 } 1090 1091 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1092 { 1093 int killed = 0; 1094 1095 if (t->running_async) { 1096 usb_cancel_packet(&t->packet); 1097 t->running_async = 0; 1098 t->cancelled = 1; 1099 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1100 killed = 1; 1101 } 1102 if (t->running_retry) { 1103 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1104 if (epctx) { 1105 epctx->retry = NULL; 1106 qemu_del_timer(epctx->kick_timer); 1107 } 1108 t->running_retry = 0; 1109 } 1110 if (t->trbs) { 1111 g_free(t->trbs); 1112 } 1113 1114 t->trbs = NULL; 1115 t->trb_count = t->trb_alloced = 0; 1116 1117 return killed; 1118 } 1119 1120 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1121 unsigned int epid) 1122 { 1123 XHCISlot *slot; 1124 XHCIEPContext *epctx; 1125 int i, xferi, killed = 0; 1126 assert(slotid >= 1 && slotid <= xhci->numslots); 1127 assert(epid >= 1 && epid <= 31); 1128 1129 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1130 1131 slot = &xhci->slots[slotid-1]; 1132 1133 if (!slot->eps[epid-1]) { 1134 return 0; 1135 } 1136 1137 epctx = slot->eps[epid-1]; 1138 1139 xferi = epctx->next_xfer; 1140 for (i = 0; i < TD_QUEUE; i++) { 1141 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1142 xferi = (xferi + 1) % TD_QUEUE; 1143 } 1144 return killed; 1145 } 1146 1147 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1148 unsigned int epid) 1149 { 1150 XHCISlot *slot; 1151 XHCIEPContext *epctx; 1152 1153 trace_usb_xhci_ep_disable(slotid, epid); 1154 assert(slotid >= 1 && slotid <= xhci->numslots); 1155 assert(epid >= 1 && epid <= 31); 1156 1157 slot = &xhci->slots[slotid-1]; 1158 1159 if (!slot->eps[epid-1]) { 1160 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1161 return CC_SUCCESS; 1162 } 1163 1164 xhci_ep_nuke_xfers(xhci, slotid, epid); 1165 1166 epctx = slot->eps[epid-1]; 1167 1168 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1169 1170 qemu_free_timer(epctx->kick_timer); 1171 g_free(epctx); 1172 slot->eps[epid-1] = NULL; 1173 1174 return CC_SUCCESS; 1175 } 1176 1177 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1178 unsigned int epid) 1179 { 1180 XHCISlot *slot; 1181 XHCIEPContext *epctx; 1182 1183 trace_usb_xhci_ep_stop(slotid, epid); 1184 assert(slotid >= 1 && slotid <= xhci->numslots); 1185 1186 if (epid < 1 || epid > 31) { 1187 fprintf(stderr, "xhci: bad ep %d\n", epid); 1188 return CC_TRB_ERROR; 1189 } 1190 1191 slot = &xhci->slots[slotid-1]; 1192 1193 if (!slot->eps[epid-1]) { 1194 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1195 return CC_EP_NOT_ENABLED_ERROR; 1196 } 1197 1198 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1199 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1200 "data might be lost\n"); 1201 } 1202 1203 epctx = slot->eps[epid-1]; 1204 1205 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1206 1207 return CC_SUCCESS; 1208 } 1209 1210 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1211 unsigned int epid) 1212 { 1213 XHCISlot *slot; 1214 XHCIEPContext *epctx; 1215 USBDevice *dev; 1216 1217 trace_usb_xhci_ep_reset(slotid, epid); 1218 assert(slotid >= 1 && slotid <= xhci->numslots); 1219 1220 if (epid < 1 || epid > 31) { 1221 fprintf(stderr, "xhci: bad ep %d\n", epid); 1222 return CC_TRB_ERROR; 1223 } 1224 1225 slot = &xhci->slots[slotid-1]; 1226 1227 if (!slot->eps[epid-1]) { 1228 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1229 return CC_EP_NOT_ENABLED_ERROR; 1230 } 1231 1232 epctx = slot->eps[epid-1]; 1233 1234 if (epctx->state != EP_HALTED) { 1235 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1236 epid, epctx->state); 1237 return CC_CONTEXT_STATE_ERROR; 1238 } 1239 1240 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1241 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1242 "data might be lost\n"); 1243 } 1244 1245 uint8_t ep = epid>>1; 1246 1247 if (epid & 1) { 1248 ep |= 0x80; 1249 } 1250 1251 dev = xhci->slots[slotid-1].uport->dev; 1252 if (!dev) { 1253 return CC_USB_TRANSACTION_ERROR; 1254 } 1255 1256 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1257 1258 return CC_SUCCESS; 1259 } 1260 1261 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1262 unsigned int epid, uint64_t pdequeue) 1263 { 1264 XHCISlot *slot; 1265 XHCIEPContext *epctx; 1266 dma_addr_t dequeue; 1267 1268 assert(slotid >= 1 && slotid <= xhci->numslots); 1269 1270 if (epid < 1 || epid > 31) { 1271 fprintf(stderr, "xhci: bad ep %d\n", epid); 1272 return CC_TRB_ERROR; 1273 } 1274 1275 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1276 dequeue = xhci_mask64(pdequeue); 1277 1278 slot = &xhci->slots[slotid-1]; 1279 1280 if (!slot->eps[epid-1]) { 1281 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1282 return CC_EP_NOT_ENABLED_ERROR; 1283 } 1284 1285 epctx = slot->eps[epid-1]; 1286 1287 1288 if (epctx->state != EP_STOPPED) { 1289 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1290 return CC_CONTEXT_STATE_ERROR; 1291 } 1292 1293 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1294 epctx->ring.ccs = dequeue & 1; 1295 1296 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1297 1298 return CC_SUCCESS; 1299 } 1300 1301 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1302 { 1303 XHCIState *xhci = xfer->xhci; 1304 int i; 1305 1306 xfer->int_req = false; 1307 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1308 for (i = 0; i < xfer->trb_count; i++) { 1309 XHCITRB *trb = &xfer->trbs[i]; 1310 dma_addr_t addr; 1311 unsigned int chunk = 0; 1312 1313 if (trb->control & TRB_TR_IOC) { 1314 xfer->int_req = true; 1315 } 1316 1317 switch (TRB_TYPE(*trb)) { 1318 case TR_DATA: 1319 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1320 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1321 goto err; 1322 } 1323 /* fallthrough */ 1324 case TR_NORMAL: 1325 case TR_ISOCH: 1326 addr = xhci_mask64(trb->parameter); 1327 chunk = trb->status & 0x1ffff; 1328 if (trb->control & TRB_TR_IDT) { 1329 if (chunk > 8 || in_xfer) { 1330 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1331 goto err; 1332 } 1333 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1334 } else { 1335 qemu_sglist_add(&xfer->sgl, addr, chunk); 1336 } 1337 break; 1338 } 1339 } 1340 1341 return 0; 1342 1343 err: 1344 qemu_sglist_destroy(&xfer->sgl); 1345 xhci_die(xhci); 1346 return -1; 1347 } 1348 1349 static void xhci_xfer_unmap(XHCITransfer *xfer) 1350 { 1351 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1352 qemu_sglist_destroy(&xfer->sgl); 1353 } 1354 1355 static void xhci_xfer_report(XHCITransfer *xfer) 1356 { 1357 uint32_t edtla = 0; 1358 unsigned int left; 1359 bool reported = 0; 1360 bool shortpkt = 0; 1361 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1362 XHCIState *xhci = xfer->xhci; 1363 int i; 1364 1365 left = xfer->packet.result < 0 ? 0 : xfer->packet.result; 1366 1367 for (i = 0; i < xfer->trb_count; i++) { 1368 XHCITRB *trb = &xfer->trbs[i]; 1369 unsigned int chunk = 0; 1370 1371 switch (TRB_TYPE(*trb)) { 1372 case TR_DATA: 1373 case TR_NORMAL: 1374 case TR_ISOCH: 1375 chunk = trb->status & 0x1ffff; 1376 if (chunk > left) { 1377 chunk = left; 1378 if (xfer->status == CC_SUCCESS) { 1379 shortpkt = 1; 1380 } 1381 } 1382 left -= chunk; 1383 edtla += chunk; 1384 break; 1385 case TR_STATUS: 1386 reported = 0; 1387 shortpkt = 0; 1388 break; 1389 } 1390 1391 if (!reported && ((trb->control & TRB_TR_IOC) || 1392 (shortpkt && (trb->control & TRB_TR_ISP)) || 1393 (xfer->status != CC_SUCCESS))) { 1394 event.slotid = xfer->slotid; 1395 event.epid = xfer->epid; 1396 event.length = (trb->status & 0x1ffff) - chunk; 1397 event.flags = 0; 1398 event.ptr = trb->addr; 1399 if (xfer->status == CC_SUCCESS) { 1400 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1401 } else { 1402 event.ccode = xfer->status; 1403 } 1404 if (TRB_TYPE(*trb) == TR_EVDATA) { 1405 event.ptr = trb->parameter; 1406 event.flags |= TRB_EV_ED; 1407 event.length = edtla & 0xffffff; 1408 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1409 edtla = 0; 1410 } 1411 xhci_event(xhci, &event, TRB_INTR(*trb)); 1412 reported = 1; 1413 if (xfer->status != CC_SUCCESS) { 1414 return; 1415 } 1416 } 1417 } 1418 } 1419 1420 static void xhci_stall_ep(XHCITransfer *xfer) 1421 { 1422 XHCIState *xhci = xfer->xhci; 1423 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1424 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1425 1426 epctx->ring.dequeue = xfer->trbs[0].addr; 1427 epctx->ring.ccs = xfer->trbs[0].ccs; 1428 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1429 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1430 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1431 } 1432 1433 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1434 XHCIEPContext *epctx); 1435 1436 static int xhci_setup_packet(XHCITransfer *xfer) 1437 { 1438 XHCIState *xhci = xfer->xhci; 1439 USBDevice *dev; 1440 USBEndpoint *ep; 1441 int dir; 1442 1443 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1444 1445 if (xfer->packet.ep) { 1446 ep = xfer->packet.ep; 1447 dev = ep->dev; 1448 } else { 1449 if (!xhci->slots[xfer->slotid-1].uport) { 1450 fprintf(stderr, "xhci: slot %d has no device\n", 1451 xfer->slotid); 1452 return -1; 1453 } 1454 dev = xhci->slots[xfer->slotid-1].uport->dev; 1455 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1456 } 1457 1458 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1459 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr, false, 1460 xfer->int_req); 1461 usb_packet_map(&xfer->packet, &xfer->sgl); 1462 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1463 xfer->packet.pid, dev->addr, ep->nr); 1464 return 0; 1465 } 1466 1467 static int xhci_complete_packet(XHCITransfer *xfer, int ret) 1468 { 1469 if (ret == USB_RET_ASYNC) { 1470 trace_usb_xhci_xfer_async(xfer); 1471 xfer->running_async = 1; 1472 xfer->running_retry = 0; 1473 xfer->complete = 0; 1474 xfer->cancelled = 0; 1475 return 0; 1476 } else if (ret == USB_RET_NAK) { 1477 trace_usb_xhci_xfer_nak(xfer); 1478 xfer->running_async = 0; 1479 xfer->running_retry = 1; 1480 xfer->complete = 0; 1481 xfer->cancelled = 0; 1482 return 0; 1483 } else { 1484 xfer->running_async = 0; 1485 xfer->running_retry = 0; 1486 xfer->complete = 1; 1487 xhci_xfer_unmap(xfer); 1488 } 1489 1490 if (ret >= 0) { 1491 trace_usb_xhci_xfer_success(xfer, ret); 1492 xfer->status = CC_SUCCESS; 1493 xhci_xfer_report(xfer); 1494 return 0; 1495 } 1496 1497 /* error */ 1498 trace_usb_xhci_xfer_error(xfer, ret); 1499 switch (ret) { 1500 case USB_RET_NODEV: 1501 xfer->status = CC_USB_TRANSACTION_ERROR; 1502 xhci_xfer_report(xfer); 1503 xhci_stall_ep(xfer); 1504 break; 1505 case USB_RET_STALL: 1506 xfer->status = CC_STALL_ERROR; 1507 xhci_xfer_report(xfer); 1508 xhci_stall_ep(xfer); 1509 break; 1510 default: 1511 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret); 1512 FIXME(); 1513 } 1514 return 0; 1515 } 1516 1517 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1518 { 1519 XHCITRB *trb_setup, *trb_status; 1520 uint8_t bmRequestType; 1521 int ret; 1522 1523 trb_setup = &xfer->trbs[0]; 1524 trb_status = &xfer->trbs[xfer->trb_count-1]; 1525 1526 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1527 1528 /* at most one Event Data TRB allowed after STATUS */ 1529 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1530 trb_status--; 1531 } 1532 1533 /* do some sanity checks */ 1534 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1535 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1536 TRB_TYPE(*trb_setup)); 1537 return -1; 1538 } 1539 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1540 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1541 TRB_TYPE(*trb_status)); 1542 return -1; 1543 } 1544 if (!(trb_setup->control & TRB_TR_IDT)) { 1545 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1546 return -1; 1547 } 1548 if ((trb_setup->status & 0x1ffff) != 8) { 1549 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1550 (trb_setup->status & 0x1ffff)); 1551 return -1; 1552 } 1553 1554 bmRequestType = trb_setup->parameter; 1555 1556 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1557 xfer->iso_xfer = false; 1558 1559 if (xhci_setup_packet(xfer) < 0) { 1560 return -1; 1561 } 1562 xfer->packet.parameter = trb_setup->parameter; 1563 1564 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1565 1566 xhci_complete_packet(xfer, ret); 1567 if (!xfer->running_async && !xfer->running_retry) { 1568 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1569 } 1570 return 0; 1571 } 1572 1573 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1574 XHCIEPContext *epctx, uint64_t mfindex) 1575 { 1576 if (xfer->trbs[0].control & TRB_TR_SIA) { 1577 uint64_t asap = ((mfindex + epctx->interval - 1) & 1578 ~(epctx->interval-1)); 1579 if (asap >= epctx->mfindex_last && 1580 asap <= epctx->mfindex_last + epctx->interval * 4) { 1581 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1582 } else { 1583 xfer->mfindex_kick = asap; 1584 } 1585 } else { 1586 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1587 & TRB_TR_FRAMEID_MASK; 1588 xfer->mfindex_kick |= mfindex & ~0x3fff; 1589 if (xfer->mfindex_kick < mfindex) { 1590 xfer->mfindex_kick += 0x4000; 1591 } 1592 } 1593 } 1594 1595 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1596 XHCIEPContext *epctx, uint64_t mfindex) 1597 { 1598 if (xfer->mfindex_kick > mfindex) { 1599 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1600 (xfer->mfindex_kick - mfindex) * 125000); 1601 xfer->running_retry = 1; 1602 } else { 1603 epctx->mfindex_last = xfer->mfindex_kick; 1604 qemu_del_timer(epctx->kick_timer); 1605 xfer->running_retry = 0; 1606 } 1607 } 1608 1609 1610 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1611 { 1612 uint64_t mfindex; 1613 int ret; 1614 1615 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1616 1617 xfer->in_xfer = epctx->type>>2; 1618 1619 switch(epctx->type) { 1620 case ET_INTR_OUT: 1621 case ET_INTR_IN: 1622 case ET_BULK_OUT: 1623 case ET_BULK_IN: 1624 xfer->pkts = 0; 1625 xfer->iso_xfer = false; 1626 break; 1627 case ET_ISO_OUT: 1628 case ET_ISO_IN: 1629 xfer->pkts = 1; 1630 xfer->iso_xfer = true; 1631 mfindex = xhci_mfindex_get(xhci); 1632 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1633 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1634 if (xfer->running_retry) { 1635 return -1; 1636 } 1637 break; 1638 default: 1639 fprintf(stderr, "xhci: unknown or unhandled EP " 1640 "(type %d, in %d, ep %02x)\n", 1641 epctx->type, xfer->in_xfer, xfer->epid); 1642 return -1; 1643 } 1644 1645 if (xhci_setup_packet(xfer) < 0) { 1646 return -1; 1647 } 1648 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1649 1650 xhci_complete_packet(xfer, ret); 1651 if (!xfer->running_async && !xfer->running_retry) { 1652 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1653 } 1654 return 0; 1655 } 1656 1657 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1658 { 1659 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1660 return xhci_submit(xhci, xfer, epctx); 1661 } 1662 1663 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1664 { 1665 XHCIEPContext *epctx; 1666 USBEndpoint *ep = NULL; 1667 uint64_t mfindex; 1668 int length; 1669 int i; 1670 1671 trace_usb_xhci_ep_kick(slotid, epid); 1672 assert(slotid >= 1 && slotid <= xhci->numslots); 1673 assert(epid >= 1 && epid <= 31); 1674 1675 if (!xhci->slots[slotid-1].enabled) { 1676 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1677 return; 1678 } 1679 epctx = xhci->slots[slotid-1].eps[epid-1]; 1680 if (!epctx) { 1681 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1682 epid, slotid); 1683 return; 1684 } 1685 1686 if (epctx->retry) { 1687 XHCITransfer *xfer = epctx->retry; 1688 int result; 1689 1690 trace_usb_xhci_xfer_retry(xfer); 1691 assert(xfer->running_retry); 1692 if (xfer->iso_xfer) { 1693 /* retry delayed iso transfer */ 1694 mfindex = xhci_mfindex_get(xhci); 1695 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1696 if (xfer->running_retry) { 1697 return; 1698 } 1699 if (xhci_setup_packet(xfer) < 0) { 1700 return; 1701 } 1702 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1703 assert(result != USB_RET_NAK); 1704 xhci_complete_packet(xfer, result); 1705 } else { 1706 /* retry nak'ed transfer */ 1707 if (xhci_setup_packet(xfer) < 0) { 1708 return; 1709 } 1710 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1711 if (result == USB_RET_NAK) { 1712 return; 1713 } 1714 xhci_complete_packet(xfer, result); 1715 } 1716 assert(!xfer->running_retry); 1717 epctx->retry = NULL; 1718 } 1719 1720 if (epctx->state == EP_HALTED) { 1721 DPRINTF("xhci: ep halted, not running schedule\n"); 1722 return; 1723 } 1724 1725 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1726 1727 while (1) { 1728 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1729 if (xfer->running_async || xfer->running_retry) { 1730 break; 1731 } 1732 length = xhci_ring_chain_length(xhci, &epctx->ring); 1733 if (length < 0) { 1734 break; 1735 } else if (length == 0) { 1736 break; 1737 } 1738 if (xfer->trbs && xfer->trb_alloced < length) { 1739 xfer->trb_count = 0; 1740 xfer->trb_alloced = 0; 1741 g_free(xfer->trbs); 1742 xfer->trbs = NULL; 1743 } 1744 if (!xfer->trbs) { 1745 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1746 xfer->trb_alloced = length; 1747 } 1748 xfer->trb_count = length; 1749 1750 for (i = 0; i < length; i++) { 1751 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1752 } 1753 xfer->xhci = xhci; 1754 xfer->epid = epid; 1755 xfer->slotid = slotid; 1756 1757 if (epid == 1) { 1758 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1759 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1760 ep = xfer->packet.ep; 1761 } else { 1762 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1763 } 1764 } else { 1765 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1766 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1767 ep = xfer->packet.ep; 1768 } else { 1769 if (!xfer->iso_xfer) { 1770 fprintf(stderr, "xhci: error firing data transfer\n"); 1771 } 1772 } 1773 } 1774 1775 if (epctx->state == EP_HALTED) { 1776 break; 1777 } 1778 if (xfer->running_retry) { 1779 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1780 epctx->retry = xfer; 1781 break; 1782 } 1783 } 1784 if (ep) { 1785 usb_device_flush_ep_queue(ep->dev, ep); 1786 } 1787 } 1788 1789 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1790 { 1791 trace_usb_xhci_slot_enable(slotid); 1792 assert(slotid >= 1 && slotid <= xhci->numslots); 1793 xhci->slots[slotid-1].enabled = 1; 1794 xhci->slots[slotid-1].uport = NULL; 1795 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1796 1797 return CC_SUCCESS; 1798 } 1799 1800 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1801 { 1802 int i; 1803 1804 trace_usb_xhci_slot_disable(slotid); 1805 assert(slotid >= 1 && slotid <= xhci->numslots); 1806 1807 for (i = 1; i <= 31; i++) { 1808 if (xhci->slots[slotid-1].eps[i-1]) { 1809 xhci_disable_ep(xhci, slotid, i); 1810 } 1811 } 1812 1813 xhci->slots[slotid-1].enabled = 0; 1814 return CC_SUCCESS; 1815 } 1816 1817 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1818 { 1819 USBPort *uport; 1820 char path[32]; 1821 int i, pos, port; 1822 1823 port = (slot_ctx[1]>>16) & 0xFF; 1824 port = xhci->ports[port-1].uport->index+1; 1825 pos = snprintf(path, sizeof(path), "%d", port); 1826 for (i = 0; i < 5; i++) { 1827 port = (slot_ctx[0] >> 4*i) & 0x0f; 1828 if (!port) { 1829 break; 1830 } 1831 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1832 } 1833 1834 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1835 if (strcmp(uport->path, path) == 0) { 1836 return uport; 1837 } 1838 } 1839 return NULL; 1840 } 1841 1842 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1843 uint64_t pictx, bool bsr) 1844 { 1845 XHCISlot *slot; 1846 USBPort *uport; 1847 USBDevice *dev; 1848 dma_addr_t ictx, octx, dcbaap; 1849 uint64_t poctx; 1850 uint32_t ictl_ctx[2]; 1851 uint32_t slot_ctx[4]; 1852 uint32_t ep0_ctx[5]; 1853 int i; 1854 TRBCCode res; 1855 1856 trace_usb_xhci_slot_address(slotid); 1857 assert(slotid >= 1 && slotid <= xhci->numslots); 1858 1859 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1860 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx)); 1861 ictx = xhci_mask64(pictx); 1862 octx = xhci_mask64(le64_to_cpu(poctx)); 1863 1864 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1865 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1866 1867 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1868 1869 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1870 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1871 ictl_ctx[0], ictl_ctx[1]); 1872 return CC_TRB_ERROR; 1873 } 1874 1875 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx)); 1876 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1877 1878 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1879 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1880 1881 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1882 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1883 1884 uport = xhci_lookup_uport(xhci, slot_ctx); 1885 if (uport == NULL) { 1886 fprintf(stderr, "xhci: port not found\n"); 1887 return CC_TRB_ERROR; 1888 } 1889 1890 dev = uport->dev; 1891 if (!dev) { 1892 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1893 return CC_USB_TRANSACTION_ERROR; 1894 } 1895 1896 for (i = 0; i < xhci->numslots; i++) { 1897 if (xhci->slots[i].uport == uport) { 1898 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1899 uport->path, i+1); 1900 return CC_TRB_ERROR; 1901 } 1902 } 1903 1904 slot = &xhci->slots[slotid-1]; 1905 slot->uport = uport; 1906 slot->ctx = octx; 1907 1908 if (bsr) { 1909 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1910 } else { 1911 slot->devaddr = xhci->devaddr++; 1912 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1913 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1914 usb_device_handle_control(dev, NULL, 1915 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1916 slot->devaddr, 0, 0, NULL); 1917 } 1918 1919 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1920 1921 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1922 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1923 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1924 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1925 1926 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1927 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1928 1929 return res; 1930 } 1931 1932 1933 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1934 uint64_t pictx, bool dc) 1935 { 1936 dma_addr_t ictx, octx; 1937 uint32_t ictl_ctx[2]; 1938 uint32_t slot_ctx[4]; 1939 uint32_t islot_ctx[4]; 1940 uint32_t ep_ctx[5]; 1941 int i; 1942 TRBCCode res; 1943 1944 trace_usb_xhci_slot_configure(slotid); 1945 assert(slotid >= 1 && slotid <= xhci->numslots); 1946 1947 ictx = xhci_mask64(pictx); 1948 octx = xhci->slots[slotid-1].ctx; 1949 1950 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1951 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1952 1953 if (dc) { 1954 for (i = 2; i <= 31; i++) { 1955 if (xhci->slots[slotid-1].eps[i-1]) { 1956 xhci_disable_ep(xhci, slotid, i); 1957 } 1958 } 1959 1960 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1961 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 1962 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 1963 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1964 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1965 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1966 1967 return CC_SUCCESS; 1968 } 1969 1970 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 1971 1972 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 1973 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1974 ictl_ctx[0], ictl_ctx[1]); 1975 return CC_TRB_ERROR; 1976 } 1977 1978 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 1979 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 1980 1981 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 1982 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 1983 return CC_CONTEXT_STATE_ERROR; 1984 } 1985 1986 for (i = 2; i <= 31; i++) { 1987 if (ictl_ctx[0] & (1<<i)) { 1988 xhci_disable_ep(xhci, slotid, i); 1989 } 1990 if (ictl_ctx[1] & (1<<i)) { 1991 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx, 1992 sizeof(ep_ctx)); 1993 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 1994 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 1995 ep_ctx[3], ep_ctx[4]); 1996 xhci_disable_ep(xhci, slotid, i); 1997 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 1998 if (res != CC_SUCCESS) { 1999 return res; 2000 } 2001 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2002 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2003 ep_ctx[3], ep_ctx[4]); 2004 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2005 } 2006 } 2007 2008 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2009 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2010 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2011 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2012 SLOT_CONTEXT_ENTRIES_SHIFT); 2013 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2014 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2015 2016 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2017 2018 return CC_SUCCESS; 2019 } 2020 2021 2022 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2023 uint64_t pictx) 2024 { 2025 dma_addr_t ictx, octx; 2026 uint32_t ictl_ctx[2]; 2027 uint32_t iep0_ctx[5]; 2028 uint32_t ep0_ctx[5]; 2029 uint32_t islot_ctx[4]; 2030 uint32_t slot_ctx[4]; 2031 2032 trace_usb_xhci_slot_evaluate(slotid); 2033 assert(slotid >= 1 && slotid <= xhci->numslots); 2034 2035 ictx = xhci_mask64(pictx); 2036 octx = xhci->slots[slotid-1].ctx; 2037 2038 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2039 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2040 2041 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx)); 2042 2043 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2044 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2045 ictl_ctx[0], ictl_ctx[1]); 2046 return CC_TRB_ERROR; 2047 } 2048 2049 if (ictl_ctx[1] & 0x1) { 2050 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx)); 2051 2052 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2053 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2054 2055 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2056 2057 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2058 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2059 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2060 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2061 2062 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2063 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2064 2065 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2066 } 2067 2068 if (ictl_ctx[1] & 0x2) { 2069 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2070 2071 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2072 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2073 iep0_ctx[3], iep0_ctx[4]); 2074 2075 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2076 2077 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2078 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2079 2080 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2081 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2082 2083 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2084 } 2085 2086 return CC_SUCCESS; 2087 } 2088 2089 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2090 { 2091 uint32_t slot_ctx[4]; 2092 dma_addr_t octx; 2093 int i; 2094 2095 trace_usb_xhci_slot_reset(slotid); 2096 assert(slotid >= 1 && slotid <= xhci->numslots); 2097 2098 octx = xhci->slots[slotid-1].ctx; 2099 2100 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2101 2102 for (i = 2; i <= 31; i++) { 2103 if (xhci->slots[slotid-1].eps[i-1]) { 2104 xhci_disable_ep(xhci, slotid, i); 2105 } 2106 } 2107 2108 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2109 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2110 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2111 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2112 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2113 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx)); 2114 2115 return CC_SUCCESS; 2116 } 2117 2118 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2119 { 2120 unsigned int slotid; 2121 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2122 if (slotid < 1 || slotid > xhci->numslots) { 2123 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2124 event->ccode = CC_TRB_ERROR; 2125 return 0; 2126 } else if (!xhci->slots[slotid-1].enabled) { 2127 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2128 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2129 return 0; 2130 } 2131 return slotid; 2132 } 2133 2134 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2135 { 2136 dma_addr_t ctx; 2137 uint8_t bw_ctx[xhci->numports+1]; 2138 2139 DPRINTF("xhci_get_port_bandwidth()\n"); 2140 2141 ctx = xhci_mask64(pctx); 2142 2143 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2144 2145 /* TODO: actually implement real values here */ 2146 bw_ctx[0] = 0; 2147 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2148 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2149 2150 return CC_SUCCESS; 2151 } 2152 2153 static uint32_t rotl(uint32_t v, unsigned count) 2154 { 2155 count &= 31; 2156 return (v << count) | (v >> (32 - count)); 2157 } 2158 2159 2160 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2161 { 2162 uint32_t val; 2163 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2164 val += rotl(lo + 0x49434878, hi & 0x1F); 2165 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2166 return ~val; 2167 } 2168 2169 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2170 { 2171 uint32_t buf[8]; 2172 uint32_t obuf[8]; 2173 dma_addr_t paddr = xhci_mask64(addr); 2174 2175 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2176 2177 memcpy(obuf, buf, sizeof(obuf)); 2178 2179 if ((buf[0] & 0xff) == 2) { 2180 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2181 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2182 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2183 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2184 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2185 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2186 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2187 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2188 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2189 } 2190 2191 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2192 } 2193 2194 static void xhci_process_commands(XHCIState *xhci) 2195 { 2196 XHCITRB trb; 2197 TRBType type; 2198 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2199 dma_addr_t addr; 2200 unsigned int i, slotid = 0; 2201 2202 DPRINTF("xhci_process_commands()\n"); 2203 if (!xhci_running(xhci)) { 2204 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2205 return; 2206 } 2207 2208 xhci->crcr_low |= CRCR_CRR; 2209 2210 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2211 event.ptr = addr; 2212 switch (type) { 2213 case CR_ENABLE_SLOT: 2214 for (i = 0; i < xhci->numslots; i++) { 2215 if (!xhci->slots[i].enabled) { 2216 break; 2217 } 2218 } 2219 if (i >= xhci->numslots) { 2220 fprintf(stderr, "xhci: no device slots available\n"); 2221 event.ccode = CC_NO_SLOTS_ERROR; 2222 } else { 2223 slotid = i+1; 2224 event.ccode = xhci_enable_slot(xhci, slotid); 2225 } 2226 break; 2227 case CR_DISABLE_SLOT: 2228 slotid = xhci_get_slot(xhci, &event, &trb); 2229 if (slotid) { 2230 event.ccode = xhci_disable_slot(xhci, slotid); 2231 } 2232 break; 2233 case CR_ADDRESS_DEVICE: 2234 slotid = xhci_get_slot(xhci, &event, &trb); 2235 if (slotid) { 2236 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2237 trb.control & TRB_CR_BSR); 2238 } 2239 break; 2240 case CR_CONFIGURE_ENDPOINT: 2241 slotid = xhci_get_slot(xhci, &event, &trb); 2242 if (slotid) { 2243 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2244 trb.control & TRB_CR_DC); 2245 } 2246 break; 2247 case CR_EVALUATE_CONTEXT: 2248 slotid = xhci_get_slot(xhci, &event, &trb); 2249 if (slotid) { 2250 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2251 } 2252 break; 2253 case CR_STOP_ENDPOINT: 2254 slotid = xhci_get_slot(xhci, &event, &trb); 2255 if (slotid) { 2256 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2257 & TRB_CR_EPID_MASK; 2258 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2259 } 2260 break; 2261 case CR_RESET_ENDPOINT: 2262 slotid = xhci_get_slot(xhci, &event, &trb); 2263 if (slotid) { 2264 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2265 & TRB_CR_EPID_MASK; 2266 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2267 } 2268 break; 2269 case CR_SET_TR_DEQUEUE: 2270 slotid = xhci_get_slot(xhci, &event, &trb); 2271 if (slotid) { 2272 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2273 & TRB_CR_EPID_MASK; 2274 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2275 trb.parameter); 2276 } 2277 break; 2278 case CR_RESET_DEVICE: 2279 slotid = xhci_get_slot(xhci, &event, &trb); 2280 if (slotid) { 2281 event.ccode = xhci_reset_slot(xhci, slotid); 2282 } 2283 break; 2284 case CR_GET_PORT_BANDWIDTH: 2285 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2286 break; 2287 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2288 xhci_via_challenge(xhci, trb.parameter); 2289 break; 2290 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2291 event.type = 48; /* NEC reply */ 2292 event.length = 0x3025; 2293 break; 2294 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2295 { 2296 uint32_t chi = trb.parameter >> 32; 2297 uint32_t clo = trb.parameter; 2298 uint32_t val = xhci_nec_challenge(chi, clo); 2299 event.length = val & 0xFFFF; 2300 event.epid = val >> 16; 2301 slotid = val >> 24; 2302 event.type = 48; /* NEC reply */ 2303 } 2304 break; 2305 default: 2306 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2307 event.ccode = CC_TRB_ERROR; 2308 break; 2309 } 2310 event.slotid = slotid; 2311 xhci_event(xhci, &event, 0); 2312 } 2313 } 2314 2315 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) 2316 { 2317 port->portsc = PORTSC_PP; 2318 if (port->uport->dev && port->uport->dev->attached && !is_detach && 2319 (1 << port->uport->dev->speed) & port->speedmask) { 2320 port->portsc |= PORTSC_CCS; 2321 switch (port->uport->dev->speed) { 2322 case USB_SPEED_LOW: 2323 port->portsc |= PORTSC_SPEED_LOW; 2324 break; 2325 case USB_SPEED_FULL: 2326 port->portsc |= PORTSC_SPEED_FULL; 2327 break; 2328 case USB_SPEED_HIGH: 2329 port->portsc |= PORTSC_SPEED_HIGH; 2330 break; 2331 case USB_SPEED_SUPER: 2332 port->portsc |= PORTSC_SPEED_SUPER; 2333 break; 2334 } 2335 } 2336 2337 if (xhci_running(xhci)) { 2338 port->portsc |= PORTSC_CSC; 2339 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2340 port->portnr << 24}; 2341 xhci_event(xhci, &ev, 0); 2342 DPRINTF("xhci: port change event for port %d\n", port->portnr); 2343 } 2344 } 2345 2346 static void xhci_reset(DeviceState *dev) 2347 { 2348 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2349 int i; 2350 2351 trace_usb_xhci_reset(); 2352 if (!(xhci->usbsts & USBSTS_HCH)) { 2353 fprintf(stderr, "xhci: reset while running!\n"); 2354 } 2355 2356 xhci->usbcmd = 0; 2357 xhci->usbsts = USBSTS_HCH; 2358 xhci->dnctrl = 0; 2359 xhci->crcr_low = 0; 2360 xhci->crcr_high = 0; 2361 xhci->dcbaap_low = 0; 2362 xhci->dcbaap_high = 0; 2363 xhci->config = 0; 2364 xhci->devaddr = 2; 2365 2366 for (i = 0; i < xhci->numslots; i++) { 2367 xhci_disable_slot(xhci, i+1); 2368 } 2369 2370 for (i = 0; i < xhci->numports; i++) { 2371 xhci_update_port(xhci, xhci->ports + i, 0); 2372 } 2373 2374 for (i = 0; i < xhci->numintrs; i++) { 2375 xhci->intr[i].iman = 0; 2376 xhci->intr[i].imod = 0; 2377 xhci->intr[i].erstsz = 0; 2378 xhci->intr[i].erstba_low = 0; 2379 xhci->intr[i].erstba_high = 0; 2380 xhci->intr[i].erdp_low = 0; 2381 xhci->intr[i].erdp_high = 0; 2382 xhci->intr[i].msix_used = 0; 2383 2384 xhci->intr[i].er_ep_idx = 0; 2385 xhci->intr[i].er_pcs = 1; 2386 xhci->intr[i].er_full = 0; 2387 xhci->intr[i].ev_buffer_put = 0; 2388 xhci->intr[i].ev_buffer_get = 0; 2389 } 2390 2391 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2392 xhci_mfwrap_update(xhci); 2393 } 2394 2395 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2396 { 2397 XHCIState *xhci = ptr; 2398 uint32_t ret; 2399 2400 switch (reg) { 2401 case 0x00: /* HCIVERSION, CAPLENGTH */ 2402 ret = 0x01000000 | LEN_CAP; 2403 break; 2404 case 0x04: /* HCSPARAMS 1 */ 2405 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2406 | (xhci->numintrs<<8) | xhci->numslots; 2407 break; 2408 case 0x08: /* HCSPARAMS 2 */ 2409 ret = 0x0000000f; 2410 break; 2411 case 0x0c: /* HCSPARAMS 3 */ 2412 ret = 0x00000000; 2413 break; 2414 case 0x10: /* HCCPARAMS */ 2415 if (sizeof(dma_addr_t) == 4) { 2416 ret = 0x00081000; 2417 } else { 2418 ret = 0x00081001; 2419 } 2420 break; 2421 case 0x14: /* DBOFF */ 2422 ret = OFF_DOORBELL; 2423 break; 2424 case 0x18: /* RTSOFF */ 2425 ret = OFF_RUNTIME; 2426 break; 2427 2428 /* extended capabilities */ 2429 case 0x20: /* Supported Protocol:00 */ 2430 ret = 0x02000402; /* USB 2.0 */ 2431 break; 2432 case 0x24: /* Supported Protocol:04 */ 2433 ret = 0x20425355; /* "USB " */ 2434 break; 2435 case 0x28: /* Supported Protocol:08 */ 2436 ret = 0x00000001 | (xhci->numports_2<<8); 2437 break; 2438 case 0x2c: /* Supported Protocol:0c */ 2439 ret = 0x00000000; /* reserved */ 2440 break; 2441 case 0x30: /* Supported Protocol:00 */ 2442 ret = 0x03000002; /* USB 3.0 */ 2443 break; 2444 case 0x34: /* Supported Protocol:04 */ 2445 ret = 0x20425355; /* "USB " */ 2446 break; 2447 case 0x38: /* Supported Protocol:08 */ 2448 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2449 break; 2450 case 0x3c: /* Supported Protocol:0c */ 2451 ret = 0x00000000; /* reserved */ 2452 break; 2453 default: 2454 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2455 ret = 0; 2456 } 2457 2458 trace_usb_xhci_cap_read(reg, ret); 2459 return ret; 2460 } 2461 2462 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2463 { 2464 XHCIPort *port = ptr; 2465 uint32_t ret; 2466 2467 switch (reg) { 2468 case 0x00: /* PORTSC */ 2469 ret = port->portsc; 2470 break; 2471 case 0x04: /* PORTPMSC */ 2472 case 0x08: /* PORTLI */ 2473 ret = 0; 2474 break; 2475 case 0x0c: /* reserved */ 2476 default: 2477 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2478 port->portnr, (uint32_t)reg); 2479 ret = 0; 2480 } 2481 2482 trace_usb_xhci_port_read(port->portnr, reg, ret); 2483 return ret; 2484 } 2485 2486 static void xhci_port_write(void *ptr, hwaddr reg, 2487 uint64_t val, unsigned size) 2488 { 2489 XHCIPort *port = ptr; 2490 uint32_t portsc; 2491 2492 trace_usb_xhci_port_write(port->portnr, reg, val); 2493 2494 switch (reg) { 2495 case 0x00: /* PORTSC */ 2496 portsc = port->portsc; 2497 /* write-1-to-clear bits*/ 2498 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2499 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2500 if (val & PORTSC_LWS) { 2501 /* overwrite PLS only when LWS=1 */ 2502 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2503 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); 2504 } 2505 /* read/write bits */ 2506 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2507 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2508 /* write-1-to-start bits */ 2509 if (val & PORTSC_PR) { 2510 DPRINTF("xhci: port %d reset\n", port); 2511 usb_device_reset(port->uport->dev); 2512 portsc |= PORTSC_PRC | PORTSC_PED; 2513 } 2514 port->portsc = portsc; 2515 break; 2516 case 0x04: /* PORTPMSC */ 2517 case 0x08: /* PORTLI */ 2518 default: 2519 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2520 port->portnr, (uint32_t)reg); 2521 } 2522 } 2523 2524 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2525 { 2526 XHCIState *xhci = ptr; 2527 uint32_t ret; 2528 2529 switch (reg) { 2530 case 0x00: /* USBCMD */ 2531 ret = xhci->usbcmd; 2532 break; 2533 case 0x04: /* USBSTS */ 2534 ret = xhci->usbsts; 2535 break; 2536 case 0x08: /* PAGESIZE */ 2537 ret = 1; /* 4KiB */ 2538 break; 2539 case 0x14: /* DNCTRL */ 2540 ret = xhci->dnctrl; 2541 break; 2542 case 0x18: /* CRCR low */ 2543 ret = xhci->crcr_low & ~0xe; 2544 break; 2545 case 0x1c: /* CRCR high */ 2546 ret = xhci->crcr_high; 2547 break; 2548 case 0x30: /* DCBAAP low */ 2549 ret = xhci->dcbaap_low; 2550 break; 2551 case 0x34: /* DCBAAP high */ 2552 ret = xhci->dcbaap_high; 2553 break; 2554 case 0x38: /* CONFIG */ 2555 ret = xhci->config; 2556 break; 2557 default: 2558 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2559 ret = 0; 2560 } 2561 2562 trace_usb_xhci_oper_read(reg, ret); 2563 return ret; 2564 } 2565 2566 static void xhci_oper_write(void *ptr, hwaddr reg, 2567 uint64_t val, unsigned size) 2568 { 2569 XHCIState *xhci = ptr; 2570 2571 trace_usb_xhci_oper_write(reg, val); 2572 2573 switch (reg) { 2574 case 0x00: /* USBCMD */ 2575 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2576 xhci_run(xhci); 2577 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2578 xhci_stop(xhci); 2579 } 2580 xhci->usbcmd = val & 0xc0f; 2581 xhci_mfwrap_update(xhci); 2582 if (val & USBCMD_HCRST) { 2583 xhci_reset(&xhci->pci_dev.qdev); 2584 } 2585 xhci_intx_update(xhci); 2586 break; 2587 2588 case 0x04: /* USBSTS */ 2589 /* these bits are write-1-to-clear */ 2590 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2591 xhci_intx_update(xhci); 2592 break; 2593 2594 case 0x14: /* DNCTRL */ 2595 xhci->dnctrl = val & 0xffff; 2596 break; 2597 case 0x18: /* CRCR low */ 2598 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2599 break; 2600 case 0x1c: /* CRCR high */ 2601 xhci->crcr_high = val; 2602 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2603 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2604 xhci->crcr_low &= ~CRCR_CRR; 2605 xhci_event(xhci, &event, 0); 2606 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2607 } else { 2608 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2609 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2610 } 2611 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2612 break; 2613 case 0x30: /* DCBAAP low */ 2614 xhci->dcbaap_low = val & 0xffffffc0; 2615 break; 2616 case 0x34: /* DCBAAP high */ 2617 xhci->dcbaap_high = val; 2618 break; 2619 case 0x38: /* CONFIG */ 2620 xhci->config = val & 0xff; 2621 break; 2622 default: 2623 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2624 } 2625 } 2626 2627 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2628 unsigned size) 2629 { 2630 XHCIState *xhci = ptr; 2631 uint32_t ret = 0; 2632 2633 if (reg < 0x20) { 2634 switch (reg) { 2635 case 0x00: /* MFINDEX */ 2636 ret = xhci_mfindex_get(xhci) & 0x3fff; 2637 break; 2638 default: 2639 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2640 (int)reg); 2641 break; 2642 } 2643 } else { 2644 int v = (reg - 0x20) / 0x20; 2645 XHCIInterrupter *intr = &xhci->intr[v]; 2646 switch (reg & 0x1f) { 2647 case 0x00: /* IMAN */ 2648 ret = intr->iman; 2649 break; 2650 case 0x04: /* IMOD */ 2651 ret = intr->imod; 2652 break; 2653 case 0x08: /* ERSTSZ */ 2654 ret = intr->erstsz; 2655 break; 2656 case 0x10: /* ERSTBA low */ 2657 ret = intr->erstba_low; 2658 break; 2659 case 0x14: /* ERSTBA high */ 2660 ret = intr->erstba_high; 2661 break; 2662 case 0x18: /* ERDP low */ 2663 ret = intr->erdp_low; 2664 break; 2665 case 0x1c: /* ERDP high */ 2666 ret = intr->erdp_high; 2667 break; 2668 } 2669 } 2670 2671 trace_usb_xhci_runtime_read(reg, ret); 2672 return ret; 2673 } 2674 2675 static void xhci_runtime_write(void *ptr, hwaddr reg, 2676 uint64_t val, unsigned size) 2677 { 2678 XHCIState *xhci = ptr; 2679 int v = (reg - 0x20) / 0x20; 2680 XHCIInterrupter *intr = &xhci->intr[v]; 2681 trace_usb_xhci_runtime_write(reg, val); 2682 2683 if (reg < 0x20) { 2684 fprintf(stderr, "%s: reg 0x%x unimplemented\n", __func__, (int)reg); 2685 return; 2686 } 2687 2688 switch (reg & 0x1f) { 2689 case 0x00: /* IMAN */ 2690 if (val & IMAN_IP) { 2691 intr->iman &= ~IMAN_IP; 2692 } 2693 intr->iman &= ~IMAN_IE; 2694 intr->iman |= val & IMAN_IE; 2695 if (v == 0) { 2696 xhci_intx_update(xhci); 2697 } 2698 xhci_msix_update(xhci, v); 2699 break; 2700 case 0x04: /* IMOD */ 2701 intr->imod = val; 2702 break; 2703 case 0x08: /* ERSTSZ */ 2704 intr->erstsz = val & 0xffff; 2705 break; 2706 case 0x10: /* ERSTBA low */ 2707 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2708 intr->erstba_low = val & 0xffffffc0; */ 2709 intr->erstba_low = val & 0xfffffff0; 2710 break; 2711 case 0x14: /* ERSTBA high */ 2712 intr->erstba_high = val; 2713 xhci_er_reset(xhci, v); 2714 break; 2715 case 0x18: /* ERDP low */ 2716 if (val & ERDP_EHB) { 2717 intr->erdp_low &= ~ERDP_EHB; 2718 } 2719 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2720 break; 2721 case 0x1c: /* ERDP high */ 2722 intr->erdp_high = val; 2723 xhci_events_update(xhci, v); 2724 break; 2725 default: 2726 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2727 (int)reg); 2728 } 2729 } 2730 2731 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 2732 unsigned size) 2733 { 2734 /* doorbells always read as 0 */ 2735 trace_usb_xhci_doorbell_read(reg, 0); 2736 return 0; 2737 } 2738 2739 static void xhci_doorbell_write(void *ptr, hwaddr reg, 2740 uint64_t val, unsigned size) 2741 { 2742 XHCIState *xhci = ptr; 2743 2744 trace_usb_xhci_doorbell_write(reg, val); 2745 2746 if (!xhci_running(xhci)) { 2747 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2748 return; 2749 } 2750 2751 reg >>= 2; 2752 2753 if (reg == 0) { 2754 if (val == 0) { 2755 xhci_process_commands(xhci); 2756 } else { 2757 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2758 (uint32_t)val); 2759 } 2760 } else { 2761 if (reg > xhci->numslots) { 2762 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2763 } else if (val > 31) { 2764 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2765 (int)reg, (uint32_t)val); 2766 } else { 2767 xhci_kick_ep(xhci, reg, val); 2768 } 2769 } 2770 } 2771 2772 static const MemoryRegionOps xhci_cap_ops = { 2773 .read = xhci_cap_read, 2774 .valid.min_access_size = 1, 2775 .valid.max_access_size = 4, 2776 .impl.min_access_size = 4, 2777 .impl.max_access_size = 4, 2778 .endianness = DEVICE_LITTLE_ENDIAN, 2779 }; 2780 2781 static const MemoryRegionOps xhci_oper_ops = { 2782 .read = xhci_oper_read, 2783 .write = xhci_oper_write, 2784 .valid.min_access_size = 4, 2785 .valid.max_access_size = 4, 2786 .endianness = DEVICE_LITTLE_ENDIAN, 2787 }; 2788 2789 static const MemoryRegionOps xhci_port_ops = { 2790 .read = xhci_port_read, 2791 .write = xhci_port_write, 2792 .valid.min_access_size = 4, 2793 .valid.max_access_size = 4, 2794 .endianness = DEVICE_LITTLE_ENDIAN, 2795 }; 2796 2797 static const MemoryRegionOps xhci_runtime_ops = { 2798 .read = xhci_runtime_read, 2799 .write = xhci_runtime_write, 2800 .valid.min_access_size = 4, 2801 .valid.max_access_size = 4, 2802 .endianness = DEVICE_LITTLE_ENDIAN, 2803 }; 2804 2805 static const MemoryRegionOps xhci_doorbell_ops = { 2806 .read = xhci_doorbell_read, 2807 .write = xhci_doorbell_write, 2808 .valid.min_access_size = 4, 2809 .valid.max_access_size = 4, 2810 .endianness = DEVICE_LITTLE_ENDIAN, 2811 }; 2812 2813 static void xhci_attach(USBPort *usbport) 2814 { 2815 XHCIState *xhci = usbport->opaque; 2816 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2817 2818 xhci_update_port(xhci, port, 0); 2819 } 2820 2821 static void xhci_detach(USBPort *usbport) 2822 { 2823 XHCIState *xhci = usbport->opaque; 2824 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2825 2826 xhci_update_port(xhci, port, 1); 2827 } 2828 2829 static void xhci_wakeup(USBPort *usbport) 2830 { 2831 XHCIState *xhci = usbport->opaque; 2832 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2833 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2834 port->portnr << 24}; 2835 uint32_t pls; 2836 2837 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; 2838 if (pls != 3) { 2839 return; 2840 } 2841 port->portsc |= 0xf << PORTSC_PLS_SHIFT; 2842 if (port->portsc & PORTSC_PLC) { 2843 return; 2844 } 2845 port->portsc |= PORTSC_PLC; 2846 xhci_event(xhci, &ev, 0); 2847 } 2848 2849 static void xhci_complete(USBPort *port, USBPacket *packet) 2850 { 2851 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2852 2853 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) { 2854 xhci_ep_nuke_one_xfer(xfer); 2855 return; 2856 } 2857 xhci_complete_packet(xfer, packet->result); 2858 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2859 } 2860 2861 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2862 { 2863 USBBus *bus = usb_bus_from_device(child); 2864 XHCIState *xhci = container_of(bus, XHCIState, bus); 2865 int i; 2866 2867 for (i = 0; i < xhci->numslots; i++) { 2868 if (xhci->slots[i].uport == uport) { 2869 xhci->slots[i].uport = NULL; 2870 } 2871 } 2872 } 2873 2874 static USBPortOps xhci_uport_ops = { 2875 .attach = xhci_attach, 2876 .detach = xhci_detach, 2877 .wakeup = xhci_wakeup, 2878 .complete = xhci_complete, 2879 .child_detach = xhci_child_detach, 2880 }; 2881 2882 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2883 { 2884 XHCISlot *slot; 2885 int slotid; 2886 2887 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 2888 slot = &xhci->slots[slotid-1]; 2889 if (slot->devaddr == dev->addr) { 2890 return slotid; 2891 } 2892 } 2893 return 0; 2894 } 2895 2896 static int xhci_find_epid(USBEndpoint *ep) 2897 { 2898 if (ep->nr == 0) { 2899 return 1; 2900 } 2901 if (ep->pid == USB_TOKEN_IN) { 2902 return ep->nr * 2 + 1; 2903 } else { 2904 return ep->nr * 2; 2905 } 2906 } 2907 2908 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 2909 { 2910 XHCIState *xhci = container_of(bus, XHCIState, bus); 2911 int slotid; 2912 2913 DPRINTF("%s\n", __func__); 2914 slotid = xhci_find_slotid(xhci, ep->dev); 2915 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 2916 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 2917 return; 2918 } 2919 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 2920 } 2921 2922 static USBBusOps xhci_bus_ops = { 2923 .wakeup_endpoint = xhci_wakeup_endpoint, 2924 }; 2925 2926 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 2927 { 2928 XHCIPort *port; 2929 int i, usbports, speedmask; 2930 2931 xhci->usbsts = USBSTS_HCH; 2932 2933 if (xhci->numports_2 > MAXPORTS_2) { 2934 xhci->numports_2 = MAXPORTS_2; 2935 } 2936 if (xhci->numports_3 > MAXPORTS_3) { 2937 xhci->numports_3 = MAXPORTS_3; 2938 } 2939 usbports = MAX(xhci->numports_2, xhci->numports_3); 2940 xhci->numports = xhci->numports_2 + xhci->numports_3; 2941 2942 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 2943 2944 for (i = 0; i < usbports; i++) { 2945 speedmask = 0; 2946 if (i < xhci->numports_2) { 2947 port = &xhci->ports[i]; 2948 port->portnr = i + 1; 2949 port->uport = &xhci->uports[i]; 2950 port->speedmask = 2951 USB_SPEED_MASK_LOW | 2952 USB_SPEED_MASK_FULL | 2953 USB_SPEED_MASK_HIGH; 2954 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 2955 speedmask |= port->speedmask; 2956 } 2957 if (i < xhci->numports_3) { 2958 port = &xhci->ports[i + xhci->numports_2]; 2959 port->portnr = i + 1 + xhci->numports_2; 2960 port->uport = &xhci->uports[i]; 2961 port->speedmask = USB_SPEED_MASK_SUPER; 2962 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 2963 speedmask |= port->speedmask; 2964 } 2965 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 2966 &xhci_uport_ops, speedmask); 2967 } 2968 } 2969 2970 static int usb_xhci_initfn(struct PCIDevice *dev) 2971 { 2972 int i, ret; 2973 2974 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 2975 2976 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 2977 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 2978 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 2979 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 2980 2981 usb_xhci_init(xhci, &dev->qdev); 2982 2983 if (xhci->numintrs > MAXINTRS) { 2984 xhci->numintrs = MAXINTRS; 2985 } 2986 if (xhci->numintrs < 1) { 2987 xhci->numintrs = 1; 2988 } 2989 if (xhci->numslots > MAXSLOTS) { 2990 xhci->numslots = MAXSLOTS; 2991 } 2992 if (xhci->numslots < 1) { 2993 xhci->numslots = 1; 2994 } 2995 2996 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 2997 2998 xhci->irq = xhci->pci_dev.irq[0]; 2999 3000 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 3001 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 3002 "capabilities", LEN_CAP); 3003 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 3004 "operational", 0x400); 3005 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 3006 "runtime", LEN_RUNTIME); 3007 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 3008 "doorbell", LEN_DOORBELL); 3009 3010 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3011 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3012 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3013 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3014 3015 for (i = 0; i < xhci->numports; i++) { 3016 XHCIPort *port = &xhci->ports[i]; 3017 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3018 port->xhci = xhci; 3019 memory_region_init_io(&port->mem, &xhci_port_ops, port, 3020 port->name, 0x10); 3021 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3022 } 3023 3024 pci_register_bar(&xhci->pci_dev, 0, 3025 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3026 &xhci->mem); 3027 3028 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 3029 assert(ret >= 0); 3030 3031 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3032 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); 3033 } 3034 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3035 msix_init(&xhci->pci_dev, xhci->numintrs, 3036 &xhci->mem, 0, OFF_MSIX_TABLE, 3037 &xhci->mem, 0, OFF_MSIX_PBA, 3038 0x90); 3039 } 3040 3041 return 0; 3042 } 3043 3044 static const VMStateDescription vmstate_xhci = { 3045 .name = "xhci", 3046 .unmigratable = 1, 3047 }; 3048 3049 static Property xhci_properties[] = { 3050 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3051 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3052 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3053 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3054 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3055 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3056 DEFINE_PROP_END_OF_LIST(), 3057 }; 3058 3059 static void xhci_class_init(ObjectClass *klass, void *data) 3060 { 3061 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3062 DeviceClass *dc = DEVICE_CLASS(klass); 3063 3064 dc->vmsd = &vmstate_xhci; 3065 dc->props = xhci_properties; 3066 dc->reset = xhci_reset; 3067 k->init = usb_xhci_initfn; 3068 k->vendor_id = PCI_VENDOR_ID_NEC; 3069 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3070 k->class_id = PCI_CLASS_SERIAL_USB; 3071 k->revision = 0x03; 3072 k->is_express = 1; 3073 } 3074 3075 static TypeInfo xhci_info = { 3076 .name = "nec-usb-xhci", 3077 .parent = TYPE_PCI_DEVICE, 3078 .instance_size = sizeof(XHCIState), 3079 .class_init = xhci_class_init, 3080 }; 3081 3082 static void xhci_register_types(void) 3083 { 3084 type_register_static(&xhci_info); 3085 } 3086 3087 type_init(xhci_register_types) 3088