1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "hw/hw.h" 22 #include "qemu-timer.h" 23 #include "hw/usb.h" 24 #include "hw/pci.h" 25 #include "hw/msi.h" 26 #include "hw/msix.h" 27 #include "trace.h" 28 29 //#define DEBUG_XHCI 30 //#define DEBUG_DATA 31 32 #ifdef DEBUG_XHCI 33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 34 #else 35 #define DPRINTF(...) do {} while (0) 36 #endif 37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \ 38 __func__, __LINE__); abort(); } while (0) 39 40 #define MAXPORTS_2 15 41 #define MAXPORTS_3 15 42 43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 44 #define MAXSLOTS 64 45 #define MAXINTRS 16 46 47 #define TD_QUEUE 24 48 49 /* Very pessimistic, let's hope it's enough for all cases */ 50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) 51 /* Do not deliver ER Full events. NEC's driver does some things not bound 52 * to the specs when it gets them */ 53 #define ER_FULL_HACK 54 55 #define LEN_CAP 0x40 56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 59 60 #define OFF_OPER LEN_CAP 61 #define OFF_RUNTIME 0x1000 62 #define OFF_DOORBELL 0x2000 63 #define OFF_MSIX_TABLE 0x3000 64 #define OFF_MSIX_PBA 0x3800 65 /* must be power of 2 */ 66 #define LEN_REGS 0x4000 67 68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 69 #error Increase OFF_RUNTIME 70 #endif 71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 72 #error Increase OFF_DOORBELL 73 #endif 74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 75 # error Increase LEN_REGS 76 #endif 77 78 /* bit definitions */ 79 #define USBCMD_RS (1<<0) 80 #define USBCMD_HCRST (1<<1) 81 #define USBCMD_INTE (1<<2) 82 #define USBCMD_HSEE (1<<3) 83 #define USBCMD_LHCRST (1<<7) 84 #define USBCMD_CSS (1<<8) 85 #define USBCMD_CRS (1<<9) 86 #define USBCMD_EWE (1<<10) 87 #define USBCMD_EU3S (1<<11) 88 89 #define USBSTS_HCH (1<<0) 90 #define USBSTS_HSE (1<<2) 91 #define USBSTS_EINT (1<<3) 92 #define USBSTS_PCD (1<<4) 93 #define USBSTS_SSS (1<<8) 94 #define USBSTS_RSS (1<<9) 95 #define USBSTS_SRE (1<<10) 96 #define USBSTS_CNR (1<<11) 97 #define USBSTS_HCE (1<<12) 98 99 100 #define PORTSC_CCS (1<<0) 101 #define PORTSC_PED (1<<1) 102 #define PORTSC_OCA (1<<3) 103 #define PORTSC_PR (1<<4) 104 #define PORTSC_PLS_SHIFT 5 105 #define PORTSC_PLS_MASK 0xf 106 #define PORTSC_PP (1<<9) 107 #define PORTSC_SPEED_SHIFT 10 108 #define PORTSC_SPEED_MASK 0xf 109 #define PORTSC_SPEED_FULL (1<<10) 110 #define PORTSC_SPEED_LOW (2<<10) 111 #define PORTSC_SPEED_HIGH (3<<10) 112 #define PORTSC_SPEED_SUPER (4<<10) 113 #define PORTSC_PIC_SHIFT 14 114 #define PORTSC_PIC_MASK 0x3 115 #define PORTSC_LWS (1<<16) 116 #define PORTSC_CSC (1<<17) 117 #define PORTSC_PEC (1<<18) 118 #define PORTSC_WRC (1<<19) 119 #define PORTSC_OCC (1<<20) 120 #define PORTSC_PRC (1<<21) 121 #define PORTSC_PLC (1<<22) 122 #define PORTSC_CEC (1<<23) 123 #define PORTSC_CAS (1<<24) 124 #define PORTSC_WCE (1<<25) 125 #define PORTSC_WDE (1<<26) 126 #define PORTSC_WOE (1<<27) 127 #define PORTSC_DR (1<<30) 128 #define PORTSC_WPR (1<<31) 129 130 #define CRCR_RCS (1<<0) 131 #define CRCR_CS (1<<1) 132 #define CRCR_CA (1<<2) 133 #define CRCR_CRR (1<<3) 134 135 #define IMAN_IP (1<<0) 136 #define IMAN_IE (1<<1) 137 138 #define ERDP_EHB (1<<3) 139 140 #define TRB_SIZE 16 141 typedef struct XHCITRB { 142 uint64_t parameter; 143 uint32_t status; 144 uint32_t control; 145 dma_addr_t addr; 146 bool ccs; 147 } XHCITRB; 148 149 enum { 150 PLS_U0 = 0, 151 PLS_U1 = 1, 152 PLS_U2 = 2, 153 PLS_U3 = 3, 154 PLS_DISABLED = 4, 155 PLS_RX_DETECT = 5, 156 PLS_INACTIVE = 6, 157 PLS_POLLING = 7, 158 PLS_RECOVERY = 8, 159 PLS_HOT_RESET = 9, 160 PLS_COMPILANCE_MODE = 10, 161 PLS_TEST_MODE = 11, 162 PLS_RESUME = 15, 163 }; 164 165 typedef enum TRBType { 166 TRB_RESERVED = 0, 167 TR_NORMAL, 168 TR_SETUP, 169 TR_DATA, 170 TR_STATUS, 171 TR_ISOCH, 172 TR_LINK, 173 TR_EVDATA, 174 TR_NOOP, 175 CR_ENABLE_SLOT, 176 CR_DISABLE_SLOT, 177 CR_ADDRESS_DEVICE, 178 CR_CONFIGURE_ENDPOINT, 179 CR_EVALUATE_CONTEXT, 180 CR_RESET_ENDPOINT, 181 CR_STOP_ENDPOINT, 182 CR_SET_TR_DEQUEUE, 183 CR_RESET_DEVICE, 184 CR_FORCE_EVENT, 185 CR_NEGOTIATE_BW, 186 CR_SET_LATENCY_TOLERANCE, 187 CR_GET_PORT_BANDWIDTH, 188 CR_FORCE_HEADER, 189 CR_NOOP, 190 ER_TRANSFER = 32, 191 ER_COMMAND_COMPLETE, 192 ER_PORT_STATUS_CHANGE, 193 ER_BANDWIDTH_REQUEST, 194 ER_DOORBELL, 195 ER_HOST_CONTROLLER, 196 ER_DEVICE_NOTIFICATION, 197 ER_MFINDEX_WRAP, 198 /* vendor specific bits */ 199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, 200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 202 } TRBType; 203 204 #define CR_LINK TR_LINK 205 206 typedef enum TRBCCode { 207 CC_INVALID = 0, 208 CC_SUCCESS, 209 CC_DATA_BUFFER_ERROR, 210 CC_BABBLE_DETECTED, 211 CC_USB_TRANSACTION_ERROR, 212 CC_TRB_ERROR, 213 CC_STALL_ERROR, 214 CC_RESOURCE_ERROR, 215 CC_BANDWIDTH_ERROR, 216 CC_NO_SLOTS_ERROR, 217 CC_INVALID_STREAM_TYPE_ERROR, 218 CC_SLOT_NOT_ENABLED_ERROR, 219 CC_EP_NOT_ENABLED_ERROR, 220 CC_SHORT_PACKET, 221 CC_RING_UNDERRUN, 222 CC_RING_OVERRUN, 223 CC_VF_ER_FULL, 224 CC_PARAMETER_ERROR, 225 CC_BANDWIDTH_OVERRUN, 226 CC_CONTEXT_STATE_ERROR, 227 CC_NO_PING_RESPONSE_ERROR, 228 CC_EVENT_RING_FULL_ERROR, 229 CC_INCOMPATIBLE_DEVICE_ERROR, 230 CC_MISSED_SERVICE_ERROR, 231 CC_COMMAND_RING_STOPPED, 232 CC_COMMAND_ABORTED, 233 CC_STOPPED, 234 CC_STOPPED_LENGTH_INVALID, 235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 236 CC_ISOCH_BUFFER_OVERRUN = 31, 237 CC_EVENT_LOST_ERROR, 238 CC_UNDEFINED_ERROR, 239 CC_INVALID_STREAM_ID_ERROR, 240 CC_SECONDARY_BANDWIDTH_ERROR, 241 CC_SPLIT_TRANSACTION_ERROR 242 } TRBCCode; 243 244 #define TRB_C (1<<0) 245 #define TRB_TYPE_SHIFT 10 246 #define TRB_TYPE_MASK 0x3f 247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 248 249 #define TRB_EV_ED (1<<2) 250 251 #define TRB_TR_ENT (1<<1) 252 #define TRB_TR_ISP (1<<2) 253 #define TRB_TR_NS (1<<3) 254 #define TRB_TR_CH (1<<4) 255 #define TRB_TR_IOC (1<<5) 256 #define TRB_TR_IDT (1<<6) 257 #define TRB_TR_TBC_SHIFT 7 258 #define TRB_TR_TBC_MASK 0x3 259 #define TRB_TR_BEI (1<<9) 260 #define TRB_TR_TLBPC_SHIFT 16 261 #define TRB_TR_TLBPC_MASK 0xf 262 #define TRB_TR_FRAMEID_SHIFT 20 263 #define TRB_TR_FRAMEID_MASK 0x7ff 264 #define TRB_TR_SIA (1<<31) 265 266 #define TRB_TR_DIR (1<<16) 267 268 #define TRB_CR_SLOTID_SHIFT 24 269 #define TRB_CR_SLOTID_MASK 0xff 270 #define TRB_CR_EPID_SHIFT 16 271 #define TRB_CR_EPID_MASK 0x1f 272 273 #define TRB_CR_BSR (1<<9) 274 #define TRB_CR_DC (1<<9) 275 276 #define TRB_LK_TC (1<<1) 277 278 #define TRB_INTR_SHIFT 22 279 #define TRB_INTR_MASK 0x3ff 280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 281 282 #define EP_TYPE_MASK 0x7 283 #define EP_TYPE_SHIFT 3 284 285 #define EP_STATE_MASK 0x7 286 #define EP_DISABLED (0<<0) 287 #define EP_RUNNING (1<<0) 288 #define EP_HALTED (2<<0) 289 #define EP_STOPPED (3<<0) 290 #define EP_ERROR (4<<0) 291 292 #define SLOT_STATE_MASK 0x1f 293 #define SLOT_STATE_SHIFT 27 294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 295 #define SLOT_ENABLED 0 296 #define SLOT_DEFAULT 1 297 #define SLOT_ADDRESSED 2 298 #define SLOT_CONFIGURED 3 299 300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 302 303 typedef struct XHCIState XHCIState; 304 305 #define get_field(data, field) \ 306 (((data) >> field##_SHIFT) & field##_MASK) 307 308 #define set_field(data, newval, field) do { \ 309 uint32_t val = *data; \ 310 val &= ~(field##_MASK << field##_SHIFT); \ 311 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 312 *data = val; \ 313 } while (0) 314 315 typedef enum EPType { 316 ET_INVALID = 0, 317 ET_ISO_OUT, 318 ET_BULK_OUT, 319 ET_INTR_OUT, 320 ET_CONTROL, 321 ET_ISO_IN, 322 ET_BULK_IN, 323 ET_INTR_IN, 324 } EPType; 325 326 typedef struct XHCIRing { 327 dma_addr_t base; 328 dma_addr_t dequeue; 329 bool ccs; 330 } XHCIRing; 331 332 typedef struct XHCIPort { 333 XHCIState *xhci; 334 uint32_t portsc; 335 uint32_t portnr; 336 USBPort *uport; 337 uint32_t speedmask; 338 char name[16]; 339 MemoryRegion mem; 340 } XHCIPort; 341 342 typedef struct XHCITransfer { 343 XHCIState *xhci; 344 USBPacket packet; 345 QEMUSGList sgl; 346 bool running_async; 347 bool running_retry; 348 bool cancelled; 349 bool complete; 350 bool int_req; 351 unsigned int iso_pkts; 352 unsigned int slotid; 353 unsigned int epid; 354 bool in_xfer; 355 bool iso_xfer; 356 357 unsigned int trb_count; 358 unsigned int trb_alloced; 359 XHCITRB *trbs; 360 361 TRBCCode status; 362 363 unsigned int pkts; 364 unsigned int pktsize; 365 unsigned int cur_pkt; 366 367 uint64_t mfindex_kick; 368 } XHCITransfer; 369 370 typedef struct XHCIEPContext { 371 XHCIState *xhci; 372 unsigned int slotid; 373 unsigned int epid; 374 375 XHCIRing ring; 376 unsigned int next_xfer; 377 unsigned int comp_xfer; 378 XHCITransfer transfers[TD_QUEUE]; 379 XHCITransfer *retry; 380 EPType type; 381 dma_addr_t pctx; 382 unsigned int max_psize; 383 uint32_t state; 384 385 /* iso xfer scheduling */ 386 unsigned int interval; 387 int64_t mfindex_last; 388 QEMUTimer *kick_timer; 389 } XHCIEPContext; 390 391 typedef struct XHCISlot { 392 bool enabled; 393 dma_addr_t ctx; 394 USBPort *uport; 395 unsigned int devaddr; 396 XHCIEPContext * eps[31]; 397 } XHCISlot; 398 399 typedef struct XHCIEvent { 400 TRBType type; 401 TRBCCode ccode; 402 uint64_t ptr; 403 uint32_t length; 404 uint32_t flags; 405 uint8_t slotid; 406 uint8_t epid; 407 } XHCIEvent; 408 409 typedef struct XHCIInterrupter { 410 uint32_t iman; 411 uint32_t imod; 412 uint32_t erstsz; 413 uint32_t erstba_low; 414 uint32_t erstba_high; 415 uint32_t erdp_low; 416 uint32_t erdp_high; 417 418 bool msix_used, er_pcs, er_full; 419 420 dma_addr_t er_start; 421 uint32_t er_size; 422 unsigned int er_ep_idx; 423 424 XHCIEvent ev_buffer[EV_QUEUE]; 425 unsigned int ev_buffer_put; 426 unsigned int ev_buffer_get; 427 428 } XHCIInterrupter; 429 430 struct XHCIState { 431 PCIDevice pci_dev; 432 USBBus bus; 433 qemu_irq irq; 434 MemoryRegion mem; 435 MemoryRegion mem_cap; 436 MemoryRegion mem_oper; 437 MemoryRegion mem_runtime; 438 MemoryRegion mem_doorbell; 439 const char *name; 440 unsigned int devaddr; 441 442 /* properties */ 443 uint32_t numports_2; 444 uint32_t numports_3; 445 uint32_t numintrs; 446 uint32_t numslots; 447 uint32_t flags; 448 449 /* Operational Registers */ 450 uint32_t usbcmd; 451 uint32_t usbsts; 452 uint32_t dnctrl; 453 uint32_t crcr_low; 454 uint32_t crcr_high; 455 uint32_t dcbaap_low; 456 uint32_t dcbaap_high; 457 uint32_t config; 458 459 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 460 XHCIPort ports[MAXPORTS]; 461 XHCISlot slots[MAXSLOTS]; 462 uint32_t numports; 463 464 /* Runtime Registers */ 465 int64_t mfindex_start; 466 QEMUTimer *mfwrap_timer; 467 XHCIInterrupter intr[MAXINTRS]; 468 469 XHCIRing cmd_ring; 470 }; 471 472 typedef struct XHCIEvRingSeg { 473 uint32_t addr_low; 474 uint32_t addr_high; 475 uint32_t size; 476 uint32_t rsvd; 477 } XHCIEvRingSeg; 478 479 enum xhci_flags { 480 XHCI_FLAG_USE_MSI = 1, 481 XHCI_FLAG_USE_MSI_X, 482 }; 483 484 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 485 unsigned int epid); 486 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 487 unsigned int epid); 488 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 489 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 490 491 static const char *TRBType_names[] = { 492 [TRB_RESERVED] = "TRB_RESERVED", 493 [TR_NORMAL] = "TR_NORMAL", 494 [TR_SETUP] = "TR_SETUP", 495 [TR_DATA] = "TR_DATA", 496 [TR_STATUS] = "TR_STATUS", 497 [TR_ISOCH] = "TR_ISOCH", 498 [TR_LINK] = "TR_LINK", 499 [TR_EVDATA] = "TR_EVDATA", 500 [TR_NOOP] = "TR_NOOP", 501 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 502 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 503 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 504 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 505 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 506 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 507 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 508 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 509 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 510 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 511 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 512 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 513 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 514 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 515 [CR_NOOP] = "CR_NOOP", 516 [ER_TRANSFER] = "ER_TRANSFER", 517 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 518 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 519 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 520 [ER_DOORBELL] = "ER_DOORBELL", 521 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 522 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 523 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 524 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", 525 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 526 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 527 }; 528 529 static const char *TRBCCode_names[] = { 530 [CC_INVALID] = "CC_INVALID", 531 [CC_SUCCESS] = "CC_SUCCESS", 532 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 533 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 534 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 535 [CC_TRB_ERROR] = "CC_TRB_ERROR", 536 [CC_STALL_ERROR] = "CC_STALL_ERROR", 537 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 538 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 539 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 540 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 541 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 542 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 543 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 544 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 545 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 546 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 547 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 548 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 549 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 550 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 551 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 552 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 553 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 554 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 555 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 556 [CC_STOPPED] = "CC_STOPPED", 557 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 558 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 559 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 560 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 561 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 562 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 563 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 564 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 565 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 566 }; 567 568 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 569 { 570 if (index >= llen || list[index] == NULL) { 571 return "???"; 572 } 573 return list[index]; 574 } 575 576 static const char *trb_name(XHCITRB *trb) 577 { 578 return lookup_name(TRB_TYPE(*trb), TRBType_names, 579 ARRAY_SIZE(TRBType_names)); 580 } 581 582 static const char *event_name(XHCIEvent *event) 583 { 584 return lookup_name(event->ccode, TRBCCode_names, 585 ARRAY_SIZE(TRBCCode_names)); 586 } 587 588 static uint64_t xhci_mfindex_get(XHCIState *xhci) 589 { 590 int64_t now = qemu_get_clock_ns(vm_clock); 591 return (now - xhci->mfindex_start) / 125000; 592 } 593 594 static void xhci_mfwrap_update(XHCIState *xhci) 595 { 596 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 597 uint32_t mfindex, left; 598 int64_t now; 599 600 if ((xhci->usbcmd & bits) == bits) { 601 now = qemu_get_clock_ns(vm_clock); 602 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 603 left = 0x4000 - mfindex; 604 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); 605 } else { 606 qemu_del_timer(xhci->mfwrap_timer); 607 } 608 } 609 610 static void xhci_mfwrap_timer(void *opaque) 611 { 612 XHCIState *xhci = opaque; 613 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 614 615 xhci_event(xhci, &wrap, 0); 616 xhci_mfwrap_update(xhci); 617 } 618 619 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 620 { 621 if (sizeof(dma_addr_t) == 4) { 622 return low; 623 } else { 624 return low | (((dma_addr_t)high << 16) << 16); 625 } 626 } 627 628 static inline dma_addr_t xhci_mask64(uint64_t addr) 629 { 630 if (sizeof(dma_addr_t) == 4) { 631 return addr & 0xffffffff; 632 } else { 633 return addr; 634 } 635 } 636 637 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 638 uint32_t *buf, size_t len) 639 { 640 int i; 641 642 assert((len % sizeof(uint32_t)) == 0); 643 644 pci_dma_read(&xhci->pci_dev, addr, buf, len); 645 646 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 647 buf[i] = le32_to_cpu(buf[i]); 648 } 649 } 650 651 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 652 uint32_t *buf, size_t len) 653 { 654 int i; 655 uint32_t tmp[len / sizeof(uint32_t)]; 656 657 assert((len % sizeof(uint32_t)) == 0); 658 659 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 660 tmp[i] = cpu_to_le32(buf[i]); 661 } 662 pci_dma_write(&xhci->pci_dev, addr, tmp, len); 663 } 664 665 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 666 { 667 int index; 668 669 if (!uport->dev) { 670 return NULL; 671 } 672 switch (uport->dev->speed) { 673 case USB_SPEED_LOW: 674 case USB_SPEED_FULL: 675 case USB_SPEED_HIGH: 676 index = uport->index; 677 break; 678 case USB_SPEED_SUPER: 679 index = uport->index + xhci->numports_2; 680 break; 681 default: 682 return NULL; 683 } 684 return &xhci->ports[index]; 685 } 686 687 static void xhci_intx_update(XHCIState *xhci) 688 { 689 int level = 0; 690 691 if (msix_enabled(&xhci->pci_dev) || 692 msi_enabled(&xhci->pci_dev)) { 693 return; 694 } 695 696 if (xhci->intr[0].iman & IMAN_IP && 697 xhci->intr[0].iman & IMAN_IE && 698 xhci->usbcmd & USBCMD_INTE) { 699 level = 1; 700 } 701 702 trace_usb_xhci_irq_intx(level); 703 qemu_set_irq(xhci->irq, level); 704 } 705 706 static void xhci_msix_update(XHCIState *xhci, int v) 707 { 708 bool enabled; 709 710 if (!msix_enabled(&xhci->pci_dev)) { 711 return; 712 } 713 714 enabled = xhci->intr[v].iman & IMAN_IE; 715 if (enabled == xhci->intr[v].msix_used) { 716 return; 717 } 718 719 if (enabled) { 720 trace_usb_xhci_irq_msix_use(v); 721 msix_vector_use(&xhci->pci_dev, v); 722 xhci->intr[v].msix_used = true; 723 } else { 724 trace_usb_xhci_irq_msix_unuse(v); 725 msix_vector_unuse(&xhci->pci_dev, v); 726 xhci->intr[v].msix_used = false; 727 } 728 } 729 730 static void xhci_intr_raise(XHCIState *xhci, int v) 731 { 732 xhci->intr[v].erdp_low |= ERDP_EHB; 733 xhci->intr[v].iman |= IMAN_IP; 734 xhci->usbsts |= USBSTS_EINT; 735 736 if (!(xhci->intr[v].iman & IMAN_IE)) { 737 return; 738 } 739 740 if (!(xhci->usbcmd & USBCMD_INTE)) { 741 return; 742 } 743 744 if (msix_enabled(&xhci->pci_dev)) { 745 trace_usb_xhci_irq_msix(v); 746 msix_notify(&xhci->pci_dev, v); 747 return; 748 } 749 750 if (msi_enabled(&xhci->pci_dev)) { 751 trace_usb_xhci_irq_msi(v); 752 msi_notify(&xhci->pci_dev, v); 753 return; 754 } 755 756 if (v == 0) { 757 trace_usb_xhci_irq_intx(1); 758 qemu_set_irq(xhci->irq, 1); 759 } 760 } 761 762 static inline int xhci_running(XHCIState *xhci) 763 { 764 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; 765 } 766 767 static void xhci_die(XHCIState *xhci) 768 { 769 xhci->usbsts |= USBSTS_HCE; 770 fprintf(stderr, "xhci: asserted controller error\n"); 771 } 772 773 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 774 { 775 XHCIInterrupter *intr = &xhci->intr[v]; 776 XHCITRB ev_trb; 777 dma_addr_t addr; 778 779 ev_trb.parameter = cpu_to_le64(event->ptr); 780 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 781 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 782 event->flags | (event->type << TRB_TYPE_SHIFT); 783 if (intr->er_pcs) { 784 ev_trb.control |= TRB_C; 785 } 786 ev_trb.control = cpu_to_le32(ev_trb.control); 787 788 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 789 event_name(event), ev_trb.parameter, 790 ev_trb.status, ev_trb.control); 791 792 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 793 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); 794 795 intr->er_ep_idx++; 796 if (intr->er_ep_idx >= intr->er_size) { 797 intr->er_ep_idx = 0; 798 intr->er_pcs = !intr->er_pcs; 799 } 800 } 801 802 static void xhci_events_update(XHCIState *xhci, int v) 803 { 804 XHCIInterrupter *intr = &xhci->intr[v]; 805 dma_addr_t erdp; 806 unsigned int dp_idx; 807 bool do_irq = 0; 808 809 if (xhci->usbsts & USBSTS_HCH) { 810 return; 811 } 812 813 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 814 if (erdp < intr->er_start || 815 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 816 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 817 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 818 v, intr->er_start, intr->er_size); 819 xhci_die(xhci); 820 return; 821 } 822 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 823 assert(dp_idx < intr->er_size); 824 825 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus 826 * deadlocks when the ER is full. Hack it by holding off events until 827 * the driver decides to free at least half of the ring */ 828 if (intr->er_full) { 829 int er_free = dp_idx - intr->er_ep_idx; 830 if (er_free <= 0) { 831 er_free += intr->er_size; 832 } 833 if (er_free < (intr->er_size/2)) { 834 DPRINTF("xhci_events_update(): event ring still " 835 "more than half full (hack)\n"); 836 return; 837 } 838 } 839 840 while (intr->ev_buffer_put != intr->ev_buffer_get) { 841 assert(intr->er_full); 842 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { 843 DPRINTF("xhci_events_update(): event ring full again\n"); 844 #ifndef ER_FULL_HACK 845 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 846 xhci_write_event(xhci, &full, v); 847 #endif 848 do_irq = 1; 849 break; 850 } 851 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; 852 xhci_write_event(xhci, event, v); 853 intr->ev_buffer_get++; 854 do_irq = 1; 855 if (intr->ev_buffer_get == EV_QUEUE) { 856 intr->ev_buffer_get = 0; 857 } 858 } 859 860 if (do_irq) { 861 xhci_intr_raise(xhci, v); 862 } 863 864 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { 865 DPRINTF("xhci_events_update(): event ring no longer full\n"); 866 intr->er_full = 0; 867 } 868 } 869 870 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 871 { 872 XHCIInterrupter *intr; 873 dma_addr_t erdp; 874 unsigned int dp_idx; 875 876 if (v >= xhci->numintrs) { 877 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 878 return; 879 } 880 intr = &xhci->intr[v]; 881 882 if (intr->er_full) { 883 DPRINTF("xhci_event(): ER full, queueing\n"); 884 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 885 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 886 return; 887 } 888 intr->ev_buffer[intr->ev_buffer_put++] = *event; 889 if (intr->ev_buffer_put == EV_QUEUE) { 890 intr->ev_buffer_put = 0; 891 } 892 return; 893 } 894 895 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 896 if (erdp < intr->er_start || 897 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 898 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 899 fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 900 v, intr->er_start, intr->er_size); 901 xhci_die(xhci); 902 return; 903 } 904 905 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 906 assert(dp_idx < intr->er_size); 907 908 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { 909 DPRINTF("xhci_event(): ER full, queueing\n"); 910 #ifndef ER_FULL_HACK 911 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 912 xhci_write_event(xhci, &full); 913 #endif 914 intr->er_full = 1; 915 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { 916 fprintf(stderr, "xhci: event queue full, dropping event!\n"); 917 return; 918 } 919 intr->ev_buffer[intr->ev_buffer_put++] = *event; 920 if (intr->ev_buffer_put == EV_QUEUE) { 921 intr->ev_buffer_put = 0; 922 } 923 } else { 924 xhci_write_event(xhci, event, v); 925 } 926 927 xhci_intr_raise(xhci, v); 928 } 929 930 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 931 dma_addr_t base) 932 { 933 ring->base = base; 934 ring->dequeue = base; 935 ring->ccs = 1; 936 } 937 938 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 939 dma_addr_t *addr) 940 { 941 while (1) { 942 TRBType type; 943 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); 944 trb->addr = ring->dequeue; 945 trb->ccs = ring->ccs; 946 le64_to_cpus(&trb->parameter); 947 le32_to_cpus(&trb->status); 948 le32_to_cpus(&trb->control); 949 950 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 951 trb->parameter, trb->status, trb->control); 952 953 if ((trb->control & TRB_C) != ring->ccs) { 954 return 0; 955 } 956 957 type = TRB_TYPE(*trb); 958 959 if (type != TR_LINK) { 960 if (addr) { 961 *addr = ring->dequeue; 962 } 963 ring->dequeue += TRB_SIZE; 964 return type; 965 } else { 966 ring->dequeue = xhci_mask64(trb->parameter); 967 if (trb->control & TRB_LK_TC) { 968 ring->ccs = !ring->ccs; 969 } 970 } 971 } 972 } 973 974 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 975 { 976 XHCITRB trb; 977 int length = 0; 978 dma_addr_t dequeue = ring->dequeue; 979 bool ccs = ring->ccs; 980 /* hack to bundle together the two/three TDs that make a setup transfer */ 981 bool control_td_set = 0; 982 983 while (1) { 984 TRBType type; 985 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); 986 le64_to_cpus(&trb.parameter); 987 le32_to_cpus(&trb.status); 988 le32_to_cpus(&trb.control); 989 990 if ((trb.control & TRB_C) != ccs) { 991 return -length; 992 } 993 994 type = TRB_TYPE(trb); 995 996 if (type == TR_LINK) { 997 dequeue = xhci_mask64(trb.parameter); 998 if (trb.control & TRB_LK_TC) { 999 ccs = !ccs; 1000 } 1001 continue; 1002 } 1003 1004 length += 1; 1005 dequeue += TRB_SIZE; 1006 1007 if (type == TR_SETUP) { 1008 control_td_set = 1; 1009 } else if (type == TR_STATUS) { 1010 control_td_set = 0; 1011 } 1012 1013 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1014 return length; 1015 } 1016 } 1017 } 1018 1019 static void xhci_er_reset(XHCIState *xhci, int v) 1020 { 1021 XHCIInterrupter *intr = &xhci->intr[v]; 1022 XHCIEvRingSeg seg; 1023 1024 if (intr->erstsz == 0) { 1025 /* disabled */ 1026 intr->er_start = 0; 1027 intr->er_size = 0; 1028 return; 1029 } 1030 /* cache the (sole) event ring segment location */ 1031 if (intr->erstsz != 1) { 1032 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1033 xhci_die(xhci); 1034 return; 1035 } 1036 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1037 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); 1038 le32_to_cpus(&seg.addr_low); 1039 le32_to_cpus(&seg.addr_high); 1040 le32_to_cpus(&seg.size); 1041 if (seg.size < 16 || seg.size > 4096) { 1042 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); 1043 xhci_die(xhci); 1044 return; 1045 } 1046 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1047 intr->er_size = seg.size; 1048 1049 intr->er_ep_idx = 0; 1050 intr->er_pcs = 1; 1051 intr->er_full = 0; 1052 1053 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1054 v, intr->er_start, intr->er_size); 1055 } 1056 1057 static void xhci_run(XHCIState *xhci) 1058 { 1059 trace_usb_xhci_run(); 1060 xhci->usbsts &= ~USBSTS_HCH; 1061 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 1062 } 1063 1064 static void xhci_stop(XHCIState *xhci) 1065 { 1066 trace_usb_xhci_stop(); 1067 xhci->usbsts |= USBSTS_HCH; 1068 xhci->crcr_low &= ~CRCR_CRR; 1069 } 1070 1071 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1072 uint32_t state) 1073 { 1074 uint32_t ctx[5]; 1075 1076 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1077 ctx[0] &= ~EP_STATE_MASK; 1078 ctx[0] |= state; 1079 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; 1080 ctx[3] = (epctx->ring.dequeue >> 16) >> 16; 1081 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1082 epctx->pctx, state, ctx[3], ctx[2]); 1083 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1084 epctx->state = state; 1085 } 1086 1087 static void xhci_ep_kick_timer(void *opaque) 1088 { 1089 XHCIEPContext *epctx = opaque; 1090 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid); 1091 } 1092 1093 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1094 unsigned int epid, dma_addr_t pctx, 1095 uint32_t *ctx) 1096 { 1097 XHCISlot *slot; 1098 XHCIEPContext *epctx; 1099 dma_addr_t dequeue; 1100 int i; 1101 1102 trace_usb_xhci_ep_enable(slotid, epid); 1103 assert(slotid >= 1 && slotid <= xhci->numslots); 1104 assert(epid >= 1 && epid <= 31); 1105 1106 slot = &xhci->slots[slotid-1]; 1107 if (slot->eps[epid-1]) { 1108 xhci_disable_ep(xhci, slotid, epid); 1109 } 1110 1111 epctx = g_malloc(sizeof(XHCIEPContext)); 1112 memset(epctx, 0, sizeof(XHCIEPContext)); 1113 epctx->xhci = xhci; 1114 epctx->slotid = slotid; 1115 epctx->epid = epid; 1116 1117 slot->eps[epid-1] = epctx; 1118 1119 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1120 xhci_ring_init(xhci, &epctx->ring, dequeue); 1121 epctx->ring.ccs = ctx[2] & 1; 1122 1123 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1124 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); 1125 epctx->pctx = pctx; 1126 epctx->max_psize = ctx[1]>>16; 1127 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1128 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", 1129 epid/2, epid%2, epctx->max_psize); 1130 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { 1131 usb_packet_init(&epctx->transfers[i].packet); 1132 } 1133 1134 epctx->interval = 1 << (ctx[0] >> 16) & 0xff; 1135 epctx->mfindex_last = 0; 1136 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); 1137 1138 epctx->state = EP_RUNNING; 1139 ctx[0] &= ~EP_STATE_MASK; 1140 ctx[0] |= EP_RUNNING; 1141 1142 return CC_SUCCESS; 1143 } 1144 1145 static int xhci_ep_nuke_one_xfer(XHCITransfer *t) 1146 { 1147 int killed = 0; 1148 1149 if (t->running_async) { 1150 usb_cancel_packet(&t->packet); 1151 t->running_async = 0; 1152 t->cancelled = 1; 1153 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); 1154 killed = 1; 1155 } 1156 if (t->running_retry) { 1157 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; 1158 if (epctx) { 1159 epctx->retry = NULL; 1160 qemu_del_timer(epctx->kick_timer); 1161 } 1162 t->running_retry = 0; 1163 } 1164 if (t->trbs) { 1165 g_free(t->trbs); 1166 } 1167 1168 t->trbs = NULL; 1169 t->trb_count = t->trb_alloced = 0; 1170 1171 return killed; 1172 } 1173 1174 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1175 unsigned int epid) 1176 { 1177 XHCISlot *slot; 1178 XHCIEPContext *epctx; 1179 int i, xferi, killed = 0; 1180 assert(slotid >= 1 && slotid <= xhci->numslots); 1181 assert(epid >= 1 && epid <= 31); 1182 1183 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1184 1185 slot = &xhci->slots[slotid-1]; 1186 1187 if (!slot->eps[epid-1]) { 1188 return 0; 1189 } 1190 1191 epctx = slot->eps[epid-1]; 1192 1193 xferi = epctx->next_xfer; 1194 for (i = 0; i < TD_QUEUE; i++) { 1195 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); 1196 xferi = (xferi + 1) % TD_QUEUE; 1197 } 1198 return killed; 1199 } 1200 1201 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1202 unsigned int epid) 1203 { 1204 XHCISlot *slot; 1205 XHCIEPContext *epctx; 1206 1207 trace_usb_xhci_ep_disable(slotid, epid); 1208 assert(slotid >= 1 && slotid <= xhci->numslots); 1209 assert(epid >= 1 && epid <= 31); 1210 1211 slot = &xhci->slots[slotid-1]; 1212 1213 if (!slot->eps[epid-1]) { 1214 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1215 return CC_SUCCESS; 1216 } 1217 1218 xhci_ep_nuke_xfers(xhci, slotid, epid); 1219 1220 epctx = slot->eps[epid-1]; 1221 1222 xhci_set_ep_state(xhci, epctx, EP_DISABLED); 1223 1224 qemu_free_timer(epctx->kick_timer); 1225 g_free(epctx); 1226 slot->eps[epid-1] = NULL; 1227 1228 return CC_SUCCESS; 1229 } 1230 1231 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1232 unsigned int epid) 1233 { 1234 XHCISlot *slot; 1235 XHCIEPContext *epctx; 1236 1237 trace_usb_xhci_ep_stop(slotid, epid); 1238 assert(slotid >= 1 && slotid <= xhci->numslots); 1239 1240 if (epid < 1 || epid > 31) { 1241 fprintf(stderr, "xhci: bad ep %d\n", epid); 1242 return CC_TRB_ERROR; 1243 } 1244 1245 slot = &xhci->slots[slotid-1]; 1246 1247 if (!slot->eps[epid-1]) { 1248 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1249 return CC_EP_NOT_ENABLED_ERROR; 1250 } 1251 1252 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1253 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " 1254 "data might be lost\n"); 1255 } 1256 1257 epctx = slot->eps[epid-1]; 1258 1259 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1260 1261 return CC_SUCCESS; 1262 } 1263 1264 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1265 unsigned int epid) 1266 { 1267 XHCISlot *slot; 1268 XHCIEPContext *epctx; 1269 USBDevice *dev; 1270 1271 trace_usb_xhci_ep_reset(slotid, epid); 1272 assert(slotid >= 1 && slotid <= xhci->numslots); 1273 1274 if (epid < 1 || epid > 31) { 1275 fprintf(stderr, "xhci: bad ep %d\n", epid); 1276 return CC_TRB_ERROR; 1277 } 1278 1279 slot = &xhci->slots[slotid-1]; 1280 1281 if (!slot->eps[epid-1]) { 1282 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1283 return CC_EP_NOT_ENABLED_ERROR; 1284 } 1285 1286 epctx = slot->eps[epid-1]; 1287 1288 if (epctx->state != EP_HALTED) { 1289 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", 1290 epid, epctx->state); 1291 return CC_CONTEXT_STATE_ERROR; 1292 } 1293 1294 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { 1295 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " 1296 "data might be lost\n"); 1297 } 1298 1299 uint8_t ep = epid>>1; 1300 1301 if (epid & 1) { 1302 ep |= 0x80; 1303 } 1304 1305 dev = xhci->slots[slotid-1].uport->dev; 1306 if (!dev) { 1307 return CC_USB_TRANSACTION_ERROR; 1308 } 1309 1310 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1311 1312 return CC_SUCCESS; 1313 } 1314 1315 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1316 unsigned int epid, uint64_t pdequeue) 1317 { 1318 XHCISlot *slot; 1319 XHCIEPContext *epctx; 1320 dma_addr_t dequeue; 1321 1322 assert(slotid >= 1 && slotid <= xhci->numslots); 1323 1324 if (epid < 1 || epid > 31) { 1325 fprintf(stderr, "xhci: bad ep %d\n", epid); 1326 return CC_TRB_ERROR; 1327 } 1328 1329 trace_usb_xhci_ep_set_dequeue(slotid, epid, pdequeue); 1330 dequeue = xhci_mask64(pdequeue); 1331 1332 slot = &xhci->slots[slotid-1]; 1333 1334 if (!slot->eps[epid-1]) { 1335 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1336 return CC_EP_NOT_ENABLED_ERROR; 1337 } 1338 1339 epctx = slot->eps[epid-1]; 1340 1341 1342 if (epctx->state != EP_STOPPED) { 1343 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1344 return CC_CONTEXT_STATE_ERROR; 1345 } 1346 1347 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1348 epctx->ring.ccs = dequeue & 1; 1349 1350 xhci_set_ep_state(xhci, epctx, EP_STOPPED); 1351 1352 return CC_SUCCESS; 1353 } 1354 1355 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1356 { 1357 XHCIState *xhci = xfer->xhci; 1358 int i; 1359 1360 xfer->int_req = false; 1361 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); 1362 for (i = 0; i < xfer->trb_count; i++) { 1363 XHCITRB *trb = &xfer->trbs[i]; 1364 dma_addr_t addr; 1365 unsigned int chunk = 0; 1366 1367 if (trb->control & TRB_TR_IOC) { 1368 xfer->int_req = true; 1369 } 1370 1371 switch (TRB_TYPE(*trb)) { 1372 case TR_DATA: 1373 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1374 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); 1375 goto err; 1376 } 1377 /* fallthrough */ 1378 case TR_NORMAL: 1379 case TR_ISOCH: 1380 addr = xhci_mask64(trb->parameter); 1381 chunk = trb->status & 0x1ffff; 1382 if (trb->control & TRB_TR_IDT) { 1383 if (chunk > 8 || in_xfer) { 1384 fprintf(stderr, "xhci: invalid immediate data TRB\n"); 1385 goto err; 1386 } 1387 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1388 } else { 1389 qemu_sglist_add(&xfer->sgl, addr, chunk); 1390 } 1391 break; 1392 } 1393 } 1394 1395 return 0; 1396 1397 err: 1398 qemu_sglist_destroy(&xfer->sgl); 1399 xhci_die(xhci); 1400 return -1; 1401 } 1402 1403 static void xhci_xfer_unmap(XHCITransfer *xfer) 1404 { 1405 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1406 qemu_sglist_destroy(&xfer->sgl); 1407 } 1408 1409 static void xhci_xfer_report(XHCITransfer *xfer) 1410 { 1411 uint32_t edtla = 0; 1412 unsigned int left; 1413 bool reported = 0; 1414 bool shortpkt = 0; 1415 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1416 XHCIState *xhci = xfer->xhci; 1417 int i; 1418 1419 left = xfer->packet.actual_length; 1420 1421 for (i = 0; i < xfer->trb_count; i++) { 1422 XHCITRB *trb = &xfer->trbs[i]; 1423 unsigned int chunk = 0; 1424 1425 switch (TRB_TYPE(*trb)) { 1426 case TR_DATA: 1427 case TR_NORMAL: 1428 case TR_ISOCH: 1429 chunk = trb->status & 0x1ffff; 1430 if (chunk > left) { 1431 chunk = left; 1432 if (xfer->status == CC_SUCCESS) { 1433 shortpkt = 1; 1434 } 1435 } 1436 left -= chunk; 1437 edtla += chunk; 1438 break; 1439 case TR_STATUS: 1440 reported = 0; 1441 shortpkt = 0; 1442 break; 1443 } 1444 1445 if (!reported && ((trb->control & TRB_TR_IOC) || 1446 (shortpkt && (trb->control & TRB_TR_ISP)) || 1447 (xfer->status != CC_SUCCESS && left == 0))) { 1448 event.slotid = xfer->slotid; 1449 event.epid = xfer->epid; 1450 event.length = (trb->status & 0x1ffff) - chunk; 1451 event.flags = 0; 1452 event.ptr = trb->addr; 1453 if (xfer->status == CC_SUCCESS) { 1454 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1455 } else { 1456 event.ccode = xfer->status; 1457 } 1458 if (TRB_TYPE(*trb) == TR_EVDATA) { 1459 event.ptr = trb->parameter; 1460 event.flags |= TRB_EV_ED; 1461 event.length = edtla & 0xffffff; 1462 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1463 edtla = 0; 1464 } 1465 xhci_event(xhci, &event, TRB_INTR(*trb)); 1466 reported = 1; 1467 if (xfer->status != CC_SUCCESS) { 1468 return; 1469 } 1470 } 1471 } 1472 } 1473 1474 static void xhci_stall_ep(XHCITransfer *xfer) 1475 { 1476 XHCIState *xhci = xfer->xhci; 1477 XHCISlot *slot = &xhci->slots[xfer->slotid-1]; 1478 XHCIEPContext *epctx = slot->eps[xfer->epid-1]; 1479 1480 epctx->ring.dequeue = xfer->trbs[0].addr; 1481 epctx->ring.ccs = xfer->trbs[0].ccs; 1482 xhci_set_ep_state(xhci, epctx, EP_HALTED); 1483 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid); 1484 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue); 1485 } 1486 1487 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1488 XHCIEPContext *epctx); 1489 1490 static int xhci_setup_packet(XHCITransfer *xfer) 1491 { 1492 XHCIState *xhci = xfer->xhci; 1493 USBDevice *dev; 1494 USBEndpoint *ep; 1495 int dir; 1496 1497 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1498 1499 if (xfer->packet.ep) { 1500 ep = xfer->packet.ep; 1501 dev = ep->dev; 1502 } else { 1503 if (!xhci->slots[xfer->slotid-1].uport) { 1504 fprintf(stderr, "xhci: slot %d has no device\n", 1505 xfer->slotid); 1506 return -1; 1507 } 1508 dev = xhci->slots[xfer->slotid-1].uport->dev; 1509 ep = usb_ep_get(dev, dir, xfer->epid >> 1); 1510 } 1511 1512 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1513 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr, false, 1514 xfer->int_req); 1515 usb_packet_map(&xfer->packet, &xfer->sgl); 1516 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1517 xfer->packet.pid, dev->addr, ep->nr); 1518 return 0; 1519 } 1520 1521 static int xhci_complete_packet(XHCITransfer *xfer) 1522 { 1523 if (xfer->packet.status == USB_RET_ASYNC) { 1524 trace_usb_xhci_xfer_async(xfer); 1525 xfer->running_async = 1; 1526 xfer->running_retry = 0; 1527 xfer->complete = 0; 1528 xfer->cancelled = 0; 1529 return 0; 1530 } else if (xfer->packet.status == USB_RET_NAK) { 1531 trace_usb_xhci_xfer_nak(xfer); 1532 xfer->running_async = 0; 1533 xfer->running_retry = 1; 1534 xfer->complete = 0; 1535 xfer->cancelled = 0; 1536 return 0; 1537 } else { 1538 xfer->running_async = 0; 1539 xfer->running_retry = 0; 1540 xfer->complete = 1; 1541 xhci_xfer_unmap(xfer); 1542 } 1543 1544 if (xfer->packet.status == USB_RET_SUCCESS) { 1545 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1546 xfer->status = CC_SUCCESS; 1547 xhci_xfer_report(xfer); 1548 return 0; 1549 } 1550 1551 /* error */ 1552 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1553 switch (xfer->packet.status) { 1554 case USB_RET_NODEV: 1555 xfer->status = CC_USB_TRANSACTION_ERROR; 1556 xhci_xfer_report(xfer); 1557 xhci_stall_ep(xfer); 1558 break; 1559 case USB_RET_STALL: 1560 xfer->status = CC_STALL_ERROR; 1561 xhci_xfer_report(xfer); 1562 xhci_stall_ep(xfer); 1563 break; 1564 default: 1565 fprintf(stderr, "%s: FIXME: status = %d\n", __func__, 1566 xfer->packet.status); 1567 FIXME(); 1568 } 1569 return 0; 1570 } 1571 1572 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1573 { 1574 XHCITRB *trb_setup, *trb_status; 1575 uint8_t bmRequestType; 1576 1577 trb_setup = &xfer->trbs[0]; 1578 trb_status = &xfer->trbs[xfer->trb_count-1]; 1579 1580 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1581 1582 /* at most one Event Data TRB allowed after STATUS */ 1583 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1584 trb_status--; 1585 } 1586 1587 /* do some sanity checks */ 1588 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1589 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", 1590 TRB_TYPE(*trb_setup)); 1591 return -1; 1592 } 1593 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1594 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", 1595 TRB_TYPE(*trb_status)); 1596 return -1; 1597 } 1598 if (!(trb_setup->control & TRB_TR_IDT)) { 1599 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); 1600 return -1; 1601 } 1602 if ((trb_setup->status & 0x1ffff) != 8) { 1603 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", 1604 (trb_setup->status & 0x1ffff)); 1605 return -1; 1606 } 1607 1608 bmRequestType = trb_setup->parameter; 1609 1610 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1611 xfer->iso_xfer = false; 1612 1613 if (xhci_setup_packet(xfer) < 0) { 1614 return -1; 1615 } 1616 xfer->packet.parameter = trb_setup->parameter; 1617 1618 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1619 1620 xhci_complete_packet(xfer); 1621 if (!xfer->running_async && !xfer->running_retry) { 1622 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1623 } 1624 return 0; 1625 } 1626 1627 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1628 XHCIEPContext *epctx, uint64_t mfindex) 1629 { 1630 if (xfer->trbs[0].control & TRB_TR_SIA) { 1631 uint64_t asap = ((mfindex + epctx->interval - 1) & 1632 ~(epctx->interval-1)); 1633 if (asap >= epctx->mfindex_last && 1634 asap <= epctx->mfindex_last + epctx->interval * 4) { 1635 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1636 } else { 1637 xfer->mfindex_kick = asap; 1638 } 1639 } else { 1640 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1641 & TRB_TR_FRAMEID_MASK; 1642 xfer->mfindex_kick |= mfindex & ~0x3fff; 1643 if (xfer->mfindex_kick < mfindex) { 1644 xfer->mfindex_kick += 0x4000; 1645 } 1646 } 1647 } 1648 1649 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1650 XHCIEPContext *epctx, uint64_t mfindex) 1651 { 1652 if (xfer->mfindex_kick > mfindex) { 1653 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + 1654 (xfer->mfindex_kick - mfindex) * 125000); 1655 xfer->running_retry = 1; 1656 } else { 1657 epctx->mfindex_last = xfer->mfindex_kick; 1658 qemu_del_timer(epctx->kick_timer); 1659 xfer->running_retry = 0; 1660 } 1661 } 1662 1663 1664 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1665 { 1666 uint64_t mfindex; 1667 1668 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1669 1670 xfer->in_xfer = epctx->type>>2; 1671 1672 switch(epctx->type) { 1673 case ET_INTR_OUT: 1674 case ET_INTR_IN: 1675 case ET_BULK_OUT: 1676 case ET_BULK_IN: 1677 xfer->pkts = 0; 1678 xfer->iso_xfer = false; 1679 break; 1680 case ET_ISO_OUT: 1681 case ET_ISO_IN: 1682 xfer->pkts = 1; 1683 xfer->iso_xfer = true; 1684 mfindex = xhci_mfindex_get(xhci); 1685 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 1686 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1687 if (xfer->running_retry) { 1688 return -1; 1689 } 1690 break; 1691 default: 1692 fprintf(stderr, "xhci: unknown or unhandled EP " 1693 "(type %d, in %d, ep %02x)\n", 1694 epctx->type, xfer->in_xfer, xfer->epid); 1695 return -1; 1696 } 1697 1698 if (xhci_setup_packet(xfer) < 0) { 1699 return -1; 1700 } 1701 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1702 1703 xhci_complete_packet(xfer); 1704 if (!xfer->running_async && !xfer->running_retry) { 1705 xhci_kick_ep(xhci, xfer->slotid, xfer->epid); 1706 } 1707 return 0; 1708 } 1709 1710 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1711 { 1712 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid); 1713 return xhci_submit(xhci, xfer, epctx); 1714 } 1715 1716 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid) 1717 { 1718 XHCIEPContext *epctx; 1719 USBEndpoint *ep = NULL; 1720 uint64_t mfindex; 1721 int length; 1722 int i; 1723 1724 trace_usb_xhci_ep_kick(slotid, epid); 1725 assert(slotid >= 1 && slotid <= xhci->numslots); 1726 assert(epid >= 1 && epid <= 31); 1727 1728 if (!xhci->slots[slotid-1].enabled) { 1729 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); 1730 return; 1731 } 1732 epctx = xhci->slots[slotid-1].eps[epid-1]; 1733 if (!epctx) { 1734 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 1735 epid, slotid); 1736 return; 1737 } 1738 1739 if (epctx->retry) { 1740 XHCITransfer *xfer = epctx->retry; 1741 1742 trace_usb_xhci_xfer_retry(xfer); 1743 assert(xfer->running_retry); 1744 if (xfer->iso_xfer) { 1745 /* retry delayed iso transfer */ 1746 mfindex = xhci_mfindex_get(xhci); 1747 xhci_check_iso_kick(xhci, xfer, epctx, mfindex); 1748 if (xfer->running_retry) { 1749 return; 1750 } 1751 if (xhci_setup_packet(xfer) < 0) { 1752 return; 1753 } 1754 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1755 assert(xfer->packet.status != USB_RET_NAK); 1756 xhci_complete_packet(xfer); 1757 } else { 1758 /* retry nak'ed transfer */ 1759 if (xhci_setup_packet(xfer) < 0) { 1760 return; 1761 } 1762 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1763 if (xfer->packet.status == USB_RET_NAK) { 1764 return; 1765 } 1766 xhci_complete_packet(xfer); 1767 } 1768 assert(!xfer->running_retry); 1769 epctx->retry = NULL; 1770 } 1771 1772 if (epctx->state == EP_HALTED) { 1773 DPRINTF("xhci: ep halted, not running schedule\n"); 1774 return; 1775 } 1776 1777 xhci_set_ep_state(xhci, epctx, EP_RUNNING); 1778 1779 while (1) { 1780 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; 1781 if (xfer->running_async || xfer->running_retry) { 1782 break; 1783 } 1784 length = xhci_ring_chain_length(xhci, &epctx->ring); 1785 if (length < 0) { 1786 break; 1787 } else if (length == 0) { 1788 break; 1789 } 1790 if (xfer->trbs && xfer->trb_alloced < length) { 1791 xfer->trb_count = 0; 1792 xfer->trb_alloced = 0; 1793 g_free(xfer->trbs); 1794 xfer->trbs = NULL; 1795 } 1796 if (!xfer->trbs) { 1797 xfer->trbs = g_malloc(sizeof(XHCITRB) * length); 1798 xfer->trb_alloced = length; 1799 } 1800 xfer->trb_count = length; 1801 1802 for (i = 0; i < length; i++) { 1803 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL)); 1804 } 1805 xfer->xhci = xhci; 1806 xfer->epid = epid; 1807 xfer->slotid = slotid; 1808 1809 if (epid == 1) { 1810 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { 1811 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1812 ep = xfer->packet.ep; 1813 } else { 1814 fprintf(stderr, "xhci: error firing CTL transfer\n"); 1815 } 1816 } else { 1817 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { 1818 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; 1819 ep = xfer->packet.ep; 1820 } else { 1821 if (!xfer->iso_xfer) { 1822 fprintf(stderr, "xhci: error firing data transfer\n"); 1823 } 1824 } 1825 } 1826 1827 if (epctx->state == EP_HALTED) { 1828 break; 1829 } 1830 if (xfer->running_retry) { 1831 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 1832 epctx->retry = xfer; 1833 break; 1834 } 1835 } 1836 if (ep) { 1837 usb_device_flush_ep_queue(ep->dev, ep); 1838 } 1839 } 1840 1841 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 1842 { 1843 trace_usb_xhci_slot_enable(slotid); 1844 assert(slotid >= 1 && slotid <= xhci->numslots); 1845 xhci->slots[slotid-1].enabled = 1; 1846 xhci->slots[slotid-1].uport = NULL; 1847 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 1848 1849 return CC_SUCCESS; 1850 } 1851 1852 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 1853 { 1854 int i; 1855 1856 trace_usb_xhci_slot_disable(slotid); 1857 assert(slotid >= 1 && slotid <= xhci->numslots); 1858 1859 for (i = 1; i <= 31; i++) { 1860 if (xhci->slots[slotid-1].eps[i-1]) { 1861 xhci_disable_ep(xhci, slotid, i); 1862 } 1863 } 1864 1865 xhci->slots[slotid-1].enabled = 0; 1866 return CC_SUCCESS; 1867 } 1868 1869 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 1870 { 1871 USBPort *uport; 1872 char path[32]; 1873 int i, pos, port; 1874 1875 port = (slot_ctx[1]>>16) & 0xFF; 1876 port = xhci->ports[port-1].uport->index+1; 1877 pos = snprintf(path, sizeof(path), "%d", port); 1878 for (i = 0; i < 5; i++) { 1879 port = (slot_ctx[0] >> 4*i) & 0x0f; 1880 if (!port) { 1881 break; 1882 } 1883 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 1884 } 1885 1886 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 1887 if (strcmp(uport->path, path) == 0) { 1888 return uport; 1889 } 1890 } 1891 return NULL; 1892 } 1893 1894 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 1895 uint64_t pictx, bool bsr) 1896 { 1897 XHCISlot *slot; 1898 USBPort *uport; 1899 USBDevice *dev; 1900 dma_addr_t ictx, octx, dcbaap; 1901 uint64_t poctx; 1902 uint32_t ictl_ctx[2]; 1903 uint32_t slot_ctx[4]; 1904 uint32_t ep0_ctx[5]; 1905 int i; 1906 TRBCCode res; 1907 1908 trace_usb_xhci_slot_address(slotid); 1909 assert(slotid >= 1 && slotid <= xhci->numslots); 1910 1911 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 1912 poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid); 1913 ictx = xhci_mask64(pictx); 1914 octx = xhci_mask64(poctx); 1915 1916 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 1917 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 1918 1919 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 1920 1921 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 1922 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 1923 ictl_ctx[0], ictl_ctx[1]); 1924 return CC_TRB_ERROR; 1925 } 1926 1927 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 1928 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 1929 1930 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 1931 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1932 1933 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 1934 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1935 1936 uport = xhci_lookup_uport(xhci, slot_ctx); 1937 if (uport == NULL) { 1938 fprintf(stderr, "xhci: port not found\n"); 1939 return CC_TRB_ERROR; 1940 } 1941 1942 dev = uport->dev; 1943 if (!dev) { 1944 fprintf(stderr, "xhci: port %s not connected\n", uport->path); 1945 return CC_USB_TRANSACTION_ERROR; 1946 } 1947 1948 for (i = 0; i < xhci->numslots; i++) { 1949 if (i == slotid-1) { 1950 continue; 1951 } 1952 if (xhci->slots[i].uport == uport) { 1953 fprintf(stderr, "xhci: port %s already assigned to slot %d\n", 1954 uport->path, i+1); 1955 return CC_TRB_ERROR; 1956 } 1957 } 1958 1959 slot = &xhci->slots[slotid-1]; 1960 slot->uport = uport; 1961 slot->ctx = octx; 1962 1963 if (bsr) { 1964 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 1965 } else { 1966 slot->devaddr = xhci->devaddr++; 1967 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; 1968 DPRINTF("xhci: device address is %d\n", slot->devaddr); 1969 usb_device_reset(dev); 1970 usb_device_handle_control(dev, NULL, 1971 DeviceOutRequest | USB_REQ_SET_ADDRESS, 1972 slot->devaddr, 0, 0, NULL); 1973 } 1974 1975 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 1976 1977 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 1978 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 1979 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 1980 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 1981 1982 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 1983 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 1984 1985 return res; 1986 } 1987 1988 1989 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 1990 uint64_t pictx, bool dc) 1991 { 1992 dma_addr_t ictx, octx; 1993 uint32_t ictl_ctx[2]; 1994 uint32_t slot_ctx[4]; 1995 uint32_t islot_ctx[4]; 1996 uint32_t ep_ctx[5]; 1997 int i; 1998 TRBCCode res; 1999 2000 trace_usb_xhci_slot_configure(slotid); 2001 assert(slotid >= 1 && slotid <= xhci->numslots); 2002 2003 ictx = xhci_mask64(pictx); 2004 octx = xhci->slots[slotid-1].ctx; 2005 2006 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2007 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2008 2009 if (dc) { 2010 for (i = 2; i <= 31; i++) { 2011 if (xhci->slots[slotid-1].eps[i-1]) { 2012 xhci_disable_ep(xhci, slotid, i); 2013 } 2014 } 2015 2016 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2017 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2018 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2019 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2020 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2021 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2022 2023 return CC_SUCCESS; 2024 } 2025 2026 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2027 2028 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2029 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2030 ictl_ctx[0], ictl_ctx[1]); 2031 return CC_TRB_ERROR; 2032 } 2033 2034 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2035 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2036 2037 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2038 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); 2039 return CC_CONTEXT_STATE_ERROR; 2040 } 2041 2042 for (i = 2; i <= 31; i++) { 2043 if (ictl_ctx[0] & (1<<i)) { 2044 xhci_disable_ep(xhci, slotid, i); 2045 } 2046 if (ictl_ctx[1] & (1<<i)) { 2047 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2048 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2049 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2050 ep_ctx[3], ep_ctx[4]); 2051 xhci_disable_ep(xhci, slotid, i); 2052 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2053 if (res != CC_SUCCESS) { 2054 return res; 2055 } 2056 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2057 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2058 ep_ctx[3], ep_ctx[4]); 2059 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2060 } 2061 } 2062 2063 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2064 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2065 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2066 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2067 SLOT_CONTEXT_ENTRIES_SHIFT); 2068 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2069 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2070 2071 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2072 2073 return CC_SUCCESS; 2074 } 2075 2076 2077 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2078 uint64_t pictx) 2079 { 2080 dma_addr_t ictx, octx; 2081 uint32_t ictl_ctx[2]; 2082 uint32_t iep0_ctx[5]; 2083 uint32_t ep0_ctx[5]; 2084 uint32_t islot_ctx[4]; 2085 uint32_t slot_ctx[4]; 2086 2087 trace_usb_xhci_slot_evaluate(slotid); 2088 assert(slotid >= 1 && slotid <= xhci->numslots); 2089 2090 ictx = xhci_mask64(pictx); 2091 octx = xhci->slots[slotid-1].ctx; 2092 2093 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2094 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2095 2096 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2097 2098 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2099 fprintf(stderr, "xhci: invalid input context control %08x %08x\n", 2100 ictl_ctx[0], ictl_ctx[1]); 2101 return CC_TRB_ERROR; 2102 } 2103 2104 if (ictl_ctx[1] & 0x1) { 2105 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2106 2107 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2108 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2109 2110 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2111 2112 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2113 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2114 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2115 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2116 2117 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2118 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2119 2120 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2121 } 2122 2123 if (ictl_ctx[1] & 0x2) { 2124 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2125 2126 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2127 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2128 iep0_ctx[3], iep0_ctx[4]); 2129 2130 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2131 2132 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2133 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2134 2135 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2136 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2137 2138 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2139 } 2140 2141 return CC_SUCCESS; 2142 } 2143 2144 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2145 { 2146 uint32_t slot_ctx[4]; 2147 dma_addr_t octx; 2148 int i; 2149 2150 trace_usb_xhci_slot_reset(slotid); 2151 assert(slotid >= 1 && slotid <= xhci->numslots); 2152 2153 octx = xhci->slots[slotid-1].ctx; 2154 2155 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2156 2157 for (i = 2; i <= 31; i++) { 2158 if (xhci->slots[slotid-1].eps[i-1]) { 2159 xhci_disable_ep(xhci, slotid, i); 2160 } 2161 } 2162 2163 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2164 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2165 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2166 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2167 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2168 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2169 2170 return CC_SUCCESS; 2171 } 2172 2173 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2174 { 2175 unsigned int slotid; 2176 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2177 if (slotid < 1 || slotid > xhci->numslots) { 2178 fprintf(stderr, "xhci: bad slot id %d\n", slotid); 2179 event->ccode = CC_TRB_ERROR; 2180 return 0; 2181 } else if (!xhci->slots[slotid-1].enabled) { 2182 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); 2183 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2184 return 0; 2185 } 2186 return slotid; 2187 } 2188 2189 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2190 { 2191 dma_addr_t ctx; 2192 uint8_t bw_ctx[xhci->numports+1]; 2193 2194 DPRINTF("xhci_get_port_bandwidth()\n"); 2195 2196 ctx = xhci_mask64(pctx); 2197 2198 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2199 2200 /* TODO: actually implement real values here */ 2201 bw_ctx[0] = 0; 2202 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2203 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); 2204 2205 return CC_SUCCESS; 2206 } 2207 2208 static uint32_t rotl(uint32_t v, unsigned count) 2209 { 2210 count &= 31; 2211 return (v << count) | (v >> (32 - count)); 2212 } 2213 2214 2215 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2216 { 2217 uint32_t val; 2218 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2219 val += rotl(lo + 0x49434878, hi & 0x1F); 2220 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2221 return ~val; 2222 } 2223 2224 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) 2225 { 2226 uint32_t buf[8]; 2227 uint32_t obuf[8]; 2228 dma_addr_t paddr = xhci_mask64(addr); 2229 2230 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); 2231 2232 memcpy(obuf, buf, sizeof(obuf)); 2233 2234 if ((buf[0] & 0xff) == 2) { 2235 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; 2236 obuf[0] |= (buf[2] * buf[3]) & 0xff; 2237 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; 2238 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; 2239 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; 2240 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; 2241 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; 2242 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; 2243 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; 2244 } 2245 2246 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); 2247 } 2248 2249 static void xhci_process_commands(XHCIState *xhci) 2250 { 2251 XHCITRB trb; 2252 TRBType type; 2253 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2254 dma_addr_t addr; 2255 unsigned int i, slotid = 0; 2256 2257 DPRINTF("xhci_process_commands()\n"); 2258 if (!xhci_running(xhci)) { 2259 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2260 return; 2261 } 2262 2263 xhci->crcr_low |= CRCR_CRR; 2264 2265 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2266 event.ptr = addr; 2267 switch (type) { 2268 case CR_ENABLE_SLOT: 2269 for (i = 0; i < xhci->numslots; i++) { 2270 if (!xhci->slots[i].enabled) { 2271 break; 2272 } 2273 } 2274 if (i >= xhci->numslots) { 2275 fprintf(stderr, "xhci: no device slots available\n"); 2276 event.ccode = CC_NO_SLOTS_ERROR; 2277 } else { 2278 slotid = i+1; 2279 event.ccode = xhci_enable_slot(xhci, slotid); 2280 } 2281 break; 2282 case CR_DISABLE_SLOT: 2283 slotid = xhci_get_slot(xhci, &event, &trb); 2284 if (slotid) { 2285 event.ccode = xhci_disable_slot(xhci, slotid); 2286 } 2287 break; 2288 case CR_ADDRESS_DEVICE: 2289 slotid = xhci_get_slot(xhci, &event, &trb); 2290 if (slotid) { 2291 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2292 trb.control & TRB_CR_BSR); 2293 } 2294 break; 2295 case CR_CONFIGURE_ENDPOINT: 2296 slotid = xhci_get_slot(xhci, &event, &trb); 2297 if (slotid) { 2298 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2299 trb.control & TRB_CR_DC); 2300 } 2301 break; 2302 case CR_EVALUATE_CONTEXT: 2303 slotid = xhci_get_slot(xhci, &event, &trb); 2304 if (slotid) { 2305 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2306 } 2307 break; 2308 case CR_STOP_ENDPOINT: 2309 slotid = xhci_get_slot(xhci, &event, &trb); 2310 if (slotid) { 2311 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2312 & TRB_CR_EPID_MASK; 2313 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2314 } 2315 break; 2316 case CR_RESET_ENDPOINT: 2317 slotid = xhci_get_slot(xhci, &event, &trb); 2318 if (slotid) { 2319 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2320 & TRB_CR_EPID_MASK; 2321 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2322 } 2323 break; 2324 case CR_SET_TR_DEQUEUE: 2325 slotid = xhci_get_slot(xhci, &event, &trb); 2326 if (slotid) { 2327 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2328 & TRB_CR_EPID_MASK; 2329 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid, 2330 trb.parameter); 2331 } 2332 break; 2333 case CR_RESET_DEVICE: 2334 slotid = xhci_get_slot(xhci, &event, &trb); 2335 if (slotid) { 2336 event.ccode = xhci_reset_slot(xhci, slotid); 2337 } 2338 break; 2339 case CR_GET_PORT_BANDWIDTH: 2340 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2341 break; 2342 case CR_VENDOR_VIA_CHALLENGE_RESPONSE: 2343 xhci_via_challenge(xhci, trb.parameter); 2344 break; 2345 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2346 event.type = 48; /* NEC reply */ 2347 event.length = 0x3025; 2348 break; 2349 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2350 { 2351 uint32_t chi = trb.parameter >> 32; 2352 uint32_t clo = trb.parameter; 2353 uint32_t val = xhci_nec_challenge(chi, clo); 2354 event.length = val & 0xFFFF; 2355 event.epid = val >> 16; 2356 slotid = val >> 24; 2357 event.type = 48; /* NEC reply */ 2358 } 2359 break; 2360 default: 2361 fprintf(stderr, "xhci: unimplemented command %d\n", type); 2362 event.ccode = CC_TRB_ERROR; 2363 break; 2364 } 2365 event.slotid = slotid; 2366 xhci_event(xhci, &event, 0); 2367 } 2368 } 2369 2370 static bool xhci_port_have_device(XHCIPort *port) 2371 { 2372 if (!port->uport->dev || !port->uport->dev->attached) { 2373 return false; /* no device present */ 2374 } 2375 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2376 return false; /* speed mismatch */ 2377 } 2378 return true; 2379 } 2380 2381 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2382 { 2383 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2384 port->portnr << 24 }; 2385 2386 if ((port->portsc & bits) == bits) { 2387 return; 2388 } 2389 port->portsc |= bits; 2390 if (!xhci_running(port->xhci)) { 2391 return; 2392 } 2393 xhci_event(port->xhci, &ev, 0); 2394 } 2395 2396 static void xhci_port_update(XHCIPort *port, int is_detach) 2397 { 2398 uint32_t pls = PLS_RX_DETECT; 2399 2400 port->portsc = PORTSC_PP; 2401 if (!is_detach && xhci_port_have_device(port)) { 2402 port->portsc |= PORTSC_CCS; 2403 switch (port->uport->dev->speed) { 2404 case USB_SPEED_LOW: 2405 port->portsc |= PORTSC_SPEED_LOW; 2406 pls = PLS_POLLING; 2407 break; 2408 case USB_SPEED_FULL: 2409 port->portsc |= PORTSC_SPEED_FULL; 2410 pls = PLS_POLLING; 2411 break; 2412 case USB_SPEED_HIGH: 2413 port->portsc |= PORTSC_SPEED_HIGH; 2414 pls = PLS_POLLING; 2415 break; 2416 case USB_SPEED_SUPER: 2417 port->portsc |= PORTSC_SPEED_SUPER; 2418 port->portsc |= PORTSC_PED; 2419 pls = PLS_U0; 2420 break; 2421 } 2422 } 2423 set_field(&port->portsc, pls, PORTSC_PLS); 2424 trace_usb_xhci_port_link(port->portnr, pls); 2425 xhci_port_notify(port, PORTSC_CSC); 2426 } 2427 2428 static void xhci_port_reset(XHCIPort *port) 2429 { 2430 trace_usb_xhci_port_reset(port->portnr); 2431 2432 if (!xhci_port_have_device(port)) { 2433 return; 2434 } 2435 2436 usb_device_reset(port->uport->dev); 2437 2438 switch (port->uport->dev->speed) { 2439 case USB_SPEED_LOW: 2440 case USB_SPEED_FULL: 2441 case USB_SPEED_HIGH: 2442 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2443 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2444 port->portsc |= PORTSC_PED; 2445 break; 2446 } 2447 2448 port->portsc &= ~PORTSC_PR; 2449 xhci_port_notify(port, PORTSC_PRC); 2450 } 2451 2452 static void xhci_reset(DeviceState *dev) 2453 { 2454 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); 2455 int i; 2456 2457 trace_usb_xhci_reset(); 2458 if (!(xhci->usbsts & USBSTS_HCH)) { 2459 fprintf(stderr, "xhci: reset while running!\n"); 2460 } 2461 2462 xhci->usbcmd = 0; 2463 xhci->usbsts = USBSTS_HCH; 2464 xhci->dnctrl = 0; 2465 xhci->crcr_low = 0; 2466 xhci->crcr_high = 0; 2467 xhci->dcbaap_low = 0; 2468 xhci->dcbaap_high = 0; 2469 xhci->config = 0; 2470 xhci->devaddr = 2; 2471 2472 for (i = 0; i < xhci->numslots; i++) { 2473 xhci_disable_slot(xhci, i+1); 2474 } 2475 2476 for (i = 0; i < xhci->numports; i++) { 2477 xhci_port_update(xhci->ports + i, 0); 2478 } 2479 2480 for (i = 0; i < xhci->numintrs; i++) { 2481 xhci->intr[i].iman = 0; 2482 xhci->intr[i].imod = 0; 2483 xhci->intr[i].erstsz = 0; 2484 xhci->intr[i].erstba_low = 0; 2485 xhci->intr[i].erstba_high = 0; 2486 xhci->intr[i].erdp_low = 0; 2487 xhci->intr[i].erdp_high = 0; 2488 xhci->intr[i].msix_used = 0; 2489 2490 xhci->intr[i].er_ep_idx = 0; 2491 xhci->intr[i].er_pcs = 1; 2492 xhci->intr[i].er_full = 0; 2493 xhci->intr[i].ev_buffer_put = 0; 2494 xhci->intr[i].ev_buffer_get = 0; 2495 } 2496 2497 xhci->mfindex_start = qemu_get_clock_ns(vm_clock); 2498 xhci_mfwrap_update(xhci); 2499 } 2500 2501 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2502 { 2503 XHCIState *xhci = ptr; 2504 uint32_t ret; 2505 2506 switch (reg) { 2507 case 0x00: /* HCIVERSION, CAPLENGTH */ 2508 ret = 0x01000000 | LEN_CAP; 2509 break; 2510 case 0x04: /* HCSPARAMS 1 */ 2511 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2512 | (xhci->numintrs<<8) | xhci->numslots; 2513 break; 2514 case 0x08: /* HCSPARAMS 2 */ 2515 ret = 0x0000000f; 2516 break; 2517 case 0x0c: /* HCSPARAMS 3 */ 2518 ret = 0x00000000; 2519 break; 2520 case 0x10: /* HCCPARAMS */ 2521 if (sizeof(dma_addr_t) == 4) { 2522 ret = 0x00081000; 2523 } else { 2524 ret = 0x00081001; 2525 } 2526 break; 2527 case 0x14: /* DBOFF */ 2528 ret = OFF_DOORBELL; 2529 break; 2530 case 0x18: /* RTSOFF */ 2531 ret = OFF_RUNTIME; 2532 break; 2533 2534 /* extended capabilities */ 2535 case 0x20: /* Supported Protocol:00 */ 2536 ret = 0x02000402; /* USB 2.0 */ 2537 break; 2538 case 0x24: /* Supported Protocol:04 */ 2539 ret = 0x20425355; /* "USB " */ 2540 break; 2541 case 0x28: /* Supported Protocol:08 */ 2542 ret = 0x00000001 | (xhci->numports_2<<8); 2543 break; 2544 case 0x2c: /* Supported Protocol:0c */ 2545 ret = 0x00000000; /* reserved */ 2546 break; 2547 case 0x30: /* Supported Protocol:00 */ 2548 ret = 0x03000002; /* USB 3.0 */ 2549 break; 2550 case 0x34: /* Supported Protocol:04 */ 2551 ret = 0x20425355; /* "USB " */ 2552 break; 2553 case 0x38: /* Supported Protocol:08 */ 2554 ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); 2555 break; 2556 case 0x3c: /* Supported Protocol:0c */ 2557 ret = 0x00000000; /* reserved */ 2558 break; 2559 default: 2560 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", (int)reg); 2561 ret = 0; 2562 } 2563 2564 trace_usb_xhci_cap_read(reg, ret); 2565 return ret; 2566 } 2567 2568 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2569 { 2570 XHCIPort *port = ptr; 2571 uint32_t ret; 2572 2573 switch (reg) { 2574 case 0x00: /* PORTSC */ 2575 ret = port->portsc; 2576 break; 2577 case 0x04: /* PORTPMSC */ 2578 case 0x08: /* PORTLI */ 2579 ret = 0; 2580 break; 2581 case 0x0c: /* reserved */ 2582 default: 2583 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n", 2584 port->portnr, (uint32_t)reg); 2585 ret = 0; 2586 } 2587 2588 trace_usb_xhci_port_read(port->portnr, reg, ret); 2589 return ret; 2590 } 2591 2592 static void xhci_port_write(void *ptr, hwaddr reg, 2593 uint64_t val, unsigned size) 2594 { 2595 XHCIPort *port = ptr; 2596 uint32_t portsc; 2597 2598 trace_usb_xhci_port_write(port->portnr, reg, val); 2599 2600 switch (reg) { 2601 case 0x00: /* PORTSC */ 2602 portsc = port->portsc; 2603 /* write-1-to-clear bits*/ 2604 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 2605 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 2606 if (val & PORTSC_LWS) { 2607 /* overwrite PLS only when LWS=1 */ 2608 uint32_t pls = get_field(val, PORTSC_PLS); 2609 set_field(&portsc, pls, PORTSC_PLS); 2610 trace_usb_xhci_port_link(port->portnr, pls); 2611 } 2612 /* read/write bits */ 2613 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 2614 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 2615 port->portsc = portsc; 2616 /* write-1-to-start bits */ 2617 if (val & PORTSC_PR) { 2618 xhci_port_reset(port); 2619 } 2620 break; 2621 case 0x04: /* PORTPMSC */ 2622 case 0x08: /* PORTLI */ 2623 default: 2624 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n", 2625 port->portnr, (uint32_t)reg); 2626 } 2627 } 2628 2629 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 2630 { 2631 XHCIState *xhci = ptr; 2632 uint32_t ret; 2633 2634 switch (reg) { 2635 case 0x00: /* USBCMD */ 2636 ret = xhci->usbcmd; 2637 break; 2638 case 0x04: /* USBSTS */ 2639 ret = xhci->usbsts; 2640 break; 2641 case 0x08: /* PAGESIZE */ 2642 ret = 1; /* 4KiB */ 2643 break; 2644 case 0x14: /* DNCTRL */ 2645 ret = xhci->dnctrl; 2646 break; 2647 case 0x18: /* CRCR low */ 2648 ret = xhci->crcr_low & ~0xe; 2649 break; 2650 case 0x1c: /* CRCR high */ 2651 ret = xhci->crcr_high; 2652 break; 2653 case 0x30: /* DCBAAP low */ 2654 ret = xhci->dcbaap_low; 2655 break; 2656 case 0x34: /* DCBAAP high */ 2657 ret = xhci->dcbaap_high; 2658 break; 2659 case 0x38: /* CONFIG */ 2660 ret = xhci->config; 2661 break; 2662 default: 2663 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg); 2664 ret = 0; 2665 } 2666 2667 trace_usb_xhci_oper_read(reg, ret); 2668 return ret; 2669 } 2670 2671 static void xhci_oper_write(void *ptr, hwaddr reg, 2672 uint64_t val, unsigned size) 2673 { 2674 XHCIState *xhci = ptr; 2675 2676 trace_usb_xhci_oper_write(reg, val); 2677 2678 switch (reg) { 2679 case 0x00: /* USBCMD */ 2680 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 2681 xhci_run(xhci); 2682 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 2683 xhci_stop(xhci); 2684 } 2685 xhci->usbcmd = val & 0xc0f; 2686 xhci_mfwrap_update(xhci); 2687 if (val & USBCMD_HCRST) { 2688 xhci_reset(&xhci->pci_dev.qdev); 2689 } 2690 xhci_intx_update(xhci); 2691 break; 2692 2693 case 0x04: /* USBSTS */ 2694 /* these bits are write-1-to-clear */ 2695 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 2696 xhci_intx_update(xhci); 2697 break; 2698 2699 case 0x14: /* DNCTRL */ 2700 xhci->dnctrl = val & 0xffff; 2701 break; 2702 case 0x18: /* CRCR low */ 2703 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 2704 break; 2705 case 0x1c: /* CRCR high */ 2706 xhci->crcr_high = val; 2707 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 2708 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 2709 xhci->crcr_low &= ~CRCR_CRR; 2710 xhci_event(xhci, &event, 0); 2711 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 2712 } else { 2713 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 2714 xhci_ring_init(xhci, &xhci->cmd_ring, base); 2715 } 2716 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 2717 break; 2718 case 0x30: /* DCBAAP low */ 2719 xhci->dcbaap_low = val & 0xffffffc0; 2720 break; 2721 case 0x34: /* DCBAAP high */ 2722 xhci->dcbaap_high = val; 2723 break; 2724 case 0x38: /* CONFIG */ 2725 xhci->config = val & 0xff; 2726 break; 2727 default: 2728 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg); 2729 } 2730 } 2731 2732 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 2733 unsigned size) 2734 { 2735 XHCIState *xhci = ptr; 2736 uint32_t ret = 0; 2737 2738 if (reg < 0x20) { 2739 switch (reg) { 2740 case 0x00: /* MFINDEX */ 2741 ret = xhci_mfindex_get(xhci) & 0x3fff; 2742 break; 2743 default: 2744 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", 2745 (int)reg); 2746 break; 2747 } 2748 } else { 2749 int v = (reg - 0x20) / 0x20; 2750 XHCIInterrupter *intr = &xhci->intr[v]; 2751 switch (reg & 0x1f) { 2752 case 0x00: /* IMAN */ 2753 ret = intr->iman; 2754 break; 2755 case 0x04: /* IMOD */ 2756 ret = intr->imod; 2757 break; 2758 case 0x08: /* ERSTSZ */ 2759 ret = intr->erstsz; 2760 break; 2761 case 0x10: /* ERSTBA low */ 2762 ret = intr->erstba_low; 2763 break; 2764 case 0x14: /* ERSTBA high */ 2765 ret = intr->erstba_high; 2766 break; 2767 case 0x18: /* ERDP low */ 2768 ret = intr->erdp_low; 2769 break; 2770 case 0x1c: /* ERDP high */ 2771 ret = intr->erdp_high; 2772 break; 2773 } 2774 } 2775 2776 trace_usb_xhci_runtime_read(reg, ret); 2777 return ret; 2778 } 2779 2780 static void xhci_runtime_write(void *ptr, hwaddr reg, 2781 uint64_t val, unsigned size) 2782 { 2783 XHCIState *xhci = ptr; 2784 int v = (reg - 0x20) / 0x20; 2785 XHCIInterrupter *intr = &xhci->intr[v]; 2786 trace_usb_xhci_runtime_write(reg, val); 2787 2788 if (reg < 0x20) { 2789 fprintf(stderr, "%s: reg 0x%x unimplemented\n", __func__, (int)reg); 2790 return; 2791 } 2792 2793 switch (reg & 0x1f) { 2794 case 0x00: /* IMAN */ 2795 if (val & IMAN_IP) { 2796 intr->iman &= ~IMAN_IP; 2797 } 2798 intr->iman &= ~IMAN_IE; 2799 intr->iman |= val & IMAN_IE; 2800 if (v == 0) { 2801 xhci_intx_update(xhci); 2802 } 2803 xhci_msix_update(xhci, v); 2804 break; 2805 case 0x04: /* IMOD */ 2806 intr->imod = val; 2807 break; 2808 case 0x08: /* ERSTSZ */ 2809 intr->erstsz = val & 0xffff; 2810 break; 2811 case 0x10: /* ERSTBA low */ 2812 /* XXX NEC driver bug: it doesn't align this to 64 bytes 2813 intr->erstba_low = val & 0xffffffc0; */ 2814 intr->erstba_low = val & 0xfffffff0; 2815 break; 2816 case 0x14: /* ERSTBA high */ 2817 intr->erstba_high = val; 2818 xhci_er_reset(xhci, v); 2819 break; 2820 case 0x18: /* ERDP low */ 2821 if (val & ERDP_EHB) { 2822 intr->erdp_low &= ~ERDP_EHB; 2823 } 2824 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 2825 break; 2826 case 0x1c: /* ERDP high */ 2827 intr->erdp_high = val; 2828 xhci_events_update(xhci, v); 2829 break; 2830 default: 2831 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", 2832 (int)reg); 2833 } 2834 } 2835 2836 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 2837 unsigned size) 2838 { 2839 /* doorbells always read as 0 */ 2840 trace_usb_xhci_doorbell_read(reg, 0); 2841 return 0; 2842 } 2843 2844 static void xhci_doorbell_write(void *ptr, hwaddr reg, 2845 uint64_t val, unsigned size) 2846 { 2847 XHCIState *xhci = ptr; 2848 2849 trace_usb_xhci_doorbell_write(reg, val); 2850 2851 if (!xhci_running(xhci)) { 2852 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); 2853 return; 2854 } 2855 2856 reg >>= 2; 2857 2858 if (reg == 0) { 2859 if (val == 0) { 2860 xhci_process_commands(xhci); 2861 } else { 2862 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", 2863 (uint32_t)val); 2864 } 2865 } else { 2866 if (reg > xhci->numslots) { 2867 fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); 2868 } else if (val > 31) { 2869 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", 2870 (int)reg, (uint32_t)val); 2871 } else { 2872 xhci_kick_ep(xhci, reg, val); 2873 } 2874 } 2875 } 2876 2877 static const MemoryRegionOps xhci_cap_ops = { 2878 .read = xhci_cap_read, 2879 .valid.min_access_size = 1, 2880 .valid.max_access_size = 4, 2881 .impl.min_access_size = 4, 2882 .impl.max_access_size = 4, 2883 .endianness = DEVICE_LITTLE_ENDIAN, 2884 }; 2885 2886 static const MemoryRegionOps xhci_oper_ops = { 2887 .read = xhci_oper_read, 2888 .write = xhci_oper_write, 2889 .valid.min_access_size = 4, 2890 .valid.max_access_size = 4, 2891 .endianness = DEVICE_LITTLE_ENDIAN, 2892 }; 2893 2894 static const MemoryRegionOps xhci_port_ops = { 2895 .read = xhci_port_read, 2896 .write = xhci_port_write, 2897 .valid.min_access_size = 4, 2898 .valid.max_access_size = 4, 2899 .endianness = DEVICE_LITTLE_ENDIAN, 2900 }; 2901 2902 static const MemoryRegionOps xhci_runtime_ops = { 2903 .read = xhci_runtime_read, 2904 .write = xhci_runtime_write, 2905 .valid.min_access_size = 4, 2906 .valid.max_access_size = 4, 2907 .endianness = DEVICE_LITTLE_ENDIAN, 2908 }; 2909 2910 static const MemoryRegionOps xhci_doorbell_ops = { 2911 .read = xhci_doorbell_read, 2912 .write = xhci_doorbell_write, 2913 .valid.min_access_size = 4, 2914 .valid.max_access_size = 4, 2915 .endianness = DEVICE_LITTLE_ENDIAN, 2916 }; 2917 2918 static void xhci_attach(USBPort *usbport) 2919 { 2920 XHCIState *xhci = usbport->opaque; 2921 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2922 2923 xhci_port_update(port, 0); 2924 } 2925 2926 static void xhci_detach(USBPort *usbport) 2927 { 2928 XHCIState *xhci = usbport->opaque; 2929 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2930 2931 xhci_port_update(port, 1); 2932 } 2933 2934 static void xhci_wakeup(USBPort *usbport) 2935 { 2936 XHCIState *xhci = usbport->opaque; 2937 XHCIPort *port = xhci_lookup_port(xhci, usbport); 2938 2939 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 2940 return; 2941 } 2942 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 2943 xhci_port_notify(port, PORTSC_PLC); 2944 } 2945 2946 static void xhci_complete(USBPort *port, USBPacket *packet) 2947 { 2948 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 2949 2950 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 2951 xhci_ep_nuke_one_xfer(xfer); 2952 return; 2953 } 2954 xhci_complete_packet(xfer); 2955 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid); 2956 } 2957 2958 static void xhci_child_detach(USBPort *uport, USBDevice *child) 2959 { 2960 USBBus *bus = usb_bus_from_device(child); 2961 XHCIState *xhci = container_of(bus, XHCIState, bus); 2962 int i; 2963 2964 for (i = 0; i < xhci->numslots; i++) { 2965 if (xhci->slots[i].uport == uport) { 2966 xhci->slots[i].uport = NULL; 2967 } 2968 } 2969 } 2970 2971 static USBPortOps xhci_uport_ops = { 2972 .attach = xhci_attach, 2973 .detach = xhci_detach, 2974 .wakeup = xhci_wakeup, 2975 .complete = xhci_complete, 2976 .child_detach = xhci_child_detach, 2977 }; 2978 2979 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev) 2980 { 2981 XHCISlot *slot; 2982 int slotid; 2983 2984 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 2985 slot = &xhci->slots[slotid-1]; 2986 if (slot->devaddr == dev->addr) { 2987 return slotid; 2988 } 2989 } 2990 return 0; 2991 } 2992 2993 static int xhci_find_epid(USBEndpoint *ep) 2994 { 2995 if (ep->nr == 0) { 2996 return 1; 2997 } 2998 if (ep->pid == USB_TOKEN_IN) { 2999 return ep->nr * 2 + 1; 3000 } else { 3001 return ep->nr * 2; 3002 } 3003 } 3004 3005 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) 3006 { 3007 XHCIState *xhci = container_of(bus, XHCIState, bus); 3008 int slotid; 3009 3010 DPRINTF("%s\n", __func__); 3011 slotid = xhci_find_slotid(xhci, ep->dev); 3012 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3013 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3014 return; 3015 } 3016 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep)); 3017 } 3018 3019 static USBBusOps xhci_bus_ops = { 3020 .wakeup_endpoint = xhci_wakeup_endpoint, 3021 }; 3022 3023 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) 3024 { 3025 XHCIPort *port; 3026 int i, usbports, speedmask; 3027 3028 xhci->usbsts = USBSTS_HCH; 3029 3030 if (xhci->numports_2 > MAXPORTS_2) { 3031 xhci->numports_2 = MAXPORTS_2; 3032 } 3033 if (xhci->numports_3 > MAXPORTS_3) { 3034 xhci->numports_3 = MAXPORTS_3; 3035 } 3036 usbports = MAX(xhci->numports_2, xhci->numports_3); 3037 xhci->numports = xhci->numports_2 + xhci->numports_3; 3038 3039 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); 3040 3041 for (i = 0; i < usbports; i++) { 3042 speedmask = 0; 3043 if (i < xhci->numports_2) { 3044 port = &xhci->ports[i]; 3045 port->portnr = i + 1; 3046 port->uport = &xhci->uports[i]; 3047 port->speedmask = 3048 USB_SPEED_MASK_LOW | 3049 USB_SPEED_MASK_FULL | 3050 USB_SPEED_MASK_HIGH; 3051 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3052 speedmask |= port->speedmask; 3053 } 3054 if (i < xhci->numports_3) { 3055 port = &xhci->ports[i + xhci->numports_2]; 3056 port->portnr = i + 1 + xhci->numports_2; 3057 port->uport = &xhci->uports[i]; 3058 port->speedmask = USB_SPEED_MASK_SUPER; 3059 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3060 speedmask |= port->speedmask; 3061 } 3062 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3063 &xhci_uport_ops, speedmask); 3064 } 3065 } 3066 3067 static int usb_xhci_initfn(struct PCIDevice *dev) 3068 { 3069 int i, ret; 3070 3071 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); 3072 3073 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3074 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3075 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; 3076 xhci->pci_dev.config[0x60] = 0x30; /* release number */ 3077 3078 usb_xhci_init(xhci, &dev->qdev); 3079 3080 if (xhci->numintrs > MAXINTRS) { 3081 xhci->numintrs = MAXINTRS; 3082 } 3083 if (xhci->numintrs < 1) { 3084 xhci->numintrs = 1; 3085 } 3086 if (xhci->numslots > MAXSLOTS) { 3087 xhci->numslots = MAXSLOTS; 3088 } 3089 if (xhci->numslots < 1) { 3090 xhci->numslots = 1; 3091 } 3092 3093 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); 3094 3095 xhci->irq = xhci->pci_dev.irq[0]; 3096 3097 memory_region_init(&xhci->mem, "xhci", LEN_REGS); 3098 memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, 3099 "capabilities", LEN_CAP); 3100 memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, 3101 "operational", 0x400); 3102 memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, 3103 "runtime", LEN_RUNTIME); 3104 memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, 3105 "doorbell", LEN_DOORBELL); 3106 3107 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3108 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3109 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3110 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3111 3112 for (i = 0; i < xhci->numports; i++) { 3113 XHCIPort *port = &xhci->ports[i]; 3114 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3115 port->xhci = xhci; 3116 memory_region_init_io(&port->mem, &xhci_port_ops, port, 3117 port->name, 0x10); 3118 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3119 } 3120 3121 pci_register_bar(&xhci->pci_dev, 0, 3122 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3123 &xhci->mem); 3124 3125 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0); 3126 assert(ret >= 0); 3127 3128 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { 3129 msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); 3130 } 3131 if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { 3132 msix_init(&xhci->pci_dev, xhci->numintrs, 3133 &xhci->mem, 0, OFF_MSIX_TABLE, 3134 &xhci->mem, 0, OFF_MSIX_PBA, 3135 0x90); 3136 } 3137 3138 return 0; 3139 } 3140 3141 static const VMStateDescription vmstate_xhci = { 3142 .name = "xhci", 3143 .unmigratable = 1, 3144 }; 3145 3146 static Property xhci_properties[] = { 3147 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), 3148 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), 3149 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3150 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3151 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3152 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3153 DEFINE_PROP_END_OF_LIST(), 3154 }; 3155 3156 static void xhci_class_init(ObjectClass *klass, void *data) 3157 { 3158 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3159 DeviceClass *dc = DEVICE_CLASS(klass); 3160 3161 dc->vmsd = &vmstate_xhci; 3162 dc->props = xhci_properties; 3163 dc->reset = xhci_reset; 3164 k->init = usb_xhci_initfn; 3165 k->vendor_id = PCI_VENDOR_ID_NEC; 3166 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3167 k->class_id = PCI_CLASS_SERIAL_USB; 3168 k->revision = 0x03; 3169 k->is_express = 1; 3170 } 3171 3172 static TypeInfo xhci_info = { 3173 .name = "nec-usb-xhci", 3174 .parent = TYPE_PCI_DEVICE, 3175 .instance_size = sizeof(XHCIState), 3176 .class_init = xhci_class_init, 3177 }; 3178 3179 static void xhci_register_types(void) 3180 { 3181 type_register_static(&xhci_info); 3182 } 3183 3184 type_init(xhci_register_types) 3185