1 /* 2 * USB xHCI controller with PCI bus emulation 3 * 4 * SPDX-FileCopyrightText: 2011 Securiforest 5 * SPDX-FileContributor: Hector Martin <hector@marcansoft.com> 6 * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * SPDX-FileCopyrightText: 2020 Xilinx 8 * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> 9 * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to 10 * hcd-xhci-pci.c 11 * 12 * This library is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU Lesser General Public 14 * License as published by the Free Software Foundation; either 15 * version 2.1 of the License, or (at your option) any later version. 16 * 17 * This library is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * Lesser General Public License for more details. 21 * 22 * You should have received a copy of the GNU Lesser General Public 23 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 24 */ 25 #include "qemu/osdep.h" 26 #include "hw/pci/pci.h" 27 #include "hw/qdev-properties.h" 28 #include "migration/vmstate.h" 29 #include "hw/pci/msi.h" 30 #include "hw/pci/msix.h" 31 #include "hcd-xhci-pci.h" 32 #include "trace.h" 33 #include "qapi/error.h" 34 35 #define OFF_MSIX_TABLE 0x3000 36 #define OFF_MSIX_PBA 0x3800 37 38 static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) 39 { 40 XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); 41 PCIDevice *pci_dev = PCI_DEVICE(s); 42 43 if (!msix_enabled(pci_dev)) { 44 return; 45 } 46 if (enable == !!xhci->intr[n].msix_used) { 47 return; 48 } 49 if (enable) { 50 trace_usb_xhci_irq_msix_use(n); 51 msix_vector_use(pci_dev, n); 52 xhci->intr[n].msix_used = true; 53 } else { 54 trace_usb_xhci_irq_msix_unuse(n); 55 msix_vector_unuse(pci_dev, n); 56 xhci->intr[n].msix_used = false; 57 } 58 } 59 60 static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) 61 { 62 XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); 63 PCIDevice *pci_dev = PCI_DEVICE(s); 64 65 if (n == 0 && 66 !(msix_enabled(pci_dev) || 67 msi_enabled(pci_dev))) { 68 pci_set_irq(pci_dev, level); 69 } 70 if (msix_enabled(pci_dev)) { 71 msix_notify(pci_dev, n); 72 return; 73 } 74 75 if (msi_enabled(pci_dev)) { 76 msi_notify(pci_dev, n); 77 return; 78 } 79 } 80 81 static void xhci_pci_reset(DeviceState *dev) 82 { 83 XHCIPciState *s = XHCI_PCI(dev); 84 85 device_legacy_reset(DEVICE(&s->xhci)); 86 } 87 88 static int xhci_pci_vmstate_post_load(void *opaque, int version_id) 89 { 90 XHCIPciState *s = XHCI_PCI(opaque); 91 PCIDevice *pci_dev = PCI_DEVICE(s); 92 int intr; 93 94 for (intr = 0; intr < s->xhci.numintrs; intr++) { 95 if (s->xhci.intr[intr].msix_used) { 96 msix_vector_use(pci_dev, intr); 97 } else { 98 msix_vector_unuse(pci_dev, intr); 99 } 100 } 101 return 0; 102 } 103 104 static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) 105 { 106 int ret; 107 Error *err = NULL; 108 XHCIPciState *s = XHCI_PCI(dev); 109 110 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 111 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 112 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 113 dev->config[0x60] = 0x30; /* release number */ 114 115 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); 116 s->xhci.intr_update = xhci_pci_intr_update; 117 s->xhci.intr_raise = xhci_pci_intr_raise; 118 object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err); 119 if (err) { 120 error_propagate(errp, err); 121 return; 122 } 123 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { 124 s->xhci.nec_quirks = true; 125 } 126 127 if (s->msi != ON_OFF_AUTO_OFF) { 128 ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err); 129 /* 130 * Any error other than -ENOTSUP(board's MSI support is broken) 131 * is a programming error 132 */ 133 assert(!ret || ret == -ENOTSUP); 134 if (ret && s->msi == ON_OFF_AUTO_ON) { 135 /* Can't satisfy user's explicit msi=on request, fail */ 136 error_append_hint(&err, "You have to use msi=auto (default) or " 137 "msi=off with this machine type.\n"); 138 error_propagate(errp, err); 139 return; 140 } 141 assert(!err || s->msi == ON_OFF_AUTO_AUTO); 142 /* With msi=auto, we fall back to MSI off silently */ 143 error_free(err); 144 } 145 pci_register_bar(dev, 0, 146 PCI_BASE_ADDRESS_SPACE_MEMORY | 147 PCI_BASE_ADDRESS_MEM_TYPE_64, 148 &s->xhci.mem); 149 150 if (pci_bus_is_express(pci_get_bus(dev)) || 151 xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 152 ret = pcie_endpoint_cap_init(dev, 0xa0); 153 assert(ret > 0); 154 } 155 156 if (s->msix != ON_OFF_AUTO_OFF) { 157 /* TODO check for errors, and should fail when msix=on */ 158 msix_init(dev, s->xhci.numintrs, 159 &s->xhci.mem, 0, OFF_MSIX_TABLE, 160 &s->xhci.mem, 0, OFF_MSIX_PBA, 161 0x90, NULL); 162 } 163 s->xhci.as = pci_get_address_space(dev); 164 } 165 166 static void usb_xhci_pci_exit(PCIDevice *dev) 167 { 168 XHCIPciState *s = XHCI_PCI(dev); 169 /* destroy msix memory region */ 170 if (dev->msix_table && dev->msix_pba 171 && dev->msix_entry_used) { 172 msix_uninit(dev, &s->xhci.mem, &s->xhci.mem); 173 } 174 } 175 176 static const VMStateDescription vmstate_xhci_pci = { 177 .name = "xhci", 178 .version_id = 1, 179 .post_load = xhci_pci_vmstate_post_load, 180 .fields = (VMStateField[]) { 181 VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState), 182 VMSTATE_MSIX(parent_obj, XHCIPciState), 183 VMSTATE_STRUCT(xhci, XHCIPciState, 1, vmstate_xhci, XHCIState), 184 VMSTATE_END_OF_LIST() 185 } 186 }; 187 188 static void xhci_instance_init(Object *obj) 189 { 190 XHCIPciState *s = XHCI_PCI(obj); 191 /* 192 * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command 193 * line, therefore, no need to wait to realize like other devices 194 */ 195 PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; 196 object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI); 197 qdev_alias_all_properties(DEVICE(&s->xhci), obj); 198 } 199 200 static void xhci_class_init(ObjectClass *klass, void *data) 201 { 202 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 203 DeviceClass *dc = DEVICE_CLASS(klass); 204 205 dc->reset = xhci_pci_reset; 206 dc->vmsd = &vmstate_xhci_pci; 207 set_bit(DEVICE_CATEGORY_USB, dc->categories); 208 k->realize = usb_xhci_pci_realize; 209 k->exit = usb_xhci_pci_exit; 210 k->class_id = PCI_CLASS_SERIAL_USB; 211 } 212 213 static const TypeInfo xhci_pci_info = { 214 .name = TYPE_XHCI_PCI, 215 .parent = TYPE_PCI_DEVICE, 216 .instance_size = sizeof(XHCIPciState), 217 .class_init = xhci_class_init, 218 .instance_init = xhci_instance_init, 219 .abstract = true, 220 .interfaces = (InterfaceInfo[]) { 221 { INTERFACE_PCIE_DEVICE }, 222 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 223 { } 224 }, 225 }; 226 227 static void qemu_xhci_class_init(ObjectClass *klass, void *data) 228 { 229 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 230 231 k->vendor_id = PCI_VENDOR_ID_REDHAT; 232 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; 233 k->revision = 0x01; 234 } 235 236 static void qemu_xhci_instance_init(Object *obj) 237 { 238 XHCIPciState *s = XHCI_PCI(obj); 239 XHCIState *xhci = &s->xhci; 240 241 s->msi = ON_OFF_AUTO_OFF; 242 s->msix = ON_OFF_AUTO_AUTO; 243 xhci->numintrs = XHCI_MAXINTRS; 244 xhci->numslots = XHCI_MAXSLOTS; 245 xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); 246 } 247 248 static const TypeInfo qemu_xhci_info = { 249 .name = TYPE_QEMU_XHCI, 250 .parent = TYPE_XHCI_PCI, 251 .class_init = qemu_xhci_class_init, 252 .instance_init = qemu_xhci_instance_init, 253 }; 254 255 static void xhci_register_types(void) 256 { 257 type_register_static(&xhci_pci_info); 258 type_register_static(&qemu_xhci_info); 259 } 260 261 type_init(xhci_register_types) 262