xref: /openbmc/qemu/hw/usb/hcd-uhci.h (revision cbb45ff0)
1 /*
2  * USB UHCI controller emulation
3  *
4  * Copyright (c) 2005 Fabrice Bellard
5  *
6  * Copyright (c) 2008 Max Krasnyansky
7  *     Magor rewrite of the UHCI data structures parser and frame processor
8  *     Support for fully async operation and multiple outstanding transactions
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a copy
11  * of this software and associated documentation files (the "Software"), to deal
12  * in the Software without restriction, including without limitation the rights
13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14  * copies of the Software, and to permit persons to whom the Software is
15  * furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26  * THE SOFTWARE.
27  */
28 #ifndef HW_USB_HCD_UHCI_H
29 #define HW_USB_HCD_UHCI_H
30 
31 #include "exec/memory.h"
32 #include "qemu/timer.h"
33 #include "hw/pci/pci.h"
34 #include "hw/usb.h"
35 
36 typedef struct UHCIQueue UHCIQueue;
37 
38 #define NB_PORTS 2
39 
40 typedef struct UHCIPort {
41     USBPort port;
42     uint16_t ctrl;
43 } UHCIPort;
44 
45 typedef struct UHCIState {
46     PCIDevice dev;
47     MemoryRegion io_bar;
48     USBBus bus; /* Note unused when we're a companion controller */
49     uint16_t cmd; /* cmd register */
50     uint16_t status;
51     uint16_t intr; /* interrupt enable register */
52     uint16_t frnum; /* frame number */
53     uint32_t fl_base_addr; /* frame list base address */
54     uint8_t sof_timing;
55     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
56     int64_t expire_time;
57     QEMUTimer *frame_timer;
58     QEMUBH *bh;
59     uint32_t frame_bytes;
60     uint32_t frame_bandwidth;
61     bool completions_only;
62     UHCIPort ports[NB_PORTS];
63     qemu_irq irq;
64     /* Interrupts that should be raised at the end of the current frame.  */
65     uint32_t pending_int_mask;
66 
67     /* Active packets */
68     QTAILQ_HEAD(, UHCIQueue) queues;
69     uint8_t num_ports_vmstate;
70 
71     /* Properties */
72     char *masterbus;
73     uint32_t firstport;
74     uint32_t maxframes;
75 } UHCIState;
76 
77 #define TYPE_UHCI "pci-uhci-usb"
78 DECLARE_INSTANCE_CHECKER(UHCIState, UHCI, TYPE_UHCI)
79 
80 typedef struct UHCIInfo {
81     const char *name;
82     uint16_t   vendor_id;
83     uint16_t   device_id;
84     uint8_t    revision;
85     uint8_t    irq_pin;
86     void       (*realize)(PCIDevice *dev, Error **errp);
87     bool       unplug;
88     bool       notuser; /* disallow user_creatable */
89 } UHCIInfo;
90 
91 void uhci_data_class_init(ObjectClass *klass, void *data);
92 void usb_uhci_common_realize(PCIDevice *dev, Error **errp);
93 
94 #endif
95