1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci/pci.h" 31 #include "qemu/timer.h" 32 #include "qemu/iov.h" 33 #include "sysemu/dma.h" 34 #include "trace.h" 35 #include "qemu/main-loop.h" 36 37 //#define DEBUG 38 //#define DEBUG_DUMP_DATA 39 40 #define UHCI_CMD_FGR (1 << 4) 41 #define UHCI_CMD_EGSM (1 << 3) 42 #define UHCI_CMD_GRESET (1 << 2) 43 #define UHCI_CMD_HCRESET (1 << 1) 44 #define UHCI_CMD_RS (1 << 0) 45 46 #define UHCI_STS_HCHALTED (1 << 5) 47 #define UHCI_STS_HCPERR (1 << 4) 48 #define UHCI_STS_HSERR (1 << 3) 49 #define UHCI_STS_RD (1 << 2) 50 #define UHCI_STS_USBERR (1 << 1) 51 #define UHCI_STS_USBINT (1 << 0) 52 53 #define TD_CTRL_SPD (1 << 29) 54 #define TD_CTRL_ERROR_SHIFT 27 55 #define TD_CTRL_IOS (1 << 25) 56 #define TD_CTRL_IOC (1 << 24) 57 #define TD_CTRL_ACTIVE (1 << 23) 58 #define TD_CTRL_STALL (1 << 22) 59 #define TD_CTRL_BABBLE (1 << 20) 60 #define TD_CTRL_NAK (1 << 19) 61 #define TD_CTRL_TIMEOUT (1 << 18) 62 63 #define UHCI_PORT_SUSPEND (1 << 12) 64 #define UHCI_PORT_RESET (1 << 9) 65 #define UHCI_PORT_LSDA (1 << 8) 66 #define UHCI_PORT_RD (1 << 6) 67 #define UHCI_PORT_ENC (1 << 3) 68 #define UHCI_PORT_EN (1 << 2) 69 #define UHCI_PORT_CSC (1 << 1) 70 #define UHCI_PORT_CCS (1 << 0) 71 72 #define UHCI_PORT_READ_ONLY (0x1bb) 73 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 74 75 #define FRAME_TIMER_FREQ 1000 76 77 #define FRAME_MAX_LOOPS 256 78 79 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 80 #define QH_VALID 32 81 82 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 83 84 #define NB_PORTS 2 85 86 enum { 87 TD_RESULT_STOP_FRAME = 10, 88 TD_RESULT_COMPLETE, 89 TD_RESULT_NEXT_QH, 90 TD_RESULT_ASYNC_START, 91 TD_RESULT_ASYNC_CONT, 92 }; 93 94 typedef struct UHCIState UHCIState; 95 typedef struct UHCIAsync UHCIAsync; 96 typedef struct UHCIQueue UHCIQueue; 97 typedef struct UHCIInfo UHCIInfo; 98 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 99 100 struct UHCIInfo { 101 const char *name; 102 uint16_t vendor_id; 103 uint16_t device_id; 104 uint8_t revision; 105 uint8_t irq_pin; 106 int (*initfn)(PCIDevice *dev); 107 bool unplug; 108 }; 109 110 struct UHCIPCIDeviceClass { 111 PCIDeviceClass parent_class; 112 UHCIInfo info; 113 }; 114 115 /* 116 * Pending async transaction. 117 * 'packet' must be the first field because completion 118 * handler does "(UHCIAsync *) pkt" cast. 119 */ 120 121 struct UHCIAsync { 122 USBPacket packet; 123 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 124 uint8_t *buf; 125 UHCIQueue *queue; 126 QTAILQ_ENTRY(UHCIAsync) next; 127 uint32_t td_addr; 128 uint8_t done; 129 }; 130 131 struct UHCIQueue { 132 uint32_t qh_addr; 133 uint32_t token; 134 UHCIState *uhci; 135 USBEndpoint *ep; 136 QTAILQ_ENTRY(UHCIQueue) next; 137 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 138 int8_t valid; 139 }; 140 141 typedef struct UHCIPort { 142 USBPort port; 143 uint16_t ctrl; 144 } UHCIPort; 145 146 struct UHCIState { 147 PCIDevice dev; 148 MemoryRegion io_bar; 149 USBBus bus; /* Note unused when we're a companion controller */ 150 uint16_t cmd; /* cmd register */ 151 uint16_t status; 152 uint16_t intr; /* interrupt enable register */ 153 uint16_t frnum; /* frame number */ 154 uint32_t fl_base_addr; /* frame list base address */ 155 uint8_t sof_timing; 156 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 157 int64_t expire_time; 158 QEMUTimer *frame_timer; 159 QEMUBH *bh; 160 uint32_t frame_bytes; 161 uint32_t frame_bandwidth; 162 bool completions_only; 163 UHCIPort ports[NB_PORTS]; 164 165 /* Interrupts that should be raised at the end of the current frame. */ 166 uint32_t pending_int_mask; 167 168 /* Active packets */ 169 QTAILQ_HEAD(, UHCIQueue) queues; 170 uint8_t num_ports_vmstate; 171 172 /* Properties */ 173 char *masterbus; 174 uint32_t firstport; 175 uint32_t maxframes; 176 }; 177 178 typedef struct UHCI_TD { 179 uint32_t link; 180 uint32_t ctrl; /* see TD_CTRL_xxx */ 181 uint32_t token; 182 uint32_t buffer; 183 } UHCI_TD; 184 185 typedef struct UHCI_QH { 186 uint32_t link; 187 uint32_t el_link; 188 } UHCI_QH; 189 190 static void uhci_async_cancel(UHCIAsync *async); 191 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 192 static void uhci_resume(void *opaque); 193 194 static inline int32_t uhci_queue_token(UHCI_TD *td) 195 { 196 if ((td->token & (0xf << 15)) == 0) { 197 /* ctrl ep, cover ep and dev, not pid! */ 198 return td->token & 0x7ff00; 199 } else { 200 /* covers ep, dev, pid -> identifies the endpoint */ 201 return td->token & 0x7ffff; 202 } 203 } 204 205 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 206 USBEndpoint *ep) 207 { 208 UHCIQueue *queue; 209 210 queue = g_new0(UHCIQueue, 1); 211 queue->uhci = s; 212 queue->qh_addr = qh_addr; 213 queue->token = uhci_queue_token(td); 214 queue->ep = ep; 215 QTAILQ_INIT(&queue->asyncs); 216 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 217 queue->valid = QH_VALID; 218 trace_usb_uhci_queue_add(queue->token); 219 return queue; 220 } 221 222 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 223 { 224 UHCIState *s = queue->uhci; 225 UHCIAsync *async; 226 227 while (!QTAILQ_EMPTY(&queue->asyncs)) { 228 async = QTAILQ_FIRST(&queue->asyncs); 229 uhci_async_cancel(async); 230 } 231 usb_device_ep_stopped(queue->ep->dev, queue->ep); 232 233 trace_usb_uhci_queue_del(queue->token, reason); 234 QTAILQ_REMOVE(&s->queues, queue, next); 235 g_free(queue); 236 } 237 238 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 239 { 240 uint32_t token = uhci_queue_token(td); 241 UHCIQueue *queue; 242 243 QTAILQ_FOREACH(queue, &s->queues, next) { 244 if (queue->token == token) { 245 return queue; 246 } 247 } 248 return NULL; 249 } 250 251 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 252 uint32_t td_addr, bool queuing) 253 { 254 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 255 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 256 257 return queue->qh_addr == qh_addr && 258 queue->token == uhci_queue_token(td) && 259 queue_token_addr == queue->ep->dev->addr && 260 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 261 first->td_addr == td_addr); 262 } 263 264 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 265 { 266 UHCIAsync *async = g_new0(UHCIAsync, 1); 267 268 async->queue = queue; 269 async->td_addr = td_addr; 270 usb_packet_init(&async->packet); 271 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 272 273 return async; 274 } 275 276 static void uhci_async_free(UHCIAsync *async) 277 { 278 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 279 usb_packet_cleanup(&async->packet); 280 if (async->buf != async->static_buf) { 281 g_free(async->buf); 282 } 283 g_free(async); 284 } 285 286 static void uhci_async_link(UHCIAsync *async) 287 { 288 UHCIQueue *queue = async->queue; 289 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 290 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 291 } 292 293 static void uhci_async_unlink(UHCIAsync *async) 294 { 295 UHCIQueue *queue = async->queue; 296 QTAILQ_REMOVE(&queue->asyncs, async, next); 297 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 298 } 299 300 static void uhci_async_cancel(UHCIAsync *async) 301 { 302 uhci_async_unlink(async); 303 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 304 async->done); 305 if (!async->done) 306 usb_cancel_packet(&async->packet); 307 uhci_async_free(async); 308 } 309 310 /* 311 * Mark all outstanding async packets as invalid. 312 * This is used for canceling them when TDs are removed by the HCD. 313 */ 314 static void uhci_async_validate_begin(UHCIState *s) 315 { 316 UHCIQueue *queue; 317 318 QTAILQ_FOREACH(queue, &s->queues, next) { 319 queue->valid--; 320 } 321 } 322 323 /* 324 * Cancel async packets that are no longer valid 325 */ 326 static void uhci_async_validate_end(UHCIState *s) 327 { 328 UHCIQueue *queue, *n; 329 330 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 331 if (!queue->valid) { 332 uhci_queue_free(queue, "validate-end"); 333 } 334 } 335 } 336 337 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 338 { 339 UHCIQueue *queue, *n; 340 341 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 342 if (queue->ep->dev == dev) { 343 uhci_queue_free(queue, "cancel-device"); 344 } 345 } 346 } 347 348 static void uhci_async_cancel_all(UHCIState *s) 349 { 350 UHCIQueue *queue, *nq; 351 352 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 353 uhci_queue_free(queue, "cancel-all"); 354 } 355 } 356 357 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 358 { 359 UHCIQueue *queue; 360 UHCIAsync *async; 361 362 QTAILQ_FOREACH(queue, &s->queues, next) { 363 QTAILQ_FOREACH(async, &queue->asyncs, next) { 364 if (async->td_addr == td_addr) { 365 return async; 366 } 367 } 368 } 369 return NULL; 370 } 371 372 static void uhci_update_irq(UHCIState *s) 373 { 374 int level; 375 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 376 ((s->status2 & 2) && (s->intr & (1 << 3))) || 377 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 378 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 379 (s->status & UHCI_STS_HSERR) || 380 (s->status & UHCI_STS_HCPERR)) { 381 level = 1; 382 } else { 383 level = 0; 384 } 385 pci_set_irq(&s->dev, level); 386 } 387 388 static void uhci_reset(void *opaque) 389 { 390 UHCIState *s = opaque; 391 uint8_t *pci_conf; 392 int i; 393 UHCIPort *port; 394 395 trace_usb_uhci_reset(); 396 397 pci_conf = s->dev.config; 398 399 pci_conf[0x6a] = 0x01; /* usb clock */ 400 pci_conf[0x6b] = 0x00; 401 s->cmd = 0; 402 s->status = 0; 403 s->status2 = 0; 404 s->intr = 0; 405 s->fl_base_addr = 0; 406 s->sof_timing = 64; 407 408 for(i = 0; i < NB_PORTS; i++) { 409 port = &s->ports[i]; 410 port->ctrl = 0x0080; 411 if (port->port.dev && port->port.dev->attached) { 412 usb_port_reset(&port->port); 413 } 414 } 415 416 uhci_async_cancel_all(s); 417 qemu_bh_cancel(s->bh); 418 uhci_update_irq(s); 419 } 420 421 static const VMStateDescription vmstate_uhci_port = { 422 .name = "uhci port", 423 .version_id = 1, 424 .minimum_version_id = 1, 425 .minimum_version_id_old = 1, 426 .fields = (VMStateField []) { 427 VMSTATE_UINT16(ctrl, UHCIPort), 428 VMSTATE_END_OF_LIST() 429 } 430 }; 431 432 static int uhci_post_load(void *opaque, int version_id) 433 { 434 UHCIState *s = opaque; 435 436 if (version_id < 2) { 437 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 438 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 439 } 440 return 0; 441 } 442 443 static const VMStateDescription vmstate_uhci = { 444 .name = "uhci", 445 .version_id = 3, 446 .minimum_version_id = 1, 447 .minimum_version_id_old = 1, 448 .post_load = uhci_post_load, 449 .fields = (VMStateField []) { 450 VMSTATE_PCI_DEVICE(dev, UHCIState), 451 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 452 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 453 vmstate_uhci_port, UHCIPort), 454 VMSTATE_UINT16(cmd, UHCIState), 455 VMSTATE_UINT16(status, UHCIState), 456 VMSTATE_UINT16(intr, UHCIState), 457 VMSTATE_UINT16(frnum, UHCIState), 458 VMSTATE_UINT32(fl_base_addr, UHCIState), 459 VMSTATE_UINT8(sof_timing, UHCIState), 460 VMSTATE_UINT8(status2, UHCIState), 461 VMSTATE_TIMER(frame_timer, UHCIState), 462 VMSTATE_INT64_V(expire_time, UHCIState, 2), 463 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 464 VMSTATE_END_OF_LIST() 465 } 466 }; 467 468 static void uhci_port_write(void *opaque, hwaddr addr, 469 uint64_t val, unsigned size) 470 { 471 UHCIState *s = opaque; 472 473 trace_usb_uhci_mmio_writew(addr, val); 474 475 switch(addr) { 476 case 0x00: 477 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 478 /* start frame processing */ 479 trace_usb_uhci_schedule_start(); 480 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 481 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 482 timer_mod(s->frame_timer, s->expire_time); 483 s->status &= ~UHCI_STS_HCHALTED; 484 } else if (!(val & UHCI_CMD_RS)) { 485 s->status |= UHCI_STS_HCHALTED; 486 } 487 if (val & UHCI_CMD_GRESET) { 488 UHCIPort *port; 489 int i; 490 491 /* send reset on the USB bus */ 492 for(i = 0; i < NB_PORTS; i++) { 493 port = &s->ports[i]; 494 usb_device_reset(port->port.dev); 495 } 496 uhci_reset(s); 497 return; 498 } 499 if (val & UHCI_CMD_HCRESET) { 500 uhci_reset(s); 501 return; 502 } 503 s->cmd = val; 504 if (val & UHCI_CMD_EGSM) { 505 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 506 (s->ports[1].ctrl & UHCI_PORT_RD)) { 507 uhci_resume(s); 508 } 509 } 510 break; 511 case 0x02: 512 s->status &= ~val; 513 /* XXX: the chip spec is not coherent, so we add a hidden 514 register to distinguish between IOC and SPD */ 515 if (val & UHCI_STS_USBINT) 516 s->status2 = 0; 517 uhci_update_irq(s); 518 break; 519 case 0x04: 520 s->intr = val; 521 uhci_update_irq(s); 522 break; 523 case 0x06: 524 if (s->status & UHCI_STS_HCHALTED) 525 s->frnum = val & 0x7ff; 526 break; 527 case 0x08: 528 s->fl_base_addr &= 0xffff0000; 529 s->fl_base_addr |= val & ~0xfff; 530 break; 531 case 0x0a: 532 s->fl_base_addr &= 0x0000ffff; 533 s->fl_base_addr |= (val << 16); 534 break; 535 case 0x0c: 536 s->sof_timing = val & 0xff; 537 break; 538 case 0x10 ... 0x1f: 539 { 540 UHCIPort *port; 541 USBDevice *dev; 542 int n; 543 544 n = (addr >> 1) & 7; 545 if (n >= NB_PORTS) 546 return; 547 port = &s->ports[n]; 548 dev = port->port.dev; 549 if (dev && dev->attached) { 550 /* port reset */ 551 if ( (val & UHCI_PORT_RESET) && 552 !(port->ctrl & UHCI_PORT_RESET) ) { 553 usb_device_reset(dev); 554 } 555 } 556 port->ctrl &= UHCI_PORT_READ_ONLY; 557 /* enabled may only be set if a device is connected */ 558 if (!(port->ctrl & UHCI_PORT_CCS)) { 559 val &= ~UHCI_PORT_EN; 560 } 561 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 562 /* some bits are reset when a '1' is written to them */ 563 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 564 } 565 break; 566 } 567 } 568 569 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 570 { 571 UHCIState *s = opaque; 572 uint32_t val; 573 574 switch(addr) { 575 case 0x00: 576 val = s->cmd; 577 break; 578 case 0x02: 579 val = s->status; 580 break; 581 case 0x04: 582 val = s->intr; 583 break; 584 case 0x06: 585 val = s->frnum; 586 break; 587 case 0x08: 588 val = s->fl_base_addr & 0xffff; 589 break; 590 case 0x0a: 591 val = (s->fl_base_addr >> 16) & 0xffff; 592 break; 593 case 0x0c: 594 val = s->sof_timing; 595 break; 596 case 0x10 ... 0x1f: 597 { 598 UHCIPort *port; 599 int n; 600 n = (addr >> 1) & 7; 601 if (n >= NB_PORTS) 602 goto read_default; 603 port = &s->ports[n]; 604 val = port->ctrl; 605 } 606 break; 607 default: 608 read_default: 609 val = 0xff7f; /* disabled port */ 610 break; 611 } 612 613 trace_usb_uhci_mmio_readw(addr, val); 614 615 return val; 616 } 617 618 /* signal resume if controller suspended */ 619 static void uhci_resume (void *opaque) 620 { 621 UHCIState *s = (UHCIState *)opaque; 622 623 if (!s) 624 return; 625 626 if (s->cmd & UHCI_CMD_EGSM) { 627 s->cmd |= UHCI_CMD_FGR; 628 s->status |= UHCI_STS_RD; 629 uhci_update_irq(s); 630 } 631 } 632 633 static void uhci_attach(USBPort *port1) 634 { 635 UHCIState *s = port1->opaque; 636 UHCIPort *port = &s->ports[port1->index]; 637 638 /* set connect status */ 639 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 640 641 /* update speed */ 642 if (port->port.dev->speed == USB_SPEED_LOW) { 643 port->ctrl |= UHCI_PORT_LSDA; 644 } else { 645 port->ctrl &= ~UHCI_PORT_LSDA; 646 } 647 648 uhci_resume(s); 649 } 650 651 static void uhci_detach(USBPort *port1) 652 { 653 UHCIState *s = port1->opaque; 654 UHCIPort *port = &s->ports[port1->index]; 655 656 uhci_async_cancel_device(s, port1->dev); 657 658 /* set connect status */ 659 if (port->ctrl & UHCI_PORT_CCS) { 660 port->ctrl &= ~UHCI_PORT_CCS; 661 port->ctrl |= UHCI_PORT_CSC; 662 } 663 /* disable port */ 664 if (port->ctrl & UHCI_PORT_EN) { 665 port->ctrl &= ~UHCI_PORT_EN; 666 port->ctrl |= UHCI_PORT_ENC; 667 } 668 669 uhci_resume(s); 670 } 671 672 static void uhci_child_detach(USBPort *port1, USBDevice *child) 673 { 674 UHCIState *s = port1->opaque; 675 676 uhci_async_cancel_device(s, child); 677 } 678 679 static void uhci_wakeup(USBPort *port1) 680 { 681 UHCIState *s = port1->opaque; 682 UHCIPort *port = &s->ports[port1->index]; 683 684 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 685 port->ctrl |= UHCI_PORT_RD; 686 uhci_resume(s); 687 } 688 } 689 690 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 691 { 692 USBDevice *dev; 693 int i; 694 695 for (i = 0; i < NB_PORTS; i++) { 696 UHCIPort *port = &s->ports[i]; 697 if (!(port->ctrl & UHCI_PORT_EN)) { 698 continue; 699 } 700 dev = usb_find_device(&port->port, addr); 701 if (dev != NULL) { 702 return dev; 703 } 704 } 705 return NULL; 706 } 707 708 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 709 { 710 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 711 le32_to_cpus(&td->link); 712 le32_to_cpus(&td->ctrl); 713 le32_to_cpus(&td->token); 714 le32_to_cpus(&td->buffer); 715 } 716 717 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 718 int status, uint32_t *int_mask) 719 { 720 uint32_t queue_token = uhci_queue_token(td); 721 int ret; 722 723 switch (status) { 724 case USB_RET_NAK: 725 td->ctrl |= TD_CTRL_NAK; 726 return TD_RESULT_NEXT_QH; 727 728 case USB_RET_STALL: 729 td->ctrl |= TD_CTRL_STALL; 730 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 731 ret = TD_RESULT_NEXT_QH; 732 break; 733 734 case USB_RET_BABBLE: 735 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 736 /* frame interrupted */ 737 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 738 ret = TD_RESULT_STOP_FRAME; 739 break; 740 741 case USB_RET_IOERROR: 742 case USB_RET_NODEV: 743 default: 744 td->ctrl |= TD_CTRL_TIMEOUT; 745 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 746 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 747 ret = TD_RESULT_NEXT_QH; 748 break; 749 } 750 751 td->ctrl &= ~TD_CTRL_ACTIVE; 752 s->status |= UHCI_STS_USBERR; 753 if (td->ctrl & TD_CTRL_IOC) { 754 *int_mask |= 0x01; 755 } 756 uhci_update_irq(s); 757 return ret; 758 } 759 760 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 761 { 762 int len = 0, max_len; 763 uint8_t pid; 764 765 max_len = ((td->token >> 21) + 1) & 0x7ff; 766 pid = td->token & 0xff; 767 768 if (td->ctrl & TD_CTRL_IOS) 769 td->ctrl &= ~TD_CTRL_ACTIVE; 770 771 if (async->packet.status != USB_RET_SUCCESS) { 772 return uhci_handle_td_error(s, td, async->td_addr, 773 async->packet.status, int_mask); 774 } 775 776 len = async->packet.actual_length; 777 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 778 779 /* The NAK bit may have been set by a previous frame, so clear it 780 here. The docs are somewhat unclear, but win2k relies on this 781 behavior. */ 782 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 783 if (td->ctrl & TD_CTRL_IOC) 784 *int_mask |= 0x01; 785 786 if (pid == USB_TOKEN_IN) { 787 pci_dma_write(&s->dev, td->buffer, async->buf, len); 788 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 789 *int_mask |= 0x02; 790 /* short packet: do not update QH */ 791 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 792 async->td_addr); 793 return TD_RESULT_NEXT_QH; 794 } 795 } 796 797 /* success */ 798 trace_usb_uhci_packet_complete_success(async->queue->token, 799 async->td_addr); 800 return TD_RESULT_COMPLETE; 801 } 802 803 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 804 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 805 { 806 int ret, max_len; 807 bool spd; 808 bool queuing = (q != NULL); 809 uint8_t pid = td->token & 0xff; 810 UHCIAsync *async = uhci_async_find_td(s, td_addr); 811 812 if (async) { 813 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 814 assert(q == NULL || q == async->queue); 815 q = async->queue; 816 } else { 817 uhci_queue_free(async->queue, "guest re-used pending td"); 818 async = NULL; 819 } 820 } 821 822 if (q == NULL) { 823 q = uhci_queue_find(s, td); 824 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 825 uhci_queue_free(q, "guest re-used qh"); 826 q = NULL; 827 } 828 } 829 830 if (q) { 831 q->valid = QH_VALID; 832 } 833 834 /* Is active ? */ 835 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 836 if (async) { 837 /* Guest marked a pending td non-active, cancel the queue */ 838 uhci_queue_free(async->queue, "pending td non-active"); 839 } 840 /* 841 * ehci11d spec page 22: "Even if the Active bit in the TD is already 842 * cleared when the TD is fetched ... an IOC interrupt is generated" 843 */ 844 if (td->ctrl & TD_CTRL_IOC) { 845 *int_mask |= 0x01; 846 } 847 return TD_RESULT_NEXT_QH; 848 } 849 850 if (async) { 851 if (queuing) { 852 /* we are busy filling the queue, we are not prepared 853 to consume completed packages then, just leave them 854 in async state */ 855 return TD_RESULT_ASYNC_CONT; 856 } 857 if (!async->done) { 858 UHCI_TD last_td; 859 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 860 /* 861 * While we are waiting for the current td to complete, the guest 862 * may have added more tds to the queue. Note we re-read the td 863 * rather then caching it, as we want to see guest made changes! 864 */ 865 uhci_read_td(s, &last_td, last->td_addr); 866 uhci_queue_fill(async->queue, &last_td); 867 868 return TD_RESULT_ASYNC_CONT; 869 } 870 uhci_async_unlink(async); 871 goto done; 872 } 873 874 if (s->completions_only) { 875 return TD_RESULT_ASYNC_CONT; 876 } 877 878 /* Allocate new packet */ 879 if (q == NULL) { 880 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 881 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 882 883 if (ep == NULL) { 884 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 885 int_mask); 886 } 887 q = uhci_queue_new(s, qh_addr, td, ep); 888 } 889 async = uhci_async_alloc(q, td_addr); 890 891 max_len = ((td->token >> 21) + 1) & 0x7ff; 892 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 893 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 894 (td->ctrl & TD_CTRL_IOC) != 0); 895 if (max_len <= sizeof(async->static_buf)) { 896 async->buf = async->static_buf; 897 } else { 898 async->buf = g_malloc(max_len); 899 } 900 usb_packet_addbuf(&async->packet, async->buf, max_len); 901 902 switch(pid) { 903 case USB_TOKEN_OUT: 904 case USB_TOKEN_SETUP: 905 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 906 usb_handle_packet(q->ep->dev, &async->packet); 907 if (async->packet.status == USB_RET_SUCCESS) { 908 async->packet.actual_length = max_len; 909 } 910 break; 911 912 case USB_TOKEN_IN: 913 usb_handle_packet(q->ep->dev, &async->packet); 914 break; 915 916 default: 917 /* invalid pid : frame interrupted */ 918 uhci_async_free(async); 919 s->status |= UHCI_STS_HCPERR; 920 uhci_update_irq(s); 921 return TD_RESULT_STOP_FRAME; 922 } 923 924 if (async->packet.status == USB_RET_ASYNC) { 925 uhci_async_link(async); 926 if (!queuing) { 927 uhci_queue_fill(q, td); 928 } 929 return TD_RESULT_ASYNC_START; 930 } 931 932 done: 933 ret = uhci_complete_td(s, td, async, int_mask); 934 uhci_async_free(async); 935 return ret; 936 } 937 938 static void uhci_async_complete(USBPort *port, USBPacket *packet) 939 { 940 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 941 UHCIState *s = async->queue->uhci; 942 943 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 944 uhci_async_cancel(async); 945 return; 946 } 947 948 async->done = 1; 949 /* Force processing of this packet *now*, needed for migration */ 950 s->completions_only = true; 951 qemu_bh_schedule(s->bh); 952 } 953 954 static int is_valid(uint32_t link) 955 { 956 return (link & 1) == 0; 957 } 958 959 static int is_qh(uint32_t link) 960 { 961 return (link & 2) != 0; 962 } 963 964 static int depth_first(uint32_t link) 965 { 966 return (link & 4) != 0; 967 } 968 969 /* QH DB used for detecting QH loops */ 970 #define UHCI_MAX_QUEUES 128 971 typedef struct { 972 uint32_t addr[UHCI_MAX_QUEUES]; 973 int count; 974 } QhDb; 975 976 static void qhdb_reset(QhDb *db) 977 { 978 db->count = 0; 979 } 980 981 /* Add QH to DB. Returns 1 if already present or DB is full. */ 982 static int qhdb_insert(QhDb *db, uint32_t addr) 983 { 984 int i; 985 for (i = 0; i < db->count; i++) 986 if (db->addr[i] == addr) 987 return 1; 988 989 if (db->count >= UHCI_MAX_QUEUES) 990 return 1; 991 992 db->addr[db->count++] = addr; 993 return 0; 994 } 995 996 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 997 { 998 uint32_t int_mask = 0; 999 uint32_t plink = td->link; 1000 UHCI_TD ptd; 1001 int ret; 1002 1003 while (is_valid(plink)) { 1004 uhci_read_td(q->uhci, &ptd, plink); 1005 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 1006 break; 1007 } 1008 if (uhci_queue_token(&ptd) != q->token) { 1009 break; 1010 } 1011 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 1012 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 1013 if (ret == TD_RESULT_ASYNC_CONT) { 1014 break; 1015 } 1016 assert(ret == TD_RESULT_ASYNC_START); 1017 assert(int_mask == 0); 1018 plink = ptd.link; 1019 } 1020 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1021 } 1022 1023 static void uhci_process_frame(UHCIState *s) 1024 { 1025 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1026 uint32_t curr_qh, td_count = 0; 1027 int cnt, ret; 1028 UHCI_TD td; 1029 UHCI_QH qh; 1030 QhDb qhdb; 1031 1032 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1033 1034 pci_dma_read(&s->dev, frame_addr, &link, 4); 1035 le32_to_cpus(&link); 1036 1037 int_mask = 0; 1038 curr_qh = 0; 1039 1040 qhdb_reset(&qhdb); 1041 1042 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1043 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1044 /* We've reached the usb 1.1 bandwidth, which is 1045 1280 bytes/frame, stop processing */ 1046 trace_usb_uhci_frame_stop_bandwidth(); 1047 break; 1048 } 1049 if (is_qh(link)) { 1050 /* QH */ 1051 trace_usb_uhci_qh_load(link & ~0xf); 1052 1053 if (qhdb_insert(&qhdb, link)) { 1054 /* 1055 * We're going in circles. Which is not a bug because 1056 * HCD is allowed to do that as part of the BW management. 1057 * 1058 * Stop processing here if no transaction has been done 1059 * since we've been here last time. 1060 */ 1061 if (td_count == 0) { 1062 trace_usb_uhci_frame_loop_stop_idle(); 1063 break; 1064 } else { 1065 trace_usb_uhci_frame_loop_continue(); 1066 td_count = 0; 1067 qhdb_reset(&qhdb); 1068 qhdb_insert(&qhdb, link); 1069 } 1070 } 1071 1072 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1073 le32_to_cpus(&qh.link); 1074 le32_to_cpus(&qh.el_link); 1075 1076 if (!is_valid(qh.el_link)) { 1077 /* QH w/o elements */ 1078 curr_qh = 0; 1079 link = qh.link; 1080 } else { 1081 /* QH with elements */ 1082 curr_qh = link; 1083 link = qh.el_link; 1084 } 1085 continue; 1086 } 1087 1088 /* TD */ 1089 uhci_read_td(s, &td, link); 1090 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1091 1092 old_td_ctrl = td.ctrl; 1093 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1094 if (old_td_ctrl != td.ctrl) { 1095 /* update the status bits of the TD */ 1096 val = cpu_to_le32(td.ctrl); 1097 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1098 } 1099 1100 switch (ret) { 1101 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1102 goto out; 1103 1104 case TD_RESULT_NEXT_QH: 1105 case TD_RESULT_ASYNC_CONT: 1106 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1107 link = curr_qh ? qh.link : td.link; 1108 continue; 1109 1110 case TD_RESULT_ASYNC_START: 1111 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1112 link = curr_qh ? qh.link : td.link; 1113 continue; 1114 1115 case TD_RESULT_COMPLETE: 1116 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1117 link = td.link; 1118 td_count++; 1119 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1120 1121 if (curr_qh) { 1122 /* update QH element link */ 1123 qh.el_link = link; 1124 val = cpu_to_le32(qh.el_link); 1125 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1126 1127 if (!depth_first(link)) { 1128 /* done with this QH */ 1129 curr_qh = 0; 1130 link = qh.link; 1131 } 1132 } 1133 break; 1134 1135 default: 1136 assert(!"unknown return code"); 1137 } 1138 1139 /* go to the next entry */ 1140 } 1141 1142 out: 1143 s->pending_int_mask |= int_mask; 1144 } 1145 1146 static void uhci_bh(void *opaque) 1147 { 1148 UHCIState *s = opaque; 1149 uhci_process_frame(s); 1150 } 1151 1152 static void uhci_frame_timer(void *opaque) 1153 { 1154 UHCIState *s = opaque; 1155 uint64_t t_now, t_last_run; 1156 int i, frames; 1157 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1158 1159 s->completions_only = false; 1160 qemu_bh_cancel(s->bh); 1161 1162 if (!(s->cmd & UHCI_CMD_RS)) { 1163 /* Full stop */ 1164 trace_usb_uhci_schedule_stop(); 1165 timer_del(s->frame_timer); 1166 uhci_async_cancel_all(s); 1167 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1168 s->status |= UHCI_STS_HCHALTED; 1169 return; 1170 } 1171 1172 /* We still store expire_time in our state, for migration */ 1173 t_last_run = s->expire_time - frame_t; 1174 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1175 1176 /* Process up to MAX_FRAMES_PER_TICK frames */ 1177 frames = (t_now - t_last_run) / frame_t; 1178 if (frames > s->maxframes) { 1179 int skipped = frames - s->maxframes; 1180 s->expire_time += skipped * frame_t; 1181 s->frnum = (s->frnum + skipped) & 0x7ff; 1182 frames -= skipped; 1183 } 1184 if (frames > MAX_FRAMES_PER_TICK) { 1185 frames = MAX_FRAMES_PER_TICK; 1186 } 1187 1188 for (i = 0; i < frames; i++) { 1189 s->frame_bytes = 0; 1190 trace_usb_uhci_frame_start(s->frnum); 1191 uhci_async_validate_begin(s); 1192 uhci_process_frame(s); 1193 uhci_async_validate_end(s); 1194 /* The spec says frnum is the frame currently being processed, and 1195 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1196 s->frnum = (s->frnum + 1) & 0x7ff; 1197 s->expire_time += frame_t; 1198 } 1199 1200 /* Complete the previous frame(s) */ 1201 if (s->pending_int_mask) { 1202 s->status2 |= s->pending_int_mask; 1203 s->status |= UHCI_STS_USBINT; 1204 uhci_update_irq(s); 1205 } 1206 s->pending_int_mask = 0; 1207 1208 timer_mod(s->frame_timer, t_now + frame_t); 1209 } 1210 1211 static const MemoryRegionOps uhci_ioport_ops = { 1212 .read = uhci_port_read, 1213 .write = uhci_port_write, 1214 .valid.min_access_size = 1, 1215 .valid.max_access_size = 4, 1216 .impl.min_access_size = 2, 1217 .impl.max_access_size = 2, 1218 .endianness = DEVICE_LITTLE_ENDIAN, 1219 }; 1220 1221 static USBPortOps uhci_port_ops = { 1222 .attach = uhci_attach, 1223 .detach = uhci_detach, 1224 .child_detach = uhci_child_detach, 1225 .wakeup = uhci_wakeup, 1226 .complete = uhci_async_complete, 1227 }; 1228 1229 static USBBusOps uhci_bus_ops = { 1230 }; 1231 1232 static int usb_uhci_common_initfn(PCIDevice *dev) 1233 { 1234 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1235 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1236 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1237 uint8_t *pci_conf = s->dev.config; 1238 int i; 1239 1240 pci_conf[PCI_CLASS_PROG] = 0x00; 1241 /* TODO: reset value should be 0. */ 1242 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1243 1244 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1245 1246 if (s->masterbus) { 1247 USBPort *ports[NB_PORTS]; 1248 for(i = 0; i < NB_PORTS; i++) { 1249 ports[i] = &s->ports[i].port; 1250 } 1251 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1252 s->firstport, s, &uhci_port_ops, 1253 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1254 return -1; 1255 } 1256 } else { 1257 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1258 for (i = 0; i < NB_PORTS; i++) { 1259 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1260 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1261 } 1262 } 1263 s->bh = qemu_bh_new(uhci_bh, s); 1264 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1265 s->num_ports_vmstate = NB_PORTS; 1266 QTAILQ_INIT(&s->queues); 1267 1268 qemu_register_reset(uhci_reset, s); 1269 1270 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1271 "uhci", 0x20); 1272 1273 /* Use region 4 for consistency with real hardware. BSD guests seem 1274 to rely on this. */ 1275 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1276 1277 return 0; 1278 } 1279 1280 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1281 { 1282 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1283 uint8_t *pci_conf = s->dev.config; 1284 1285 /* USB misc control 1/2 */ 1286 pci_set_long(pci_conf + 0x40,0x00001000); 1287 /* PM capability */ 1288 pci_set_long(pci_conf + 0x80,0x00020001); 1289 /* USB legacy support */ 1290 pci_set_long(pci_conf + 0xc0,0x00002000); 1291 1292 return usb_uhci_common_initfn(dev); 1293 } 1294 1295 static void usb_uhci_exit(PCIDevice *dev) 1296 { 1297 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1298 1299 memory_region_destroy(&s->io_bar); 1300 } 1301 1302 static Property uhci_properties[] = { 1303 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1304 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1305 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1306 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1307 DEFINE_PROP_END_OF_LIST(), 1308 }; 1309 1310 static void uhci_class_init(ObjectClass *klass, void *data) 1311 { 1312 DeviceClass *dc = DEVICE_CLASS(klass); 1313 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1314 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1315 UHCIInfo *info = data; 1316 1317 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; 1318 k->exit = info->unplug ? usb_uhci_exit : NULL; 1319 k->vendor_id = info->vendor_id; 1320 k->device_id = info->device_id; 1321 k->revision = info->revision; 1322 k->class_id = PCI_CLASS_SERIAL_USB; 1323 dc->hotpluggable = false; 1324 dc->vmsd = &vmstate_uhci; 1325 dc->props = uhci_properties; 1326 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1327 u->info = *info; 1328 } 1329 1330 static UHCIInfo uhci_info[] = { 1331 { 1332 .name = "piix3-usb-uhci", 1333 .vendor_id = PCI_VENDOR_ID_INTEL, 1334 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1335 .revision = 0x01, 1336 .irq_pin = 3, 1337 .unplug = true, 1338 },{ 1339 .name = "piix4-usb-uhci", 1340 .vendor_id = PCI_VENDOR_ID_INTEL, 1341 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1342 .revision = 0x01, 1343 .irq_pin = 3, 1344 .unplug = true, 1345 },{ 1346 .name = "vt82c686b-usb-uhci", 1347 .vendor_id = PCI_VENDOR_ID_VIA, 1348 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1349 .revision = 0x01, 1350 .irq_pin = 3, 1351 .initfn = usb_uhci_vt82c686b_initfn, 1352 .unplug = true, 1353 },{ 1354 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1355 .vendor_id = PCI_VENDOR_ID_INTEL, 1356 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1357 .revision = 0x03, 1358 .irq_pin = 0, 1359 .unplug = false, 1360 },{ 1361 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1362 .vendor_id = PCI_VENDOR_ID_INTEL, 1363 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1364 .revision = 0x03, 1365 .irq_pin = 1, 1366 .unplug = false, 1367 },{ 1368 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1369 .vendor_id = PCI_VENDOR_ID_INTEL, 1370 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1371 .revision = 0x03, 1372 .irq_pin = 2, 1373 .unplug = false, 1374 },{ 1375 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1376 .vendor_id = PCI_VENDOR_ID_INTEL, 1377 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1378 .revision = 0x03, 1379 .irq_pin = 0, 1380 .unplug = false, 1381 },{ 1382 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1383 .vendor_id = PCI_VENDOR_ID_INTEL, 1384 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1385 .revision = 0x03, 1386 .irq_pin = 1, 1387 .unplug = false, 1388 },{ 1389 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1390 .vendor_id = PCI_VENDOR_ID_INTEL, 1391 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1392 .revision = 0x03, 1393 .irq_pin = 2, 1394 .unplug = false, 1395 } 1396 }; 1397 1398 static void uhci_register_types(void) 1399 { 1400 TypeInfo uhci_type_info = { 1401 .parent = TYPE_PCI_DEVICE, 1402 .instance_size = sizeof(UHCIState), 1403 .class_size = sizeof(UHCIPCIDeviceClass), 1404 .class_init = uhci_class_init, 1405 }; 1406 int i; 1407 1408 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1409 uhci_type_info.name = uhci_info[i].name; 1410 uhci_type_info.class_data = uhci_info + i; 1411 type_register(&uhci_type_info); 1412 } 1413 } 1414 1415 type_init(uhci_register_types) 1416