1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "qemu/osdep.h" 29 #include "hw/hw.h" 30 #include "hw/usb.h" 31 #include "hw/usb/uhci-regs.h" 32 #include "hw/pci/pci.h" 33 #include "qapi/error.h" 34 #include "qemu/timer.h" 35 #include "qemu/iov.h" 36 #include "sysemu/dma.h" 37 #include "trace.h" 38 #include "qemu/main-loop.h" 39 40 #define FRAME_TIMER_FREQ 1000 41 42 #define FRAME_MAX_LOOPS 256 43 44 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 45 #define QH_VALID 32 46 47 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 48 49 #define NB_PORTS 2 50 51 enum { 52 TD_RESULT_STOP_FRAME = 10, 53 TD_RESULT_COMPLETE, 54 TD_RESULT_NEXT_QH, 55 TD_RESULT_ASYNC_START, 56 TD_RESULT_ASYNC_CONT, 57 }; 58 59 typedef struct UHCIState UHCIState; 60 typedef struct UHCIAsync UHCIAsync; 61 typedef struct UHCIQueue UHCIQueue; 62 typedef struct UHCIInfo UHCIInfo; 63 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 64 65 struct UHCIInfo { 66 const char *name; 67 uint16_t vendor_id; 68 uint16_t device_id; 69 uint8_t revision; 70 uint8_t irq_pin; 71 void (*realize)(PCIDevice *dev, Error **errp); 72 bool unplug; 73 }; 74 75 struct UHCIPCIDeviceClass { 76 PCIDeviceClass parent_class; 77 UHCIInfo info; 78 }; 79 80 /* 81 * Pending async transaction. 82 * 'packet' must be the first field because completion 83 * handler does "(UHCIAsync *) pkt" cast. 84 */ 85 86 struct UHCIAsync { 87 USBPacket packet; 88 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 89 uint8_t *buf; 90 UHCIQueue *queue; 91 QTAILQ_ENTRY(UHCIAsync) next; 92 uint32_t td_addr; 93 uint8_t done; 94 }; 95 96 struct UHCIQueue { 97 uint32_t qh_addr; 98 uint32_t token; 99 UHCIState *uhci; 100 USBEndpoint *ep; 101 QTAILQ_ENTRY(UHCIQueue) next; 102 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 103 int8_t valid; 104 }; 105 106 typedef struct UHCIPort { 107 USBPort port; 108 uint16_t ctrl; 109 } UHCIPort; 110 111 struct UHCIState { 112 PCIDevice dev; 113 MemoryRegion io_bar; 114 USBBus bus; /* Note unused when we're a companion controller */ 115 uint16_t cmd; /* cmd register */ 116 uint16_t status; 117 uint16_t intr; /* interrupt enable register */ 118 uint16_t frnum; /* frame number */ 119 uint32_t fl_base_addr; /* frame list base address */ 120 uint8_t sof_timing; 121 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 122 int64_t expire_time; 123 QEMUTimer *frame_timer; 124 QEMUBH *bh; 125 uint32_t frame_bytes; 126 uint32_t frame_bandwidth; 127 bool completions_only; 128 UHCIPort ports[NB_PORTS]; 129 130 /* Interrupts that should be raised at the end of the current frame. */ 131 uint32_t pending_int_mask; 132 133 /* Active packets */ 134 QTAILQ_HEAD(, UHCIQueue) queues; 135 uint8_t num_ports_vmstate; 136 137 /* Properties */ 138 char *masterbus; 139 uint32_t firstport; 140 uint32_t maxframes; 141 }; 142 143 typedef struct UHCI_TD { 144 uint32_t link; 145 uint32_t ctrl; /* see TD_CTRL_xxx */ 146 uint32_t token; 147 uint32_t buffer; 148 } UHCI_TD; 149 150 typedef struct UHCI_QH { 151 uint32_t link; 152 uint32_t el_link; 153 } UHCI_QH; 154 155 static void uhci_async_cancel(UHCIAsync *async); 156 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 157 static void uhci_resume(void *opaque); 158 159 #define TYPE_UHCI "pci-uhci-usb" 160 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI) 161 162 static inline int32_t uhci_queue_token(UHCI_TD *td) 163 { 164 if ((td->token & (0xf << 15)) == 0) { 165 /* ctrl ep, cover ep and dev, not pid! */ 166 return td->token & 0x7ff00; 167 } else { 168 /* covers ep, dev, pid -> identifies the endpoint */ 169 return td->token & 0x7ffff; 170 } 171 } 172 173 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 174 USBEndpoint *ep) 175 { 176 UHCIQueue *queue; 177 178 queue = g_new0(UHCIQueue, 1); 179 queue->uhci = s; 180 queue->qh_addr = qh_addr; 181 queue->token = uhci_queue_token(td); 182 queue->ep = ep; 183 QTAILQ_INIT(&queue->asyncs); 184 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 185 queue->valid = QH_VALID; 186 trace_usb_uhci_queue_add(queue->token); 187 return queue; 188 } 189 190 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 191 { 192 UHCIState *s = queue->uhci; 193 UHCIAsync *async; 194 195 while (!QTAILQ_EMPTY(&queue->asyncs)) { 196 async = QTAILQ_FIRST(&queue->asyncs); 197 uhci_async_cancel(async); 198 } 199 usb_device_ep_stopped(queue->ep->dev, queue->ep); 200 201 trace_usb_uhci_queue_del(queue->token, reason); 202 QTAILQ_REMOVE(&s->queues, queue, next); 203 g_free(queue); 204 } 205 206 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 207 { 208 uint32_t token = uhci_queue_token(td); 209 UHCIQueue *queue; 210 211 QTAILQ_FOREACH(queue, &s->queues, next) { 212 if (queue->token == token) { 213 return queue; 214 } 215 } 216 return NULL; 217 } 218 219 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 220 uint32_t td_addr, bool queuing) 221 { 222 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 223 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 224 225 return queue->qh_addr == qh_addr && 226 queue->token == uhci_queue_token(td) && 227 queue_token_addr == queue->ep->dev->addr && 228 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 229 first->td_addr == td_addr); 230 } 231 232 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 233 { 234 UHCIAsync *async = g_new0(UHCIAsync, 1); 235 236 async->queue = queue; 237 async->td_addr = td_addr; 238 usb_packet_init(&async->packet); 239 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 240 241 return async; 242 } 243 244 static void uhci_async_free(UHCIAsync *async) 245 { 246 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 247 usb_packet_cleanup(&async->packet); 248 if (async->buf != async->static_buf) { 249 g_free(async->buf); 250 } 251 g_free(async); 252 } 253 254 static void uhci_async_link(UHCIAsync *async) 255 { 256 UHCIQueue *queue = async->queue; 257 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 258 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 259 } 260 261 static void uhci_async_unlink(UHCIAsync *async) 262 { 263 UHCIQueue *queue = async->queue; 264 QTAILQ_REMOVE(&queue->asyncs, async, next); 265 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 266 } 267 268 static void uhci_async_cancel(UHCIAsync *async) 269 { 270 uhci_async_unlink(async); 271 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 272 async->done); 273 if (!async->done) 274 usb_cancel_packet(&async->packet); 275 uhci_async_free(async); 276 } 277 278 /* 279 * Mark all outstanding async packets as invalid. 280 * This is used for canceling them when TDs are removed by the HCD. 281 */ 282 static void uhci_async_validate_begin(UHCIState *s) 283 { 284 UHCIQueue *queue; 285 286 QTAILQ_FOREACH(queue, &s->queues, next) { 287 queue->valid--; 288 } 289 } 290 291 /* 292 * Cancel async packets that are no longer valid 293 */ 294 static void uhci_async_validate_end(UHCIState *s) 295 { 296 UHCIQueue *queue, *n; 297 298 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 299 if (!queue->valid) { 300 uhci_queue_free(queue, "validate-end"); 301 } 302 } 303 } 304 305 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 306 { 307 UHCIQueue *queue, *n; 308 309 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 310 if (queue->ep->dev == dev) { 311 uhci_queue_free(queue, "cancel-device"); 312 } 313 } 314 } 315 316 static void uhci_async_cancel_all(UHCIState *s) 317 { 318 UHCIQueue *queue, *nq; 319 320 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 321 uhci_queue_free(queue, "cancel-all"); 322 } 323 } 324 325 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 326 { 327 UHCIQueue *queue; 328 UHCIAsync *async; 329 330 QTAILQ_FOREACH(queue, &s->queues, next) { 331 QTAILQ_FOREACH(async, &queue->asyncs, next) { 332 if (async->td_addr == td_addr) { 333 return async; 334 } 335 } 336 } 337 return NULL; 338 } 339 340 static void uhci_update_irq(UHCIState *s) 341 { 342 int level; 343 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 344 ((s->status2 & 2) && (s->intr & (1 << 3))) || 345 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 346 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 347 (s->status & UHCI_STS_HSERR) || 348 (s->status & UHCI_STS_HCPERR)) { 349 level = 1; 350 } else { 351 level = 0; 352 } 353 pci_set_irq(&s->dev, level); 354 } 355 356 static void uhci_reset(DeviceState *dev) 357 { 358 PCIDevice *d = PCI_DEVICE(dev); 359 UHCIState *s = UHCI(d); 360 uint8_t *pci_conf; 361 int i; 362 UHCIPort *port; 363 364 trace_usb_uhci_reset(); 365 366 pci_conf = s->dev.config; 367 368 pci_conf[0x6a] = 0x01; /* usb clock */ 369 pci_conf[0x6b] = 0x00; 370 s->cmd = 0; 371 s->status = UHCI_STS_HCHALTED; 372 s->status2 = 0; 373 s->intr = 0; 374 s->fl_base_addr = 0; 375 s->sof_timing = 64; 376 377 for(i = 0; i < NB_PORTS; i++) { 378 port = &s->ports[i]; 379 port->ctrl = 0x0080; 380 if (port->port.dev && port->port.dev->attached) { 381 usb_port_reset(&port->port); 382 } 383 } 384 385 uhci_async_cancel_all(s); 386 qemu_bh_cancel(s->bh); 387 uhci_update_irq(s); 388 } 389 390 static const VMStateDescription vmstate_uhci_port = { 391 .name = "uhci port", 392 .version_id = 1, 393 .minimum_version_id = 1, 394 .fields = (VMStateField[]) { 395 VMSTATE_UINT16(ctrl, UHCIPort), 396 VMSTATE_END_OF_LIST() 397 } 398 }; 399 400 static int uhci_post_load(void *opaque, int version_id) 401 { 402 UHCIState *s = opaque; 403 404 if (version_id < 2) { 405 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 406 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 407 } 408 return 0; 409 } 410 411 static const VMStateDescription vmstate_uhci = { 412 .name = "uhci", 413 .version_id = 3, 414 .minimum_version_id = 1, 415 .post_load = uhci_post_load, 416 .fields = (VMStateField[]) { 417 VMSTATE_PCI_DEVICE(dev, UHCIState), 418 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 419 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 420 vmstate_uhci_port, UHCIPort), 421 VMSTATE_UINT16(cmd, UHCIState), 422 VMSTATE_UINT16(status, UHCIState), 423 VMSTATE_UINT16(intr, UHCIState), 424 VMSTATE_UINT16(frnum, UHCIState), 425 VMSTATE_UINT32(fl_base_addr, UHCIState), 426 VMSTATE_UINT8(sof_timing, UHCIState), 427 VMSTATE_UINT8(status2, UHCIState), 428 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 429 VMSTATE_INT64_V(expire_time, UHCIState, 2), 430 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 431 VMSTATE_END_OF_LIST() 432 } 433 }; 434 435 static void uhci_port_write(void *opaque, hwaddr addr, 436 uint64_t val, unsigned size) 437 { 438 UHCIState *s = opaque; 439 440 trace_usb_uhci_mmio_writew(addr, val); 441 442 switch(addr) { 443 case 0x00: 444 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 445 /* start frame processing */ 446 trace_usb_uhci_schedule_start(); 447 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 448 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 449 timer_mod(s->frame_timer, s->expire_time); 450 s->status &= ~UHCI_STS_HCHALTED; 451 } else if (!(val & UHCI_CMD_RS)) { 452 s->status |= UHCI_STS_HCHALTED; 453 } 454 if (val & UHCI_CMD_GRESET) { 455 UHCIPort *port; 456 int i; 457 458 /* send reset on the USB bus */ 459 for(i = 0; i < NB_PORTS; i++) { 460 port = &s->ports[i]; 461 usb_device_reset(port->port.dev); 462 } 463 uhci_reset(DEVICE(s)); 464 return; 465 } 466 if (val & UHCI_CMD_HCRESET) { 467 uhci_reset(DEVICE(s)); 468 return; 469 } 470 s->cmd = val; 471 if (val & UHCI_CMD_EGSM) { 472 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 473 (s->ports[1].ctrl & UHCI_PORT_RD)) { 474 uhci_resume(s); 475 } 476 } 477 break; 478 case 0x02: 479 s->status &= ~val; 480 /* XXX: the chip spec is not coherent, so we add a hidden 481 register to distinguish between IOC and SPD */ 482 if (val & UHCI_STS_USBINT) 483 s->status2 = 0; 484 uhci_update_irq(s); 485 break; 486 case 0x04: 487 s->intr = val; 488 uhci_update_irq(s); 489 break; 490 case 0x06: 491 if (s->status & UHCI_STS_HCHALTED) 492 s->frnum = val & 0x7ff; 493 break; 494 case 0x08: 495 s->fl_base_addr &= 0xffff0000; 496 s->fl_base_addr |= val & ~0xfff; 497 break; 498 case 0x0a: 499 s->fl_base_addr &= 0x0000ffff; 500 s->fl_base_addr |= (val << 16); 501 break; 502 case 0x0c: 503 s->sof_timing = val & 0xff; 504 break; 505 case 0x10 ... 0x1f: 506 { 507 UHCIPort *port; 508 USBDevice *dev; 509 int n; 510 511 n = (addr >> 1) & 7; 512 if (n >= NB_PORTS) 513 return; 514 port = &s->ports[n]; 515 dev = port->port.dev; 516 if (dev && dev->attached) { 517 /* port reset */ 518 if ( (val & UHCI_PORT_RESET) && 519 !(port->ctrl & UHCI_PORT_RESET) ) { 520 usb_device_reset(dev); 521 } 522 } 523 port->ctrl &= UHCI_PORT_READ_ONLY; 524 /* enabled may only be set if a device is connected */ 525 if (!(port->ctrl & UHCI_PORT_CCS)) { 526 val &= ~UHCI_PORT_EN; 527 } 528 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 529 /* some bits are reset when a '1' is written to them */ 530 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 531 } 532 break; 533 } 534 } 535 536 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 537 { 538 UHCIState *s = opaque; 539 uint32_t val; 540 541 switch(addr) { 542 case 0x00: 543 val = s->cmd; 544 break; 545 case 0x02: 546 val = s->status; 547 break; 548 case 0x04: 549 val = s->intr; 550 break; 551 case 0x06: 552 val = s->frnum; 553 break; 554 case 0x08: 555 val = s->fl_base_addr & 0xffff; 556 break; 557 case 0x0a: 558 val = (s->fl_base_addr >> 16) & 0xffff; 559 break; 560 case 0x0c: 561 val = s->sof_timing; 562 break; 563 case 0x10 ... 0x1f: 564 { 565 UHCIPort *port; 566 int n; 567 n = (addr >> 1) & 7; 568 if (n >= NB_PORTS) 569 goto read_default; 570 port = &s->ports[n]; 571 val = port->ctrl; 572 } 573 break; 574 default: 575 read_default: 576 val = 0xff7f; /* disabled port */ 577 break; 578 } 579 580 trace_usb_uhci_mmio_readw(addr, val); 581 582 return val; 583 } 584 585 /* signal resume if controller suspended */ 586 static void uhci_resume (void *opaque) 587 { 588 UHCIState *s = (UHCIState *)opaque; 589 590 if (!s) 591 return; 592 593 if (s->cmd & UHCI_CMD_EGSM) { 594 s->cmd |= UHCI_CMD_FGR; 595 s->status |= UHCI_STS_RD; 596 uhci_update_irq(s); 597 } 598 } 599 600 static void uhci_attach(USBPort *port1) 601 { 602 UHCIState *s = port1->opaque; 603 UHCIPort *port = &s->ports[port1->index]; 604 605 /* set connect status */ 606 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 607 608 /* update speed */ 609 if (port->port.dev->speed == USB_SPEED_LOW) { 610 port->ctrl |= UHCI_PORT_LSDA; 611 } else { 612 port->ctrl &= ~UHCI_PORT_LSDA; 613 } 614 615 uhci_resume(s); 616 } 617 618 static void uhci_detach(USBPort *port1) 619 { 620 UHCIState *s = port1->opaque; 621 UHCIPort *port = &s->ports[port1->index]; 622 623 uhci_async_cancel_device(s, port1->dev); 624 625 /* set connect status */ 626 if (port->ctrl & UHCI_PORT_CCS) { 627 port->ctrl &= ~UHCI_PORT_CCS; 628 port->ctrl |= UHCI_PORT_CSC; 629 } 630 /* disable port */ 631 if (port->ctrl & UHCI_PORT_EN) { 632 port->ctrl &= ~UHCI_PORT_EN; 633 port->ctrl |= UHCI_PORT_ENC; 634 } 635 636 uhci_resume(s); 637 } 638 639 static void uhci_child_detach(USBPort *port1, USBDevice *child) 640 { 641 UHCIState *s = port1->opaque; 642 643 uhci_async_cancel_device(s, child); 644 } 645 646 static void uhci_wakeup(USBPort *port1) 647 { 648 UHCIState *s = port1->opaque; 649 UHCIPort *port = &s->ports[port1->index]; 650 651 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 652 port->ctrl |= UHCI_PORT_RD; 653 uhci_resume(s); 654 } 655 } 656 657 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 658 { 659 USBDevice *dev; 660 int i; 661 662 for (i = 0; i < NB_PORTS; i++) { 663 UHCIPort *port = &s->ports[i]; 664 if (!(port->ctrl & UHCI_PORT_EN)) { 665 continue; 666 } 667 dev = usb_find_device(&port->port, addr); 668 if (dev != NULL) { 669 return dev; 670 } 671 } 672 return NULL; 673 } 674 675 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 676 { 677 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 678 le32_to_cpus(&td->link); 679 le32_to_cpus(&td->ctrl); 680 le32_to_cpus(&td->token); 681 le32_to_cpus(&td->buffer); 682 } 683 684 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 685 int status, uint32_t *int_mask) 686 { 687 uint32_t queue_token = uhci_queue_token(td); 688 int ret; 689 690 switch (status) { 691 case USB_RET_NAK: 692 td->ctrl |= TD_CTRL_NAK; 693 return TD_RESULT_NEXT_QH; 694 695 case USB_RET_STALL: 696 td->ctrl |= TD_CTRL_STALL; 697 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 698 ret = TD_RESULT_NEXT_QH; 699 break; 700 701 case USB_RET_BABBLE: 702 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 703 /* frame interrupted */ 704 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 705 ret = TD_RESULT_STOP_FRAME; 706 break; 707 708 case USB_RET_IOERROR: 709 case USB_RET_NODEV: 710 default: 711 td->ctrl |= TD_CTRL_TIMEOUT; 712 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 713 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 714 ret = TD_RESULT_NEXT_QH; 715 break; 716 } 717 718 td->ctrl &= ~TD_CTRL_ACTIVE; 719 s->status |= UHCI_STS_USBERR; 720 if (td->ctrl & TD_CTRL_IOC) { 721 *int_mask |= 0x01; 722 } 723 uhci_update_irq(s); 724 return ret; 725 } 726 727 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 728 { 729 int len = 0, max_len; 730 uint8_t pid; 731 732 max_len = ((td->token >> 21) + 1) & 0x7ff; 733 pid = td->token & 0xff; 734 735 if (td->ctrl & TD_CTRL_IOS) 736 td->ctrl &= ~TD_CTRL_ACTIVE; 737 738 if (async->packet.status != USB_RET_SUCCESS) { 739 return uhci_handle_td_error(s, td, async->td_addr, 740 async->packet.status, int_mask); 741 } 742 743 len = async->packet.actual_length; 744 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 745 746 /* The NAK bit may have been set by a previous frame, so clear it 747 here. The docs are somewhat unclear, but win2k relies on this 748 behavior. */ 749 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 750 if (td->ctrl & TD_CTRL_IOC) 751 *int_mask |= 0x01; 752 753 if (pid == USB_TOKEN_IN) { 754 pci_dma_write(&s->dev, td->buffer, async->buf, len); 755 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 756 *int_mask |= 0x02; 757 /* short packet: do not update QH */ 758 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 759 async->td_addr); 760 return TD_RESULT_NEXT_QH; 761 } 762 } 763 764 /* success */ 765 trace_usb_uhci_packet_complete_success(async->queue->token, 766 async->td_addr); 767 return TD_RESULT_COMPLETE; 768 } 769 770 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 771 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 772 { 773 int ret, max_len; 774 bool spd; 775 bool queuing = (q != NULL); 776 uint8_t pid = td->token & 0xff; 777 UHCIAsync *async; 778 779 async = uhci_async_find_td(s, td_addr); 780 if (async) { 781 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 782 assert(q == NULL || q == async->queue); 783 q = async->queue; 784 } else { 785 uhci_queue_free(async->queue, "guest re-used pending td"); 786 async = NULL; 787 } 788 } 789 790 if (q == NULL) { 791 q = uhci_queue_find(s, td); 792 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 793 uhci_queue_free(q, "guest re-used qh"); 794 q = NULL; 795 } 796 } 797 798 if (q) { 799 q->valid = QH_VALID; 800 } 801 802 /* Is active ? */ 803 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 804 if (async) { 805 /* Guest marked a pending td non-active, cancel the queue */ 806 uhci_queue_free(async->queue, "pending td non-active"); 807 } 808 /* 809 * ehci11d spec page 22: "Even if the Active bit in the TD is already 810 * cleared when the TD is fetched ... an IOC interrupt is generated" 811 */ 812 if (td->ctrl & TD_CTRL_IOC) { 813 *int_mask |= 0x01; 814 } 815 return TD_RESULT_NEXT_QH; 816 } 817 818 switch (pid) { 819 case USB_TOKEN_OUT: 820 case USB_TOKEN_SETUP: 821 case USB_TOKEN_IN: 822 break; 823 default: 824 /* invalid pid : frame interrupted */ 825 s->status |= UHCI_STS_HCPERR; 826 s->cmd &= ~UHCI_CMD_RS; 827 uhci_update_irq(s); 828 return TD_RESULT_STOP_FRAME; 829 } 830 831 if (async) { 832 if (queuing) { 833 /* we are busy filling the queue, we are not prepared 834 to consume completed packages then, just leave them 835 in async state */ 836 return TD_RESULT_ASYNC_CONT; 837 } 838 if (!async->done) { 839 UHCI_TD last_td; 840 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 841 /* 842 * While we are waiting for the current td to complete, the guest 843 * may have added more tds to the queue. Note we re-read the td 844 * rather then caching it, as we want to see guest made changes! 845 */ 846 uhci_read_td(s, &last_td, last->td_addr); 847 uhci_queue_fill(async->queue, &last_td); 848 849 return TD_RESULT_ASYNC_CONT; 850 } 851 uhci_async_unlink(async); 852 goto done; 853 } 854 855 if (s->completions_only) { 856 return TD_RESULT_ASYNC_CONT; 857 } 858 859 /* Allocate new packet */ 860 if (q == NULL) { 861 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 862 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 863 864 if (ep == NULL) { 865 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 866 int_mask); 867 } 868 q = uhci_queue_new(s, qh_addr, td, ep); 869 } 870 async = uhci_async_alloc(q, td_addr); 871 872 max_len = ((td->token >> 21) + 1) & 0x7ff; 873 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 874 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 875 (td->ctrl & TD_CTRL_IOC) != 0); 876 if (max_len <= sizeof(async->static_buf)) { 877 async->buf = async->static_buf; 878 } else { 879 async->buf = g_malloc(max_len); 880 } 881 usb_packet_addbuf(&async->packet, async->buf, max_len); 882 883 switch(pid) { 884 case USB_TOKEN_OUT: 885 case USB_TOKEN_SETUP: 886 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 887 usb_handle_packet(q->ep->dev, &async->packet); 888 if (async->packet.status == USB_RET_SUCCESS) { 889 async->packet.actual_length = max_len; 890 } 891 break; 892 893 case USB_TOKEN_IN: 894 usb_handle_packet(q->ep->dev, &async->packet); 895 break; 896 897 default: 898 abort(); /* Never to execute */ 899 } 900 901 if (async->packet.status == USB_RET_ASYNC) { 902 uhci_async_link(async); 903 if (!queuing) { 904 uhci_queue_fill(q, td); 905 } 906 return TD_RESULT_ASYNC_START; 907 } 908 909 done: 910 ret = uhci_complete_td(s, td, async, int_mask); 911 uhci_async_free(async); 912 return ret; 913 } 914 915 static void uhci_async_complete(USBPort *port, USBPacket *packet) 916 { 917 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 918 UHCIState *s = async->queue->uhci; 919 920 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 921 uhci_async_cancel(async); 922 return; 923 } 924 925 async->done = 1; 926 /* Force processing of this packet *now*, needed for migration */ 927 s->completions_only = true; 928 qemu_bh_schedule(s->bh); 929 } 930 931 static int is_valid(uint32_t link) 932 { 933 return (link & 1) == 0; 934 } 935 936 static int is_qh(uint32_t link) 937 { 938 return (link & 2) != 0; 939 } 940 941 static int depth_first(uint32_t link) 942 { 943 return (link & 4) != 0; 944 } 945 946 /* QH DB used for detecting QH loops */ 947 #define UHCI_MAX_QUEUES 128 948 typedef struct { 949 uint32_t addr[UHCI_MAX_QUEUES]; 950 int count; 951 } QhDb; 952 953 static void qhdb_reset(QhDb *db) 954 { 955 db->count = 0; 956 } 957 958 /* Add QH to DB. Returns 1 if already present or DB is full. */ 959 static int qhdb_insert(QhDb *db, uint32_t addr) 960 { 961 int i; 962 for (i = 0; i < db->count; i++) 963 if (db->addr[i] == addr) 964 return 1; 965 966 if (db->count >= UHCI_MAX_QUEUES) 967 return 1; 968 969 db->addr[db->count++] = addr; 970 return 0; 971 } 972 973 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 974 { 975 uint32_t int_mask = 0; 976 uint32_t plink = td->link; 977 UHCI_TD ptd; 978 int ret; 979 980 while (is_valid(plink)) { 981 uhci_read_td(q->uhci, &ptd, plink); 982 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 983 break; 984 } 985 if (uhci_queue_token(&ptd) != q->token) { 986 break; 987 } 988 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 989 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 990 if (ret == TD_RESULT_ASYNC_CONT) { 991 break; 992 } 993 assert(ret == TD_RESULT_ASYNC_START); 994 assert(int_mask == 0); 995 plink = ptd.link; 996 } 997 usb_device_flush_ep_queue(q->ep->dev, q->ep); 998 } 999 1000 static void uhci_process_frame(UHCIState *s) 1001 { 1002 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1003 uint32_t curr_qh, td_count = 0; 1004 int cnt, ret; 1005 UHCI_TD td; 1006 UHCI_QH qh; 1007 QhDb qhdb; 1008 1009 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1010 1011 pci_dma_read(&s->dev, frame_addr, &link, 4); 1012 le32_to_cpus(&link); 1013 1014 int_mask = 0; 1015 curr_qh = 0; 1016 1017 qhdb_reset(&qhdb); 1018 1019 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1020 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1021 /* We've reached the usb 1.1 bandwidth, which is 1022 1280 bytes/frame, stop processing */ 1023 trace_usb_uhci_frame_stop_bandwidth(); 1024 break; 1025 } 1026 if (is_qh(link)) { 1027 /* QH */ 1028 trace_usb_uhci_qh_load(link & ~0xf); 1029 1030 if (qhdb_insert(&qhdb, link)) { 1031 /* 1032 * We're going in circles. Which is not a bug because 1033 * HCD is allowed to do that as part of the BW management. 1034 * 1035 * Stop processing here if no transaction has been done 1036 * since we've been here last time. 1037 */ 1038 if (td_count == 0) { 1039 trace_usb_uhci_frame_loop_stop_idle(); 1040 break; 1041 } else { 1042 trace_usb_uhci_frame_loop_continue(); 1043 td_count = 0; 1044 qhdb_reset(&qhdb); 1045 qhdb_insert(&qhdb, link); 1046 } 1047 } 1048 1049 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1050 le32_to_cpus(&qh.link); 1051 le32_to_cpus(&qh.el_link); 1052 1053 if (!is_valid(qh.el_link)) { 1054 /* QH w/o elements */ 1055 curr_qh = 0; 1056 link = qh.link; 1057 } else { 1058 /* QH with elements */ 1059 curr_qh = link; 1060 link = qh.el_link; 1061 } 1062 continue; 1063 } 1064 1065 /* TD */ 1066 uhci_read_td(s, &td, link); 1067 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1068 1069 old_td_ctrl = td.ctrl; 1070 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1071 if (old_td_ctrl != td.ctrl) { 1072 /* update the status bits of the TD */ 1073 val = cpu_to_le32(td.ctrl); 1074 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1075 } 1076 1077 switch (ret) { 1078 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1079 goto out; 1080 1081 case TD_RESULT_NEXT_QH: 1082 case TD_RESULT_ASYNC_CONT: 1083 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1084 link = curr_qh ? qh.link : td.link; 1085 continue; 1086 1087 case TD_RESULT_ASYNC_START: 1088 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1089 link = curr_qh ? qh.link : td.link; 1090 continue; 1091 1092 case TD_RESULT_COMPLETE: 1093 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1094 link = td.link; 1095 td_count++; 1096 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1097 1098 if (curr_qh) { 1099 /* update QH element link */ 1100 qh.el_link = link; 1101 val = cpu_to_le32(qh.el_link); 1102 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1103 1104 if (!depth_first(link)) { 1105 /* done with this QH */ 1106 curr_qh = 0; 1107 link = qh.link; 1108 } 1109 } 1110 break; 1111 1112 default: 1113 assert(!"unknown return code"); 1114 } 1115 1116 /* go to the next entry */ 1117 } 1118 1119 out: 1120 s->pending_int_mask |= int_mask; 1121 } 1122 1123 static void uhci_bh(void *opaque) 1124 { 1125 UHCIState *s = opaque; 1126 uhci_process_frame(s); 1127 } 1128 1129 static void uhci_frame_timer(void *opaque) 1130 { 1131 UHCIState *s = opaque; 1132 uint64_t t_now, t_last_run; 1133 int i, frames; 1134 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1135 1136 s->completions_only = false; 1137 qemu_bh_cancel(s->bh); 1138 1139 if (!(s->cmd & UHCI_CMD_RS)) { 1140 /* Full stop */ 1141 trace_usb_uhci_schedule_stop(); 1142 timer_del(s->frame_timer); 1143 uhci_async_cancel_all(s); 1144 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1145 s->status |= UHCI_STS_HCHALTED; 1146 return; 1147 } 1148 1149 /* We still store expire_time in our state, for migration */ 1150 t_last_run = s->expire_time - frame_t; 1151 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1152 1153 /* Process up to MAX_FRAMES_PER_TICK frames */ 1154 frames = (t_now - t_last_run) / frame_t; 1155 if (frames > s->maxframes) { 1156 int skipped = frames - s->maxframes; 1157 s->expire_time += skipped * frame_t; 1158 s->frnum = (s->frnum + skipped) & 0x7ff; 1159 frames -= skipped; 1160 } 1161 if (frames > MAX_FRAMES_PER_TICK) { 1162 frames = MAX_FRAMES_PER_TICK; 1163 } 1164 1165 for (i = 0; i < frames; i++) { 1166 s->frame_bytes = 0; 1167 trace_usb_uhci_frame_start(s->frnum); 1168 uhci_async_validate_begin(s); 1169 uhci_process_frame(s); 1170 uhci_async_validate_end(s); 1171 /* The spec says frnum is the frame currently being processed, and 1172 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1173 s->frnum = (s->frnum + 1) & 0x7ff; 1174 s->expire_time += frame_t; 1175 } 1176 1177 /* Complete the previous frame(s) */ 1178 if (s->pending_int_mask) { 1179 s->status2 |= s->pending_int_mask; 1180 s->status |= UHCI_STS_USBINT; 1181 uhci_update_irq(s); 1182 } 1183 s->pending_int_mask = 0; 1184 1185 timer_mod(s->frame_timer, t_now + frame_t); 1186 } 1187 1188 static const MemoryRegionOps uhci_ioport_ops = { 1189 .read = uhci_port_read, 1190 .write = uhci_port_write, 1191 .valid.min_access_size = 1, 1192 .valid.max_access_size = 4, 1193 .impl.min_access_size = 2, 1194 .impl.max_access_size = 2, 1195 .endianness = DEVICE_LITTLE_ENDIAN, 1196 }; 1197 1198 static USBPortOps uhci_port_ops = { 1199 .attach = uhci_attach, 1200 .detach = uhci_detach, 1201 .child_detach = uhci_child_detach, 1202 .wakeup = uhci_wakeup, 1203 .complete = uhci_async_complete, 1204 }; 1205 1206 static USBBusOps uhci_bus_ops = { 1207 }; 1208 1209 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1210 { 1211 Error *err = NULL; 1212 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1213 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1214 UHCIState *s = UHCI(dev); 1215 uint8_t *pci_conf = s->dev.config; 1216 int i; 1217 1218 pci_conf[PCI_CLASS_PROG] = 0x00; 1219 /* TODO: reset value should be 0. */ 1220 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1221 1222 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1223 1224 if (s->masterbus) { 1225 USBPort *ports[NB_PORTS]; 1226 for(i = 0; i < NB_PORTS; i++) { 1227 ports[i] = &s->ports[i].port; 1228 } 1229 usb_register_companion(s->masterbus, ports, NB_PORTS, 1230 s->firstport, s, &uhci_port_ops, 1231 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1232 &err); 1233 if (err) { 1234 error_propagate(errp, err); 1235 return; 1236 } 1237 } else { 1238 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1239 for (i = 0; i < NB_PORTS; i++) { 1240 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1241 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1242 } 1243 } 1244 s->bh = qemu_bh_new(uhci_bh, s); 1245 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1246 s->num_ports_vmstate = NB_PORTS; 1247 QTAILQ_INIT(&s->queues); 1248 1249 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1250 "uhci", 0x20); 1251 1252 /* Use region 4 for consistency with real hardware. BSD guests seem 1253 to rely on this. */ 1254 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1255 } 1256 1257 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) 1258 { 1259 UHCIState *s = UHCI(dev); 1260 uint8_t *pci_conf = s->dev.config; 1261 1262 /* USB misc control 1/2 */ 1263 pci_set_long(pci_conf + 0x40,0x00001000); 1264 /* PM capability */ 1265 pci_set_long(pci_conf + 0x80,0x00020001); 1266 /* USB legacy support */ 1267 pci_set_long(pci_conf + 0xc0,0x00002000); 1268 1269 usb_uhci_common_realize(dev, errp); 1270 } 1271 1272 static void usb_uhci_exit(PCIDevice *dev) 1273 { 1274 UHCIState *s = UHCI(dev); 1275 1276 trace_usb_uhci_exit(); 1277 1278 if (s->frame_timer) { 1279 timer_del(s->frame_timer); 1280 timer_free(s->frame_timer); 1281 s->frame_timer = NULL; 1282 } 1283 1284 if (s->bh) { 1285 qemu_bh_delete(s->bh); 1286 } 1287 1288 uhci_async_cancel_all(s); 1289 1290 if (!s->masterbus) { 1291 usb_bus_release(&s->bus); 1292 } 1293 } 1294 1295 static Property uhci_properties_companion[] = { 1296 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1297 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1298 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1299 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1300 DEFINE_PROP_END_OF_LIST(), 1301 }; 1302 static Property uhci_properties_standalone[] = { 1303 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1304 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1305 DEFINE_PROP_END_OF_LIST(), 1306 }; 1307 1308 static void uhci_class_init(ObjectClass *klass, void *data) 1309 { 1310 DeviceClass *dc = DEVICE_CLASS(klass); 1311 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1312 1313 k->class_id = PCI_CLASS_SERIAL_USB; 1314 dc->vmsd = &vmstate_uhci; 1315 dc->reset = uhci_reset; 1316 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1317 } 1318 1319 static const TypeInfo uhci_pci_type_info = { 1320 .name = TYPE_UHCI, 1321 .parent = TYPE_PCI_DEVICE, 1322 .instance_size = sizeof(UHCIState), 1323 .class_size = sizeof(UHCIPCIDeviceClass), 1324 .abstract = true, 1325 .class_init = uhci_class_init, 1326 .interfaces = (InterfaceInfo[]) { 1327 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1328 { }, 1329 }, 1330 }; 1331 1332 static void uhci_data_class_init(ObjectClass *klass, void *data) 1333 { 1334 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1335 DeviceClass *dc = DEVICE_CLASS(klass); 1336 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1337 UHCIInfo *info = data; 1338 1339 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1340 k->exit = info->unplug ? usb_uhci_exit : NULL; 1341 k->vendor_id = info->vendor_id; 1342 k->device_id = info->device_id; 1343 k->revision = info->revision; 1344 if (!info->unplug) { 1345 /* uhci controllers in companion setups can't be hotplugged */ 1346 dc->hotpluggable = false; 1347 dc->props = uhci_properties_companion; 1348 } else { 1349 dc->props = uhci_properties_standalone; 1350 } 1351 u->info = *info; 1352 } 1353 1354 static UHCIInfo uhci_info[] = { 1355 { 1356 .name = "piix3-usb-uhci", 1357 .vendor_id = PCI_VENDOR_ID_INTEL, 1358 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1359 .revision = 0x01, 1360 .irq_pin = 3, 1361 .unplug = true, 1362 },{ 1363 .name = "piix4-usb-uhci", 1364 .vendor_id = PCI_VENDOR_ID_INTEL, 1365 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1366 .revision = 0x01, 1367 .irq_pin = 3, 1368 .unplug = true, 1369 },{ 1370 .name = "vt82c686b-usb-uhci", 1371 .vendor_id = PCI_VENDOR_ID_VIA, 1372 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1373 .revision = 0x01, 1374 .irq_pin = 3, 1375 .realize = usb_uhci_vt82c686b_realize, 1376 .unplug = true, 1377 },{ 1378 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1379 .vendor_id = PCI_VENDOR_ID_INTEL, 1380 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1381 .revision = 0x03, 1382 .irq_pin = 0, 1383 .unplug = false, 1384 },{ 1385 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1386 .vendor_id = PCI_VENDOR_ID_INTEL, 1387 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1388 .revision = 0x03, 1389 .irq_pin = 1, 1390 .unplug = false, 1391 },{ 1392 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1393 .vendor_id = PCI_VENDOR_ID_INTEL, 1394 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1395 .revision = 0x03, 1396 .irq_pin = 2, 1397 .unplug = false, 1398 },{ 1399 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1400 .vendor_id = PCI_VENDOR_ID_INTEL, 1401 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1402 .revision = 0x03, 1403 .irq_pin = 0, 1404 .unplug = false, 1405 },{ 1406 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1407 .vendor_id = PCI_VENDOR_ID_INTEL, 1408 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1409 .revision = 0x03, 1410 .irq_pin = 1, 1411 .unplug = false, 1412 },{ 1413 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1414 .vendor_id = PCI_VENDOR_ID_INTEL, 1415 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1416 .revision = 0x03, 1417 .irq_pin = 2, 1418 .unplug = false, 1419 } 1420 }; 1421 1422 static void uhci_register_types(void) 1423 { 1424 TypeInfo uhci_type_info = { 1425 .parent = TYPE_UHCI, 1426 .class_init = uhci_data_class_init, 1427 }; 1428 int i; 1429 1430 type_register_static(&uhci_pci_type_info); 1431 1432 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1433 uhci_type_info.name = uhci_info[i].name; 1434 uhci_type_info.class_data = uhci_info + i; 1435 type_register(&uhci_type_info); 1436 } 1437 } 1438 1439 type_init(uhci_register_types) 1440