1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci.h" 31 #include "qemu-timer.h" 32 #include "iov.h" 33 #include "dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 #define NB_PORTS 2 79 80 enum { 81 TD_RESULT_STOP_FRAME = 10, 82 TD_RESULT_COMPLETE, 83 TD_RESULT_NEXT_QH, 84 TD_RESULT_ASYNC_START, 85 TD_RESULT_ASYNC_CONT, 86 }; 87 88 typedef struct UHCIState UHCIState; 89 typedef struct UHCIAsync UHCIAsync; 90 typedef struct UHCIQueue UHCIQueue; 91 92 /* 93 * Pending async transaction. 94 * 'packet' must be the first field because completion 95 * handler does "(UHCIAsync *) pkt" cast. 96 */ 97 98 struct UHCIAsync { 99 USBPacket packet; 100 QEMUSGList sgl; 101 UHCIQueue *queue; 102 QTAILQ_ENTRY(UHCIAsync) next; 103 uint32_t td; 104 uint8_t isoc; 105 uint8_t done; 106 }; 107 108 struct UHCIQueue { 109 uint32_t token; 110 UHCIState *uhci; 111 QTAILQ_ENTRY(UHCIQueue) next; 112 QTAILQ_HEAD(, UHCIAsync) asyncs; 113 int8_t valid; 114 }; 115 116 typedef struct UHCIPort { 117 USBPort port; 118 uint16_t ctrl; 119 } UHCIPort; 120 121 struct UHCIState { 122 PCIDevice dev; 123 MemoryRegion io_bar; 124 USBBus bus; /* Note unused when we're a companion controller */ 125 uint16_t cmd; /* cmd register */ 126 uint16_t status; 127 uint16_t intr; /* interrupt enable register */ 128 uint16_t frnum; /* frame number */ 129 uint32_t fl_base_addr; /* frame list base address */ 130 uint8_t sof_timing; 131 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 132 int64_t expire_time; 133 QEMUTimer *frame_timer; 134 QEMUBH *bh; 135 uint32_t frame_bytes; 136 uint32_t frame_bandwidth; 137 UHCIPort ports[NB_PORTS]; 138 139 /* Interrupts that should be raised at the end of the current frame. */ 140 uint32_t pending_int_mask; 141 int irq_pin; 142 143 /* Active packets */ 144 QTAILQ_HEAD(, UHCIQueue) queues; 145 uint8_t num_ports_vmstate; 146 147 /* Properties */ 148 char *masterbus; 149 uint32_t firstport; 150 }; 151 152 typedef struct UHCI_TD { 153 uint32_t link; 154 uint32_t ctrl; /* see TD_CTRL_xxx */ 155 uint32_t token; 156 uint32_t buffer; 157 } UHCI_TD; 158 159 typedef struct UHCI_QH { 160 uint32_t link; 161 uint32_t el_link; 162 } UHCI_QH; 163 164 static inline int32_t uhci_queue_token(UHCI_TD *td) 165 { 166 /* covers ep, dev, pid -> identifies the endpoint */ 167 return td->token & 0x7ffff; 168 } 169 170 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) 171 { 172 uint32_t token = uhci_queue_token(td); 173 UHCIQueue *queue; 174 175 QTAILQ_FOREACH(queue, &s->queues, next) { 176 if (queue->token == token) { 177 return queue; 178 } 179 } 180 181 queue = g_new0(UHCIQueue, 1); 182 queue->uhci = s; 183 queue->token = token; 184 QTAILQ_INIT(&queue->asyncs); 185 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 186 trace_usb_uhci_queue_add(queue->token); 187 return queue; 188 } 189 190 static void uhci_queue_free(UHCIQueue *queue) 191 { 192 UHCIState *s = queue->uhci; 193 194 trace_usb_uhci_queue_del(queue->token); 195 QTAILQ_REMOVE(&s->queues, queue, next); 196 g_free(queue); 197 } 198 199 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) 200 { 201 UHCIAsync *async = g_new0(UHCIAsync, 1); 202 203 async->queue = queue; 204 async->td = addr; 205 usb_packet_init(&async->packet); 206 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 207 trace_usb_uhci_packet_add(async->queue->token, async->td); 208 209 return async; 210 } 211 212 static void uhci_async_free(UHCIAsync *async) 213 { 214 trace_usb_uhci_packet_del(async->queue->token, async->td); 215 usb_packet_cleanup(&async->packet); 216 qemu_sglist_destroy(&async->sgl); 217 g_free(async); 218 } 219 220 static void uhci_async_link(UHCIAsync *async) 221 { 222 UHCIQueue *queue = async->queue; 223 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 224 trace_usb_uhci_packet_link_async(async->queue->token, async->td); 225 } 226 227 static void uhci_async_unlink(UHCIAsync *async) 228 { 229 UHCIQueue *queue = async->queue; 230 QTAILQ_REMOVE(&queue->asyncs, async, next); 231 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); 232 } 233 234 static void uhci_async_cancel(UHCIAsync *async) 235 { 236 trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); 237 if (!async->done) 238 usb_cancel_packet(&async->packet); 239 uhci_async_free(async); 240 } 241 242 /* 243 * Mark all outstanding async packets as invalid. 244 * This is used for canceling them when TDs are removed by the HCD. 245 */ 246 static void uhci_async_validate_begin(UHCIState *s) 247 { 248 UHCIQueue *queue; 249 250 QTAILQ_FOREACH(queue, &s->queues, next) { 251 queue->valid--; 252 } 253 } 254 255 /* 256 * Cancel async packets that are no longer valid 257 */ 258 static void uhci_async_validate_end(UHCIState *s) 259 { 260 UHCIQueue *queue, *n; 261 UHCIAsync *async; 262 263 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 264 if (queue->valid > 0) { 265 continue; 266 } 267 while (!QTAILQ_EMPTY(&queue->asyncs)) { 268 async = QTAILQ_FIRST(&queue->asyncs); 269 uhci_async_unlink(async); 270 uhci_async_cancel(async); 271 } 272 uhci_queue_free(queue); 273 } 274 } 275 276 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 277 { 278 UHCIQueue *queue; 279 UHCIAsync *curr, *n; 280 281 QTAILQ_FOREACH(queue, &s->queues, next) { 282 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 283 if (!usb_packet_is_inflight(&curr->packet) || 284 curr->packet.ep->dev != dev) { 285 continue; 286 } 287 uhci_async_unlink(curr); 288 uhci_async_cancel(curr); 289 } 290 } 291 } 292 293 static void uhci_async_cancel_all(UHCIState *s) 294 { 295 UHCIQueue *queue, *nq; 296 UHCIAsync *curr, *n; 297 298 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 299 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 300 uhci_async_unlink(curr); 301 uhci_async_cancel(curr); 302 } 303 uhci_queue_free(queue); 304 } 305 } 306 307 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) 308 { 309 uint32_t token = uhci_queue_token(td); 310 UHCIQueue *queue; 311 UHCIAsync *async; 312 313 QTAILQ_FOREACH(queue, &s->queues, next) { 314 if (queue->token == token) { 315 break; 316 } 317 } 318 if (queue == NULL) { 319 return NULL; 320 } 321 322 QTAILQ_FOREACH(async, &queue->asyncs, next) { 323 if (async->td == addr) { 324 return async; 325 } 326 } 327 328 return NULL; 329 } 330 331 static void uhci_update_irq(UHCIState *s) 332 { 333 int level; 334 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 335 ((s->status2 & 2) && (s->intr & (1 << 3))) || 336 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 337 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 338 (s->status & UHCI_STS_HSERR) || 339 (s->status & UHCI_STS_HCPERR)) { 340 level = 1; 341 } else { 342 level = 0; 343 } 344 qemu_set_irq(s->dev.irq[s->irq_pin], level); 345 } 346 347 static void uhci_reset(void *opaque) 348 { 349 UHCIState *s = opaque; 350 uint8_t *pci_conf; 351 int i; 352 UHCIPort *port; 353 354 trace_usb_uhci_reset(); 355 356 pci_conf = s->dev.config; 357 358 pci_conf[0x6a] = 0x01; /* usb clock */ 359 pci_conf[0x6b] = 0x00; 360 s->cmd = 0; 361 s->status = 0; 362 s->status2 = 0; 363 s->intr = 0; 364 s->fl_base_addr = 0; 365 s->sof_timing = 64; 366 367 for(i = 0; i < NB_PORTS; i++) { 368 port = &s->ports[i]; 369 port->ctrl = 0x0080; 370 if (port->port.dev && port->port.dev->attached) { 371 usb_port_reset(&port->port); 372 } 373 } 374 375 uhci_async_cancel_all(s); 376 qemu_bh_cancel(s->bh); 377 uhci_update_irq(s); 378 } 379 380 static const VMStateDescription vmstate_uhci_port = { 381 .name = "uhci port", 382 .version_id = 1, 383 .minimum_version_id = 1, 384 .minimum_version_id_old = 1, 385 .fields = (VMStateField []) { 386 VMSTATE_UINT16(ctrl, UHCIPort), 387 VMSTATE_END_OF_LIST() 388 } 389 }; 390 391 static int uhci_post_load(void *opaque, int version_id) 392 { 393 UHCIState *s = opaque; 394 395 if (version_id < 2) { 396 s->expire_time = qemu_get_clock_ns(vm_clock) + 397 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 398 } 399 return 0; 400 } 401 402 static const VMStateDescription vmstate_uhci = { 403 .name = "uhci", 404 .version_id = 2, 405 .minimum_version_id = 1, 406 .minimum_version_id_old = 1, 407 .post_load = uhci_post_load, 408 .fields = (VMStateField []) { 409 VMSTATE_PCI_DEVICE(dev, UHCIState), 410 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 411 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 412 vmstate_uhci_port, UHCIPort), 413 VMSTATE_UINT16(cmd, UHCIState), 414 VMSTATE_UINT16(status, UHCIState), 415 VMSTATE_UINT16(intr, UHCIState), 416 VMSTATE_UINT16(frnum, UHCIState), 417 VMSTATE_UINT32(fl_base_addr, UHCIState), 418 VMSTATE_UINT8(sof_timing, UHCIState), 419 VMSTATE_UINT8(status2, UHCIState), 420 VMSTATE_TIMER(frame_timer, UHCIState), 421 VMSTATE_INT64_V(expire_time, UHCIState, 2), 422 VMSTATE_END_OF_LIST() 423 } 424 }; 425 426 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 427 { 428 UHCIState *s = opaque; 429 430 addr &= 0x1f; 431 switch(addr) { 432 case 0x0c: 433 s->sof_timing = val; 434 break; 435 } 436 } 437 438 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) 439 { 440 UHCIState *s = opaque; 441 uint32_t val; 442 443 addr &= 0x1f; 444 switch(addr) { 445 case 0x0c: 446 val = s->sof_timing; 447 break; 448 default: 449 val = 0xff; 450 break; 451 } 452 return val; 453 } 454 455 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 456 { 457 UHCIState *s = opaque; 458 459 addr &= 0x1f; 460 trace_usb_uhci_mmio_writew(addr, val); 461 462 switch(addr) { 463 case 0x00: 464 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 465 /* start frame processing */ 466 trace_usb_uhci_schedule_start(); 467 s->expire_time = qemu_get_clock_ns(vm_clock) + 468 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 469 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 470 s->status &= ~UHCI_STS_HCHALTED; 471 } else if (!(val & UHCI_CMD_RS)) { 472 s->status |= UHCI_STS_HCHALTED; 473 } 474 if (val & UHCI_CMD_GRESET) { 475 UHCIPort *port; 476 int i; 477 478 /* send reset on the USB bus */ 479 for(i = 0; i < NB_PORTS; i++) { 480 port = &s->ports[i]; 481 usb_device_reset(port->port.dev); 482 } 483 uhci_reset(s); 484 return; 485 } 486 if (val & UHCI_CMD_HCRESET) { 487 uhci_reset(s); 488 return; 489 } 490 s->cmd = val; 491 break; 492 case 0x02: 493 s->status &= ~val; 494 /* XXX: the chip spec is not coherent, so we add a hidden 495 register to distinguish between IOC and SPD */ 496 if (val & UHCI_STS_USBINT) 497 s->status2 = 0; 498 uhci_update_irq(s); 499 break; 500 case 0x04: 501 s->intr = val; 502 uhci_update_irq(s); 503 break; 504 case 0x06: 505 if (s->status & UHCI_STS_HCHALTED) 506 s->frnum = val & 0x7ff; 507 break; 508 case 0x10 ... 0x1f: 509 { 510 UHCIPort *port; 511 USBDevice *dev; 512 int n; 513 514 n = (addr >> 1) & 7; 515 if (n >= NB_PORTS) 516 return; 517 port = &s->ports[n]; 518 dev = port->port.dev; 519 if (dev && dev->attached) { 520 /* port reset */ 521 if ( (val & UHCI_PORT_RESET) && 522 !(port->ctrl & UHCI_PORT_RESET) ) { 523 usb_device_reset(dev); 524 } 525 } 526 port->ctrl &= UHCI_PORT_READ_ONLY; 527 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 528 /* some bits are reset when a '1' is written to them */ 529 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 530 } 531 break; 532 } 533 } 534 535 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) 536 { 537 UHCIState *s = opaque; 538 uint32_t val; 539 540 addr &= 0x1f; 541 switch(addr) { 542 case 0x00: 543 val = s->cmd; 544 break; 545 case 0x02: 546 val = s->status; 547 break; 548 case 0x04: 549 val = s->intr; 550 break; 551 case 0x06: 552 val = s->frnum; 553 break; 554 case 0x10 ... 0x1f: 555 { 556 UHCIPort *port; 557 int n; 558 n = (addr >> 1) & 7; 559 if (n >= NB_PORTS) 560 goto read_default; 561 port = &s->ports[n]; 562 val = port->ctrl; 563 } 564 break; 565 default: 566 read_default: 567 val = 0xff7f; /* disabled port */ 568 break; 569 } 570 571 trace_usb_uhci_mmio_readw(addr, val); 572 573 return val; 574 } 575 576 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 577 { 578 UHCIState *s = opaque; 579 580 addr &= 0x1f; 581 trace_usb_uhci_mmio_writel(addr, val); 582 583 switch(addr) { 584 case 0x08: 585 s->fl_base_addr = val & ~0xfff; 586 break; 587 } 588 } 589 590 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) 591 { 592 UHCIState *s = opaque; 593 uint32_t val; 594 595 addr &= 0x1f; 596 switch(addr) { 597 case 0x08: 598 val = s->fl_base_addr; 599 break; 600 default: 601 val = 0xffffffff; 602 break; 603 } 604 trace_usb_uhci_mmio_readl(addr, val); 605 return val; 606 } 607 608 /* signal resume if controller suspended */ 609 static void uhci_resume (void *opaque) 610 { 611 UHCIState *s = (UHCIState *)opaque; 612 613 if (!s) 614 return; 615 616 if (s->cmd & UHCI_CMD_EGSM) { 617 s->cmd |= UHCI_CMD_FGR; 618 s->status |= UHCI_STS_RD; 619 uhci_update_irq(s); 620 } 621 } 622 623 static void uhci_attach(USBPort *port1) 624 { 625 UHCIState *s = port1->opaque; 626 UHCIPort *port = &s->ports[port1->index]; 627 628 /* set connect status */ 629 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 630 631 /* update speed */ 632 if (port->port.dev->speed == USB_SPEED_LOW) { 633 port->ctrl |= UHCI_PORT_LSDA; 634 } else { 635 port->ctrl &= ~UHCI_PORT_LSDA; 636 } 637 638 uhci_resume(s); 639 } 640 641 static void uhci_detach(USBPort *port1) 642 { 643 UHCIState *s = port1->opaque; 644 UHCIPort *port = &s->ports[port1->index]; 645 646 uhci_async_cancel_device(s, port1->dev); 647 648 /* set connect status */ 649 if (port->ctrl & UHCI_PORT_CCS) { 650 port->ctrl &= ~UHCI_PORT_CCS; 651 port->ctrl |= UHCI_PORT_CSC; 652 } 653 /* disable port */ 654 if (port->ctrl & UHCI_PORT_EN) { 655 port->ctrl &= ~UHCI_PORT_EN; 656 port->ctrl |= UHCI_PORT_ENC; 657 } 658 659 uhci_resume(s); 660 } 661 662 static void uhci_child_detach(USBPort *port1, USBDevice *child) 663 { 664 UHCIState *s = port1->opaque; 665 666 uhci_async_cancel_device(s, child); 667 } 668 669 static void uhci_wakeup(USBPort *port1) 670 { 671 UHCIState *s = port1->opaque; 672 UHCIPort *port = &s->ports[port1->index]; 673 674 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 675 port->ctrl |= UHCI_PORT_RD; 676 uhci_resume(s); 677 } 678 } 679 680 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 681 { 682 USBDevice *dev; 683 int i; 684 685 for (i = 0; i < NB_PORTS; i++) { 686 UHCIPort *port = &s->ports[i]; 687 if (!(port->ctrl & UHCI_PORT_EN)) { 688 continue; 689 } 690 dev = usb_find_device(&port->port, addr); 691 if (dev != NULL) { 692 return dev; 693 } 694 } 695 return NULL; 696 } 697 698 static void uhci_async_complete(USBPort *port, USBPacket *packet); 699 static void uhci_process_frame(UHCIState *s); 700 701 /* return -1 if fatal error (frame must be stopped) 702 0 if TD successful 703 1 if TD unsuccessful or inactive 704 */ 705 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 706 { 707 int len = 0, max_len, err, ret; 708 uint8_t pid; 709 710 max_len = ((td->token >> 21) + 1) & 0x7ff; 711 pid = td->token & 0xff; 712 713 ret = async->packet.result; 714 715 if (td->ctrl & TD_CTRL_IOS) 716 td->ctrl &= ~TD_CTRL_ACTIVE; 717 718 if (ret < 0) 719 goto out; 720 721 len = async->packet.result; 722 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 723 724 /* The NAK bit may have been set by a previous frame, so clear it 725 here. The docs are somewhat unclear, but win2k relies on this 726 behavior. */ 727 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 728 if (td->ctrl & TD_CTRL_IOC) 729 *int_mask |= 0x01; 730 731 if (pid == USB_TOKEN_IN) { 732 if (len > max_len) { 733 ret = USB_RET_BABBLE; 734 goto out; 735 } 736 737 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 738 *int_mask |= 0x02; 739 /* short packet: do not update QH */ 740 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 741 async->td); 742 return TD_RESULT_NEXT_QH; 743 } 744 } 745 746 /* success */ 747 trace_usb_uhci_packet_complete_success(async->queue->token, async->td); 748 return TD_RESULT_COMPLETE; 749 750 out: 751 switch(ret) { 752 case USB_RET_STALL: 753 td->ctrl |= TD_CTRL_STALL; 754 td->ctrl &= ~TD_CTRL_ACTIVE; 755 s->status |= UHCI_STS_USBERR; 756 if (td->ctrl & TD_CTRL_IOC) { 757 *int_mask |= 0x01; 758 } 759 uhci_update_irq(s); 760 trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); 761 return TD_RESULT_NEXT_QH; 762 763 case USB_RET_BABBLE: 764 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 765 td->ctrl &= ~TD_CTRL_ACTIVE; 766 s->status |= UHCI_STS_USBERR; 767 if (td->ctrl & TD_CTRL_IOC) { 768 *int_mask |= 0x01; 769 } 770 uhci_update_irq(s); 771 /* frame interrupted */ 772 trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); 773 return TD_RESULT_STOP_FRAME; 774 775 case USB_RET_NAK: 776 td->ctrl |= TD_CTRL_NAK; 777 if (pid == USB_TOKEN_SETUP) 778 break; 779 return TD_RESULT_NEXT_QH; 780 781 case USB_RET_IOERROR: 782 case USB_RET_NODEV: 783 default: 784 break; 785 } 786 787 /* Retry the TD if error count is not zero */ 788 789 td->ctrl |= TD_CTRL_TIMEOUT; 790 err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; 791 if (err != 0) { 792 err--; 793 if (err == 0) { 794 td->ctrl &= ~TD_CTRL_ACTIVE; 795 s->status |= UHCI_STS_USBERR; 796 if (td->ctrl & TD_CTRL_IOC) 797 *int_mask |= 0x01; 798 uhci_update_irq(s); 799 trace_usb_uhci_packet_complete_error(async->queue->token, 800 async->td); 801 } 802 } 803 td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | 804 (err << TD_CTRL_ERROR_SHIFT); 805 return TD_RESULT_NEXT_QH; 806 } 807 808 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, 809 uint32_t *int_mask, bool queuing) 810 { 811 UHCIAsync *async; 812 int len = 0, max_len; 813 uint8_t pid; 814 USBDevice *dev; 815 USBEndpoint *ep; 816 817 /* Is active ? */ 818 if (!(td->ctrl & TD_CTRL_ACTIVE)) 819 return TD_RESULT_NEXT_QH; 820 821 async = uhci_async_find_td(s, addr, td); 822 if (async) { 823 /* Already submitted */ 824 async->queue->valid = 32; 825 826 if (!async->done) 827 return TD_RESULT_ASYNC_CONT; 828 if (queuing) { 829 /* we are busy filling the queue, we are not prepared 830 to consume completed packages then, just leave them 831 in async state */ 832 return TD_RESULT_ASYNC_CONT; 833 } 834 835 uhci_async_unlink(async); 836 goto done; 837 } 838 839 /* Allocate new packet */ 840 async = uhci_async_alloc(uhci_queue_get(s, td), addr); 841 842 /* valid needs to be large enough to handle 10 frame delay 843 * for initial isochronous requests 844 */ 845 async->queue->valid = 32; 846 async->isoc = td->ctrl & TD_CTRL_IOS; 847 848 max_len = ((td->token >> 21) + 1) & 0x7ff; 849 pid = td->token & 0xff; 850 851 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 852 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 853 usb_packet_setup(&async->packet, pid, ep); 854 qemu_sglist_add(&async->sgl, td->buffer, max_len); 855 usb_packet_map(&async->packet, &async->sgl); 856 857 switch(pid) { 858 case USB_TOKEN_OUT: 859 case USB_TOKEN_SETUP: 860 len = usb_handle_packet(dev, &async->packet); 861 if (len >= 0) 862 len = max_len; 863 break; 864 865 case USB_TOKEN_IN: 866 len = usb_handle_packet(dev, &async->packet); 867 break; 868 869 default: 870 /* invalid pid : frame interrupted */ 871 uhci_async_free(async); 872 s->status |= UHCI_STS_HCPERR; 873 uhci_update_irq(s); 874 return TD_RESULT_STOP_FRAME; 875 } 876 877 if (len == USB_RET_ASYNC) { 878 uhci_async_link(async); 879 return TD_RESULT_ASYNC_START; 880 } 881 882 async->packet.result = len; 883 884 done: 885 len = uhci_complete_td(s, td, async, int_mask); 886 usb_packet_unmap(&async->packet, &async->sgl); 887 uhci_async_free(async); 888 return len; 889 } 890 891 static void uhci_async_complete(USBPort *port, USBPacket *packet) 892 { 893 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 894 UHCIState *s = async->queue->uhci; 895 896 if (async->isoc) { 897 UHCI_TD td; 898 uint32_t link = async->td; 899 uint32_t int_mask = 0, val; 900 901 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 902 le32_to_cpus(&td.link); 903 le32_to_cpus(&td.ctrl); 904 le32_to_cpus(&td.token); 905 le32_to_cpus(&td.buffer); 906 907 uhci_async_unlink(async); 908 uhci_complete_td(s, &td, async, &int_mask); 909 s->pending_int_mask |= int_mask; 910 911 /* update the status bits of the TD */ 912 val = cpu_to_le32(td.ctrl); 913 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 914 uhci_async_free(async); 915 } else { 916 async->done = 1; 917 if (s->frame_bytes < s->frame_bandwidth) { 918 qemu_bh_schedule(s->bh); 919 } 920 } 921 } 922 923 static int is_valid(uint32_t link) 924 { 925 return (link & 1) == 0; 926 } 927 928 static int is_qh(uint32_t link) 929 { 930 return (link & 2) != 0; 931 } 932 933 static int depth_first(uint32_t link) 934 { 935 return (link & 4) != 0; 936 } 937 938 /* QH DB used for detecting QH loops */ 939 #define UHCI_MAX_QUEUES 128 940 typedef struct { 941 uint32_t addr[UHCI_MAX_QUEUES]; 942 int count; 943 } QhDb; 944 945 static void qhdb_reset(QhDb *db) 946 { 947 db->count = 0; 948 } 949 950 /* Add QH to DB. Returns 1 if already present or DB is full. */ 951 static int qhdb_insert(QhDb *db, uint32_t addr) 952 { 953 int i; 954 for (i = 0; i < db->count; i++) 955 if (db->addr[i] == addr) 956 return 1; 957 958 if (db->count >= UHCI_MAX_QUEUES) 959 return 1; 960 961 db->addr[db->count++] = addr; 962 return 0; 963 } 964 965 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) 966 { 967 uint32_t int_mask = 0; 968 uint32_t plink = td->link; 969 uint32_t token = uhci_queue_token(td); 970 UHCI_TD ptd; 971 int ret; 972 973 while (is_valid(plink)) { 974 pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); 975 le32_to_cpus(&ptd.link); 976 le32_to_cpus(&ptd.ctrl); 977 le32_to_cpus(&ptd.token); 978 le32_to_cpus(&ptd.buffer); 979 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 980 break; 981 } 982 if (uhci_queue_token(&ptd) != token) { 983 break; 984 } 985 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 986 ret = uhci_handle_td(s, plink, &ptd, &int_mask, true); 987 if (ret == TD_RESULT_ASYNC_CONT) { 988 break; 989 } 990 assert(ret == TD_RESULT_ASYNC_START); 991 assert(int_mask == 0); 992 plink = ptd.link; 993 } 994 } 995 996 static void uhci_process_frame(UHCIState *s) 997 { 998 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 999 uint32_t curr_qh, td_count = 0; 1000 int cnt, ret; 1001 UHCI_TD td; 1002 UHCI_QH qh; 1003 QhDb qhdb; 1004 1005 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1006 1007 pci_dma_read(&s->dev, frame_addr, &link, 4); 1008 le32_to_cpus(&link); 1009 1010 int_mask = 0; 1011 curr_qh = 0; 1012 1013 qhdb_reset(&qhdb); 1014 1015 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1016 if (s->frame_bytes >= s->frame_bandwidth) { 1017 /* We've reached the usb 1.1 bandwidth, which is 1018 1280 bytes/frame, stop processing */ 1019 trace_usb_uhci_frame_stop_bandwidth(); 1020 break; 1021 } 1022 if (is_qh(link)) { 1023 /* QH */ 1024 trace_usb_uhci_qh_load(link & ~0xf); 1025 1026 if (qhdb_insert(&qhdb, link)) { 1027 /* 1028 * We're going in circles. Which is not a bug because 1029 * HCD is allowed to do that as part of the BW management. 1030 * 1031 * Stop processing here if no transaction has been done 1032 * since we've been here last time. 1033 */ 1034 if (td_count == 0) { 1035 trace_usb_uhci_frame_loop_stop_idle(); 1036 break; 1037 } else { 1038 trace_usb_uhci_frame_loop_continue(); 1039 td_count = 0; 1040 qhdb_reset(&qhdb); 1041 qhdb_insert(&qhdb, link); 1042 } 1043 } 1044 1045 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1046 le32_to_cpus(&qh.link); 1047 le32_to_cpus(&qh.el_link); 1048 1049 if (!is_valid(qh.el_link)) { 1050 /* QH w/o elements */ 1051 curr_qh = 0; 1052 link = qh.link; 1053 } else { 1054 /* QH with elements */ 1055 curr_qh = link; 1056 link = qh.el_link; 1057 } 1058 continue; 1059 } 1060 1061 /* TD */ 1062 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 1063 le32_to_cpus(&td.link); 1064 le32_to_cpus(&td.ctrl); 1065 le32_to_cpus(&td.token); 1066 le32_to_cpus(&td.buffer); 1067 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1068 1069 old_td_ctrl = td.ctrl; 1070 ret = uhci_handle_td(s, link, &td, &int_mask, false); 1071 if (old_td_ctrl != td.ctrl) { 1072 /* update the status bits of the TD */ 1073 val = cpu_to_le32(td.ctrl); 1074 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1075 } 1076 1077 switch (ret) { 1078 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1079 goto out; 1080 1081 case TD_RESULT_NEXT_QH: 1082 case TD_RESULT_ASYNC_CONT: 1083 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1084 link = curr_qh ? qh.link : td.link; 1085 continue; 1086 1087 case TD_RESULT_ASYNC_START: 1088 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1089 if (is_valid(td.link)) { 1090 uhci_fill_queue(s, &td); 1091 } 1092 link = curr_qh ? qh.link : td.link; 1093 continue; 1094 1095 case TD_RESULT_COMPLETE: 1096 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1097 link = td.link; 1098 td_count++; 1099 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1100 1101 if (curr_qh) { 1102 /* update QH element link */ 1103 qh.el_link = link; 1104 val = cpu_to_le32(qh.el_link); 1105 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1106 1107 if (!depth_first(link)) { 1108 /* done with this QH */ 1109 curr_qh = 0; 1110 link = qh.link; 1111 } 1112 } 1113 break; 1114 1115 default: 1116 assert(!"unknown return code"); 1117 } 1118 1119 /* go to the next entry */ 1120 } 1121 1122 out: 1123 s->pending_int_mask |= int_mask; 1124 } 1125 1126 static void uhci_bh(void *opaque) 1127 { 1128 UHCIState *s = opaque; 1129 uhci_process_frame(s); 1130 } 1131 1132 static void uhci_frame_timer(void *opaque) 1133 { 1134 UHCIState *s = opaque; 1135 1136 /* prepare the timer for the next frame */ 1137 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); 1138 s->frame_bytes = 0; 1139 qemu_bh_cancel(s->bh); 1140 1141 if (!(s->cmd & UHCI_CMD_RS)) { 1142 /* Full stop */ 1143 trace_usb_uhci_schedule_stop(); 1144 qemu_del_timer(s->frame_timer); 1145 uhci_async_cancel_all(s); 1146 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1147 s->status |= UHCI_STS_HCHALTED; 1148 return; 1149 } 1150 1151 /* Complete the previous frame */ 1152 if (s->pending_int_mask) { 1153 s->status2 |= s->pending_int_mask; 1154 s->status |= UHCI_STS_USBINT; 1155 uhci_update_irq(s); 1156 } 1157 s->pending_int_mask = 0; 1158 1159 /* Start new frame */ 1160 s->frnum = (s->frnum + 1) & 0x7ff; 1161 1162 trace_usb_uhci_frame_start(s->frnum); 1163 1164 uhci_async_validate_begin(s); 1165 1166 uhci_process_frame(s); 1167 1168 uhci_async_validate_end(s); 1169 1170 qemu_mod_timer(s->frame_timer, s->expire_time); 1171 } 1172 1173 static const MemoryRegionPortio uhci_portio[] = { 1174 { 0, 32, 2, .write = uhci_ioport_writew, }, 1175 { 0, 32, 2, .read = uhci_ioport_readw, }, 1176 { 0, 32, 4, .write = uhci_ioport_writel, }, 1177 { 0, 32, 4, .read = uhci_ioport_readl, }, 1178 { 0, 32, 1, .write = uhci_ioport_writeb, }, 1179 { 0, 32, 1, .read = uhci_ioport_readb, }, 1180 PORTIO_END_OF_LIST() 1181 }; 1182 1183 static const MemoryRegionOps uhci_ioport_ops = { 1184 .old_portio = uhci_portio, 1185 }; 1186 1187 static USBPortOps uhci_port_ops = { 1188 .attach = uhci_attach, 1189 .detach = uhci_detach, 1190 .child_detach = uhci_child_detach, 1191 .wakeup = uhci_wakeup, 1192 .complete = uhci_async_complete, 1193 }; 1194 1195 static USBBusOps uhci_bus_ops = { 1196 }; 1197 1198 static int usb_uhci_common_initfn(PCIDevice *dev) 1199 { 1200 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1201 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1202 uint8_t *pci_conf = s->dev.config; 1203 int i; 1204 1205 pci_conf[PCI_CLASS_PROG] = 0x00; 1206 /* TODO: reset value should be 0. */ 1207 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1208 1209 switch (pc->device_id) { 1210 case PCI_DEVICE_ID_INTEL_82801I_UHCI1: 1211 s->irq_pin = 0; /* A */ 1212 break; 1213 case PCI_DEVICE_ID_INTEL_82801I_UHCI2: 1214 s->irq_pin = 1; /* B */ 1215 break; 1216 case PCI_DEVICE_ID_INTEL_82801I_UHCI3: 1217 s->irq_pin = 2; /* C */ 1218 break; 1219 default: 1220 s->irq_pin = 3; /* D */ 1221 break; 1222 } 1223 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); 1224 1225 if (s->masterbus) { 1226 USBPort *ports[NB_PORTS]; 1227 for(i = 0; i < NB_PORTS; i++) { 1228 ports[i] = &s->ports[i].port; 1229 } 1230 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1231 s->firstport, s, &uhci_port_ops, 1232 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1233 return -1; 1234 } 1235 } else { 1236 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1237 for (i = 0; i < NB_PORTS; i++) { 1238 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1239 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1240 } 1241 } 1242 s->bh = qemu_bh_new(uhci_bh, s); 1243 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1244 s->num_ports_vmstate = NB_PORTS; 1245 QTAILQ_INIT(&s->queues); 1246 1247 qemu_register_reset(uhci_reset, s); 1248 1249 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1250 /* Use region 4 for consistency with real hardware. BSD guests seem 1251 to rely on this. */ 1252 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1253 1254 return 0; 1255 } 1256 1257 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1258 { 1259 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1260 uint8_t *pci_conf = s->dev.config; 1261 1262 /* USB misc control 1/2 */ 1263 pci_set_long(pci_conf + 0x40,0x00001000); 1264 /* PM capability */ 1265 pci_set_long(pci_conf + 0x80,0x00020001); 1266 /* USB legacy support */ 1267 pci_set_long(pci_conf + 0xc0,0x00002000); 1268 1269 return usb_uhci_common_initfn(dev); 1270 } 1271 1272 static void usb_uhci_exit(PCIDevice *dev) 1273 { 1274 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1275 1276 memory_region_destroy(&s->io_bar); 1277 } 1278 1279 static Property uhci_properties[] = { 1280 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1281 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1282 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1283 DEFINE_PROP_END_OF_LIST(), 1284 }; 1285 1286 static void piix3_uhci_class_init(ObjectClass *klass, void *data) 1287 { 1288 DeviceClass *dc = DEVICE_CLASS(klass); 1289 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1290 1291 k->init = usb_uhci_common_initfn; 1292 k->exit = usb_uhci_exit; 1293 k->vendor_id = PCI_VENDOR_ID_INTEL; 1294 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; 1295 k->revision = 0x01; 1296 k->class_id = PCI_CLASS_SERIAL_USB; 1297 dc->vmsd = &vmstate_uhci; 1298 dc->props = uhci_properties; 1299 } 1300 1301 static TypeInfo piix3_uhci_info = { 1302 .name = "piix3-usb-uhci", 1303 .parent = TYPE_PCI_DEVICE, 1304 .instance_size = sizeof(UHCIState), 1305 .class_init = piix3_uhci_class_init, 1306 }; 1307 1308 static void piix4_uhci_class_init(ObjectClass *klass, void *data) 1309 { 1310 DeviceClass *dc = DEVICE_CLASS(klass); 1311 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1312 1313 k->init = usb_uhci_common_initfn; 1314 k->exit = usb_uhci_exit; 1315 k->vendor_id = PCI_VENDOR_ID_INTEL; 1316 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; 1317 k->revision = 0x01; 1318 k->class_id = PCI_CLASS_SERIAL_USB; 1319 dc->vmsd = &vmstate_uhci; 1320 dc->props = uhci_properties; 1321 } 1322 1323 static TypeInfo piix4_uhci_info = { 1324 .name = "piix4-usb-uhci", 1325 .parent = TYPE_PCI_DEVICE, 1326 .instance_size = sizeof(UHCIState), 1327 .class_init = piix4_uhci_class_init, 1328 }; 1329 1330 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) 1331 { 1332 DeviceClass *dc = DEVICE_CLASS(klass); 1333 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1334 1335 k->init = usb_uhci_vt82c686b_initfn; 1336 k->exit = usb_uhci_exit; 1337 k->vendor_id = PCI_VENDOR_ID_VIA; 1338 k->device_id = PCI_DEVICE_ID_VIA_UHCI; 1339 k->revision = 0x01; 1340 k->class_id = PCI_CLASS_SERIAL_USB; 1341 dc->vmsd = &vmstate_uhci; 1342 dc->props = uhci_properties; 1343 } 1344 1345 static TypeInfo vt82c686b_uhci_info = { 1346 .name = "vt82c686b-usb-uhci", 1347 .parent = TYPE_PCI_DEVICE, 1348 .instance_size = sizeof(UHCIState), 1349 .class_init = vt82c686b_uhci_class_init, 1350 }; 1351 1352 static void ich9_uhci1_class_init(ObjectClass *klass, void *data) 1353 { 1354 DeviceClass *dc = DEVICE_CLASS(klass); 1355 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1356 1357 k->init = usb_uhci_common_initfn; 1358 k->vendor_id = PCI_VENDOR_ID_INTEL; 1359 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; 1360 k->revision = 0x03; 1361 k->class_id = PCI_CLASS_SERIAL_USB; 1362 dc->vmsd = &vmstate_uhci; 1363 dc->props = uhci_properties; 1364 } 1365 1366 static TypeInfo ich9_uhci1_info = { 1367 .name = "ich9-usb-uhci1", 1368 .parent = TYPE_PCI_DEVICE, 1369 .instance_size = sizeof(UHCIState), 1370 .class_init = ich9_uhci1_class_init, 1371 }; 1372 1373 static void ich9_uhci2_class_init(ObjectClass *klass, void *data) 1374 { 1375 DeviceClass *dc = DEVICE_CLASS(klass); 1376 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1377 1378 k->init = usb_uhci_common_initfn; 1379 k->vendor_id = PCI_VENDOR_ID_INTEL; 1380 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; 1381 k->revision = 0x03; 1382 k->class_id = PCI_CLASS_SERIAL_USB; 1383 dc->vmsd = &vmstate_uhci; 1384 dc->props = uhci_properties; 1385 } 1386 1387 static TypeInfo ich9_uhci2_info = { 1388 .name = "ich9-usb-uhci2", 1389 .parent = TYPE_PCI_DEVICE, 1390 .instance_size = sizeof(UHCIState), 1391 .class_init = ich9_uhci2_class_init, 1392 }; 1393 1394 static void ich9_uhci3_class_init(ObjectClass *klass, void *data) 1395 { 1396 DeviceClass *dc = DEVICE_CLASS(klass); 1397 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1398 1399 k->init = usb_uhci_common_initfn; 1400 k->vendor_id = PCI_VENDOR_ID_INTEL; 1401 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; 1402 k->revision = 0x03; 1403 k->class_id = PCI_CLASS_SERIAL_USB; 1404 dc->vmsd = &vmstate_uhci; 1405 dc->props = uhci_properties; 1406 } 1407 1408 static TypeInfo ich9_uhci3_info = { 1409 .name = "ich9-usb-uhci3", 1410 .parent = TYPE_PCI_DEVICE, 1411 .instance_size = sizeof(UHCIState), 1412 .class_init = ich9_uhci3_class_init, 1413 }; 1414 1415 static void uhci_register_types(void) 1416 { 1417 type_register_static(&piix3_uhci_info); 1418 type_register_static(&piix4_uhci_info); 1419 type_register_static(&vt82c686b_uhci_info); 1420 type_register_static(&ich9_uhci1_info); 1421 type_register_static(&ich9_uhci2_info); 1422 type_register_static(&ich9_uhci3_info); 1423 } 1424 1425 type_init(uhci_register_types) 1426