1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/usb/uhci-regs.h" 31 #include "hw/pci/pci.h" 32 #include "qemu/timer.h" 33 #include "qemu/iov.h" 34 #include "sysemu/dma.h" 35 #include "trace.h" 36 #include "qemu/main-loop.h" 37 38 #define FRAME_TIMER_FREQ 1000 39 40 #define FRAME_MAX_LOOPS 256 41 42 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 43 #define QH_VALID 32 44 45 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 46 47 #define NB_PORTS 2 48 49 enum { 50 TD_RESULT_STOP_FRAME = 10, 51 TD_RESULT_COMPLETE, 52 TD_RESULT_NEXT_QH, 53 TD_RESULT_ASYNC_START, 54 TD_RESULT_ASYNC_CONT, 55 }; 56 57 typedef struct UHCIState UHCIState; 58 typedef struct UHCIAsync UHCIAsync; 59 typedef struct UHCIQueue UHCIQueue; 60 typedef struct UHCIInfo UHCIInfo; 61 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 62 63 struct UHCIInfo { 64 const char *name; 65 uint16_t vendor_id; 66 uint16_t device_id; 67 uint8_t revision; 68 uint8_t irq_pin; 69 int (*initfn)(PCIDevice *dev); 70 bool unplug; 71 }; 72 73 struct UHCIPCIDeviceClass { 74 PCIDeviceClass parent_class; 75 UHCIInfo info; 76 }; 77 78 /* 79 * Pending async transaction. 80 * 'packet' must be the first field because completion 81 * handler does "(UHCIAsync *) pkt" cast. 82 */ 83 84 struct UHCIAsync { 85 USBPacket packet; 86 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 87 uint8_t *buf; 88 UHCIQueue *queue; 89 QTAILQ_ENTRY(UHCIAsync) next; 90 uint32_t td_addr; 91 uint8_t done; 92 }; 93 94 struct UHCIQueue { 95 uint32_t qh_addr; 96 uint32_t token; 97 UHCIState *uhci; 98 USBEndpoint *ep; 99 QTAILQ_ENTRY(UHCIQueue) next; 100 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 101 int8_t valid; 102 }; 103 104 typedef struct UHCIPort { 105 USBPort port; 106 uint16_t ctrl; 107 } UHCIPort; 108 109 struct UHCIState { 110 PCIDevice dev; 111 MemoryRegion io_bar; 112 USBBus bus; /* Note unused when we're a companion controller */ 113 uint16_t cmd; /* cmd register */ 114 uint16_t status; 115 uint16_t intr; /* interrupt enable register */ 116 uint16_t frnum; /* frame number */ 117 uint32_t fl_base_addr; /* frame list base address */ 118 uint8_t sof_timing; 119 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 120 int64_t expire_time; 121 QEMUTimer *frame_timer; 122 QEMUBH *bh; 123 uint32_t frame_bytes; 124 uint32_t frame_bandwidth; 125 bool completions_only; 126 UHCIPort ports[NB_PORTS]; 127 128 /* Interrupts that should be raised at the end of the current frame. */ 129 uint32_t pending_int_mask; 130 131 /* Active packets */ 132 QTAILQ_HEAD(, UHCIQueue) queues; 133 uint8_t num_ports_vmstate; 134 135 /* Properties */ 136 char *masterbus; 137 uint32_t firstport; 138 uint32_t maxframes; 139 }; 140 141 typedef struct UHCI_TD { 142 uint32_t link; 143 uint32_t ctrl; /* see TD_CTRL_xxx */ 144 uint32_t token; 145 uint32_t buffer; 146 } UHCI_TD; 147 148 typedef struct UHCI_QH { 149 uint32_t link; 150 uint32_t el_link; 151 } UHCI_QH; 152 153 static void uhci_async_cancel(UHCIAsync *async); 154 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 155 static void uhci_resume(void *opaque); 156 157 static inline int32_t uhci_queue_token(UHCI_TD *td) 158 { 159 if ((td->token & (0xf << 15)) == 0) { 160 /* ctrl ep, cover ep and dev, not pid! */ 161 return td->token & 0x7ff00; 162 } else { 163 /* covers ep, dev, pid -> identifies the endpoint */ 164 return td->token & 0x7ffff; 165 } 166 } 167 168 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 169 USBEndpoint *ep) 170 { 171 UHCIQueue *queue; 172 173 queue = g_new0(UHCIQueue, 1); 174 queue->uhci = s; 175 queue->qh_addr = qh_addr; 176 queue->token = uhci_queue_token(td); 177 queue->ep = ep; 178 QTAILQ_INIT(&queue->asyncs); 179 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 180 queue->valid = QH_VALID; 181 trace_usb_uhci_queue_add(queue->token); 182 return queue; 183 } 184 185 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 186 { 187 UHCIState *s = queue->uhci; 188 UHCIAsync *async; 189 190 while (!QTAILQ_EMPTY(&queue->asyncs)) { 191 async = QTAILQ_FIRST(&queue->asyncs); 192 uhci_async_cancel(async); 193 } 194 usb_device_ep_stopped(queue->ep->dev, queue->ep); 195 196 trace_usb_uhci_queue_del(queue->token, reason); 197 QTAILQ_REMOVE(&s->queues, queue, next); 198 g_free(queue); 199 } 200 201 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 202 { 203 uint32_t token = uhci_queue_token(td); 204 UHCIQueue *queue; 205 206 QTAILQ_FOREACH(queue, &s->queues, next) { 207 if (queue->token == token) { 208 return queue; 209 } 210 } 211 return NULL; 212 } 213 214 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 215 uint32_t td_addr, bool queuing) 216 { 217 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 218 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 219 220 return queue->qh_addr == qh_addr && 221 queue->token == uhci_queue_token(td) && 222 queue_token_addr == queue->ep->dev->addr && 223 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 224 first->td_addr == td_addr); 225 } 226 227 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 228 { 229 UHCIAsync *async = g_new0(UHCIAsync, 1); 230 231 async->queue = queue; 232 async->td_addr = td_addr; 233 usb_packet_init(&async->packet); 234 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 235 236 return async; 237 } 238 239 static void uhci_async_free(UHCIAsync *async) 240 { 241 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 242 usb_packet_cleanup(&async->packet); 243 if (async->buf != async->static_buf) { 244 g_free(async->buf); 245 } 246 g_free(async); 247 } 248 249 static void uhci_async_link(UHCIAsync *async) 250 { 251 UHCIQueue *queue = async->queue; 252 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 253 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 254 } 255 256 static void uhci_async_unlink(UHCIAsync *async) 257 { 258 UHCIQueue *queue = async->queue; 259 QTAILQ_REMOVE(&queue->asyncs, async, next); 260 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 261 } 262 263 static void uhci_async_cancel(UHCIAsync *async) 264 { 265 uhci_async_unlink(async); 266 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 267 async->done); 268 if (!async->done) 269 usb_cancel_packet(&async->packet); 270 uhci_async_free(async); 271 } 272 273 /* 274 * Mark all outstanding async packets as invalid. 275 * This is used for canceling them when TDs are removed by the HCD. 276 */ 277 static void uhci_async_validate_begin(UHCIState *s) 278 { 279 UHCIQueue *queue; 280 281 QTAILQ_FOREACH(queue, &s->queues, next) { 282 queue->valid--; 283 } 284 } 285 286 /* 287 * Cancel async packets that are no longer valid 288 */ 289 static void uhci_async_validate_end(UHCIState *s) 290 { 291 UHCIQueue *queue, *n; 292 293 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 294 if (!queue->valid) { 295 uhci_queue_free(queue, "validate-end"); 296 } 297 } 298 } 299 300 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 301 { 302 UHCIQueue *queue, *n; 303 304 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 305 if (queue->ep->dev == dev) { 306 uhci_queue_free(queue, "cancel-device"); 307 } 308 } 309 } 310 311 static void uhci_async_cancel_all(UHCIState *s) 312 { 313 UHCIQueue *queue, *nq; 314 315 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 316 uhci_queue_free(queue, "cancel-all"); 317 } 318 } 319 320 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 321 { 322 UHCIQueue *queue; 323 UHCIAsync *async; 324 325 QTAILQ_FOREACH(queue, &s->queues, next) { 326 QTAILQ_FOREACH(async, &queue->asyncs, next) { 327 if (async->td_addr == td_addr) { 328 return async; 329 } 330 } 331 } 332 return NULL; 333 } 334 335 static void uhci_update_irq(UHCIState *s) 336 { 337 int level; 338 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 339 ((s->status2 & 2) && (s->intr & (1 << 3))) || 340 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 341 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 342 (s->status & UHCI_STS_HSERR) || 343 (s->status & UHCI_STS_HCPERR)) { 344 level = 1; 345 } else { 346 level = 0; 347 } 348 pci_set_irq(&s->dev, level); 349 } 350 351 static void uhci_reset(void *opaque) 352 { 353 UHCIState *s = opaque; 354 uint8_t *pci_conf; 355 int i; 356 UHCIPort *port; 357 358 trace_usb_uhci_reset(); 359 360 pci_conf = s->dev.config; 361 362 pci_conf[0x6a] = 0x01; /* usb clock */ 363 pci_conf[0x6b] = 0x00; 364 s->cmd = 0; 365 s->status = 0; 366 s->status2 = 0; 367 s->intr = 0; 368 s->fl_base_addr = 0; 369 s->sof_timing = 64; 370 371 for(i = 0; i < NB_PORTS; i++) { 372 port = &s->ports[i]; 373 port->ctrl = 0x0080; 374 if (port->port.dev && port->port.dev->attached) { 375 usb_port_reset(&port->port); 376 } 377 } 378 379 uhci_async_cancel_all(s); 380 qemu_bh_cancel(s->bh); 381 uhci_update_irq(s); 382 } 383 384 static const VMStateDescription vmstate_uhci_port = { 385 .name = "uhci port", 386 .version_id = 1, 387 .minimum_version_id = 1, 388 .fields = (VMStateField[]) { 389 VMSTATE_UINT16(ctrl, UHCIPort), 390 VMSTATE_END_OF_LIST() 391 } 392 }; 393 394 static int uhci_post_load(void *opaque, int version_id) 395 { 396 UHCIState *s = opaque; 397 398 if (version_id < 2) { 399 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 400 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 401 } 402 return 0; 403 } 404 405 static const VMStateDescription vmstate_uhci = { 406 .name = "uhci", 407 .version_id = 3, 408 .minimum_version_id = 1, 409 .post_load = uhci_post_load, 410 .fields = (VMStateField[]) { 411 VMSTATE_PCI_DEVICE(dev, UHCIState), 412 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 413 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 414 vmstate_uhci_port, UHCIPort), 415 VMSTATE_UINT16(cmd, UHCIState), 416 VMSTATE_UINT16(status, UHCIState), 417 VMSTATE_UINT16(intr, UHCIState), 418 VMSTATE_UINT16(frnum, UHCIState), 419 VMSTATE_UINT32(fl_base_addr, UHCIState), 420 VMSTATE_UINT8(sof_timing, UHCIState), 421 VMSTATE_UINT8(status2, UHCIState), 422 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 423 VMSTATE_INT64_V(expire_time, UHCIState, 2), 424 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 425 VMSTATE_END_OF_LIST() 426 } 427 }; 428 429 static void uhci_port_write(void *opaque, hwaddr addr, 430 uint64_t val, unsigned size) 431 { 432 UHCIState *s = opaque; 433 434 trace_usb_uhci_mmio_writew(addr, val); 435 436 switch(addr) { 437 case 0x00: 438 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 439 /* start frame processing */ 440 trace_usb_uhci_schedule_start(); 441 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 442 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 443 timer_mod(s->frame_timer, s->expire_time); 444 s->status &= ~UHCI_STS_HCHALTED; 445 } else if (!(val & UHCI_CMD_RS)) { 446 s->status |= UHCI_STS_HCHALTED; 447 } 448 if (val & UHCI_CMD_GRESET) { 449 UHCIPort *port; 450 int i; 451 452 /* send reset on the USB bus */ 453 for(i = 0; i < NB_PORTS; i++) { 454 port = &s->ports[i]; 455 usb_device_reset(port->port.dev); 456 } 457 uhci_reset(s); 458 return; 459 } 460 if (val & UHCI_CMD_HCRESET) { 461 uhci_reset(s); 462 return; 463 } 464 s->cmd = val; 465 if (val & UHCI_CMD_EGSM) { 466 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 467 (s->ports[1].ctrl & UHCI_PORT_RD)) { 468 uhci_resume(s); 469 } 470 } 471 break; 472 case 0x02: 473 s->status &= ~val; 474 /* XXX: the chip spec is not coherent, so we add a hidden 475 register to distinguish between IOC and SPD */ 476 if (val & UHCI_STS_USBINT) 477 s->status2 = 0; 478 uhci_update_irq(s); 479 break; 480 case 0x04: 481 s->intr = val; 482 uhci_update_irq(s); 483 break; 484 case 0x06: 485 if (s->status & UHCI_STS_HCHALTED) 486 s->frnum = val & 0x7ff; 487 break; 488 case 0x08: 489 s->fl_base_addr &= 0xffff0000; 490 s->fl_base_addr |= val & ~0xfff; 491 break; 492 case 0x0a: 493 s->fl_base_addr &= 0x0000ffff; 494 s->fl_base_addr |= (val << 16); 495 break; 496 case 0x0c: 497 s->sof_timing = val & 0xff; 498 break; 499 case 0x10 ... 0x1f: 500 { 501 UHCIPort *port; 502 USBDevice *dev; 503 int n; 504 505 n = (addr >> 1) & 7; 506 if (n >= NB_PORTS) 507 return; 508 port = &s->ports[n]; 509 dev = port->port.dev; 510 if (dev && dev->attached) { 511 /* port reset */ 512 if ( (val & UHCI_PORT_RESET) && 513 !(port->ctrl & UHCI_PORT_RESET) ) { 514 usb_device_reset(dev); 515 } 516 } 517 port->ctrl &= UHCI_PORT_READ_ONLY; 518 /* enabled may only be set if a device is connected */ 519 if (!(port->ctrl & UHCI_PORT_CCS)) { 520 val &= ~UHCI_PORT_EN; 521 } 522 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 523 /* some bits are reset when a '1' is written to them */ 524 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 525 } 526 break; 527 } 528 } 529 530 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 531 { 532 UHCIState *s = opaque; 533 uint32_t val; 534 535 switch(addr) { 536 case 0x00: 537 val = s->cmd; 538 break; 539 case 0x02: 540 val = s->status; 541 break; 542 case 0x04: 543 val = s->intr; 544 break; 545 case 0x06: 546 val = s->frnum; 547 break; 548 case 0x08: 549 val = s->fl_base_addr & 0xffff; 550 break; 551 case 0x0a: 552 val = (s->fl_base_addr >> 16) & 0xffff; 553 break; 554 case 0x0c: 555 val = s->sof_timing; 556 break; 557 case 0x10 ... 0x1f: 558 { 559 UHCIPort *port; 560 int n; 561 n = (addr >> 1) & 7; 562 if (n >= NB_PORTS) 563 goto read_default; 564 port = &s->ports[n]; 565 val = port->ctrl; 566 } 567 break; 568 default: 569 read_default: 570 val = 0xff7f; /* disabled port */ 571 break; 572 } 573 574 trace_usb_uhci_mmio_readw(addr, val); 575 576 return val; 577 } 578 579 /* signal resume if controller suspended */ 580 static void uhci_resume (void *opaque) 581 { 582 UHCIState *s = (UHCIState *)opaque; 583 584 if (!s) 585 return; 586 587 if (s->cmd & UHCI_CMD_EGSM) { 588 s->cmd |= UHCI_CMD_FGR; 589 s->status |= UHCI_STS_RD; 590 uhci_update_irq(s); 591 } 592 } 593 594 static void uhci_attach(USBPort *port1) 595 { 596 UHCIState *s = port1->opaque; 597 UHCIPort *port = &s->ports[port1->index]; 598 599 /* set connect status */ 600 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 601 602 /* update speed */ 603 if (port->port.dev->speed == USB_SPEED_LOW) { 604 port->ctrl |= UHCI_PORT_LSDA; 605 } else { 606 port->ctrl &= ~UHCI_PORT_LSDA; 607 } 608 609 uhci_resume(s); 610 } 611 612 static void uhci_detach(USBPort *port1) 613 { 614 UHCIState *s = port1->opaque; 615 UHCIPort *port = &s->ports[port1->index]; 616 617 uhci_async_cancel_device(s, port1->dev); 618 619 /* set connect status */ 620 if (port->ctrl & UHCI_PORT_CCS) { 621 port->ctrl &= ~UHCI_PORT_CCS; 622 port->ctrl |= UHCI_PORT_CSC; 623 } 624 /* disable port */ 625 if (port->ctrl & UHCI_PORT_EN) { 626 port->ctrl &= ~UHCI_PORT_EN; 627 port->ctrl |= UHCI_PORT_ENC; 628 } 629 630 uhci_resume(s); 631 } 632 633 static void uhci_child_detach(USBPort *port1, USBDevice *child) 634 { 635 UHCIState *s = port1->opaque; 636 637 uhci_async_cancel_device(s, child); 638 } 639 640 static void uhci_wakeup(USBPort *port1) 641 { 642 UHCIState *s = port1->opaque; 643 UHCIPort *port = &s->ports[port1->index]; 644 645 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 646 port->ctrl |= UHCI_PORT_RD; 647 uhci_resume(s); 648 } 649 } 650 651 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 652 { 653 USBDevice *dev; 654 int i; 655 656 for (i = 0; i < NB_PORTS; i++) { 657 UHCIPort *port = &s->ports[i]; 658 if (!(port->ctrl & UHCI_PORT_EN)) { 659 continue; 660 } 661 dev = usb_find_device(&port->port, addr); 662 if (dev != NULL) { 663 return dev; 664 } 665 } 666 return NULL; 667 } 668 669 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 670 { 671 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 672 le32_to_cpus(&td->link); 673 le32_to_cpus(&td->ctrl); 674 le32_to_cpus(&td->token); 675 le32_to_cpus(&td->buffer); 676 } 677 678 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 679 int status, uint32_t *int_mask) 680 { 681 uint32_t queue_token = uhci_queue_token(td); 682 int ret; 683 684 switch (status) { 685 case USB_RET_NAK: 686 td->ctrl |= TD_CTRL_NAK; 687 return TD_RESULT_NEXT_QH; 688 689 case USB_RET_STALL: 690 td->ctrl |= TD_CTRL_STALL; 691 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 692 ret = TD_RESULT_NEXT_QH; 693 break; 694 695 case USB_RET_BABBLE: 696 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 697 /* frame interrupted */ 698 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 699 ret = TD_RESULT_STOP_FRAME; 700 break; 701 702 case USB_RET_IOERROR: 703 case USB_RET_NODEV: 704 default: 705 td->ctrl |= TD_CTRL_TIMEOUT; 706 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 707 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 708 ret = TD_RESULT_NEXT_QH; 709 break; 710 } 711 712 td->ctrl &= ~TD_CTRL_ACTIVE; 713 s->status |= UHCI_STS_USBERR; 714 if (td->ctrl & TD_CTRL_IOC) { 715 *int_mask |= 0x01; 716 } 717 uhci_update_irq(s); 718 return ret; 719 } 720 721 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 722 { 723 int len = 0, max_len; 724 uint8_t pid; 725 726 max_len = ((td->token >> 21) + 1) & 0x7ff; 727 pid = td->token & 0xff; 728 729 if (td->ctrl & TD_CTRL_IOS) 730 td->ctrl &= ~TD_CTRL_ACTIVE; 731 732 if (async->packet.status != USB_RET_SUCCESS) { 733 return uhci_handle_td_error(s, td, async->td_addr, 734 async->packet.status, int_mask); 735 } 736 737 len = async->packet.actual_length; 738 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 739 740 /* The NAK bit may have been set by a previous frame, so clear it 741 here. The docs are somewhat unclear, but win2k relies on this 742 behavior. */ 743 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 744 if (td->ctrl & TD_CTRL_IOC) 745 *int_mask |= 0x01; 746 747 if (pid == USB_TOKEN_IN) { 748 pci_dma_write(&s->dev, td->buffer, async->buf, len); 749 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 750 *int_mask |= 0x02; 751 /* short packet: do not update QH */ 752 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 753 async->td_addr); 754 return TD_RESULT_NEXT_QH; 755 } 756 } 757 758 /* success */ 759 trace_usb_uhci_packet_complete_success(async->queue->token, 760 async->td_addr); 761 return TD_RESULT_COMPLETE; 762 } 763 764 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 765 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 766 { 767 int ret, max_len; 768 bool spd; 769 bool queuing = (q != NULL); 770 uint8_t pid = td->token & 0xff; 771 UHCIAsync *async = uhci_async_find_td(s, td_addr); 772 773 if (async) { 774 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 775 assert(q == NULL || q == async->queue); 776 q = async->queue; 777 } else { 778 uhci_queue_free(async->queue, "guest re-used pending td"); 779 async = NULL; 780 } 781 } 782 783 if (q == NULL) { 784 q = uhci_queue_find(s, td); 785 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 786 uhci_queue_free(q, "guest re-used qh"); 787 q = NULL; 788 } 789 } 790 791 if (q) { 792 q->valid = QH_VALID; 793 } 794 795 /* Is active ? */ 796 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 797 if (async) { 798 /* Guest marked a pending td non-active, cancel the queue */ 799 uhci_queue_free(async->queue, "pending td non-active"); 800 } 801 /* 802 * ehci11d spec page 22: "Even if the Active bit in the TD is already 803 * cleared when the TD is fetched ... an IOC interrupt is generated" 804 */ 805 if (td->ctrl & TD_CTRL_IOC) { 806 *int_mask |= 0x01; 807 } 808 return TD_RESULT_NEXT_QH; 809 } 810 811 if (async) { 812 if (queuing) { 813 /* we are busy filling the queue, we are not prepared 814 to consume completed packages then, just leave them 815 in async state */ 816 return TD_RESULT_ASYNC_CONT; 817 } 818 if (!async->done) { 819 UHCI_TD last_td; 820 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 821 /* 822 * While we are waiting for the current td to complete, the guest 823 * may have added more tds to the queue. Note we re-read the td 824 * rather then caching it, as we want to see guest made changes! 825 */ 826 uhci_read_td(s, &last_td, last->td_addr); 827 uhci_queue_fill(async->queue, &last_td); 828 829 return TD_RESULT_ASYNC_CONT; 830 } 831 uhci_async_unlink(async); 832 goto done; 833 } 834 835 if (s->completions_only) { 836 return TD_RESULT_ASYNC_CONT; 837 } 838 839 /* Allocate new packet */ 840 if (q == NULL) { 841 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 842 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 843 844 if (ep == NULL) { 845 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 846 int_mask); 847 } 848 q = uhci_queue_new(s, qh_addr, td, ep); 849 } 850 async = uhci_async_alloc(q, td_addr); 851 852 max_len = ((td->token >> 21) + 1) & 0x7ff; 853 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 854 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 855 (td->ctrl & TD_CTRL_IOC) != 0); 856 if (max_len <= sizeof(async->static_buf)) { 857 async->buf = async->static_buf; 858 } else { 859 async->buf = g_malloc(max_len); 860 } 861 usb_packet_addbuf(&async->packet, async->buf, max_len); 862 863 switch(pid) { 864 case USB_TOKEN_OUT: 865 case USB_TOKEN_SETUP: 866 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 867 usb_handle_packet(q->ep->dev, &async->packet); 868 if (async->packet.status == USB_RET_SUCCESS) { 869 async->packet.actual_length = max_len; 870 } 871 break; 872 873 case USB_TOKEN_IN: 874 usb_handle_packet(q->ep->dev, &async->packet); 875 break; 876 877 default: 878 /* invalid pid : frame interrupted */ 879 uhci_async_free(async); 880 s->status |= UHCI_STS_HCPERR; 881 uhci_update_irq(s); 882 return TD_RESULT_STOP_FRAME; 883 } 884 885 if (async->packet.status == USB_RET_ASYNC) { 886 uhci_async_link(async); 887 if (!queuing) { 888 uhci_queue_fill(q, td); 889 } 890 return TD_RESULT_ASYNC_START; 891 } 892 893 done: 894 ret = uhci_complete_td(s, td, async, int_mask); 895 uhci_async_free(async); 896 return ret; 897 } 898 899 static void uhci_async_complete(USBPort *port, USBPacket *packet) 900 { 901 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 902 UHCIState *s = async->queue->uhci; 903 904 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 905 uhci_async_cancel(async); 906 return; 907 } 908 909 async->done = 1; 910 /* Force processing of this packet *now*, needed for migration */ 911 s->completions_only = true; 912 qemu_bh_schedule(s->bh); 913 } 914 915 static int is_valid(uint32_t link) 916 { 917 return (link & 1) == 0; 918 } 919 920 static int is_qh(uint32_t link) 921 { 922 return (link & 2) != 0; 923 } 924 925 static int depth_first(uint32_t link) 926 { 927 return (link & 4) != 0; 928 } 929 930 /* QH DB used for detecting QH loops */ 931 #define UHCI_MAX_QUEUES 128 932 typedef struct { 933 uint32_t addr[UHCI_MAX_QUEUES]; 934 int count; 935 } QhDb; 936 937 static void qhdb_reset(QhDb *db) 938 { 939 db->count = 0; 940 } 941 942 /* Add QH to DB. Returns 1 if already present or DB is full. */ 943 static int qhdb_insert(QhDb *db, uint32_t addr) 944 { 945 int i; 946 for (i = 0; i < db->count; i++) 947 if (db->addr[i] == addr) 948 return 1; 949 950 if (db->count >= UHCI_MAX_QUEUES) 951 return 1; 952 953 db->addr[db->count++] = addr; 954 return 0; 955 } 956 957 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 958 { 959 uint32_t int_mask = 0; 960 uint32_t plink = td->link; 961 UHCI_TD ptd; 962 int ret; 963 964 while (is_valid(plink)) { 965 uhci_read_td(q->uhci, &ptd, plink); 966 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 967 break; 968 } 969 if (uhci_queue_token(&ptd) != q->token) { 970 break; 971 } 972 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 973 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 974 if (ret == TD_RESULT_ASYNC_CONT) { 975 break; 976 } 977 assert(ret == TD_RESULT_ASYNC_START); 978 assert(int_mask == 0); 979 plink = ptd.link; 980 } 981 usb_device_flush_ep_queue(q->ep->dev, q->ep); 982 } 983 984 static void uhci_process_frame(UHCIState *s) 985 { 986 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 987 uint32_t curr_qh, td_count = 0; 988 int cnt, ret; 989 UHCI_TD td; 990 UHCI_QH qh; 991 QhDb qhdb; 992 993 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 994 995 pci_dma_read(&s->dev, frame_addr, &link, 4); 996 le32_to_cpus(&link); 997 998 int_mask = 0; 999 curr_qh = 0; 1000 1001 qhdb_reset(&qhdb); 1002 1003 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1004 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1005 /* We've reached the usb 1.1 bandwidth, which is 1006 1280 bytes/frame, stop processing */ 1007 trace_usb_uhci_frame_stop_bandwidth(); 1008 break; 1009 } 1010 if (is_qh(link)) { 1011 /* QH */ 1012 trace_usb_uhci_qh_load(link & ~0xf); 1013 1014 if (qhdb_insert(&qhdb, link)) { 1015 /* 1016 * We're going in circles. Which is not a bug because 1017 * HCD is allowed to do that as part of the BW management. 1018 * 1019 * Stop processing here if no transaction has been done 1020 * since we've been here last time. 1021 */ 1022 if (td_count == 0) { 1023 trace_usb_uhci_frame_loop_stop_idle(); 1024 break; 1025 } else { 1026 trace_usb_uhci_frame_loop_continue(); 1027 td_count = 0; 1028 qhdb_reset(&qhdb); 1029 qhdb_insert(&qhdb, link); 1030 } 1031 } 1032 1033 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1034 le32_to_cpus(&qh.link); 1035 le32_to_cpus(&qh.el_link); 1036 1037 if (!is_valid(qh.el_link)) { 1038 /* QH w/o elements */ 1039 curr_qh = 0; 1040 link = qh.link; 1041 } else { 1042 /* QH with elements */ 1043 curr_qh = link; 1044 link = qh.el_link; 1045 } 1046 continue; 1047 } 1048 1049 /* TD */ 1050 uhci_read_td(s, &td, link); 1051 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1052 1053 old_td_ctrl = td.ctrl; 1054 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1055 if (old_td_ctrl != td.ctrl) { 1056 /* update the status bits of the TD */ 1057 val = cpu_to_le32(td.ctrl); 1058 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1059 } 1060 1061 switch (ret) { 1062 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1063 goto out; 1064 1065 case TD_RESULT_NEXT_QH: 1066 case TD_RESULT_ASYNC_CONT: 1067 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1068 link = curr_qh ? qh.link : td.link; 1069 continue; 1070 1071 case TD_RESULT_ASYNC_START: 1072 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1073 link = curr_qh ? qh.link : td.link; 1074 continue; 1075 1076 case TD_RESULT_COMPLETE: 1077 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1078 link = td.link; 1079 td_count++; 1080 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1081 1082 if (curr_qh) { 1083 /* update QH element link */ 1084 qh.el_link = link; 1085 val = cpu_to_le32(qh.el_link); 1086 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1087 1088 if (!depth_first(link)) { 1089 /* done with this QH */ 1090 curr_qh = 0; 1091 link = qh.link; 1092 } 1093 } 1094 break; 1095 1096 default: 1097 assert(!"unknown return code"); 1098 } 1099 1100 /* go to the next entry */ 1101 } 1102 1103 out: 1104 s->pending_int_mask |= int_mask; 1105 } 1106 1107 static void uhci_bh(void *opaque) 1108 { 1109 UHCIState *s = opaque; 1110 uhci_process_frame(s); 1111 } 1112 1113 static void uhci_frame_timer(void *opaque) 1114 { 1115 UHCIState *s = opaque; 1116 uint64_t t_now, t_last_run; 1117 int i, frames; 1118 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1119 1120 s->completions_only = false; 1121 qemu_bh_cancel(s->bh); 1122 1123 if (!(s->cmd & UHCI_CMD_RS)) { 1124 /* Full stop */ 1125 trace_usb_uhci_schedule_stop(); 1126 timer_del(s->frame_timer); 1127 uhci_async_cancel_all(s); 1128 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1129 s->status |= UHCI_STS_HCHALTED; 1130 return; 1131 } 1132 1133 /* We still store expire_time in our state, for migration */ 1134 t_last_run = s->expire_time - frame_t; 1135 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1136 1137 /* Process up to MAX_FRAMES_PER_TICK frames */ 1138 frames = (t_now - t_last_run) / frame_t; 1139 if (frames > s->maxframes) { 1140 int skipped = frames - s->maxframes; 1141 s->expire_time += skipped * frame_t; 1142 s->frnum = (s->frnum + skipped) & 0x7ff; 1143 frames -= skipped; 1144 } 1145 if (frames > MAX_FRAMES_PER_TICK) { 1146 frames = MAX_FRAMES_PER_TICK; 1147 } 1148 1149 for (i = 0; i < frames; i++) { 1150 s->frame_bytes = 0; 1151 trace_usb_uhci_frame_start(s->frnum); 1152 uhci_async_validate_begin(s); 1153 uhci_process_frame(s); 1154 uhci_async_validate_end(s); 1155 /* The spec says frnum is the frame currently being processed, and 1156 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1157 s->frnum = (s->frnum + 1) & 0x7ff; 1158 s->expire_time += frame_t; 1159 } 1160 1161 /* Complete the previous frame(s) */ 1162 if (s->pending_int_mask) { 1163 s->status2 |= s->pending_int_mask; 1164 s->status |= UHCI_STS_USBINT; 1165 uhci_update_irq(s); 1166 } 1167 s->pending_int_mask = 0; 1168 1169 timer_mod(s->frame_timer, t_now + frame_t); 1170 } 1171 1172 static const MemoryRegionOps uhci_ioport_ops = { 1173 .read = uhci_port_read, 1174 .write = uhci_port_write, 1175 .valid.min_access_size = 1, 1176 .valid.max_access_size = 4, 1177 .impl.min_access_size = 2, 1178 .impl.max_access_size = 2, 1179 .endianness = DEVICE_LITTLE_ENDIAN, 1180 }; 1181 1182 static USBPortOps uhci_port_ops = { 1183 .attach = uhci_attach, 1184 .detach = uhci_detach, 1185 .child_detach = uhci_child_detach, 1186 .wakeup = uhci_wakeup, 1187 .complete = uhci_async_complete, 1188 }; 1189 1190 static USBBusOps uhci_bus_ops = { 1191 }; 1192 1193 static int usb_uhci_common_initfn(PCIDevice *dev) 1194 { 1195 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1196 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1197 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1198 uint8_t *pci_conf = s->dev.config; 1199 int i; 1200 1201 pci_conf[PCI_CLASS_PROG] = 0x00; 1202 /* TODO: reset value should be 0. */ 1203 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1204 1205 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1206 1207 if (s->masterbus) { 1208 USBPort *ports[NB_PORTS]; 1209 for(i = 0; i < NB_PORTS; i++) { 1210 ports[i] = &s->ports[i].port; 1211 } 1212 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1213 s->firstport, s, &uhci_port_ops, 1214 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1215 return -1; 1216 } 1217 } else { 1218 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1219 for (i = 0; i < NB_PORTS; i++) { 1220 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1221 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1222 } 1223 } 1224 s->bh = qemu_bh_new(uhci_bh, s); 1225 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1226 s->num_ports_vmstate = NB_PORTS; 1227 QTAILQ_INIT(&s->queues); 1228 1229 qemu_register_reset(uhci_reset, s); 1230 1231 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1232 "uhci", 0x20); 1233 1234 /* Use region 4 for consistency with real hardware. BSD guests seem 1235 to rely on this. */ 1236 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1237 1238 return 0; 1239 } 1240 1241 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1242 { 1243 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1244 uint8_t *pci_conf = s->dev.config; 1245 1246 /* USB misc control 1/2 */ 1247 pci_set_long(pci_conf + 0x40,0x00001000); 1248 /* PM capability */ 1249 pci_set_long(pci_conf + 0x80,0x00020001); 1250 /* USB legacy support */ 1251 pci_set_long(pci_conf + 0xc0,0x00002000); 1252 1253 return usb_uhci_common_initfn(dev); 1254 } 1255 1256 static void usb_uhci_exit(PCIDevice *dev) 1257 { 1258 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1259 1260 trace_usb_uhci_exit(); 1261 1262 if (s->frame_timer) { 1263 timer_del(s->frame_timer); 1264 timer_free(s->frame_timer); 1265 s->frame_timer = NULL; 1266 } 1267 1268 if (s->bh) { 1269 qemu_bh_delete(s->bh); 1270 } 1271 1272 uhci_async_cancel_all(s); 1273 1274 if (!s->masterbus) { 1275 usb_bus_release(&s->bus); 1276 } 1277 } 1278 1279 static Property uhci_properties_companion[] = { 1280 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1281 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1282 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1283 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1284 DEFINE_PROP_END_OF_LIST(), 1285 }; 1286 static Property uhci_properties_standalone[] = { 1287 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1288 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1289 DEFINE_PROP_END_OF_LIST(), 1290 }; 1291 1292 static void uhci_class_init(ObjectClass *klass, void *data) 1293 { 1294 DeviceClass *dc = DEVICE_CLASS(klass); 1295 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1296 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1297 UHCIInfo *info = data; 1298 1299 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; 1300 k->exit = info->unplug ? usb_uhci_exit : NULL; 1301 k->vendor_id = info->vendor_id; 1302 k->device_id = info->device_id; 1303 k->revision = info->revision; 1304 k->class_id = PCI_CLASS_SERIAL_USB; 1305 dc->vmsd = &vmstate_uhci; 1306 if (!info->unplug) { 1307 /* uhci controllers in companion setups can't be hotplugged */ 1308 dc->hotpluggable = false; 1309 dc->props = uhci_properties_companion; 1310 } else { 1311 dc->props = uhci_properties_standalone; 1312 } 1313 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1314 u->info = *info; 1315 } 1316 1317 static UHCIInfo uhci_info[] = { 1318 { 1319 .name = "piix3-usb-uhci", 1320 .vendor_id = PCI_VENDOR_ID_INTEL, 1321 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1322 .revision = 0x01, 1323 .irq_pin = 3, 1324 .unplug = true, 1325 },{ 1326 .name = "piix4-usb-uhci", 1327 .vendor_id = PCI_VENDOR_ID_INTEL, 1328 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1329 .revision = 0x01, 1330 .irq_pin = 3, 1331 .unplug = true, 1332 },{ 1333 .name = "vt82c686b-usb-uhci", 1334 .vendor_id = PCI_VENDOR_ID_VIA, 1335 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1336 .revision = 0x01, 1337 .irq_pin = 3, 1338 .initfn = usb_uhci_vt82c686b_initfn, 1339 .unplug = true, 1340 },{ 1341 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1342 .vendor_id = PCI_VENDOR_ID_INTEL, 1343 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1344 .revision = 0x03, 1345 .irq_pin = 0, 1346 .unplug = false, 1347 },{ 1348 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1349 .vendor_id = PCI_VENDOR_ID_INTEL, 1350 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1351 .revision = 0x03, 1352 .irq_pin = 1, 1353 .unplug = false, 1354 },{ 1355 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1356 .vendor_id = PCI_VENDOR_ID_INTEL, 1357 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1358 .revision = 0x03, 1359 .irq_pin = 2, 1360 .unplug = false, 1361 },{ 1362 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1363 .vendor_id = PCI_VENDOR_ID_INTEL, 1364 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1365 .revision = 0x03, 1366 .irq_pin = 0, 1367 .unplug = false, 1368 },{ 1369 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1370 .vendor_id = PCI_VENDOR_ID_INTEL, 1371 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1372 .revision = 0x03, 1373 .irq_pin = 1, 1374 .unplug = false, 1375 },{ 1376 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1377 .vendor_id = PCI_VENDOR_ID_INTEL, 1378 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1379 .revision = 0x03, 1380 .irq_pin = 2, 1381 .unplug = false, 1382 } 1383 }; 1384 1385 static void uhci_register_types(void) 1386 { 1387 TypeInfo uhci_type_info = { 1388 .parent = TYPE_PCI_DEVICE, 1389 .instance_size = sizeof(UHCIState), 1390 .class_size = sizeof(UHCIPCIDeviceClass), 1391 .class_init = uhci_class_init, 1392 }; 1393 int i; 1394 1395 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1396 uhci_type_info.name = uhci_info[i].name; 1397 uhci_type_info.class_data = uhci_info + i; 1398 type_register(&uhci_type_info); 1399 } 1400 } 1401 1402 type_init(uhci_register_types) 1403