1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci/pci.h" 31 #include "qemu/timer.h" 32 #include "qemu/iov.h" 33 #include "sysemu/dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 79 #define QH_VALID 32 80 81 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 82 83 #define NB_PORTS 2 84 85 enum { 86 TD_RESULT_STOP_FRAME = 10, 87 TD_RESULT_COMPLETE, 88 TD_RESULT_NEXT_QH, 89 TD_RESULT_ASYNC_START, 90 TD_RESULT_ASYNC_CONT, 91 }; 92 93 typedef struct UHCIState UHCIState; 94 typedef struct UHCIAsync UHCIAsync; 95 typedef struct UHCIQueue UHCIQueue; 96 typedef struct UHCIInfo UHCIInfo; 97 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 98 99 struct UHCIInfo { 100 const char *name; 101 uint16_t vendor_id; 102 uint16_t device_id; 103 uint8_t revision; 104 uint8_t irq_pin; 105 int (*initfn)(PCIDevice *dev); 106 bool unplug; 107 }; 108 109 struct UHCIPCIDeviceClass { 110 PCIDeviceClass parent_class; 111 UHCIInfo info; 112 }; 113 114 /* 115 * Pending async transaction. 116 * 'packet' must be the first field because completion 117 * handler does "(UHCIAsync *) pkt" cast. 118 */ 119 120 struct UHCIAsync { 121 USBPacket packet; 122 QEMUSGList sgl; 123 UHCIQueue *queue; 124 QTAILQ_ENTRY(UHCIAsync) next; 125 uint32_t td_addr; 126 uint8_t done; 127 }; 128 129 struct UHCIQueue { 130 uint32_t qh_addr; 131 uint32_t token; 132 UHCIState *uhci; 133 USBEndpoint *ep; 134 QTAILQ_ENTRY(UHCIQueue) next; 135 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 136 int8_t valid; 137 }; 138 139 typedef struct UHCIPort { 140 USBPort port; 141 uint16_t ctrl; 142 } UHCIPort; 143 144 struct UHCIState { 145 PCIDevice dev; 146 MemoryRegion io_bar; 147 USBBus bus; /* Note unused when we're a companion controller */ 148 uint16_t cmd; /* cmd register */ 149 uint16_t status; 150 uint16_t intr; /* interrupt enable register */ 151 uint16_t frnum; /* frame number */ 152 uint32_t fl_base_addr; /* frame list base address */ 153 uint8_t sof_timing; 154 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 155 int64_t expire_time; 156 QEMUTimer *frame_timer; 157 QEMUBH *bh; 158 uint32_t frame_bytes; 159 uint32_t frame_bandwidth; 160 bool completions_only; 161 UHCIPort ports[NB_PORTS]; 162 163 /* Interrupts that should be raised at the end of the current frame. */ 164 uint32_t pending_int_mask; 165 int irq_pin; 166 167 /* Active packets */ 168 QTAILQ_HEAD(, UHCIQueue) queues; 169 uint8_t num_ports_vmstate; 170 171 /* Properties */ 172 char *masterbus; 173 uint32_t firstport; 174 uint32_t maxframes; 175 }; 176 177 typedef struct UHCI_TD { 178 uint32_t link; 179 uint32_t ctrl; /* see TD_CTRL_xxx */ 180 uint32_t token; 181 uint32_t buffer; 182 } UHCI_TD; 183 184 typedef struct UHCI_QH { 185 uint32_t link; 186 uint32_t el_link; 187 } UHCI_QH; 188 189 static void uhci_async_cancel(UHCIAsync *async); 190 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 191 192 static inline int32_t uhci_queue_token(UHCI_TD *td) 193 { 194 if ((td->token & (0xf << 15)) == 0) { 195 /* ctrl ep, cover ep and dev, not pid! */ 196 return td->token & 0x7ff00; 197 } else { 198 /* covers ep, dev, pid -> identifies the endpoint */ 199 return td->token & 0x7ffff; 200 } 201 } 202 203 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 204 USBEndpoint *ep) 205 { 206 UHCIQueue *queue; 207 208 queue = g_new0(UHCIQueue, 1); 209 queue->uhci = s; 210 queue->qh_addr = qh_addr; 211 queue->token = uhci_queue_token(td); 212 queue->ep = ep; 213 QTAILQ_INIT(&queue->asyncs); 214 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 215 queue->valid = QH_VALID; 216 trace_usb_uhci_queue_add(queue->token); 217 return queue; 218 } 219 220 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 221 { 222 UHCIState *s = queue->uhci; 223 UHCIAsync *async; 224 225 while (!QTAILQ_EMPTY(&queue->asyncs)) { 226 async = QTAILQ_FIRST(&queue->asyncs); 227 uhci_async_cancel(async); 228 } 229 usb_device_ep_stopped(queue->ep->dev, queue->ep); 230 231 trace_usb_uhci_queue_del(queue->token, reason); 232 QTAILQ_REMOVE(&s->queues, queue, next); 233 g_free(queue); 234 } 235 236 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 237 { 238 uint32_t token = uhci_queue_token(td); 239 UHCIQueue *queue; 240 241 QTAILQ_FOREACH(queue, &s->queues, next) { 242 if (queue->token == token) { 243 return queue; 244 } 245 } 246 return NULL; 247 } 248 249 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 250 uint32_t td_addr, bool queuing) 251 { 252 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 253 254 return queue->qh_addr == qh_addr && 255 queue->token == uhci_queue_token(td) && 256 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 257 first->td_addr == td_addr); 258 } 259 260 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 261 { 262 UHCIAsync *async = g_new0(UHCIAsync, 1); 263 264 async->queue = queue; 265 async->td_addr = td_addr; 266 usb_packet_init(&async->packet); 267 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 268 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 269 270 return async; 271 } 272 273 static void uhci_async_free(UHCIAsync *async) 274 { 275 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 276 usb_packet_cleanup(&async->packet); 277 qemu_sglist_destroy(&async->sgl); 278 g_free(async); 279 } 280 281 static void uhci_async_link(UHCIAsync *async) 282 { 283 UHCIQueue *queue = async->queue; 284 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 285 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 286 } 287 288 static void uhci_async_unlink(UHCIAsync *async) 289 { 290 UHCIQueue *queue = async->queue; 291 QTAILQ_REMOVE(&queue->asyncs, async, next); 292 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 293 } 294 295 static void uhci_async_cancel(UHCIAsync *async) 296 { 297 uhci_async_unlink(async); 298 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 299 async->done); 300 if (!async->done) 301 usb_cancel_packet(&async->packet); 302 usb_packet_unmap(&async->packet, &async->sgl); 303 uhci_async_free(async); 304 } 305 306 /* 307 * Mark all outstanding async packets as invalid. 308 * This is used for canceling them when TDs are removed by the HCD. 309 */ 310 static void uhci_async_validate_begin(UHCIState *s) 311 { 312 UHCIQueue *queue; 313 314 QTAILQ_FOREACH(queue, &s->queues, next) { 315 queue->valid--; 316 } 317 } 318 319 /* 320 * Cancel async packets that are no longer valid 321 */ 322 static void uhci_async_validate_end(UHCIState *s) 323 { 324 UHCIQueue *queue, *n; 325 326 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 327 if (!queue->valid) { 328 uhci_queue_free(queue, "validate-end"); 329 } 330 } 331 } 332 333 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 334 { 335 UHCIQueue *queue, *n; 336 337 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 338 if (queue->ep->dev == dev) { 339 uhci_queue_free(queue, "cancel-device"); 340 } 341 } 342 } 343 344 static void uhci_async_cancel_all(UHCIState *s) 345 { 346 UHCIQueue *queue, *nq; 347 348 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 349 uhci_queue_free(queue, "cancel-all"); 350 } 351 } 352 353 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 354 { 355 UHCIQueue *queue; 356 UHCIAsync *async; 357 358 QTAILQ_FOREACH(queue, &s->queues, next) { 359 QTAILQ_FOREACH(async, &queue->asyncs, next) { 360 if (async->td_addr == td_addr) { 361 return async; 362 } 363 } 364 } 365 return NULL; 366 } 367 368 static void uhci_update_irq(UHCIState *s) 369 { 370 int level; 371 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 372 ((s->status2 & 2) && (s->intr & (1 << 3))) || 373 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 374 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 375 (s->status & UHCI_STS_HSERR) || 376 (s->status & UHCI_STS_HCPERR)) { 377 level = 1; 378 } else { 379 level = 0; 380 } 381 qemu_set_irq(s->dev.irq[s->irq_pin], level); 382 } 383 384 static void uhci_reset(void *opaque) 385 { 386 UHCIState *s = opaque; 387 uint8_t *pci_conf; 388 int i; 389 UHCIPort *port; 390 391 trace_usb_uhci_reset(); 392 393 pci_conf = s->dev.config; 394 395 pci_conf[0x6a] = 0x01; /* usb clock */ 396 pci_conf[0x6b] = 0x00; 397 s->cmd = 0; 398 s->status = 0; 399 s->status2 = 0; 400 s->intr = 0; 401 s->fl_base_addr = 0; 402 s->sof_timing = 64; 403 404 for(i = 0; i < NB_PORTS; i++) { 405 port = &s->ports[i]; 406 port->ctrl = 0x0080; 407 if (port->port.dev && port->port.dev->attached) { 408 usb_port_reset(&port->port); 409 } 410 } 411 412 uhci_async_cancel_all(s); 413 qemu_bh_cancel(s->bh); 414 uhci_update_irq(s); 415 } 416 417 static const VMStateDescription vmstate_uhci_port = { 418 .name = "uhci port", 419 .version_id = 1, 420 .minimum_version_id = 1, 421 .minimum_version_id_old = 1, 422 .fields = (VMStateField []) { 423 VMSTATE_UINT16(ctrl, UHCIPort), 424 VMSTATE_END_OF_LIST() 425 } 426 }; 427 428 static int uhci_post_load(void *opaque, int version_id) 429 { 430 UHCIState *s = opaque; 431 432 if (version_id < 2) { 433 s->expire_time = qemu_get_clock_ns(vm_clock) + 434 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 435 } 436 return 0; 437 } 438 439 static const VMStateDescription vmstate_uhci = { 440 .name = "uhci", 441 .version_id = 3, 442 .minimum_version_id = 1, 443 .minimum_version_id_old = 1, 444 .post_load = uhci_post_load, 445 .fields = (VMStateField []) { 446 VMSTATE_PCI_DEVICE(dev, UHCIState), 447 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 448 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 449 vmstate_uhci_port, UHCIPort), 450 VMSTATE_UINT16(cmd, UHCIState), 451 VMSTATE_UINT16(status, UHCIState), 452 VMSTATE_UINT16(intr, UHCIState), 453 VMSTATE_UINT16(frnum, UHCIState), 454 VMSTATE_UINT32(fl_base_addr, UHCIState), 455 VMSTATE_UINT8(sof_timing, UHCIState), 456 VMSTATE_UINT8(status2, UHCIState), 457 VMSTATE_TIMER(frame_timer, UHCIState), 458 VMSTATE_INT64_V(expire_time, UHCIState, 2), 459 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 460 VMSTATE_END_OF_LIST() 461 } 462 }; 463 464 static void uhci_port_write(void *opaque, hwaddr addr, 465 uint64_t val, unsigned size) 466 { 467 UHCIState *s = opaque; 468 469 trace_usb_uhci_mmio_writew(addr, val); 470 471 switch(addr) { 472 case 0x00: 473 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 474 /* start frame processing */ 475 trace_usb_uhci_schedule_start(); 476 s->expire_time = qemu_get_clock_ns(vm_clock) + 477 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 478 qemu_mod_timer(s->frame_timer, s->expire_time); 479 s->status &= ~UHCI_STS_HCHALTED; 480 } else if (!(val & UHCI_CMD_RS)) { 481 s->status |= UHCI_STS_HCHALTED; 482 } 483 if (val & UHCI_CMD_GRESET) { 484 UHCIPort *port; 485 int i; 486 487 /* send reset on the USB bus */ 488 for(i = 0; i < NB_PORTS; i++) { 489 port = &s->ports[i]; 490 usb_device_reset(port->port.dev); 491 } 492 uhci_reset(s); 493 return; 494 } 495 if (val & UHCI_CMD_HCRESET) { 496 uhci_reset(s); 497 return; 498 } 499 s->cmd = val; 500 break; 501 case 0x02: 502 s->status &= ~val; 503 /* XXX: the chip spec is not coherent, so we add a hidden 504 register to distinguish between IOC and SPD */ 505 if (val & UHCI_STS_USBINT) 506 s->status2 = 0; 507 uhci_update_irq(s); 508 break; 509 case 0x04: 510 s->intr = val; 511 uhci_update_irq(s); 512 break; 513 case 0x06: 514 if (s->status & UHCI_STS_HCHALTED) 515 s->frnum = val & 0x7ff; 516 break; 517 case 0x08: 518 s->fl_base_addr &= 0xffff0000; 519 s->fl_base_addr |= val & ~0xfff; 520 break; 521 case 0x0a: 522 s->fl_base_addr &= 0x0000ffff; 523 s->fl_base_addr |= (val << 16); 524 break; 525 case 0x0c: 526 s->sof_timing = val & 0xff; 527 break; 528 case 0x10 ... 0x1f: 529 { 530 UHCIPort *port; 531 USBDevice *dev; 532 int n; 533 534 n = (addr >> 1) & 7; 535 if (n >= NB_PORTS) 536 return; 537 port = &s->ports[n]; 538 dev = port->port.dev; 539 if (dev && dev->attached) { 540 /* port reset */ 541 if ( (val & UHCI_PORT_RESET) && 542 !(port->ctrl & UHCI_PORT_RESET) ) { 543 usb_device_reset(dev); 544 } 545 } 546 port->ctrl &= UHCI_PORT_READ_ONLY; 547 /* enabled may only be set if a device is connected */ 548 if (!(port->ctrl & UHCI_PORT_CCS)) { 549 val &= ~UHCI_PORT_EN; 550 } 551 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 552 /* some bits are reset when a '1' is written to them */ 553 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 554 } 555 break; 556 } 557 } 558 559 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 560 { 561 UHCIState *s = opaque; 562 uint32_t val; 563 564 switch(addr) { 565 case 0x00: 566 val = s->cmd; 567 break; 568 case 0x02: 569 val = s->status; 570 break; 571 case 0x04: 572 val = s->intr; 573 break; 574 case 0x06: 575 val = s->frnum; 576 break; 577 case 0x08: 578 val = s->fl_base_addr & 0xffff; 579 break; 580 case 0x0a: 581 val = (s->fl_base_addr >> 16) & 0xffff; 582 break; 583 case 0x0c: 584 val = s->sof_timing; 585 break; 586 case 0x10 ... 0x1f: 587 { 588 UHCIPort *port; 589 int n; 590 n = (addr >> 1) & 7; 591 if (n >= NB_PORTS) 592 goto read_default; 593 port = &s->ports[n]; 594 val = port->ctrl; 595 } 596 break; 597 default: 598 read_default: 599 val = 0xff7f; /* disabled port */ 600 break; 601 } 602 603 trace_usb_uhci_mmio_readw(addr, val); 604 605 return val; 606 } 607 608 /* signal resume if controller suspended */ 609 static void uhci_resume (void *opaque) 610 { 611 UHCIState *s = (UHCIState *)opaque; 612 613 if (!s) 614 return; 615 616 if (s->cmd & UHCI_CMD_EGSM) { 617 s->cmd |= UHCI_CMD_FGR; 618 s->status |= UHCI_STS_RD; 619 uhci_update_irq(s); 620 } 621 } 622 623 static void uhci_attach(USBPort *port1) 624 { 625 UHCIState *s = port1->opaque; 626 UHCIPort *port = &s->ports[port1->index]; 627 628 /* set connect status */ 629 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 630 631 /* update speed */ 632 if (port->port.dev->speed == USB_SPEED_LOW) { 633 port->ctrl |= UHCI_PORT_LSDA; 634 } else { 635 port->ctrl &= ~UHCI_PORT_LSDA; 636 } 637 638 uhci_resume(s); 639 } 640 641 static void uhci_detach(USBPort *port1) 642 { 643 UHCIState *s = port1->opaque; 644 UHCIPort *port = &s->ports[port1->index]; 645 646 uhci_async_cancel_device(s, port1->dev); 647 648 /* set connect status */ 649 if (port->ctrl & UHCI_PORT_CCS) { 650 port->ctrl &= ~UHCI_PORT_CCS; 651 port->ctrl |= UHCI_PORT_CSC; 652 } 653 /* disable port */ 654 if (port->ctrl & UHCI_PORT_EN) { 655 port->ctrl &= ~UHCI_PORT_EN; 656 port->ctrl |= UHCI_PORT_ENC; 657 } 658 659 uhci_resume(s); 660 } 661 662 static void uhci_child_detach(USBPort *port1, USBDevice *child) 663 { 664 UHCIState *s = port1->opaque; 665 666 uhci_async_cancel_device(s, child); 667 } 668 669 static void uhci_wakeup(USBPort *port1) 670 { 671 UHCIState *s = port1->opaque; 672 UHCIPort *port = &s->ports[port1->index]; 673 674 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 675 port->ctrl |= UHCI_PORT_RD; 676 uhci_resume(s); 677 } 678 } 679 680 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 681 { 682 USBDevice *dev; 683 int i; 684 685 for (i = 0; i < NB_PORTS; i++) { 686 UHCIPort *port = &s->ports[i]; 687 if (!(port->ctrl & UHCI_PORT_EN)) { 688 continue; 689 } 690 dev = usb_find_device(&port->port, addr); 691 if (dev != NULL) { 692 return dev; 693 } 694 } 695 return NULL; 696 } 697 698 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 699 { 700 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 701 le32_to_cpus(&td->link); 702 le32_to_cpus(&td->ctrl); 703 le32_to_cpus(&td->token); 704 le32_to_cpus(&td->buffer); 705 } 706 707 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 708 int status, uint32_t *int_mask) 709 { 710 uint32_t queue_token = uhci_queue_token(td); 711 int ret; 712 713 switch (status) { 714 case USB_RET_NAK: 715 td->ctrl |= TD_CTRL_NAK; 716 return TD_RESULT_NEXT_QH; 717 718 case USB_RET_STALL: 719 td->ctrl |= TD_CTRL_STALL; 720 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 721 ret = TD_RESULT_NEXT_QH; 722 break; 723 724 case USB_RET_BABBLE: 725 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 726 /* frame interrupted */ 727 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 728 ret = TD_RESULT_STOP_FRAME; 729 break; 730 731 case USB_RET_IOERROR: 732 case USB_RET_NODEV: 733 default: 734 td->ctrl |= TD_CTRL_TIMEOUT; 735 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 736 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 737 ret = TD_RESULT_NEXT_QH; 738 break; 739 } 740 741 td->ctrl &= ~TD_CTRL_ACTIVE; 742 s->status |= UHCI_STS_USBERR; 743 if (td->ctrl & TD_CTRL_IOC) { 744 *int_mask |= 0x01; 745 } 746 uhci_update_irq(s); 747 return ret; 748 } 749 750 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 751 { 752 int len = 0, max_len; 753 uint8_t pid; 754 755 max_len = ((td->token >> 21) + 1) & 0x7ff; 756 pid = td->token & 0xff; 757 758 if (td->ctrl & TD_CTRL_IOS) 759 td->ctrl &= ~TD_CTRL_ACTIVE; 760 761 if (async->packet.status != USB_RET_SUCCESS) { 762 return uhci_handle_td_error(s, td, async->td_addr, 763 async->packet.status, int_mask); 764 } 765 766 len = async->packet.actual_length; 767 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 768 769 /* The NAK bit may have been set by a previous frame, so clear it 770 here. The docs are somewhat unclear, but win2k relies on this 771 behavior. */ 772 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 773 if (td->ctrl & TD_CTRL_IOC) 774 *int_mask |= 0x01; 775 776 if (pid == USB_TOKEN_IN) { 777 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 778 *int_mask |= 0x02; 779 /* short packet: do not update QH */ 780 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 781 async->td_addr); 782 return TD_RESULT_NEXT_QH; 783 } 784 } 785 786 /* success */ 787 trace_usb_uhci_packet_complete_success(async->queue->token, 788 async->td_addr); 789 return TD_RESULT_COMPLETE; 790 } 791 792 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 793 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 794 { 795 int ret, max_len; 796 bool spd; 797 bool queuing = (q != NULL); 798 uint8_t pid = td->token & 0xff; 799 UHCIAsync *async = uhci_async_find_td(s, td_addr); 800 801 if (async) { 802 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 803 assert(q == NULL || q == async->queue); 804 q = async->queue; 805 } else { 806 uhci_queue_free(async->queue, "guest re-used pending td"); 807 async = NULL; 808 } 809 } 810 811 if (q == NULL) { 812 q = uhci_queue_find(s, td); 813 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 814 uhci_queue_free(q, "guest re-used qh"); 815 q = NULL; 816 } 817 } 818 819 if (q) { 820 q->valid = QH_VALID; 821 } 822 823 /* Is active ? */ 824 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 825 if (async) { 826 /* Guest marked a pending td non-active, cancel the queue */ 827 uhci_queue_free(async->queue, "pending td non-active"); 828 } 829 /* 830 * ehci11d spec page 22: "Even if the Active bit in the TD is already 831 * cleared when the TD is fetched ... an IOC interrupt is generated" 832 */ 833 if (td->ctrl & TD_CTRL_IOC) { 834 *int_mask |= 0x01; 835 } 836 return TD_RESULT_NEXT_QH; 837 } 838 839 if (async) { 840 if (queuing) { 841 /* we are busy filling the queue, we are not prepared 842 to consume completed packages then, just leave them 843 in async state */ 844 return TD_RESULT_ASYNC_CONT; 845 } 846 if (!async->done) { 847 UHCI_TD last_td; 848 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 849 /* 850 * While we are waiting for the current td to complete, the guest 851 * may have added more tds to the queue. Note we re-read the td 852 * rather then caching it, as we want to see guest made changes! 853 */ 854 uhci_read_td(s, &last_td, last->td_addr); 855 uhci_queue_fill(async->queue, &last_td); 856 857 return TD_RESULT_ASYNC_CONT; 858 } 859 uhci_async_unlink(async); 860 goto done; 861 } 862 863 if (s->completions_only) { 864 return TD_RESULT_ASYNC_CONT; 865 } 866 867 /* Allocate new packet */ 868 if (q == NULL) { 869 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 870 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 871 872 if (ep == NULL) { 873 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 874 int_mask); 875 } 876 q = uhci_queue_new(s, qh_addr, td, ep); 877 } 878 async = uhci_async_alloc(q, td_addr); 879 880 max_len = ((td->token >> 21) + 1) & 0x7ff; 881 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 882 usb_packet_setup(&async->packet, pid, q->ep, td_addr, spd, 883 (td->ctrl & TD_CTRL_IOC) != 0); 884 qemu_sglist_add(&async->sgl, td->buffer, max_len); 885 usb_packet_map(&async->packet, &async->sgl); 886 887 switch(pid) { 888 case USB_TOKEN_OUT: 889 case USB_TOKEN_SETUP: 890 usb_handle_packet(q->ep->dev, &async->packet); 891 if (async->packet.status == USB_RET_SUCCESS) { 892 async->packet.actual_length = max_len; 893 } 894 break; 895 896 case USB_TOKEN_IN: 897 usb_handle_packet(q->ep->dev, &async->packet); 898 break; 899 900 default: 901 /* invalid pid : frame interrupted */ 902 usb_packet_unmap(&async->packet, &async->sgl); 903 uhci_async_free(async); 904 s->status |= UHCI_STS_HCPERR; 905 uhci_update_irq(s); 906 return TD_RESULT_STOP_FRAME; 907 } 908 909 if (async->packet.status == USB_RET_ASYNC) { 910 uhci_async_link(async); 911 if (!queuing) { 912 uhci_queue_fill(q, td); 913 } 914 return TD_RESULT_ASYNC_START; 915 } 916 917 done: 918 ret = uhci_complete_td(s, td, async, int_mask); 919 usb_packet_unmap(&async->packet, &async->sgl); 920 uhci_async_free(async); 921 return ret; 922 } 923 924 static void uhci_async_complete(USBPort *port, USBPacket *packet) 925 { 926 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 927 UHCIState *s = async->queue->uhci; 928 929 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 930 uhci_async_cancel(async); 931 return; 932 } 933 934 async->done = 1; 935 /* Force processing of this packet *now*, needed for migration */ 936 s->completions_only = true; 937 qemu_bh_schedule(s->bh); 938 } 939 940 static int is_valid(uint32_t link) 941 { 942 return (link & 1) == 0; 943 } 944 945 static int is_qh(uint32_t link) 946 { 947 return (link & 2) != 0; 948 } 949 950 static int depth_first(uint32_t link) 951 { 952 return (link & 4) != 0; 953 } 954 955 /* QH DB used for detecting QH loops */ 956 #define UHCI_MAX_QUEUES 128 957 typedef struct { 958 uint32_t addr[UHCI_MAX_QUEUES]; 959 int count; 960 } QhDb; 961 962 static void qhdb_reset(QhDb *db) 963 { 964 db->count = 0; 965 } 966 967 /* Add QH to DB. Returns 1 if already present or DB is full. */ 968 static int qhdb_insert(QhDb *db, uint32_t addr) 969 { 970 int i; 971 for (i = 0; i < db->count; i++) 972 if (db->addr[i] == addr) 973 return 1; 974 975 if (db->count >= UHCI_MAX_QUEUES) 976 return 1; 977 978 db->addr[db->count++] = addr; 979 return 0; 980 } 981 982 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 983 { 984 uint32_t int_mask = 0; 985 uint32_t plink = td->link; 986 UHCI_TD ptd; 987 int ret; 988 989 while (is_valid(plink)) { 990 uhci_read_td(q->uhci, &ptd, plink); 991 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 992 break; 993 } 994 if (uhci_queue_token(&ptd) != q->token) { 995 break; 996 } 997 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 998 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 999 if (ret == TD_RESULT_ASYNC_CONT) { 1000 break; 1001 } 1002 assert(ret == TD_RESULT_ASYNC_START); 1003 assert(int_mask == 0); 1004 plink = ptd.link; 1005 } 1006 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1007 } 1008 1009 static void uhci_process_frame(UHCIState *s) 1010 { 1011 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1012 uint32_t curr_qh, td_count = 0; 1013 int cnt, ret; 1014 UHCI_TD td; 1015 UHCI_QH qh; 1016 QhDb qhdb; 1017 1018 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1019 1020 pci_dma_read(&s->dev, frame_addr, &link, 4); 1021 le32_to_cpus(&link); 1022 1023 int_mask = 0; 1024 curr_qh = 0; 1025 1026 qhdb_reset(&qhdb); 1027 1028 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1029 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1030 /* We've reached the usb 1.1 bandwidth, which is 1031 1280 bytes/frame, stop processing */ 1032 trace_usb_uhci_frame_stop_bandwidth(); 1033 break; 1034 } 1035 if (is_qh(link)) { 1036 /* QH */ 1037 trace_usb_uhci_qh_load(link & ~0xf); 1038 1039 if (qhdb_insert(&qhdb, link)) { 1040 /* 1041 * We're going in circles. Which is not a bug because 1042 * HCD is allowed to do that as part of the BW management. 1043 * 1044 * Stop processing here if no transaction has been done 1045 * since we've been here last time. 1046 */ 1047 if (td_count == 0) { 1048 trace_usb_uhci_frame_loop_stop_idle(); 1049 break; 1050 } else { 1051 trace_usb_uhci_frame_loop_continue(); 1052 td_count = 0; 1053 qhdb_reset(&qhdb); 1054 qhdb_insert(&qhdb, link); 1055 } 1056 } 1057 1058 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1059 le32_to_cpus(&qh.link); 1060 le32_to_cpus(&qh.el_link); 1061 1062 if (!is_valid(qh.el_link)) { 1063 /* QH w/o elements */ 1064 curr_qh = 0; 1065 link = qh.link; 1066 } else { 1067 /* QH with elements */ 1068 curr_qh = link; 1069 link = qh.el_link; 1070 } 1071 continue; 1072 } 1073 1074 /* TD */ 1075 uhci_read_td(s, &td, link); 1076 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1077 1078 old_td_ctrl = td.ctrl; 1079 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1080 if (old_td_ctrl != td.ctrl) { 1081 /* update the status bits of the TD */ 1082 val = cpu_to_le32(td.ctrl); 1083 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1084 } 1085 1086 switch (ret) { 1087 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1088 goto out; 1089 1090 case TD_RESULT_NEXT_QH: 1091 case TD_RESULT_ASYNC_CONT: 1092 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1093 link = curr_qh ? qh.link : td.link; 1094 continue; 1095 1096 case TD_RESULT_ASYNC_START: 1097 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1098 link = curr_qh ? qh.link : td.link; 1099 continue; 1100 1101 case TD_RESULT_COMPLETE: 1102 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1103 link = td.link; 1104 td_count++; 1105 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1106 1107 if (curr_qh) { 1108 /* update QH element link */ 1109 qh.el_link = link; 1110 val = cpu_to_le32(qh.el_link); 1111 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1112 1113 if (!depth_first(link)) { 1114 /* done with this QH */ 1115 curr_qh = 0; 1116 link = qh.link; 1117 } 1118 } 1119 break; 1120 1121 default: 1122 assert(!"unknown return code"); 1123 } 1124 1125 /* go to the next entry */ 1126 } 1127 1128 out: 1129 s->pending_int_mask |= int_mask; 1130 } 1131 1132 static void uhci_bh(void *opaque) 1133 { 1134 UHCIState *s = opaque; 1135 uhci_process_frame(s); 1136 } 1137 1138 static void uhci_frame_timer(void *opaque) 1139 { 1140 UHCIState *s = opaque; 1141 uint64_t t_now, t_last_run; 1142 int i, frames; 1143 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1144 1145 s->completions_only = false; 1146 qemu_bh_cancel(s->bh); 1147 1148 if (!(s->cmd & UHCI_CMD_RS)) { 1149 /* Full stop */ 1150 trace_usb_uhci_schedule_stop(); 1151 qemu_del_timer(s->frame_timer); 1152 uhci_async_cancel_all(s); 1153 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1154 s->status |= UHCI_STS_HCHALTED; 1155 return; 1156 } 1157 1158 /* We still store expire_time in our state, for migration */ 1159 t_last_run = s->expire_time - frame_t; 1160 t_now = qemu_get_clock_ns(vm_clock); 1161 1162 /* Process up to MAX_FRAMES_PER_TICK frames */ 1163 frames = (t_now - t_last_run) / frame_t; 1164 if (frames > s->maxframes) { 1165 int skipped = frames - s->maxframes; 1166 s->expire_time += skipped * frame_t; 1167 s->frnum = (s->frnum + skipped) & 0x7ff; 1168 frames -= skipped; 1169 } 1170 if (frames > MAX_FRAMES_PER_TICK) { 1171 frames = MAX_FRAMES_PER_TICK; 1172 } 1173 1174 for (i = 0; i < frames; i++) { 1175 s->frame_bytes = 0; 1176 trace_usb_uhci_frame_start(s->frnum); 1177 uhci_async_validate_begin(s); 1178 uhci_process_frame(s); 1179 uhci_async_validate_end(s); 1180 /* The spec says frnum is the frame currently being processed, and 1181 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1182 s->frnum = (s->frnum + 1) & 0x7ff; 1183 s->expire_time += frame_t; 1184 } 1185 1186 /* Complete the previous frame(s) */ 1187 if (s->pending_int_mask) { 1188 s->status2 |= s->pending_int_mask; 1189 s->status |= UHCI_STS_USBINT; 1190 uhci_update_irq(s); 1191 } 1192 s->pending_int_mask = 0; 1193 1194 qemu_mod_timer(s->frame_timer, t_now + frame_t); 1195 } 1196 1197 static const MemoryRegionOps uhci_ioport_ops = { 1198 .read = uhci_port_read, 1199 .write = uhci_port_write, 1200 .valid.min_access_size = 1, 1201 .valid.max_access_size = 4, 1202 .impl.min_access_size = 2, 1203 .impl.max_access_size = 2, 1204 .endianness = DEVICE_LITTLE_ENDIAN, 1205 }; 1206 1207 static USBPortOps uhci_port_ops = { 1208 .attach = uhci_attach, 1209 .detach = uhci_detach, 1210 .child_detach = uhci_child_detach, 1211 .wakeup = uhci_wakeup, 1212 .complete = uhci_async_complete, 1213 }; 1214 1215 static USBBusOps uhci_bus_ops = { 1216 }; 1217 1218 static int usb_uhci_common_initfn(PCIDevice *dev) 1219 { 1220 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1221 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1222 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1223 uint8_t *pci_conf = s->dev.config; 1224 int i; 1225 1226 pci_conf[PCI_CLASS_PROG] = 0x00; 1227 /* TODO: reset value should be 0. */ 1228 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1229 1230 s->irq_pin = u->info.irq_pin; 1231 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); 1232 1233 if (s->masterbus) { 1234 USBPort *ports[NB_PORTS]; 1235 for(i = 0; i < NB_PORTS; i++) { 1236 ports[i] = &s->ports[i].port; 1237 } 1238 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1239 s->firstport, s, &uhci_port_ops, 1240 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1241 return -1; 1242 } 1243 } else { 1244 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1245 for (i = 0; i < NB_PORTS; i++) { 1246 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1247 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1248 } 1249 } 1250 s->bh = qemu_bh_new(uhci_bh, s); 1251 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1252 s->num_ports_vmstate = NB_PORTS; 1253 QTAILQ_INIT(&s->queues); 1254 1255 qemu_register_reset(uhci_reset, s); 1256 1257 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1258 /* Use region 4 for consistency with real hardware. BSD guests seem 1259 to rely on this. */ 1260 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1261 1262 return 0; 1263 } 1264 1265 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1266 { 1267 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1268 uint8_t *pci_conf = s->dev.config; 1269 1270 /* USB misc control 1/2 */ 1271 pci_set_long(pci_conf + 0x40,0x00001000); 1272 /* PM capability */ 1273 pci_set_long(pci_conf + 0x80,0x00020001); 1274 /* USB legacy support */ 1275 pci_set_long(pci_conf + 0xc0,0x00002000); 1276 1277 return usb_uhci_common_initfn(dev); 1278 } 1279 1280 static void usb_uhci_exit(PCIDevice *dev) 1281 { 1282 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1283 1284 memory_region_destroy(&s->io_bar); 1285 } 1286 1287 static Property uhci_properties[] = { 1288 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1289 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1290 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1291 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1292 DEFINE_PROP_END_OF_LIST(), 1293 }; 1294 1295 static void uhci_class_init(ObjectClass *klass, void *data) 1296 { 1297 DeviceClass *dc = DEVICE_CLASS(klass); 1298 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1299 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1300 UHCIInfo *info = data; 1301 1302 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; 1303 k->exit = info->unplug ? usb_uhci_exit : NULL; 1304 k->vendor_id = info->vendor_id; 1305 k->device_id = info->device_id; 1306 k->revision = info->revision; 1307 k->class_id = PCI_CLASS_SERIAL_USB; 1308 k->no_hotplug = 1; 1309 dc->vmsd = &vmstate_uhci; 1310 dc->props = uhci_properties; 1311 u->info = *info; 1312 } 1313 1314 static UHCIInfo uhci_info[] = { 1315 { 1316 .name = "piix3-usb-uhci", 1317 .vendor_id = PCI_VENDOR_ID_INTEL, 1318 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1319 .revision = 0x01, 1320 .irq_pin = 3, 1321 .unplug = true, 1322 },{ 1323 .name = "piix4-usb-uhci", 1324 .vendor_id = PCI_VENDOR_ID_INTEL, 1325 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1326 .revision = 0x01, 1327 .irq_pin = 3, 1328 .unplug = true, 1329 },{ 1330 .name = "vt82c686b-usb-uhci", 1331 .vendor_id = PCI_VENDOR_ID_VIA, 1332 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1333 .revision = 0x01, 1334 .irq_pin = 3, 1335 .initfn = usb_uhci_vt82c686b_initfn, 1336 .unplug = true, 1337 },{ 1338 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1339 .vendor_id = PCI_VENDOR_ID_INTEL, 1340 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1341 .revision = 0x03, 1342 .irq_pin = 0, 1343 .unplug = false, 1344 },{ 1345 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1346 .vendor_id = PCI_VENDOR_ID_INTEL, 1347 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1348 .revision = 0x03, 1349 .irq_pin = 1, 1350 .unplug = false, 1351 },{ 1352 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1353 .vendor_id = PCI_VENDOR_ID_INTEL, 1354 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1355 .revision = 0x03, 1356 .irq_pin = 2, 1357 .unplug = false, 1358 },{ 1359 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1360 .vendor_id = PCI_VENDOR_ID_INTEL, 1361 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1362 .revision = 0x03, 1363 .irq_pin = 0, 1364 .unplug = false, 1365 },{ 1366 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1367 .vendor_id = PCI_VENDOR_ID_INTEL, 1368 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1369 .revision = 0x03, 1370 .irq_pin = 1, 1371 .unplug = false, 1372 },{ 1373 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1374 .vendor_id = PCI_VENDOR_ID_INTEL, 1375 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1376 .revision = 0x03, 1377 .irq_pin = 2, 1378 .unplug = false, 1379 } 1380 }; 1381 1382 static void uhci_register_types(void) 1383 { 1384 TypeInfo uhci_type_info = { 1385 .parent = TYPE_PCI_DEVICE, 1386 .instance_size = sizeof(UHCIState), 1387 .class_size = sizeof(UHCIPCIDeviceClass), 1388 .class_init = uhci_class_init, 1389 }; 1390 int i; 1391 1392 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1393 uhci_type_info.name = uhci_info[i].name; 1394 uhci_type_info.class_data = uhci_info + i; 1395 type_register(&uhci_type_info); 1396 } 1397 } 1398 1399 type_init(uhci_register_types) 1400