1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci/pci.h" 31 #include "qemu/timer.h" 32 #include "qemu/iov.h" 33 #include "sysemu/dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 79 #define QH_VALID 32 80 81 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 82 83 #define NB_PORTS 2 84 85 enum { 86 TD_RESULT_STOP_FRAME = 10, 87 TD_RESULT_COMPLETE, 88 TD_RESULT_NEXT_QH, 89 TD_RESULT_ASYNC_START, 90 TD_RESULT_ASYNC_CONT, 91 }; 92 93 typedef struct UHCIState UHCIState; 94 typedef struct UHCIAsync UHCIAsync; 95 typedef struct UHCIQueue UHCIQueue; 96 typedef struct UHCIInfo UHCIInfo; 97 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 98 99 struct UHCIInfo { 100 const char *name; 101 uint16_t vendor_id; 102 uint16_t device_id; 103 uint8_t revision; 104 uint8_t irq_pin; 105 int (*initfn)(PCIDevice *dev); 106 bool unplug; 107 }; 108 109 struct UHCIPCIDeviceClass { 110 PCIDeviceClass parent_class; 111 UHCIInfo info; 112 }; 113 114 /* 115 * Pending async transaction. 116 * 'packet' must be the first field because completion 117 * handler does "(UHCIAsync *) pkt" cast. 118 */ 119 120 struct UHCIAsync { 121 USBPacket packet; 122 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 123 uint8_t *buf; 124 UHCIQueue *queue; 125 QTAILQ_ENTRY(UHCIAsync) next; 126 uint32_t td_addr; 127 uint8_t done; 128 }; 129 130 struct UHCIQueue { 131 uint32_t qh_addr; 132 uint32_t token; 133 UHCIState *uhci; 134 USBEndpoint *ep; 135 QTAILQ_ENTRY(UHCIQueue) next; 136 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 137 int8_t valid; 138 }; 139 140 typedef struct UHCIPort { 141 USBPort port; 142 uint16_t ctrl; 143 } UHCIPort; 144 145 struct UHCIState { 146 PCIDevice dev; 147 MemoryRegion io_bar; 148 USBBus bus; /* Note unused when we're a companion controller */ 149 uint16_t cmd; /* cmd register */ 150 uint16_t status; 151 uint16_t intr; /* interrupt enable register */ 152 uint16_t frnum; /* frame number */ 153 uint32_t fl_base_addr; /* frame list base address */ 154 uint8_t sof_timing; 155 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 156 int64_t expire_time; 157 QEMUTimer *frame_timer; 158 QEMUBH *bh; 159 uint32_t frame_bytes; 160 uint32_t frame_bandwidth; 161 bool completions_only; 162 UHCIPort ports[NB_PORTS]; 163 164 /* Interrupts that should be raised at the end of the current frame. */ 165 uint32_t pending_int_mask; 166 int irq_pin; 167 168 /* Active packets */ 169 QTAILQ_HEAD(, UHCIQueue) queues; 170 uint8_t num_ports_vmstate; 171 172 /* Properties */ 173 char *masterbus; 174 uint32_t firstport; 175 uint32_t maxframes; 176 }; 177 178 typedef struct UHCI_TD { 179 uint32_t link; 180 uint32_t ctrl; /* see TD_CTRL_xxx */ 181 uint32_t token; 182 uint32_t buffer; 183 } UHCI_TD; 184 185 typedef struct UHCI_QH { 186 uint32_t link; 187 uint32_t el_link; 188 } UHCI_QH; 189 190 static void uhci_async_cancel(UHCIAsync *async); 191 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 192 193 static inline int32_t uhci_queue_token(UHCI_TD *td) 194 { 195 if ((td->token & (0xf << 15)) == 0) { 196 /* ctrl ep, cover ep and dev, not pid! */ 197 return td->token & 0x7ff00; 198 } else { 199 /* covers ep, dev, pid -> identifies the endpoint */ 200 return td->token & 0x7ffff; 201 } 202 } 203 204 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 205 USBEndpoint *ep) 206 { 207 UHCIQueue *queue; 208 209 queue = g_new0(UHCIQueue, 1); 210 queue->uhci = s; 211 queue->qh_addr = qh_addr; 212 queue->token = uhci_queue_token(td); 213 queue->ep = ep; 214 QTAILQ_INIT(&queue->asyncs); 215 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 216 queue->valid = QH_VALID; 217 trace_usb_uhci_queue_add(queue->token); 218 return queue; 219 } 220 221 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 222 { 223 UHCIState *s = queue->uhci; 224 UHCIAsync *async; 225 226 while (!QTAILQ_EMPTY(&queue->asyncs)) { 227 async = QTAILQ_FIRST(&queue->asyncs); 228 uhci_async_cancel(async); 229 } 230 usb_device_ep_stopped(queue->ep->dev, queue->ep); 231 232 trace_usb_uhci_queue_del(queue->token, reason); 233 QTAILQ_REMOVE(&s->queues, queue, next); 234 g_free(queue); 235 } 236 237 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 238 { 239 uint32_t token = uhci_queue_token(td); 240 UHCIQueue *queue; 241 242 QTAILQ_FOREACH(queue, &s->queues, next) { 243 if (queue->token == token) { 244 return queue; 245 } 246 } 247 return NULL; 248 } 249 250 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 251 uint32_t td_addr, bool queuing) 252 { 253 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 254 255 return queue->qh_addr == qh_addr && 256 queue->token == uhci_queue_token(td) && 257 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 258 first->td_addr == td_addr); 259 } 260 261 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 262 { 263 UHCIAsync *async = g_new0(UHCIAsync, 1); 264 265 async->queue = queue; 266 async->td_addr = td_addr; 267 usb_packet_init(&async->packet); 268 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 269 270 return async; 271 } 272 273 static void uhci_async_free(UHCIAsync *async) 274 { 275 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 276 usb_packet_cleanup(&async->packet); 277 if (async->buf != async->static_buf) { 278 g_free(async->buf); 279 } 280 g_free(async); 281 } 282 283 static void uhci_async_link(UHCIAsync *async) 284 { 285 UHCIQueue *queue = async->queue; 286 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 287 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 288 } 289 290 static void uhci_async_unlink(UHCIAsync *async) 291 { 292 UHCIQueue *queue = async->queue; 293 QTAILQ_REMOVE(&queue->asyncs, async, next); 294 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 295 } 296 297 static void uhci_async_cancel(UHCIAsync *async) 298 { 299 uhci_async_unlink(async); 300 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 301 async->done); 302 if (!async->done) 303 usb_cancel_packet(&async->packet); 304 uhci_async_free(async); 305 } 306 307 /* 308 * Mark all outstanding async packets as invalid. 309 * This is used for canceling them when TDs are removed by the HCD. 310 */ 311 static void uhci_async_validate_begin(UHCIState *s) 312 { 313 UHCIQueue *queue; 314 315 QTAILQ_FOREACH(queue, &s->queues, next) { 316 queue->valid--; 317 } 318 } 319 320 /* 321 * Cancel async packets that are no longer valid 322 */ 323 static void uhci_async_validate_end(UHCIState *s) 324 { 325 UHCIQueue *queue, *n; 326 327 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 328 if (!queue->valid) { 329 uhci_queue_free(queue, "validate-end"); 330 } 331 } 332 } 333 334 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 335 { 336 UHCIQueue *queue, *n; 337 338 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 339 if (queue->ep->dev == dev) { 340 uhci_queue_free(queue, "cancel-device"); 341 } 342 } 343 } 344 345 static void uhci_async_cancel_all(UHCIState *s) 346 { 347 UHCIQueue *queue, *nq; 348 349 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 350 uhci_queue_free(queue, "cancel-all"); 351 } 352 } 353 354 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 355 { 356 UHCIQueue *queue; 357 UHCIAsync *async; 358 359 QTAILQ_FOREACH(queue, &s->queues, next) { 360 QTAILQ_FOREACH(async, &queue->asyncs, next) { 361 if (async->td_addr == td_addr) { 362 return async; 363 } 364 } 365 } 366 return NULL; 367 } 368 369 static void uhci_update_irq(UHCIState *s) 370 { 371 int level; 372 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 373 ((s->status2 & 2) && (s->intr & (1 << 3))) || 374 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 375 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 376 (s->status & UHCI_STS_HSERR) || 377 (s->status & UHCI_STS_HCPERR)) { 378 level = 1; 379 } else { 380 level = 0; 381 } 382 qemu_set_irq(s->dev.irq[s->irq_pin], level); 383 } 384 385 static void uhci_reset(void *opaque) 386 { 387 UHCIState *s = opaque; 388 uint8_t *pci_conf; 389 int i; 390 UHCIPort *port; 391 392 trace_usb_uhci_reset(); 393 394 pci_conf = s->dev.config; 395 396 pci_conf[0x6a] = 0x01; /* usb clock */ 397 pci_conf[0x6b] = 0x00; 398 s->cmd = 0; 399 s->status = 0; 400 s->status2 = 0; 401 s->intr = 0; 402 s->fl_base_addr = 0; 403 s->sof_timing = 64; 404 405 for(i = 0; i < NB_PORTS; i++) { 406 port = &s->ports[i]; 407 port->ctrl = 0x0080; 408 if (port->port.dev && port->port.dev->attached) { 409 usb_port_reset(&port->port); 410 } 411 } 412 413 uhci_async_cancel_all(s); 414 qemu_bh_cancel(s->bh); 415 uhci_update_irq(s); 416 } 417 418 static const VMStateDescription vmstate_uhci_port = { 419 .name = "uhci port", 420 .version_id = 1, 421 .minimum_version_id = 1, 422 .minimum_version_id_old = 1, 423 .fields = (VMStateField []) { 424 VMSTATE_UINT16(ctrl, UHCIPort), 425 VMSTATE_END_OF_LIST() 426 } 427 }; 428 429 static int uhci_post_load(void *opaque, int version_id) 430 { 431 UHCIState *s = opaque; 432 433 if (version_id < 2) { 434 s->expire_time = qemu_get_clock_ns(vm_clock) + 435 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 436 } 437 return 0; 438 } 439 440 static const VMStateDescription vmstate_uhci = { 441 .name = "uhci", 442 .version_id = 3, 443 .minimum_version_id = 1, 444 .minimum_version_id_old = 1, 445 .post_load = uhci_post_load, 446 .fields = (VMStateField []) { 447 VMSTATE_PCI_DEVICE(dev, UHCIState), 448 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 449 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 450 vmstate_uhci_port, UHCIPort), 451 VMSTATE_UINT16(cmd, UHCIState), 452 VMSTATE_UINT16(status, UHCIState), 453 VMSTATE_UINT16(intr, UHCIState), 454 VMSTATE_UINT16(frnum, UHCIState), 455 VMSTATE_UINT32(fl_base_addr, UHCIState), 456 VMSTATE_UINT8(sof_timing, UHCIState), 457 VMSTATE_UINT8(status2, UHCIState), 458 VMSTATE_TIMER(frame_timer, UHCIState), 459 VMSTATE_INT64_V(expire_time, UHCIState, 2), 460 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 461 VMSTATE_END_OF_LIST() 462 } 463 }; 464 465 static void uhci_port_write(void *opaque, hwaddr addr, 466 uint64_t val, unsigned size) 467 { 468 UHCIState *s = opaque; 469 470 trace_usb_uhci_mmio_writew(addr, val); 471 472 switch(addr) { 473 case 0x00: 474 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 475 /* start frame processing */ 476 trace_usb_uhci_schedule_start(); 477 s->expire_time = qemu_get_clock_ns(vm_clock) + 478 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 479 qemu_mod_timer(s->frame_timer, s->expire_time); 480 s->status &= ~UHCI_STS_HCHALTED; 481 } else if (!(val & UHCI_CMD_RS)) { 482 s->status |= UHCI_STS_HCHALTED; 483 } 484 if (val & UHCI_CMD_GRESET) { 485 UHCIPort *port; 486 int i; 487 488 /* send reset on the USB bus */ 489 for(i = 0; i < NB_PORTS; i++) { 490 port = &s->ports[i]; 491 usb_device_reset(port->port.dev); 492 } 493 uhci_reset(s); 494 return; 495 } 496 if (val & UHCI_CMD_HCRESET) { 497 uhci_reset(s); 498 return; 499 } 500 s->cmd = val; 501 break; 502 case 0x02: 503 s->status &= ~val; 504 /* XXX: the chip spec is not coherent, so we add a hidden 505 register to distinguish between IOC and SPD */ 506 if (val & UHCI_STS_USBINT) 507 s->status2 = 0; 508 uhci_update_irq(s); 509 break; 510 case 0x04: 511 s->intr = val; 512 uhci_update_irq(s); 513 break; 514 case 0x06: 515 if (s->status & UHCI_STS_HCHALTED) 516 s->frnum = val & 0x7ff; 517 break; 518 case 0x08: 519 s->fl_base_addr &= 0xffff0000; 520 s->fl_base_addr |= val & ~0xfff; 521 break; 522 case 0x0a: 523 s->fl_base_addr &= 0x0000ffff; 524 s->fl_base_addr |= (val << 16); 525 break; 526 case 0x0c: 527 s->sof_timing = val & 0xff; 528 break; 529 case 0x10 ... 0x1f: 530 { 531 UHCIPort *port; 532 USBDevice *dev; 533 int n; 534 535 n = (addr >> 1) & 7; 536 if (n >= NB_PORTS) 537 return; 538 port = &s->ports[n]; 539 dev = port->port.dev; 540 if (dev && dev->attached) { 541 /* port reset */ 542 if ( (val & UHCI_PORT_RESET) && 543 !(port->ctrl & UHCI_PORT_RESET) ) { 544 usb_device_reset(dev); 545 } 546 } 547 port->ctrl &= UHCI_PORT_READ_ONLY; 548 /* enabled may only be set if a device is connected */ 549 if (!(port->ctrl & UHCI_PORT_CCS)) { 550 val &= ~UHCI_PORT_EN; 551 } 552 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 553 /* some bits are reset when a '1' is written to them */ 554 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 555 } 556 break; 557 } 558 } 559 560 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 561 { 562 UHCIState *s = opaque; 563 uint32_t val; 564 565 switch(addr) { 566 case 0x00: 567 val = s->cmd; 568 break; 569 case 0x02: 570 val = s->status; 571 break; 572 case 0x04: 573 val = s->intr; 574 break; 575 case 0x06: 576 val = s->frnum; 577 break; 578 case 0x08: 579 val = s->fl_base_addr & 0xffff; 580 break; 581 case 0x0a: 582 val = (s->fl_base_addr >> 16) & 0xffff; 583 break; 584 case 0x0c: 585 val = s->sof_timing; 586 break; 587 case 0x10 ... 0x1f: 588 { 589 UHCIPort *port; 590 int n; 591 n = (addr >> 1) & 7; 592 if (n >= NB_PORTS) 593 goto read_default; 594 port = &s->ports[n]; 595 val = port->ctrl; 596 } 597 break; 598 default: 599 read_default: 600 val = 0xff7f; /* disabled port */ 601 break; 602 } 603 604 trace_usb_uhci_mmio_readw(addr, val); 605 606 return val; 607 } 608 609 /* signal resume if controller suspended */ 610 static void uhci_resume (void *opaque) 611 { 612 UHCIState *s = (UHCIState *)opaque; 613 614 if (!s) 615 return; 616 617 if (s->cmd & UHCI_CMD_EGSM) { 618 s->cmd |= UHCI_CMD_FGR; 619 s->status |= UHCI_STS_RD; 620 uhci_update_irq(s); 621 } 622 } 623 624 static void uhci_attach(USBPort *port1) 625 { 626 UHCIState *s = port1->opaque; 627 UHCIPort *port = &s->ports[port1->index]; 628 629 /* set connect status */ 630 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 631 632 /* update speed */ 633 if (port->port.dev->speed == USB_SPEED_LOW) { 634 port->ctrl |= UHCI_PORT_LSDA; 635 } else { 636 port->ctrl &= ~UHCI_PORT_LSDA; 637 } 638 639 uhci_resume(s); 640 } 641 642 static void uhci_detach(USBPort *port1) 643 { 644 UHCIState *s = port1->opaque; 645 UHCIPort *port = &s->ports[port1->index]; 646 647 uhci_async_cancel_device(s, port1->dev); 648 649 /* set connect status */ 650 if (port->ctrl & UHCI_PORT_CCS) { 651 port->ctrl &= ~UHCI_PORT_CCS; 652 port->ctrl |= UHCI_PORT_CSC; 653 } 654 /* disable port */ 655 if (port->ctrl & UHCI_PORT_EN) { 656 port->ctrl &= ~UHCI_PORT_EN; 657 port->ctrl |= UHCI_PORT_ENC; 658 } 659 660 uhci_resume(s); 661 } 662 663 static void uhci_child_detach(USBPort *port1, USBDevice *child) 664 { 665 UHCIState *s = port1->opaque; 666 667 uhci_async_cancel_device(s, child); 668 } 669 670 static void uhci_wakeup(USBPort *port1) 671 { 672 UHCIState *s = port1->opaque; 673 UHCIPort *port = &s->ports[port1->index]; 674 675 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 676 port->ctrl |= UHCI_PORT_RD; 677 uhci_resume(s); 678 } 679 } 680 681 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 682 { 683 USBDevice *dev; 684 int i; 685 686 for (i = 0; i < NB_PORTS; i++) { 687 UHCIPort *port = &s->ports[i]; 688 if (!(port->ctrl & UHCI_PORT_EN)) { 689 continue; 690 } 691 dev = usb_find_device(&port->port, addr); 692 if (dev != NULL) { 693 return dev; 694 } 695 } 696 return NULL; 697 } 698 699 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 700 { 701 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 702 le32_to_cpus(&td->link); 703 le32_to_cpus(&td->ctrl); 704 le32_to_cpus(&td->token); 705 le32_to_cpus(&td->buffer); 706 } 707 708 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 709 int status, uint32_t *int_mask) 710 { 711 uint32_t queue_token = uhci_queue_token(td); 712 int ret; 713 714 switch (status) { 715 case USB_RET_NAK: 716 td->ctrl |= TD_CTRL_NAK; 717 return TD_RESULT_NEXT_QH; 718 719 case USB_RET_STALL: 720 td->ctrl |= TD_CTRL_STALL; 721 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 722 ret = TD_RESULT_NEXT_QH; 723 break; 724 725 case USB_RET_BABBLE: 726 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 727 /* frame interrupted */ 728 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 729 ret = TD_RESULT_STOP_FRAME; 730 break; 731 732 case USB_RET_IOERROR: 733 case USB_RET_NODEV: 734 default: 735 td->ctrl |= TD_CTRL_TIMEOUT; 736 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 737 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 738 ret = TD_RESULT_NEXT_QH; 739 break; 740 } 741 742 td->ctrl &= ~TD_CTRL_ACTIVE; 743 s->status |= UHCI_STS_USBERR; 744 if (td->ctrl & TD_CTRL_IOC) { 745 *int_mask |= 0x01; 746 } 747 uhci_update_irq(s); 748 return ret; 749 } 750 751 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 752 { 753 int len = 0, max_len; 754 uint8_t pid; 755 756 max_len = ((td->token >> 21) + 1) & 0x7ff; 757 pid = td->token & 0xff; 758 759 if (td->ctrl & TD_CTRL_IOS) 760 td->ctrl &= ~TD_CTRL_ACTIVE; 761 762 if (async->packet.status != USB_RET_SUCCESS) { 763 return uhci_handle_td_error(s, td, async->td_addr, 764 async->packet.status, int_mask); 765 } 766 767 len = async->packet.actual_length; 768 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 769 770 /* The NAK bit may have been set by a previous frame, so clear it 771 here. The docs are somewhat unclear, but win2k relies on this 772 behavior. */ 773 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 774 if (td->ctrl & TD_CTRL_IOC) 775 *int_mask |= 0x01; 776 777 if (pid == USB_TOKEN_IN) { 778 pci_dma_write(&s->dev, td->buffer, async->buf, len); 779 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 780 *int_mask |= 0x02; 781 /* short packet: do not update QH */ 782 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 783 async->td_addr); 784 return TD_RESULT_NEXT_QH; 785 } 786 } 787 788 /* success */ 789 trace_usb_uhci_packet_complete_success(async->queue->token, 790 async->td_addr); 791 return TD_RESULT_COMPLETE; 792 } 793 794 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 795 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 796 { 797 int ret, max_len; 798 bool spd; 799 bool queuing = (q != NULL); 800 uint8_t pid = td->token & 0xff; 801 UHCIAsync *async = uhci_async_find_td(s, td_addr); 802 803 if (async) { 804 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 805 assert(q == NULL || q == async->queue); 806 q = async->queue; 807 } else { 808 uhci_queue_free(async->queue, "guest re-used pending td"); 809 async = NULL; 810 } 811 } 812 813 if (q == NULL) { 814 q = uhci_queue_find(s, td); 815 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 816 uhci_queue_free(q, "guest re-used qh"); 817 q = NULL; 818 } 819 } 820 821 if (q) { 822 q->valid = QH_VALID; 823 } 824 825 /* Is active ? */ 826 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 827 if (async) { 828 /* Guest marked a pending td non-active, cancel the queue */ 829 uhci_queue_free(async->queue, "pending td non-active"); 830 } 831 /* 832 * ehci11d spec page 22: "Even if the Active bit in the TD is already 833 * cleared when the TD is fetched ... an IOC interrupt is generated" 834 */ 835 if (td->ctrl & TD_CTRL_IOC) { 836 *int_mask |= 0x01; 837 } 838 return TD_RESULT_NEXT_QH; 839 } 840 841 if (async) { 842 if (queuing) { 843 /* we are busy filling the queue, we are not prepared 844 to consume completed packages then, just leave them 845 in async state */ 846 return TD_RESULT_ASYNC_CONT; 847 } 848 if (!async->done) { 849 UHCI_TD last_td; 850 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 851 /* 852 * While we are waiting for the current td to complete, the guest 853 * may have added more tds to the queue. Note we re-read the td 854 * rather then caching it, as we want to see guest made changes! 855 */ 856 uhci_read_td(s, &last_td, last->td_addr); 857 uhci_queue_fill(async->queue, &last_td); 858 859 return TD_RESULT_ASYNC_CONT; 860 } 861 uhci_async_unlink(async); 862 goto done; 863 } 864 865 if (s->completions_only) { 866 return TD_RESULT_ASYNC_CONT; 867 } 868 869 /* Allocate new packet */ 870 if (q == NULL) { 871 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 872 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 873 874 if (ep == NULL) { 875 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 876 int_mask); 877 } 878 q = uhci_queue_new(s, qh_addr, td, ep); 879 } 880 async = uhci_async_alloc(q, td_addr); 881 882 max_len = ((td->token >> 21) + 1) & 0x7ff; 883 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 884 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 885 (td->ctrl & TD_CTRL_IOC) != 0); 886 if (max_len <= sizeof(async->static_buf)) { 887 async->buf = async->static_buf; 888 } else { 889 async->buf = g_malloc(max_len); 890 } 891 usb_packet_addbuf(&async->packet, async->buf, max_len); 892 893 switch(pid) { 894 case USB_TOKEN_OUT: 895 case USB_TOKEN_SETUP: 896 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 897 usb_handle_packet(q->ep->dev, &async->packet); 898 if (async->packet.status == USB_RET_SUCCESS) { 899 async->packet.actual_length = max_len; 900 } 901 break; 902 903 case USB_TOKEN_IN: 904 usb_handle_packet(q->ep->dev, &async->packet); 905 break; 906 907 default: 908 /* invalid pid : frame interrupted */ 909 uhci_async_free(async); 910 s->status |= UHCI_STS_HCPERR; 911 uhci_update_irq(s); 912 return TD_RESULT_STOP_FRAME; 913 } 914 915 if (async->packet.status == USB_RET_ASYNC) { 916 uhci_async_link(async); 917 if (!queuing) { 918 uhci_queue_fill(q, td); 919 } 920 return TD_RESULT_ASYNC_START; 921 } 922 923 done: 924 ret = uhci_complete_td(s, td, async, int_mask); 925 uhci_async_free(async); 926 return ret; 927 } 928 929 static void uhci_async_complete(USBPort *port, USBPacket *packet) 930 { 931 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 932 UHCIState *s = async->queue->uhci; 933 934 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 935 uhci_async_cancel(async); 936 return; 937 } 938 939 async->done = 1; 940 /* Force processing of this packet *now*, needed for migration */ 941 s->completions_only = true; 942 qemu_bh_schedule(s->bh); 943 } 944 945 static int is_valid(uint32_t link) 946 { 947 return (link & 1) == 0; 948 } 949 950 static int is_qh(uint32_t link) 951 { 952 return (link & 2) != 0; 953 } 954 955 static int depth_first(uint32_t link) 956 { 957 return (link & 4) != 0; 958 } 959 960 /* QH DB used for detecting QH loops */ 961 #define UHCI_MAX_QUEUES 128 962 typedef struct { 963 uint32_t addr[UHCI_MAX_QUEUES]; 964 int count; 965 } QhDb; 966 967 static void qhdb_reset(QhDb *db) 968 { 969 db->count = 0; 970 } 971 972 /* Add QH to DB. Returns 1 if already present or DB is full. */ 973 static int qhdb_insert(QhDb *db, uint32_t addr) 974 { 975 int i; 976 for (i = 0; i < db->count; i++) 977 if (db->addr[i] == addr) 978 return 1; 979 980 if (db->count >= UHCI_MAX_QUEUES) 981 return 1; 982 983 db->addr[db->count++] = addr; 984 return 0; 985 } 986 987 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 988 { 989 uint32_t int_mask = 0; 990 uint32_t plink = td->link; 991 UHCI_TD ptd; 992 int ret; 993 994 while (is_valid(plink)) { 995 uhci_read_td(q->uhci, &ptd, plink); 996 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 997 break; 998 } 999 if (uhci_queue_token(&ptd) != q->token) { 1000 break; 1001 } 1002 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 1003 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 1004 if (ret == TD_RESULT_ASYNC_CONT) { 1005 break; 1006 } 1007 assert(ret == TD_RESULT_ASYNC_START); 1008 assert(int_mask == 0); 1009 plink = ptd.link; 1010 } 1011 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1012 } 1013 1014 static void uhci_process_frame(UHCIState *s) 1015 { 1016 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1017 uint32_t curr_qh, td_count = 0; 1018 int cnt, ret; 1019 UHCI_TD td; 1020 UHCI_QH qh; 1021 QhDb qhdb; 1022 1023 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1024 1025 pci_dma_read(&s->dev, frame_addr, &link, 4); 1026 le32_to_cpus(&link); 1027 1028 int_mask = 0; 1029 curr_qh = 0; 1030 1031 qhdb_reset(&qhdb); 1032 1033 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1034 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1035 /* We've reached the usb 1.1 bandwidth, which is 1036 1280 bytes/frame, stop processing */ 1037 trace_usb_uhci_frame_stop_bandwidth(); 1038 break; 1039 } 1040 if (is_qh(link)) { 1041 /* QH */ 1042 trace_usb_uhci_qh_load(link & ~0xf); 1043 1044 if (qhdb_insert(&qhdb, link)) { 1045 /* 1046 * We're going in circles. Which is not a bug because 1047 * HCD is allowed to do that as part of the BW management. 1048 * 1049 * Stop processing here if no transaction has been done 1050 * since we've been here last time. 1051 */ 1052 if (td_count == 0) { 1053 trace_usb_uhci_frame_loop_stop_idle(); 1054 break; 1055 } else { 1056 trace_usb_uhci_frame_loop_continue(); 1057 td_count = 0; 1058 qhdb_reset(&qhdb); 1059 qhdb_insert(&qhdb, link); 1060 } 1061 } 1062 1063 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1064 le32_to_cpus(&qh.link); 1065 le32_to_cpus(&qh.el_link); 1066 1067 if (!is_valid(qh.el_link)) { 1068 /* QH w/o elements */ 1069 curr_qh = 0; 1070 link = qh.link; 1071 } else { 1072 /* QH with elements */ 1073 curr_qh = link; 1074 link = qh.el_link; 1075 } 1076 continue; 1077 } 1078 1079 /* TD */ 1080 uhci_read_td(s, &td, link); 1081 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1082 1083 old_td_ctrl = td.ctrl; 1084 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1085 if (old_td_ctrl != td.ctrl) { 1086 /* update the status bits of the TD */ 1087 val = cpu_to_le32(td.ctrl); 1088 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1089 } 1090 1091 switch (ret) { 1092 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1093 goto out; 1094 1095 case TD_RESULT_NEXT_QH: 1096 case TD_RESULT_ASYNC_CONT: 1097 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1098 link = curr_qh ? qh.link : td.link; 1099 continue; 1100 1101 case TD_RESULT_ASYNC_START: 1102 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1103 link = curr_qh ? qh.link : td.link; 1104 continue; 1105 1106 case TD_RESULT_COMPLETE: 1107 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1108 link = td.link; 1109 td_count++; 1110 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1111 1112 if (curr_qh) { 1113 /* update QH element link */ 1114 qh.el_link = link; 1115 val = cpu_to_le32(qh.el_link); 1116 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1117 1118 if (!depth_first(link)) { 1119 /* done with this QH */ 1120 curr_qh = 0; 1121 link = qh.link; 1122 } 1123 } 1124 break; 1125 1126 default: 1127 assert(!"unknown return code"); 1128 } 1129 1130 /* go to the next entry */ 1131 } 1132 1133 out: 1134 s->pending_int_mask |= int_mask; 1135 } 1136 1137 static void uhci_bh(void *opaque) 1138 { 1139 UHCIState *s = opaque; 1140 uhci_process_frame(s); 1141 } 1142 1143 static void uhci_frame_timer(void *opaque) 1144 { 1145 UHCIState *s = opaque; 1146 uint64_t t_now, t_last_run; 1147 int i, frames; 1148 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1149 1150 s->completions_only = false; 1151 qemu_bh_cancel(s->bh); 1152 1153 if (!(s->cmd & UHCI_CMD_RS)) { 1154 /* Full stop */ 1155 trace_usb_uhci_schedule_stop(); 1156 qemu_del_timer(s->frame_timer); 1157 uhci_async_cancel_all(s); 1158 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1159 s->status |= UHCI_STS_HCHALTED; 1160 return; 1161 } 1162 1163 /* We still store expire_time in our state, for migration */ 1164 t_last_run = s->expire_time - frame_t; 1165 t_now = qemu_get_clock_ns(vm_clock); 1166 1167 /* Process up to MAX_FRAMES_PER_TICK frames */ 1168 frames = (t_now - t_last_run) / frame_t; 1169 if (frames > s->maxframes) { 1170 int skipped = frames - s->maxframes; 1171 s->expire_time += skipped * frame_t; 1172 s->frnum = (s->frnum + skipped) & 0x7ff; 1173 frames -= skipped; 1174 } 1175 if (frames > MAX_FRAMES_PER_TICK) { 1176 frames = MAX_FRAMES_PER_TICK; 1177 } 1178 1179 for (i = 0; i < frames; i++) { 1180 s->frame_bytes = 0; 1181 trace_usb_uhci_frame_start(s->frnum); 1182 uhci_async_validate_begin(s); 1183 uhci_process_frame(s); 1184 uhci_async_validate_end(s); 1185 /* The spec says frnum is the frame currently being processed, and 1186 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1187 s->frnum = (s->frnum + 1) & 0x7ff; 1188 s->expire_time += frame_t; 1189 } 1190 1191 /* Complete the previous frame(s) */ 1192 if (s->pending_int_mask) { 1193 s->status2 |= s->pending_int_mask; 1194 s->status |= UHCI_STS_USBINT; 1195 uhci_update_irq(s); 1196 } 1197 s->pending_int_mask = 0; 1198 1199 qemu_mod_timer(s->frame_timer, t_now + frame_t); 1200 } 1201 1202 static const MemoryRegionOps uhci_ioport_ops = { 1203 .read = uhci_port_read, 1204 .write = uhci_port_write, 1205 .valid.min_access_size = 1, 1206 .valid.max_access_size = 4, 1207 .impl.min_access_size = 2, 1208 .impl.max_access_size = 2, 1209 .endianness = DEVICE_LITTLE_ENDIAN, 1210 }; 1211 1212 static USBPortOps uhci_port_ops = { 1213 .attach = uhci_attach, 1214 .detach = uhci_detach, 1215 .child_detach = uhci_child_detach, 1216 .wakeup = uhci_wakeup, 1217 .complete = uhci_async_complete, 1218 }; 1219 1220 static USBBusOps uhci_bus_ops = { 1221 }; 1222 1223 static int usb_uhci_common_initfn(PCIDevice *dev) 1224 { 1225 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1226 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1227 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1228 uint8_t *pci_conf = s->dev.config; 1229 int i; 1230 1231 pci_conf[PCI_CLASS_PROG] = 0x00; 1232 /* TODO: reset value should be 0. */ 1233 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1234 1235 s->irq_pin = u->info.irq_pin; 1236 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); 1237 1238 if (s->masterbus) { 1239 USBPort *ports[NB_PORTS]; 1240 for(i = 0; i < NB_PORTS; i++) { 1241 ports[i] = &s->ports[i].port; 1242 } 1243 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1244 s->firstport, s, &uhci_port_ops, 1245 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1246 return -1; 1247 } 1248 } else { 1249 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1250 for (i = 0; i < NB_PORTS; i++) { 1251 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1252 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1253 } 1254 } 1255 s->bh = qemu_bh_new(uhci_bh, s); 1256 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1257 s->num_ports_vmstate = NB_PORTS; 1258 QTAILQ_INIT(&s->queues); 1259 1260 qemu_register_reset(uhci_reset, s); 1261 1262 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1263 "uhci", 0x20); 1264 1265 /* Use region 4 for consistency with real hardware. BSD guests seem 1266 to rely on this. */ 1267 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1268 1269 return 0; 1270 } 1271 1272 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1273 { 1274 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1275 uint8_t *pci_conf = s->dev.config; 1276 1277 /* USB misc control 1/2 */ 1278 pci_set_long(pci_conf + 0x40,0x00001000); 1279 /* PM capability */ 1280 pci_set_long(pci_conf + 0x80,0x00020001); 1281 /* USB legacy support */ 1282 pci_set_long(pci_conf + 0xc0,0x00002000); 1283 1284 return usb_uhci_common_initfn(dev); 1285 } 1286 1287 static void usb_uhci_exit(PCIDevice *dev) 1288 { 1289 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1290 1291 memory_region_destroy(&s->io_bar); 1292 } 1293 1294 static Property uhci_properties[] = { 1295 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1296 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1297 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1298 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1299 DEFINE_PROP_END_OF_LIST(), 1300 }; 1301 1302 static void uhci_class_init(ObjectClass *klass, void *data) 1303 { 1304 DeviceClass *dc = DEVICE_CLASS(klass); 1305 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1306 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1307 UHCIInfo *info = data; 1308 1309 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; 1310 k->exit = info->unplug ? usb_uhci_exit : NULL; 1311 k->vendor_id = info->vendor_id; 1312 k->device_id = info->device_id; 1313 k->revision = info->revision; 1314 k->class_id = PCI_CLASS_SERIAL_USB; 1315 k->no_hotplug = 1; 1316 dc->vmsd = &vmstate_uhci; 1317 dc->props = uhci_properties; 1318 u->info = *info; 1319 } 1320 1321 static UHCIInfo uhci_info[] = { 1322 { 1323 .name = "piix3-usb-uhci", 1324 .vendor_id = PCI_VENDOR_ID_INTEL, 1325 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1326 .revision = 0x01, 1327 .irq_pin = 3, 1328 .unplug = true, 1329 },{ 1330 .name = "piix4-usb-uhci", 1331 .vendor_id = PCI_VENDOR_ID_INTEL, 1332 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1333 .revision = 0x01, 1334 .irq_pin = 3, 1335 .unplug = true, 1336 },{ 1337 .name = "vt82c686b-usb-uhci", 1338 .vendor_id = PCI_VENDOR_ID_VIA, 1339 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1340 .revision = 0x01, 1341 .irq_pin = 3, 1342 .initfn = usb_uhci_vt82c686b_initfn, 1343 .unplug = true, 1344 },{ 1345 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1346 .vendor_id = PCI_VENDOR_ID_INTEL, 1347 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1348 .revision = 0x03, 1349 .irq_pin = 0, 1350 .unplug = false, 1351 },{ 1352 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1353 .vendor_id = PCI_VENDOR_ID_INTEL, 1354 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1355 .revision = 0x03, 1356 .irq_pin = 1, 1357 .unplug = false, 1358 },{ 1359 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1360 .vendor_id = PCI_VENDOR_ID_INTEL, 1361 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1362 .revision = 0x03, 1363 .irq_pin = 2, 1364 .unplug = false, 1365 },{ 1366 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1367 .vendor_id = PCI_VENDOR_ID_INTEL, 1368 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1369 .revision = 0x03, 1370 .irq_pin = 0, 1371 .unplug = false, 1372 },{ 1373 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1374 .vendor_id = PCI_VENDOR_ID_INTEL, 1375 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1376 .revision = 0x03, 1377 .irq_pin = 1, 1378 .unplug = false, 1379 },{ 1380 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1381 .vendor_id = PCI_VENDOR_ID_INTEL, 1382 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1383 .revision = 0x03, 1384 .irq_pin = 2, 1385 .unplug = false, 1386 } 1387 }; 1388 1389 static void uhci_register_types(void) 1390 { 1391 TypeInfo uhci_type_info = { 1392 .parent = TYPE_PCI_DEVICE, 1393 .instance_size = sizeof(UHCIState), 1394 .class_size = sizeof(UHCIPCIDeviceClass), 1395 .class_init = uhci_class_init, 1396 }; 1397 int i; 1398 1399 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1400 uhci_type_info.name = uhci_info[i].name; 1401 uhci_type_info.class_data = uhci_info + i; 1402 type_register(&uhci_type_info); 1403 } 1404 } 1405 1406 type_init(uhci_register_types) 1407