1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/hw.h" 31 #include "hw/usb.h" 32 #include "hw/usb/uhci-regs.h" 33 #include "hw/pci/pci.h" 34 #include "qapi/error.h" 35 #include "qemu/timer.h" 36 #include "qemu/iov.h" 37 #include "sysemu/dma.h" 38 #include "trace.h" 39 #include "qemu/main-loop.h" 40 #include "qemu/module.h" 41 42 #define FRAME_TIMER_FREQ 1000 43 44 #define FRAME_MAX_LOOPS 256 45 46 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 47 #define QH_VALID 32 48 49 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 50 51 #define NB_PORTS 2 52 53 enum { 54 TD_RESULT_STOP_FRAME = 10, 55 TD_RESULT_COMPLETE, 56 TD_RESULT_NEXT_QH, 57 TD_RESULT_ASYNC_START, 58 TD_RESULT_ASYNC_CONT, 59 }; 60 61 typedef struct UHCIState UHCIState; 62 typedef struct UHCIAsync UHCIAsync; 63 typedef struct UHCIQueue UHCIQueue; 64 typedef struct UHCIInfo UHCIInfo; 65 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 66 67 struct UHCIInfo { 68 const char *name; 69 uint16_t vendor_id; 70 uint16_t device_id; 71 uint8_t revision; 72 uint8_t irq_pin; 73 void (*realize)(PCIDevice *dev, Error **errp); 74 bool unplug; 75 }; 76 77 struct UHCIPCIDeviceClass { 78 PCIDeviceClass parent_class; 79 UHCIInfo info; 80 }; 81 82 /* 83 * Pending async transaction. 84 * 'packet' must be the first field because completion 85 * handler does "(UHCIAsync *) pkt" cast. 86 */ 87 88 struct UHCIAsync { 89 USBPacket packet; 90 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 91 uint8_t *buf; 92 UHCIQueue *queue; 93 QTAILQ_ENTRY(UHCIAsync) next; 94 uint32_t td_addr; 95 uint8_t done; 96 }; 97 98 struct UHCIQueue { 99 uint32_t qh_addr; 100 uint32_t token; 101 UHCIState *uhci; 102 USBEndpoint *ep; 103 QTAILQ_ENTRY(UHCIQueue) next; 104 QTAILQ_HEAD(, UHCIAsync) asyncs; 105 int8_t valid; 106 }; 107 108 typedef struct UHCIPort { 109 USBPort port; 110 uint16_t ctrl; 111 } UHCIPort; 112 113 struct UHCIState { 114 PCIDevice dev; 115 MemoryRegion io_bar; 116 USBBus bus; /* Note unused when we're a companion controller */ 117 uint16_t cmd; /* cmd register */ 118 uint16_t status; 119 uint16_t intr; /* interrupt enable register */ 120 uint16_t frnum; /* frame number */ 121 uint32_t fl_base_addr; /* frame list base address */ 122 uint8_t sof_timing; 123 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 124 int64_t expire_time; 125 QEMUTimer *frame_timer; 126 QEMUBH *bh; 127 uint32_t frame_bytes; 128 uint32_t frame_bandwidth; 129 bool completions_only; 130 UHCIPort ports[NB_PORTS]; 131 132 /* Interrupts that should be raised at the end of the current frame. */ 133 uint32_t pending_int_mask; 134 135 /* Active packets */ 136 QTAILQ_HEAD(, UHCIQueue) queues; 137 uint8_t num_ports_vmstate; 138 139 /* Properties */ 140 char *masterbus; 141 uint32_t firstport; 142 uint32_t maxframes; 143 }; 144 145 typedef struct UHCI_TD { 146 uint32_t link; 147 uint32_t ctrl; /* see TD_CTRL_xxx */ 148 uint32_t token; 149 uint32_t buffer; 150 } UHCI_TD; 151 152 typedef struct UHCI_QH { 153 uint32_t link; 154 uint32_t el_link; 155 } UHCI_QH; 156 157 static void uhci_async_cancel(UHCIAsync *async); 158 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 159 static void uhci_resume(void *opaque); 160 161 #define TYPE_UHCI "pci-uhci-usb" 162 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI) 163 164 static inline int32_t uhci_queue_token(UHCI_TD *td) 165 { 166 if ((td->token & (0xf << 15)) == 0) { 167 /* ctrl ep, cover ep and dev, not pid! */ 168 return td->token & 0x7ff00; 169 } else { 170 /* covers ep, dev, pid -> identifies the endpoint */ 171 return td->token & 0x7ffff; 172 } 173 } 174 175 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 176 USBEndpoint *ep) 177 { 178 UHCIQueue *queue; 179 180 queue = g_new0(UHCIQueue, 1); 181 queue->uhci = s; 182 queue->qh_addr = qh_addr; 183 queue->token = uhci_queue_token(td); 184 queue->ep = ep; 185 QTAILQ_INIT(&queue->asyncs); 186 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 187 queue->valid = QH_VALID; 188 trace_usb_uhci_queue_add(queue->token); 189 return queue; 190 } 191 192 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 193 { 194 UHCIState *s = queue->uhci; 195 UHCIAsync *async; 196 197 while (!QTAILQ_EMPTY(&queue->asyncs)) { 198 async = QTAILQ_FIRST(&queue->asyncs); 199 uhci_async_cancel(async); 200 } 201 usb_device_ep_stopped(queue->ep->dev, queue->ep); 202 203 trace_usb_uhci_queue_del(queue->token, reason); 204 QTAILQ_REMOVE(&s->queues, queue, next); 205 g_free(queue); 206 } 207 208 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 209 { 210 uint32_t token = uhci_queue_token(td); 211 UHCIQueue *queue; 212 213 QTAILQ_FOREACH(queue, &s->queues, next) { 214 if (queue->token == token) { 215 return queue; 216 } 217 } 218 return NULL; 219 } 220 221 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 222 uint32_t td_addr, bool queuing) 223 { 224 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 225 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 226 227 return queue->qh_addr == qh_addr && 228 queue->token == uhci_queue_token(td) && 229 queue_token_addr == queue->ep->dev->addr && 230 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 231 first->td_addr == td_addr); 232 } 233 234 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 235 { 236 UHCIAsync *async = g_new0(UHCIAsync, 1); 237 238 async->queue = queue; 239 async->td_addr = td_addr; 240 usb_packet_init(&async->packet); 241 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 242 243 return async; 244 } 245 246 static void uhci_async_free(UHCIAsync *async) 247 { 248 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 249 usb_packet_cleanup(&async->packet); 250 if (async->buf != async->static_buf) { 251 g_free(async->buf); 252 } 253 g_free(async); 254 } 255 256 static void uhci_async_link(UHCIAsync *async) 257 { 258 UHCIQueue *queue = async->queue; 259 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 260 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 261 } 262 263 static void uhci_async_unlink(UHCIAsync *async) 264 { 265 UHCIQueue *queue = async->queue; 266 QTAILQ_REMOVE(&queue->asyncs, async, next); 267 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 268 } 269 270 static void uhci_async_cancel(UHCIAsync *async) 271 { 272 uhci_async_unlink(async); 273 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 274 async->done); 275 if (!async->done) 276 usb_cancel_packet(&async->packet); 277 uhci_async_free(async); 278 } 279 280 /* 281 * Mark all outstanding async packets as invalid. 282 * This is used for canceling them when TDs are removed by the HCD. 283 */ 284 static void uhci_async_validate_begin(UHCIState *s) 285 { 286 UHCIQueue *queue; 287 288 QTAILQ_FOREACH(queue, &s->queues, next) { 289 queue->valid--; 290 } 291 } 292 293 /* 294 * Cancel async packets that are no longer valid 295 */ 296 static void uhci_async_validate_end(UHCIState *s) 297 { 298 UHCIQueue *queue, *n; 299 300 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 301 if (!queue->valid) { 302 uhci_queue_free(queue, "validate-end"); 303 } 304 } 305 } 306 307 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 308 { 309 UHCIQueue *queue, *n; 310 311 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 312 if (queue->ep->dev == dev) { 313 uhci_queue_free(queue, "cancel-device"); 314 } 315 } 316 } 317 318 static void uhci_async_cancel_all(UHCIState *s) 319 { 320 UHCIQueue *queue, *nq; 321 322 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 323 uhci_queue_free(queue, "cancel-all"); 324 } 325 } 326 327 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 328 { 329 UHCIQueue *queue; 330 UHCIAsync *async; 331 332 QTAILQ_FOREACH(queue, &s->queues, next) { 333 QTAILQ_FOREACH(async, &queue->asyncs, next) { 334 if (async->td_addr == td_addr) { 335 return async; 336 } 337 } 338 } 339 return NULL; 340 } 341 342 static void uhci_update_irq(UHCIState *s) 343 { 344 int level; 345 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 346 ((s->status2 & 2) && (s->intr & (1 << 3))) || 347 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 348 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 349 (s->status & UHCI_STS_HSERR) || 350 (s->status & UHCI_STS_HCPERR)) { 351 level = 1; 352 } else { 353 level = 0; 354 } 355 pci_set_irq(&s->dev, level); 356 } 357 358 static void uhci_reset(DeviceState *dev) 359 { 360 PCIDevice *d = PCI_DEVICE(dev); 361 UHCIState *s = UHCI(d); 362 uint8_t *pci_conf; 363 int i; 364 UHCIPort *port; 365 366 trace_usb_uhci_reset(); 367 368 pci_conf = s->dev.config; 369 370 pci_conf[0x6a] = 0x01; /* usb clock */ 371 pci_conf[0x6b] = 0x00; 372 s->cmd = 0; 373 s->status = UHCI_STS_HCHALTED; 374 s->status2 = 0; 375 s->intr = 0; 376 s->fl_base_addr = 0; 377 s->sof_timing = 64; 378 379 for(i = 0; i < NB_PORTS; i++) { 380 port = &s->ports[i]; 381 port->ctrl = 0x0080; 382 if (port->port.dev && port->port.dev->attached) { 383 usb_port_reset(&port->port); 384 } 385 } 386 387 uhci_async_cancel_all(s); 388 qemu_bh_cancel(s->bh); 389 uhci_update_irq(s); 390 } 391 392 static const VMStateDescription vmstate_uhci_port = { 393 .name = "uhci port", 394 .version_id = 1, 395 .minimum_version_id = 1, 396 .fields = (VMStateField[]) { 397 VMSTATE_UINT16(ctrl, UHCIPort), 398 VMSTATE_END_OF_LIST() 399 } 400 }; 401 402 static int uhci_post_load(void *opaque, int version_id) 403 { 404 UHCIState *s = opaque; 405 406 if (version_id < 2) { 407 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 408 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 409 } 410 return 0; 411 } 412 413 static const VMStateDescription vmstate_uhci = { 414 .name = "uhci", 415 .version_id = 3, 416 .minimum_version_id = 1, 417 .post_load = uhci_post_load, 418 .fields = (VMStateField[]) { 419 VMSTATE_PCI_DEVICE(dev, UHCIState), 420 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 421 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 422 vmstate_uhci_port, UHCIPort), 423 VMSTATE_UINT16(cmd, UHCIState), 424 VMSTATE_UINT16(status, UHCIState), 425 VMSTATE_UINT16(intr, UHCIState), 426 VMSTATE_UINT16(frnum, UHCIState), 427 VMSTATE_UINT32(fl_base_addr, UHCIState), 428 VMSTATE_UINT8(sof_timing, UHCIState), 429 VMSTATE_UINT8(status2, UHCIState), 430 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 431 VMSTATE_INT64_V(expire_time, UHCIState, 2), 432 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 433 VMSTATE_END_OF_LIST() 434 } 435 }; 436 437 static void uhci_port_write(void *opaque, hwaddr addr, 438 uint64_t val, unsigned size) 439 { 440 UHCIState *s = opaque; 441 442 trace_usb_uhci_mmio_writew(addr, val); 443 444 switch(addr) { 445 case 0x00: 446 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 447 /* start frame processing */ 448 trace_usb_uhci_schedule_start(); 449 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 450 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 451 timer_mod(s->frame_timer, s->expire_time); 452 s->status &= ~UHCI_STS_HCHALTED; 453 } else if (!(val & UHCI_CMD_RS)) { 454 s->status |= UHCI_STS_HCHALTED; 455 } 456 if (val & UHCI_CMD_GRESET) { 457 UHCIPort *port; 458 int i; 459 460 /* send reset on the USB bus */ 461 for(i = 0; i < NB_PORTS; i++) { 462 port = &s->ports[i]; 463 usb_device_reset(port->port.dev); 464 } 465 uhci_reset(DEVICE(s)); 466 return; 467 } 468 if (val & UHCI_CMD_HCRESET) { 469 uhci_reset(DEVICE(s)); 470 return; 471 } 472 s->cmd = val; 473 if (val & UHCI_CMD_EGSM) { 474 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 475 (s->ports[1].ctrl & UHCI_PORT_RD)) { 476 uhci_resume(s); 477 } 478 } 479 break; 480 case 0x02: 481 s->status &= ~val; 482 /* XXX: the chip spec is not coherent, so we add a hidden 483 register to distinguish between IOC and SPD */ 484 if (val & UHCI_STS_USBINT) 485 s->status2 = 0; 486 uhci_update_irq(s); 487 break; 488 case 0x04: 489 s->intr = val; 490 uhci_update_irq(s); 491 break; 492 case 0x06: 493 if (s->status & UHCI_STS_HCHALTED) 494 s->frnum = val & 0x7ff; 495 break; 496 case 0x08: 497 s->fl_base_addr &= 0xffff0000; 498 s->fl_base_addr |= val & ~0xfff; 499 break; 500 case 0x0a: 501 s->fl_base_addr &= 0x0000ffff; 502 s->fl_base_addr |= (val << 16); 503 break; 504 case 0x0c: 505 s->sof_timing = val & 0xff; 506 break; 507 case 0x10 ... 0x1f: 508 { 509 UHCIPort *port; 510 USBDevice *dev; 511 int n; 512 513 n = (addr >> 1) & 7; 514 if (n >= NB_PORTS) 515 return; 516 port = &s->ports[n]; 517 dev = port->port.dev; 518 if (dev && dev->attached) { 519 /* port reset */ 520 if ( (val & UHCI_PORT_RESET) && 521 !(port->ctrl & UHCI_PORT_RESET) ) { 522 usb_device_reset(dev); 523 } 524 } 525 port->ctrl &= UHCI_PORT_READ_ONLY; 526 /* enabled may only be set if a device is connected */ 527 if (!(port->ctrl & UHCI_PORT_CCS)) { 528 val &= ~UHCI_PORT_EN; 529 } 530 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 531 /* some bits are reset when a '1' is written to them */ 532 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 533 } 534 break; 535 } 536 } 537 538 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 539 { 540 UHCIState *s = opaque; 541 uint32_t val; 542 543 switch(addr) { 544 case 0x00: 545 val = s->cmd; 546 break; 547 case 0x02: 548 val = s->status; 549 break; 550 case 0x04: 551 val = s->intr; 552 break; 553 case 0x06: 554 val = s->frnum; 555 break; 556 case 0x08: 557 val = s->fl_base_addr & 0xffff; 558 break; 559 case 0x0a: 560 val = (s->fl_base_addr >> 16) & 0xffff; 561 break; 562 case 0x0c: 563 val = s->sof_timing; 564 break; 565 case 0x10 ... 0x1f: 566 { 567 UHCIPort *port; 568 int n; 569 n = (addr >> 1) & 7; 570 if (n >= NB_PORTS) 571 goto read_default; 572 port = &s->ports[n]; 573 val = port->ctrl; 574 } 575 break; 576 default: 577 read_default: 578 val = 0xff7f; /* disabled port */ 579 break; 580 } 581 582 trace_usb_uhci_mmio_readw(addr, val); 583 584 return val; 585 } 586 587 /* signal resume if controller suspended */ 588 static void uhci_resume (void *opaque) 589 { 590 UHCIState *s = (UHCIState *)opaque; 591 592 if (!s) 593 return; 594 595 if (s->cmd & UHCI_CMD_EGSM) { 596 s->cmd |= UHCI_CMD_FGR; 597 s->status |= UHCI_STS_RD; 598 uhci_update_irq(s); 599 } 600 } 601 602 static void uhci_attach(USBPort *port1) 603 { 604 UHCIState *s = port1->opaque; 605 UHCIPort *port = &s->ports[port1->index]; 606 607 /* set connect status */ 608 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 609 610 /* update speed */ 611 if (port->port.dev->speed == USB_SPEED_LOW) { 612 port->ctrl |= UHCI_PORT_LSDA; 613 } else { 614 port->ctrl &= ~UHCI_PORT_LSDA; 615 } 616 617 uhci_resume(s); 618 } 619 620 static void uhci_detach(USBPort *port1) 621 { 622 UHCIState *s = port1->opaque; 623 UHCIPort *port = &s->ports[port1->index]; 624 625 uhci_async_cancel_device(s, port1->dev); 626 627 /* set connect status */ 628 if (port->ctrl & UHCI_PORT_CCS) { 629 port->ctrl &= ~UHCI_PORT_CCS; 630 port->ctrl |= UHCI_PORT_CSC; 631 } 632 /* disable port */ 633 if (port->ctrl & UHCI_PORT_EN) { 634 port->ctrl &= ~UHCI_PORT_EN; 635 port->ctrl |= UHCI_PORT_ENC; 636 } 637 638 uhci_resume(s); 639 } 640 641 static void uhci_child_detach(USBPort *port1, USBDevice *child) 642 { 643 UHCIState *s = port1->opaque; 644 645 uhci_async_cancel_device(s, child); 646 } 647 648 static void uhci_wakeup(USBPort *port1) 649 { 650 UHCIState *s = port1->opaque; 651 UHCIPort *port = &s->ports[port1->index]; 652 653 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 654 port->ctrl |= UHCI_PORT_RD; 655 uhci_resume(s); 656 } 657 } 658 659 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 660 { 661 USBDevice *dev; 662 int i; 663 664 for (i = 0; i < NB_PORTS; i++) { 665 UHCIPort *port = &s->ports[i]; 666 if (!(port->ctrl & UHCI_PORT_EN)) { 667 continue; 668 } 669 dev = usb_find_device(&port->port, addr); 670 if (dev != NULL) { 671 return dev; 672 } 673 } 674 return NULL; 675 } 676 677 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 678 { 679 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 680 le32_to_cpus(&td->link); 681 le32_to_cpus(&td->ctrl); 682 le32_to_cpus(&td->token); 683 le32_to_cpus(&td->buffer); 684 } 685 686 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 687 int status, uint32_t *int_mask) 688 { 689 uint32_t queue_token = uhci_queue_token(td); 690 int ret; 691 692 switch (status) { 693 case USB_RET_NAK: 694 td->ctrl |= TD_CTRL_NAK; 695 return TD_RESULT_NEXT_QH; 696 697 case USB_RET_STALL: 698 td->ctrl |= TD_CTRL_STALL; 699 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 700 ret = TD_RESULT_NEXT_QH; 701 break; 702 703 case USB_RET_BABBLE: 704 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 705 /* frame interrupted */ 706 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 707 ret = TD_RESULT_STOP_FRAME; 708 break; 709 710 case USB_RET_IOERROR: 711 case USB_RET_NODEV: 712 default: 713 td->ctrl |= TD_CTRL_TIMEOUT; 714 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 715 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 716 ret = TD_RESULT_NEXT_QH; 717 break; 718 } 719 720 td->ctrl &= ~TD_CTRL_ACTIVE; 721 s->status |= UHCI_STS_USBERR; 722 if (td->ctrl & TD_CTRL_IOC) { 723 *int_mask |= 0x01; 724 } 725 uhci_update_irq(s); 726 return ret; 727 } 728 729 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 730 { 731 int len = 0, max_len; 732 uint8_t pid; 733 734 max_len = ((td->token >> 21) + 1) & 0x7ff; 735 pid = td->token & 0xff; 736 737 if (td->ctrl & TD_CTRL_IOS) 738 td->ctrl &= ~TD_CTRL_ACTIVE; 739 740 if (async->packet.status != USB_RET_SUCCESS) { 741 return uhci_handle_td_error(s, td, async->td_addr, 742 async->packet.status, int_mask); 743 } 744 745 len = async->packet.actual_length; 746 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 747 748 /* The NAK bit may have been set by a previous frame, so clear it 749 here. The docs are somewhat unclear, but win2k relies on this 750 behavior. */ 751 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 752 if (td->ctrl & TD_CTRL_IOC) 753 *int_mask |= 0x01; 754 755 if (pid == USB_TOKEN_IN) { 756 pci_dma_write(&s->dev, td->buffer, async->buf, len); 757 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 758 *int_mask |= 0x02; 759 /* short packet: do not update QH */ 760 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 761 async->td_addr); 762 return TD_RESULT_NEXT_QH; 763 } 764 } 765 766 /* success */ 767 trace_usb_uhci_packet_complete_success(async->queue->token, 768 async->td_addr); 769 return TD_RESULT_COMPLETE; 770 } 771 772 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 773 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 774 { 775 int ret, max_len; 776 bool spd; 777 bool queuing = (q != NULL); 778 uint8_t pid = td->token & 0xff; 779 UHCIAsync *async; 780 781 async = uhci_async_find_td(s, td_addr); 782 if (async) { 783 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 784 assert(q == NULL || q == async->queue); 785 q = async->queue; 786 } else { 787 uhci_queue_free(async->queue, "guest re-used pending td"); 788 async = NULL; 789 } 790 } 791 792 if (q == NULL) { 793 q = uhci_queue_find(s, td); 794 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 795 uhci_queue_free(q, "guest re-used qh"); 796 q = NULL; 797 } 798 } 799 800 if (q) { 801 q->valid = QH_VALID; 802 } 803 804 /* Is active ? */ 805 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 806 if (async) { 807 /* Guest marked a pending td non-active, cancel the queue */ 808 uhci_queue_free(async->queue, "pending td non-active"); 809 } 810 /* 811 * ehci11d spec page 22: "Even if the Active bit in the TD is already 812 * cleared when the TD is fetched ... an IOC interrupt is generated" 813 */ 814 if (td->ctrl & TD_CTRL_IOC) { 815 *int_mask |= 0x01; 816 } 817 return TD_RESULT_NEXT_QH; 818 } 819 820 switch (pid) { 821 case USB_TOKEN_OUT: 822 case USB_TOKEN_SETUP: 823 case USB_TOKEN_IN: 824 break; 825 default: 826 /* invalid pid : frame interrupted */ 827 s->status |= UHCI_STS_HCPERR; 828 s->cmd &= ~UHCI_CMD_RS; 829 uhci_update_irq(s); 830 return TD_RESULT_STOP_FRAME; 831 } 832 833 if (async) { 834 if (queuing) { 835 /* we are busy filling the queue, we are not prepared 836 to consume completed packages then, just leave them 837 in async state */ 838 return TD_RESULT_ASYNC_CONT; 839 } 840 if (!async->done) { 841 UHCI_TD last_td; 842 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); 843 /* 844 * While we are waiting for the current td to complete, the guest 845 * may have added more tds to the queue. Note we re-read the td 846 * rather then caching it, as we want to see guest made changes! 847 */ 848 uhci_read_td(s, &last_td, last->td_addr); 849 uhci_queue_fill(async->queue, &last_td); 850 851 return TD_RESULT_ASYNC_CONT; 852 } 853 uhci_async_unlink(async); 854 goto done; 855 } 856 857 if (s->completions_only) { 858 return TD_RESULT_ASYNC_CONT; 859 } 860 861 /* Allocate new packet */ 862 if (q == NULL) { 863 USBDevice *dev; 864 USBEndpoint *ep; 865 866 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 867 if (dev == NULL) { 868 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 869 int_mask); 870 } 871 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 872 q = uhci_queue_new(s, qh_addr, td, ep); 873 } 874 async = uhci_async_alloc(q, td_addr); 875 876 max_len = ((td->token >> 21) + 1) & 0x7ff; 877 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 878 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 879 (td->ctrl & TD_CTRL_IOC) != 0); 880 if (max_len <= sizeof(async->static_buf)) { 881 async->buf = async->static_buf; 882 } else { 883 async->buf = g_malloc(max_len); 884 } 885 usb_packet_addbuf(&async->packet, async->buf, max_len); 886 887 switch(pid) { 888 case USB_TOKEN_OUT: 889 case USB_TOKEN_SETUP: 890 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 891 usb_handle_packet(q->ep->dev, &async->packet); 892 if (async->packet.status == USB_RET_SUCCESS) { 893 async->packet.actual_length = max_len; 894 } 895 break; 896 897 case USB_TOKEN_IN: 898 usb_handle_packet(q->ep->dev, &async->packet); 899 break; 900 901 default: 902 abort(); /* Never to execute */ 903 } 904 905 if (async->packet.status == USB_RET_ASYNC) { 906 uhci_async_link(async); 907 if (!queuing) { 908 uhci_queue_fill(q, td); 909 } 910 return TD_RESULT_ASYNC_START; 911 } 912 913 done: 914 ret = uhci_complete_td(s, td, async, int_mask); 915 uhci_async_free(async); 916 return ret; 917 } 918 919 static void uhci_async_complete(USBPort *port, USBPacket *packet) 920 { 921 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 922 UHCIState *s = async->queue->uhci; 923 924 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 925 uhci_async_cancel(async); 926 return; 927 } 928 929 async->done = 1; 930 /* Force processing of this packet *now*, needed for migration */ 931 s->completions_only = true; 932 qemu_bh_schedule(s->bh); 933 } 934 935 static int is_valid(uint32_t link) 936 { 937 return (link & 1) == 0; 938 } 939 940 static int is_qh(uint32_t link) 941 { 942 return (link & 2) != 0; 943 } 944 945 static int depth_first(uint32_t link) 946 { 947 return (link & 4) != 0; 948 } 949 950 /* QH DB used for detecting QH loops */ 951 #define UHCI_MAX_QUEUES 128 952 typedef struct { 953 uint32_t addr[UHCI_MAX_QUEUES]; 954 int count; 955 } QhDb; 956 957 static void qhdb_reset(QhDb *db) 958 { 959 db->count = 0; 960 } 961 962 /* Add QH to DB. Returns 1 if already present or DB is full. */ 963 static int qhdb_insert(QhDb *db, uint32_t addr) 964 { 965 int i; 966 for (i = 0; i < db->count; i++) 967 if (db->addr[i] == addr) 968 return 1; 969 970 if (db->count >= UHCI_MAX_QUEUES) 971 return 1; 972 973 db->addr[db->count++] = addr; 974 return 0; 975 } 976 977 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 978 { 979 uint32_t int_mask = 0; 980 uint32_t plink = td->link; 981 UHCI_TD ptd; 982 int ret; 983 984 while (is_valid(plink)) { 985 uhci_read_td(q->uhci, &ptd, plink); 986 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 987 break; 988 } 989 if (uhci_queue_token(&ptd) != q->token) { 990 break; 991 } 992 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 993 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 994 if (ret == TD_RESULT_ASYNC_CONT) { 995 break; 996 } 997 assert(ret == TD_RESULT_ASYNC_START); 998 assert(int_mask == 0); 999 plink = ptd.link; 1000 } 1001 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1002 } 1003 1004 static void uhci_process_frame(UHCIState *s) 1005 { 1006 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1007 uint32_t curr_qh, td_count = 0; 1008 int cnt, ret; 1009 UHCI_TD td; 1010 UHCI_QH qh; 1011 QhDb qhdb; 1012 1013 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1014 1015 pci_dma_read(&s->dev, frame_addr, &link, 4); 1016 le32_to_cpus(&link); 1017 1018 int_mask = 0; 1019 curr_qh = 0; 1020 1021 qhdb_reset(&qhdb); 1022 1023 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1024 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1025 /* We've reached the usb 1.1 bandwidth, which is 1026 1280 bytes/frame, stop processing */ 1027 trace_usb_uhci_frame_stop_bandwidth(); 1028 break; 1029 } 1030 if (is_qh(link)) { 1031 /* QH */ 1032 trace_usb_uhci_qh_load(link & ~0xf); 1033 1034 if (qhdb_insert(&qhdb, link)) { 1035 /* 1036 * We're going in circles. Which is not a bug because 1037 * HCD is allowed to do that as part of the BW management. 1038 * 1039 * Stop processing here if no transaction has been done 1040 * since we've been here last time. 1041 */ 1042 if (td_count == 0) { 1043 trace_usb_uhci_frame_loop_stop_idle(); 1044 break; 1045 } else { 1046 trace_usb_uhci_frame_loop_continue(); 1047 td_count = 0; 1048 qhdb_reset(&qhdb); 1049 qhdb_insert(&qhdb, link); 1050 } 1051 } 1052 1053 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1054 le32_to_cpus(&qh.link); 1055 le32_to_cpus(&qh.el_link); 1056 1057 if (!is_valid(qh.el_link)) { 1058 /* QH w/o elements */ 1059 curr_qh = 0; 1060 link = qh.link; 1061 } else { 1062 /* QH with elements */ 1063 curr_qh = link; 1064 link = qh.el_link; 1065 } 1066 continue; 1067 } 1068 1069 /* TD */ 1070 uhci_read_td(s, &td, link); 1071 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1072 1073 old_td_ctrl = td.ctrl; 1074 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1075 if (old_td_ctrl != td.ctrl) { 1076 /* update the status bits of the TD */ 1077 val = cpu_to_le32(td.ctrl); 1078 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1079 } 1080 1081 switch (ret) { 1082 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1083 goto out; 1084 1085 case TD_RESULT_NEXT_QH: 1086 case TD_RESULT_ASYNC_CONT: 1087 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1088 link = curr_qh ? qh.link : td.link; 1089 continue; 1090 1091 case TD_RESULT_ASYNC_START: 1092 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1093 link = curr_qh ? qh.link : td.link; 1094 continue; 1095 1096 case TD_RESULT_COMPLETE: 1097 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1098 link = td.link; 1099 td_count++; 1100 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1101 1102 if (curr_qh) { 1103 /* update QH element link */ 1104 qh.el_link = link; 1105 val = cpu_to_le32(qh.el_link); 1106 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1107 1108 if (!depth_first(link)) { 1109 /* done with this QH */ 1110 curr_qh = 0; 1111 link = qh.link; 1112 } 1113 } 1114 break; 1115 1116 default: 1117 assert(!"unknown return code"); 1118 } 1119 1120 /* go to the next entry */ 1121 } 1122 1123 out: 1124 s->pending_int_mask |= int_mask; 1125 } 1126 1127 static void uhci_bh(void *opaque) 1128 { 1129 UHCIState *s = opaque; 1130 uhci_process_frame(s); 1131 } 1132 1133 static void uhci_frame_timer(void *opaque) 1134 { 1135 UHCIState *s = opaque; 1136 uint64_t t_now, t_last_run; 1137 int i, frames; 1138 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1139 1140 s->completions_only = false; 1141 qemu_bh_cancel(s->bh); 1142 1143 if (!(s->cmd & UHCI_CMD_RS)) { 1144 /* Full stop */ 1145 trace_usb_uhci_schedule_stop(); 1146 timer_del(s->frame_timer); 1147 uhci_async_cancel_all(s); 1148 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1149 s->status |= UHCI_STS_HCHALTED; 1150 return; 1151 } 1152 1153 /* We still store expire_time in our state, for migration */ 1154 t_last_run = s->expire_time - frame_t; 1155 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1156 1157 /* Process up to MAX_FRAMES_PER_TICK frames */ 1158 frames = (t_now - t_last_run) / frame_t; 1159 if (frames > s->maxframes) { 1160 int skipped = frames - s->maxframes; 1161 s->expire_time += skipped * frame_t; 1162 s->frnum = (s->frnum + skipped) & 0x7ff; 1163 frames -= skipped; 1164 } 1165 if (frames > MAX_FRAMES_PER_TICK) { 1166 frames = MAX_FRAMES_PER_TICK; 1167 } 1168 1169 for (i = 0; i < frames; i++) { 1170 s->frame_bytes = 0; 1171 trace_usb_uhci_frame_start(s->frnum); 1172 uhci_async_validate_begin(s); 1173 uhci_process_frame(s); 1174 uhci_async_validate_end(s); 1175 /* The spec says frnum is the frame currently being processed, and 1176 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1177 s->frnum = (s->frnum + 1) & 0x7ff; 1178 s->expire_time += frame_t; 1179 } 1180 1181 /* Complete the previous frame(s) */ 1182 if (s->pending_int_mask) { 1183 s->status2 |= s->pending_int_mask; 1184 s->status |= UHCI_STS_USBINT; 1185 uhci_update_irq(s); 1186 } 1187 s->pending_int_mask = 0; 1188 1189 timer_mod(s->frame_timer, t_now + frame_t); 1190 } 1191 1192 static const MemoryRegionOps uhci_ioport_ops = { 1193 .read = uhci_port_read, 1194 .write = uhci_port_write, 1195 .valid.min_access_size = 1, 1196 .valid.max_access_size = 4, 1197 .impl.min_access_size = 2, 1198 .impl.max_access_size = 2, 1199 .endianness = DEVICE_LITTLE_ENDIAN, 1200 }; 1201 1202 static USBPortOps uhci_port_ops = { 1203 .attach = uhci_attach, 1204 .detach = uhci_detach, 1205 .child_detach = uhci_child_detach, 1206 .wakeup = uhci_wakeup, 1207 .complete = uhci_async_complete, 1208 }; 1209 1210 static USBBusOps uhci_bus_ops = { 1211 }; 1212 1213 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1214 { 1215 Error *err = NULL; 1216 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1217 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1218 UHCIState *s = UHCI(dev); 1219 uint8_t *pci_conf = s->dev.config; 1220 int i; 1221 1222 pci_conf[PCI_CLASS_PROG] = 0x00; 1223 /* TODO: reset value should be 0. */ 1224 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1225 1226 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1227 1228 if (s->masterbus) { 1229 USBPort *ports[NB_PORTS]; 1230 for(i = 0; i < NB_PORTS; i++) { 1231 ports[i] = &s->ports[i].port; 1232 } 1233 usb_register_companion(s->masterbus, ports, NB_PORTS, 1234 s->firstport, s, &uhci_port_ops, 1235 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1236 &err); 1237 if (err) { 1238 error_propagate(errp, err); 1239 return; 1240 } 1241 } else { 1242 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1243 for (i = 0; i < NB_PORTS; i++) { 1244 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1245 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1246 } 1247 } 1248 s->bh = qemu_bh_new(uhci_bh, s); 1249 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1250 s->num_ports_vmstate = NB_PORTS; 1251 QTAILQ_INIT(&s->queues); 1252 1253 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1254 "uhci", 0x20); 1255 1256 /* Use region 4 for consistency with real hardware. BSD guests seem 1257 to rely on this. */ 1258 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1259 } 1260 1261 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) 1262 { 1263 UHCIState *s = UHCI(dev); 1264 uint8_t *pci_conf = s->dev.config; 1265 1266 /* USB misc control 1/2 */ 1267 pci_set_long(pci_conf + 0x40,0x00001000); 1268 /* PM capability */ 1269 pci_set_long(pci_conf + 0x80,0x00020001); 1270 /* USB legacy support */ 1271 pci_set_long(pci_conf + 0xc0,0x00002000); 1272 1273 usb_uhci_common_realize(dev, errp); 1274 } 1275 1276 static void usb_uhci_exit(PCIDevice *dev) 1277 { 1278 UHCIState *s = UHCI(dev); 1279 1280 trace_usb_uhci_exit(); 1281 1282 if (s->frame_timer) { 1283 timer_del(s->frame_timer); 1284 timer_free(s->frame_timer); 1285 s->frame_timer = NULL; 1286 } 1287 1288 if (s->bh) { 1289 qemu_bh_delete(s->bh); 1290 } 1291 1292 uhci_async_cancel_all(s); 1293 1294 if (!s->masterbus) { 1295 usb_bus_release(&s->bus); 1296 } 1297 } 1298 1299 static Property uhci_properties_companion[] = { 1300 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1301 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1302 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1303 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1304 DEFINE_PROP_END_OF_LIST(), 1305 }; 1306 static Property uhci_properties_standalone[] = { 1307 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1308 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1309 DEFINE_PROP_END_OF_LIST(), 1310 }; 1311 1312 static void uhci_class_init(ObjectClass *klass, void *data) 1313 { 1314 DeviceClass *dc = DEVICE_CLASS(klass); 1315 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1316 1317 k->class_id = PCI_CLASS_SERIAL_USB; 1318 dc->vmsd = &vmstate_uhci; 1319 dc->reset = uhci_reset; 1320 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1321 } 1322 1323 static const TypeInfo uhci_pci_type_info = { 1324 .name = TYPE_UHCI, 1325 .parent = TYPE_PCI_DEVICE, 1326 .instance_size = sizeof(UHCIState), 1327 .class_size = sizeof(UHCIPCIDeviceClass), 1328 .abstract = true, 1329 .class_init = uhci_class_init, 1330 .interfaces = (InterfaceInfo[]) { 1331 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1332 { }, 1333 }, 1334 }; 1335 1336 static void uhci_data_class_init(ObjectClass *klass, void *data) 1337 { 1338 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1339 DeviceClass *dc = DEVICE_CLASS(klass); 1340 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1341 UHCIInfo *info = data; 1342 1343 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1344 k->exit = info->unplug ? usb_uhci_exit : NULL; 1345 k->vendor_id = info->vendor_id; 1346 k->device_id = info->device_id; 1347 k->revision = info->revision; 1348 if (!info->unplug) { 1349 /* uhci controllers in companion setups can't be hotplugged */ 1350 dc->hotpluggable = false; 1351 dc->props = uhci_properties_companion; 1352 } else { 1353 dc->props = uhci_properties_standalone; 1354 } 1355 u->info = *info; 1356 } 1357 1358 static UHCIInfo uhci_info[] = { 1359 { 1360 .name = "piix3-usb-uhci", 1361 .vendor_id = PCI_VENDOR_ID_INTEL, 1362 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1363 .revision = 0x01, 1364 .irq_pin = 3, 1365 .unplug = true, 1366 },{ 1367 .name = "piix4-usb-uhci", 1368 .vendor_id = PCI_VENDOR_ID_INTEL, 1369 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1370 .revision = 0x01, 1371 .irq_pin = 3, 1372 .unplug = true, 1373 },{ 1374 .name = "vt82c686b-usb-uhci", 1375 .vendor_id = PCI_VENDOR_ID_VIA, 1376 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1377 .revision = 0x01, 1378 .irq_pin = 3, 1379 .realize = usb_uhci_vt82c686b_realize, 1380 .unplug = true, 1381 },{ 1382 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1383 .vendor_id = PCI_VENDOR_ID_INTEL, 1384 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1385 .revision = 0x03, 1386 .irq_pin = 0, 1387 .unplug = false, 1388 },{ 1389 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1390 .vendor_id = PCI_VENDOR_ID_INTEL, 1391 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1392 .revision = 0x03, 1393 .irq_pin = 1, 1394 .unplug = false, 1395 },{ 1396 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1397 .vendor_id = PCI_VENDOR_ID_INTEL, 1398 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1399 .revision = 0x03, 1400 .irq_pin = 2, 1401 .unplug = false, 1402 },{ 1403 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1404 .vendor_id = PCI_VENDOR_ID_INTEL, 1405 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1406 .revision = 0x03, 1407 .irq_pin = 0, 1408 .unplug = false, 1409 },{ 1410 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1411 .vendor_id = PCI_VENDOR_ID_INTEL, 1412 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1413 .revision = 0x03, 1414 .irq_pin = 1, 1415 .unplug = false, 1416 },{ 1417 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1418 .vendor_id = PCI_VENDOR_ID_INTEL, 1419 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1420 .revision = 0x03, 1421 .irq_pin = 2, 1422 .unplug = false, 1423 } 1424 }; 1425 1426 static void uhci_register_types(void) 1427 { 1428 TypeInfo uhci_type_info = { 1429 .parent = TYPE_UHCI, 1430 .class_init = uhci_data_class_init, 1431 }; 1432 int i; 1433 1434 type_register_static(&uhci_pci_type_info); 1435 1436 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1437 uhci_type_info.name = uhci_info[i].name; 1438 uhci_type_info.class_data = uhci_info + i; 1439 type_register(&uhci_type_info); 1440 } 1441 } 1442 1443 type_init(uhci_register_types) 1444