1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci/pci.h" 31 #include "qemu/timer.h" 32 #include "qemu/iov.h" 33 #include "sysemu/dma.h" 34 #include "trace.h" 35 #include "qemu/main-loop.h" 36 37 //#define DEBUG 38 //#define DEBUG_DUMP_DATA 39 40 #define UHCI_CMD_FGR (1 << 4) 41 #define UHCI_CMD_EGSM (1 << 3) 42 #define UHCI_CMD_GRESET (1 << 2) 43 #define UHCI_CMD_HCRESET (1 << 1) 44 #define UHCI_CMD_RS (1 << 0) 45 46 #define UHCI_STS_HCHALTED (1 << 5) 47 #define UHCI_STS_HCPERR (1 << 4) 48 #define UHCI_STS_HSERR (1 << 3) 49 #define UHCI_STS_RD (1 << 2) 50 #define UHCI_STS_USBERR (1 << 1) 51 #define UHCI_STS_USBINT (1 << 0) 52 53 #define TD_CTRL_SPD (1 << 29) 54 #define TD_CTRL_ERROR_SHIFT 27 55 #define TD_CTRL_IOS (1 << 25) 56 #define TD_CTRL_IOC (1 << 24) 57 #define TD_CTRL_ACTIVE (1 << 23) 58 #define TD_CTRL_STALL (1 << 22) 59 #define TD_CTRL_BABBLE (1 << 20) 60 #define TD_CTRL_NAK (1 << 19) 61 #define TD_CTRL_TIMEOUT (1 << 18) 62 63 #define UHCI_PORT_SUSPEND (1 << 12) 64 #define UHCI_PORT_RESET (1 << 9) 65 #define UHCI_PORT_LSDA (1 << 8) 66 #define UHCI_PORT_RD (1 << 6) 67 #define UHCI_PORT_ENC (1 << 3) 68 #define UHCI_PORT_EN (1 << 2) 69 #define UHCI_PORT_CSC (1 << 1) 70 #define UHCI_PORT_CCS (1 << 0) 71 72 #define UHCI_PORT_READ_ONLY (0x1bb) 73 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 74 75 #define FRAME_TIMER_FREQ 1000 76 77 #define FRAME_MAX_LOOPS 256 78 79 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 80 #define QH_VALID 32 81 82 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 83 84 #define NB_PORTS 2 85 86 enum { 87 TD_RESULT_STOP_FRAME = 10, 88 TD_RESULT_COMPLETE, 89 TD_RESULT_NEXT_QH, 90 TD_RESULT_ASYNC_START, 91 TD_RESULT_ASYNC_CONT, 92 }; 93 94 typedef struct UHCIState UHCIState; 95 typedef struct UHCIAsync UHCIAsync; 96 typedef struct UHCIQueue UHCIQueue; 97 typedef struct UHCIInfo UHCIInfo; 98 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 99 100 struct UHCIInfo { 101 const char *name; 102 uint16_t vendor_id; 103 uint16_t device_id; 104 uint8_t revision; 105 uint8_t irq_pin; 106 int (*initfn)(PCIDevice *dev); 107 bool unplug; 108 }; 109 110 struct UHCIPCIDeviceClass { 111 PCIDeviceClass parent_class; 112 UHCIInfo info; 113 }; 114 115 /* 116 * Pending async transaction. 117 * 'packet' must be the first field because completion 118 * handler does "(UHCIAsync *) pkt" cast. 119 */ 120 121 struct UHCIAsync { 122 USBPacket packet; 123 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 124 uint8_t *buf; 125 UHCIQueue *queue; 126 QTAILQ_ENTRY(UHCIAsync) next; 127 uint32_t td_addr; 128 uint8_t done; 129 }; 130 131 struct UHCIQueue { 132 uint32_t qh_addr; 133 uint32_t token; 134 UHCIState *uhci; 135 USBEndpoint *ep; 136 QTAILQ_ENTRY(UHCIQueue) next; 137 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 138 int8_t valid; 139 }; 140 141 typedef struct UHCIPort { 142 USBPort port; 143 uint16_t ctrl; 144 } UHCIPort; 145 146 struct UHCIState { 147 PCIDevice dev; 148 MemoryRegion io_bar; 149 USBBus bus; /* Note unused when we're a companion controller */ 150 uint16_t cmd; /* cmd register */ 151 uint16_t status; 152 uint16_t intr; /* interrupt enable register */ 153 uint16_t frnum; /* frame number */ 154 uint32_t fl_base_addr; /* frame list base address */ 155 uint8_t sof_timing; 156 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 157 int64_t expire_time; 158 QEMUTimer *frame_timer; 159 QEMUBH *bh; 160 uint32_t frame_bytes; 161 uint32_t frame_bandwidth; 162 bool completions_only; 163 UHCIPort ports[NB_PORTS]; 164 165 /* Interrupts that should be raised at the end of the current frame. */ 166 uint32_t pending_int_mask; 167 168 /* Active packets */ 169 QTAILQ_HEAD(, UHCIQueue) queues; 170 uint8_t num_ports_vmstate; 171 172 /* Properties */ 173 char *masterbus; 174 uint32_t firstport; 175 uint32_t maxframes; 176 }; 177 178 typedef struct UHCI_TD { 179 uint32_t link; 180 uint32_t ctrl; /* see TD_CTRL_xxx */ 181 uint32_t token; 182 uint32_t buffer; 183 } UHCI_TD; 184 185 typedef struct UHCI_QH { 186 uint32_t link; 187 uint32_t el_link; 188 } UHCI_QH; 189 190 static void uhci_async_cancel(UHCIAsync *async); 191 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 192 static void uhci_resume(void *opaque); 193 194 static inline int32_t uhci_queue_token(UHCI_TD *td) 195 { 196 if ((td->token & (0xf << 15)) == 0) { 197 /* ctrl ep, cover ep and dev, not pid! */ 198 return td->token & 0x7ff00; 199 } else { 200 /* covers ep, dev, pid -> identifies the endpoint */ 201 return td->token & 0x7ffff; 202 } 203 } 204 205 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 206 USBEndpoint *ep) 207 { 208 UHCIQueue *queue; 209 210 queue = g_new0(UHCIQueue, 1); 211 queue->uhci = s; 212 queue->qh_addr = qh_addr; 213 queue->token = uhci_queue_token(td); 214 queue->ep = ep; 215 QTAILQ_INIT(&queue->asyncs); 216 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 217 queue->valid = QH_VALID; 218 trace_usb_uhci_queue_add(queue->token); 219 return queue; 220 } 221 222 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 223 { 224 UHCIState *s = queue->uhci; 225 UHCIAsync *async; 226 227 while (!QTAILQ_EMPTY(&queue->asyncs)) { 228 async = QTAILQ_FIRST(&queue->asyncs); 229 uhci_async_cancel(async); 230 } 231 usb_device_ep_stopped(queue->ep->dev, queue->ep); 232 233 trace_usb_uhci_queue_del(queue->token, reason); 234 QTAILQ_REMOVE(&s->queues, queue, next); 235 g_free(queue); 236 } 237 238 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 239 { 240 uint32_t token = uhci_queue_token(td); 241 UHCIQueue *queue; 242 243 QTAILQ_FOREACH(queue, &s->queues, next) { 244 if (queue->token == token) { 245 return queue; 246 } 247 } 248 return NULL; 249 } 250 251 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 252 uint32_t td_addr, bool queuing) 253 { 254 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 255 256 return queue->qh_addr == qh_addr && 257 queue->token == uhci_queue_token(td) && 258 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 259 first->td_addr == td_addr); 260 } 261 262 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 263 { 264 UHCIAsync *async = g_new0(UHCIAsync, 1); 265 266 async->queue = queue; 267 async->td_addr = td_addr; 268 usb_packet_init(&async->packet); 269 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 270 271 return async; 272 } 273 274 static void uhci_async_free(UHCIAsync *async) 275 { 276 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 277 usb_packet_cleanup(&async->packet); 278 if (async->buf != async->static_buf) { 279 g_free(async->buf); 280 } 281 g_free(async); 282 } 283 284 static void uhci_async_link(UHCIAsync *async) 285 { 286 UHCIQueue *queue = async->queue; 287 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 288 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 289 } 290 291 static void uhci_async_unlink(UHCIAsync *async) 292 { 293 UHCIQueue *queue = async->queue; 294 QTAILQ_REMOVE(&queue->asyncs, async, next); 295 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 296 } 297 298 static void uhci_async_cancel(UHCIAsync *async) 299 { 300 uhci_async_unlink(async); 301 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 302 async->done); 303 if (!async->done) 304 usb_cancel_packet(&async->packet); 305 uhci_async_free(async); 306 } 307 308 /* 309 * Mark all outstanding async packets as invalid. 310 * This is used for canceling them when TDs are removed by the HCD. 311 */ 312 static void uhci_async_validate_begin(UHCIState *s) 313 { 314 UHCIQueue *queue; 315 316 QTAILQ_FOREACH(queue, &s->queues, next) { 317 queue->valid--; 318 } 319 } 320 321 /* 322 * Cancel async packets that are no longer valid 323 */ 324 static void uhci_async_validate_end(UHCIState *s) 325 { 326 UHCIQueue *queue, *n; 327 328 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 329 if (!queue->valid) { 330 uhci_queue_free(queue, "validate-end"); 331 } 332 } 333 } 334 335 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 336 { 337 UHCIQueue *queue, *n; 338 339 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 340 if (queue->ep->dev == dev) { 341 uhci_queue_free(queue, "cancel-device"); 342 } 343 } 344 } 345 346 static void uhci_async_cancel_all(UHCIState *s) 347 { 348 UHCIQueue *queue, *nq; 349 350 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 351 uhci_queue_free(queue, "cancel-all"); 352 } 353 } 354 355 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 356 { 357 UHCIQueue *queue; 358 UHCIAsync *async; 359 360 QTAILQ_FOREACH(queue, &s->queues, next) { 361 QTAILQ_FOREACH(async, &queue->asyncs, next) { 362 if (async->td_addr == td_addr) { 363 return async; 364 } 365 } 366 } 367 return NULL; 368 } 369 370 static void uhci_update_irq(UHCIState *s) 371 { 372 int level; 373 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 374 ((s->status2 & 2) && (s->intr & (1 << 3))) || 375 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 376 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 377 (s->status & UHCI_STS_HSERR) || 378 (s->status & UHCI_STS_HCPERR)) { 379 level = 1; 380 } else { 381 level = 0; 382 } 383 pci_set_irq(&s->dev, level); 384 } 385 386 static void uhci_reset(void *opaque) 387 { 388 UHCIState *s = opaque; 389 uint8_t *pci_conf; 390 int i; 391 UHCIPort *port; 392 393 trace_usb_uhci_reset(); 394 395 pci_conf = s->dev.config; 396 397 pci_conf[0x6a] = 0x01; /* usb clock */ 398 pci_conf[0x6b] = 0x00; 399 s->cmd = 0; 400 s->status = 0; 401 s->status2 = 0; 402 s->intr = 0; 403 s->fl_base_addr = 0; 404 s->sof_timing = 64; 405 406 for(i = 0; i < NB_PORTS; i++) { 407 port = &s->ports[i]; 408 port->ctrl = 0x0080; 409 if (port->port.dev && port->port.dev->attached) { 410 usb_port_reset(&port->port); 411 } 412 } 413 414 uhci_async_cancel_all(s); 415 qemu_bh_cancel(s->bh); 416 uhci_update_irq(s); 417 } 418 419 static const VMStateDescription vmstate_uhci_port = { 420 .name = "uhci port", 421 .version_id = 1, 422 .minimum_version_id = 1, 423 .minimum_version_id_old = 1, 424 .fields = (VMStateField []) { 425 VMSTATE_UINT16(ctrl, UHCIPort), 426 VMSTATE_END_OF_LIST() 427 } 428 }; 429 430 static int uhci_post_load(void *opaque, int version_id) 431 { 432 UHCIState *s = opaque; 433 434 if (version_id < 2) { 435 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 436 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 437 } 438 return 0; 439 } 440 441 static const VMStateDescription vmstate_uhci = { 442 .name = "uhci", 443 .version_id = 3, 444 .minimum_version_id = 1, 445 .minimum_version_id_old = 1, 446 .post_load = uhci_post_load, 447 .fields = (VMStateField []) { 448 VMSTATE_PCI_DEVICE(dev, UHCIState), 449 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 450 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 451 vmstate_uhci_port, UHCIPort), 452 VMSTATE_UINT16(cmd, UHCIState), 453 VMSTATE_UINT16(status, UHCIState), 454 VMSTATE_UINT16(intr, UHCIState), 455 VMSTATE_UINT16(frnum, UHCIState), 456 VMSTATE_UINT32(fl_base_addr, UHCIState), 457 VMSTATE_UINT8(sof_timing, UHCIState), 458 VMSTATE_UINT8(status2, UHCIState), 459 VMSTATE_TIMER(frame_timer, UHCIState), 460 VMSTATE_INT64_V(expire_time, UHCIState, 2), 461 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 462 VMSTATE_END_OF_LIST() 463 } 464 }; 465 466 static void uhci_port_write(void *opaque, hwaddr addr, 467 uint64_t val, unsigned size) 468 { 469 UHCIState *s = opaque; 470 471 trace_usb_uhci_mmio_writew(addr, val); 472 473 switch(addr) { 474 case 0x00: 475 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 476 /* start frame processing */ 477 trace_usb_uhci_schedule_start(); 478 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 479 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 480 timer_mod(s->frame_timer, s->expire_time); 481 s->status &= ~UHCI_STS_HCHALTED; 482 } else if (!(val & UHCI_CMD_RS)) { 483 s->status |= UHCI_STS_HCHALTED; 484 } 485 if (val & UHCI_CMD_GRESET) { 486 UHCIPort *port; 487 int i; 488 489 /* send reset on the USB bus */ 490 for(i = 0; i < NB_PORTS; i++) { 491 port = &s->ports[i]; 492 usb_device_reset(port->port.dev); 493 } 494 uhci_reset(s); 495 return; 496 } 497 if (val & UHCI_CMD_HCRESET) { 498 uhci_reset(s); 499 return; 500 } 501 s->cmd = val; 502 if (val & UHCI_CMD_EGSM) { 503 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 504 (s->ports[1].ctrl & UHCI_PORT_RD)) { 505 uhci_resume(s); 506 } 507 } 508 break; 509 case 0x02: 510 s->status &= ~val; 511 /* XXX: the chip spec is not coherent, so we add a hidden 512 register to distinguish between IOC and SPD */ 513 if (val & UHCI_STS_USBINT) 514 s->status2 = 0; 515 uhci_update_irq(s); 516 break; 517 case 0x04: 518 s->intr = val; 519 uhci_update_irq(s); 520 break; 521 case 0x06: 522 if (s->status & UHCI_STS_HCHALTED) 523 s->frnum = val & 0x7ff; 524 break; 525 case 0x08: 526 s->fl_base_addr &= 0xffff0000; 527 s->fl_base_addr |= val & ~0xfff; 528 break; 529 case 0x0a: 530 s->fl_base_addr &= 0x0000ffff; 531 s->fl_base_addr |= (val << 16); 532 break; 533 case 0x0c: 534 s->sof_timing = val & 0xff; 535 break; 536 case 0x10 ... 0x1f: 537 { 538 UHCIPort *port; 539 USBDevice *dev; 540 int n; 541 542 n = (addr >> 1) & 7; 543 if (n >= NB_PORTS) 544 return; 545 port = &s->ports[n]; 546 dev = port->port.dev; 547 if (dev && dev->attached) { 548 /* port reset */ 549 if ( (val & UHCI_PORT_RESET) && 550 !(port->ctrl & UHCI_PORT_RESET) ) { 551 usb_device_reset(dev); 552 } 553 } 554 port->ctrl &= UHCI_PORT_READ_ONLY; 555 /* enabled may only be set if a device is connected */ 556 if (!(port->ctrl & UHCI_PORT_CCS)) { 557 val &= ~UHCI_PORT_EN; 558 } 559 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 560 /* some bits are reset when a '1' is written to them */ 561 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 562 } 563 break; 564 } 565 } 566 567 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 568 { 569 UHCIState *s = opaque; 570 uint32_t val; 571 572 switch(addr) { 573 case 0x00: 574 val = s->cmd; 575 break; 576 case 0x02: 577 val = s->status; 578 break; 579 case 0x04: 580 val = s->intr; 581 break; 582 case 0x06: 583 val = s->frnum; 584 break; 585 case 0x08: 586 val = s->fl_base_addr & 0xffff; 587 break; 588 case 0x0a: 589 val = (s->fl_base_addr >> 16) & 0xffff; 590 break; 591 case 0x0c: 592 val = s->sof_timing; 593 break; 594 case 0x10 ... 0x1f: 595 { 596 UHCIPort *port; 597 int n; 598 n = (addr >> 1) & 7; 599 if (n >= NB_PORTS) 600 goto read_default; 601 port = &s->ports[n]; 602 val = port->ctrl; 603 } 604 break; 605 default: 606 read_default: 607 val = 0xff7f; /* disabled port */ 608 break; 609 } 610 611 trace_usb_uhci_mmio_readw(addr, val); 612 613 return val; 614 } 615 616 /* signal resume if controller suspended */ 617 static void uhci_resume (void *opaque) 618 { 619 UHCIState *s = (UHCIState *)opaque; 620 621 if (!s) 622 return; 623 624 if (s->cmd & UHCI_CMD_EGSM) { 625 s->cmd |= UHCI_CMD_FGR; 626 s->status |= UHCI_STS_RD; 627 uhci_update_irq(s); 628 } 629 } 630 631 static void uhci_attach(USBPort *port1) 632 { 633 UHCIState *s = port1->opaque; 634 UHCIPort *port = &s->ports[port1->index]; 635 636 /* set connect status */ 637 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 638 639 /* update speed */ 640 if (port->port.dev->speed == USB_SPEED_LOW) { 641 port->ctrl |= UHCI_PORT_LSDA; 642 } else { 643 port->ctrl &= ~UHCI_PORT_LSDA; 644 } 645 646 uhci_resume(s); 647 } 648 649 static void uhci_detach(USBPort *port1) 650 { 651 UHCIState *s = port1->opaque; 652 UHCIPort *port = &s->ports[port1->index]; 653 654 uhci_async_cancel_device(s, port1->dev); 655 656 /* set connect status */ 657 if (port->ctrl & UHCI_PORT_CCS) { 658 port->ctrl &= ~UHCI_PORT_CCS; 659 port->ctrl |= UHCI_PORT_CSC; 660 } 661 /* disable port */ 662 if (port->ctrl & UHCI_PORT_EN) { 663 port->ctrl &= ~UHCI_PORT_EN; 664 port->ctrl |= UHCI_PORT_ENC; 665 } 666 667 uhci_resume(s); 668 } 669 670 static void uhci_child_detach(USBPort *port1, USBDevice *child) 671 { 672 UHCIState *s = port1->opaque; 673 674 uhci_async_cancel_device(s, child); 675 } 676 677 static void uhci_wakeup(USBPort *port1) 678 { 679 UHCIState *s = port1->opaque; 680 UHCIPort *port = &s->ports[port1->index]; 681 682 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 683 port->ctrl |= UHCI_PORT_RD; 684 uhci_resume(s); 685 } 686 } 687 688 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 689 { 690 USBDevice *dev; 691 int i; 692 693 for (i = 0; i < NB_PORTS; i++) { 694 UHCIPort *port = &s->ports[i]; 695 if (!(port->ctrl & UHCI_PORT_EN)) { 696 continue; 697 } 698 dev = usb_find_device(&port->port, addr); 699 if (dev != NULL) { 700 return dev; 701 } 702 } 703 return NULL; 704 } 705 706 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 707 { 708 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 709 le32_to_cpus(&td->link); 710 le32_to_cpus(&td->ctrl); 711 le32_to_cpus(&td->token); 712 le32_to_cpus(&td->buffer); 713 } 714 715 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 716 int status, uint32_t *int_mask) 717 { 718 uint32_t queue_token = uhci_queue_token(td); 719 int ret; 720 721 switch (status) { 722 case USB_RET_NAK: 723 td->ctrl |= TD_CTRL_NAK; 724 return TD_RESULT_NEXT_QH; 725 726 case USB_RET_STALL: 727 td->ctrl |= TD_CTRL_STALL; 728 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 729 ret = TD_RESULT_NEXT_QH; 730 break; 731 732 case USB_RET_BABBLE: 733 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 734 /* frame interrupted */ 735 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 736 ret = TD_RESULT_STOP_FRAME; 737 break; 738 739 case USB_RET_IOERROR: 740 case USB_RET_NODEV: 741 default: 742 td->ctrl |= TD_CTRL_TIMEOUT; 743 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 744 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 745 ret = TD_RESULT_NEXT_QH; 746 break; 747 } 748 749 td->ctrl &= ~TD_CTRL_ACTIVE; 750 s->status |= UHCI_STS_USBERR; 751 if (td->ctrl & TD_CTRL_IOC) { 752 *int_mask |= 0x01; 753 } 754 uhci_update_irq(s); 755 return ret; 756 } 757 758 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 759 { 760 int len = 0, max_len; 761 uint8_t pid; 762 763 max_len = ((td->token >> 21) + 1) & 0x7ff; 764 pid = td->token & 0xff; 765 766 if (td->ctrl & TD_CTRL_IOS) 767 td->ctrl &= ~TD_CTRL_ACTIVE; 768 769 if (async->packet.status != USB_RET_SUCCESS) { 770 return uhci_handle_td_error(s, td, async->td_addr, 771 async->packet.status, int_mask); 772 } 773 774 len = async->packet.actual_length; 775 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 776 777 /* The NAK bit may have been set by a previous frame, so clear it 778 here. The docs are somewhat unclear, but win2k relies on this 779 behavior. */ 780 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 781 if (td->ctrl & TD_CTRL_IOC) 782 *int_mask |= 0x01; 783 784 if (pid == USB_TOKEN_IN) { 785 pci_dma_write(&s->dev, td->buffer, async->buf, len); 786 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 787 *int_mask |= 0x02; 788 /* short packet: do not update QH */ 789 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 790 async->td_addr); 791 return TD_RESULT_NEXT_QH; 792 } 793 } 794 795 /* success */ 796 trace_usb_uhci_packet_complete_success(async->queue->token, 797 async->td_addr); 798 return TD_RESULT_COMPLETE; 799 } 800 801 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 802 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 803 { 804 int ret, max_len; 805 bool spd; 806 bool queuing = (q != NULL); 807 uint8_t pid = td->token & 0xff; 808 UHCIAsync *async = uhci_async_find_td(s, td_addr); 809 810 if (async) { 811 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 812 assert(q == NULL || q == async->queue); 813 q = async->queue; 814 } else { 815 uhci_queue_free(async->queue, "guest re-used pending td"); 816 async = NULL; 817 } 818 } 819 820 if (q == NULL) { 821 q = uhci_queue_find(s, td); 822 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 823 uhci_queue_free(q, "guest re-used qh"); 824 q = NULL; 825 } 826 } 827 828 if (q) { 829 q->valid = QH_VALID; 830 } 831 832 /* Is active ? */ 833 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 834 if (async) { 835 /* Guest marked a pending td non-active, cancel the queue */ 836 uhci_queue_free(async->queue, "pending td non-active"); 837 } 838 /* 839 * ehci11d spec page 22: "Even if the Active bit in the TD is already 840 * cleared when the TD is fetched ... an IOC interrupt is generated" 841 */ 842 if (td->ctrl & TD_CTRL_IOC) { 843 *int_mask |= 0x01; 844 } 845 return TD_RESULT_NEXT_QH; 846 } 847 848 if (async) { 849 if (queuing) { 850 /* we are busy filling the queue, we are not prepared 851 to consume completed packages then, just leave them 852 in async state */ 853 return TD_RESULT_ASYNC_CONT; 854 } 855 if (!async->done) { 856 UHCI_TD last_td; 857 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 858 /* 859 * While we are waiting for the current td to complete, the guest 860 * may have added more tds to the queue. Note we re-read the td 861 * rather then caching it, as we want to see guest made changes! 862 */ 863 uhci_read_td(s, &last_td, last->td_addr); 864 uhci_queue_fill(async->queue, &last_td); 865 866 return TD_RESULT_ASYNC_CONT; 867 } 868 uhci_async_unlink(async); 869 goto done; 870 } 871 872 if (s->completions_only) { 873 return TD_RESULT_ASYNC_CONT; 874 } 875 876 /* Allocate new packet */ 877 if (q == NULL) { 878 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 879 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 880 881 if (ep == NULL) { 882 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 883 int_mask); 884 } 885 q = uhci_queue_new(s, qh_addr, td, ep); 886 } 887 async = uhci_async_alloc(q, td_addr); 888 889 max_len = ((td->token >> 21) + 1) & 0x7ff; 890 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 891 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 892 (td->ctrl & TD_CTRL_IOC) != 0); 893 if (max_len <= sizeof(async->static_buf)) { 894 async->buf = async->static_buf; 895 } else { 896 async->buf = g_malloc(max_len); 897 } 898 usb_packet_addbuf(&async->packet, async->buf, max_len); 899 900 switch(pid) { 901 case USB_TOKEN_OUT: 902 case USB_TOKEN_SETUP: 903 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 904 usb_handle_packet(q->ep->dev, &async->packet); 905 if (async->packet.status == USB_RET_SUCCESS) { 906 async->packet.actual_length = max_len; 907 } 908 break; 909 910 case USB_TOKEN_IN: 911 usb_handle_packet(q->ep->dev, &async->packet); 912 break; 913 914 default: 915 /* invalid pid : frame interrupted */ 916 uhci_async_free(async); 917 s->status |= UHCI_STS_HCPERR; 918 uhci_update_irq(s); 919 return TD_RESULT_STOP_FRAME; 920 } 921 922 if (async->packet.status == USB_RET_ASYNC) { 923 uhci_async_link(async); 924 if (!queuing) { 925 uhci_queue_fill(q, td); 926 } 927 return TD_RESULT_ASYNC_START; 928 } 929 930 done: 931 ret = uhci_complete_td(s, td, async, int_mask); 932 uhci_async_free(async); 933 return ret; 934 } 935 936 static void uhci_async_complete(USBPort *port, USBPacket *packet) 937 { 938 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 939 UHCIState *s = async->queue->uhci; 940 941 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 942 uhci_async_cancel(async); 943 return; 944 } 945 946 async->done = 1; 947 /* Force processing of this packet *now*, needed for migration */ 948 s->completions_only = true; 949 qemu_bh_schedule(s->bh); 950 } 951 952 static int is_valid(uint32_t link) 953 { 954 return (link & 1) == 0; 955 } 956 957 static int is_qh(uint32_t link) 958 { 959 return (link & 2) != 0; 960 } 961 962 static int depth_first(uint32_t link) 963 { 964 return (link & 4) != 0; 965 } 966 967 /* QH DB used for detecting QH loops */ 968 #define UHCI_MAX_QUEUES 128 969 typedef struct { 970 uint32_t addr[UHCI_MAX_QUEUES]; 971 int count; 972 } QhDb; 973 974 static void qhdb_reset(QhDb *db) 975 { 976 db->count = 0; 977 } 978 979 /* Add QH to DB. Returns 1 if already present or DB is full. */ 980 static int qhdb_insert(QhDb *db, uint32_t addr) 981 { 982 int i; 983 for (i = 0; i < db->count; i++) 984 if (db->addr[i] == addr) 985 return 1; 986 987 if (db->count >= UHCI_MAX_QUEUES) 988 return 1; 989 990 db->addr[db->count++] = addr; 991 return 0; 992 } 993 994 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 995 { 996 uint32_t int_mask = 0; 997 uint32_t plink = td->link; 998 UHCI_TD ptd; 999 int ret; 1000 1001 while (is_valid(plink)) { 1002 uhci_read_td(q->uhci, &ptd, plink); 1003 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 1004 break; 1005 } 1006 if (uhci_queue_token(&ptd) != q->token) { 1007 break; 1008 } 1009 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 1010 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 1011 if (ret == TD_RESULT_ASYNC_CONT) { 1012 break; 1013 } 1014 assert(ret == TD_RESULT_ASYNC_START); 1015 assert(int_mask == 0); 1016 plink = ptd.link; 1017 } 1018 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1019 } 1020 1021 static void uhci_process_frame(UHCIState *s) 1022 { 1023 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1024 uint32_t curr_qh, td_count = 0; 1025 int cnt, ret; 1026 UHCI_TD td; 1027 UHCI_QH qh; 1028 QhDb qhdb; 1029 1030 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1031 1032 pci_dma_read(&s->dev, frame_addr, &link, 4); 1033 le32_to_cpus(&link); 1034 1035 int_mask = 0; 1036 curr_qh = 0; 1037 1038 qhdb_reset(&qhdb); 1039 1040 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1041 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1042 /* We've reached the usb 1.1 bandwidth, which is 1043 1280 bytes/frame, stop processing */ 1044 trace_usb_uhci_frame_stop_bandwidth(); 1045 break; 1046 } 1047 if (is_qh(link)) { 1048 /* QH */ 1049 trace_usb_uhci_qh_load(link & ~0xf); 1050 1051 if (qhdb_insert(&qhdb, link)) { 1052 /* 1053 * We're going in circles. Which is not a bug because 1054 * HCD is allowed to do that as part of the BW management. 1055 * 1056 * Stop processing here if no transaction has been done 1057 * since we've been here last time. 1058 */ 1059 if (td_count == 0) { 1060 trace_usb_uhci_frame_loop_stop_idle(); 1061 break; 1062 } else { 1063 trace_usb_uhci_frame_loop_continue(); 1064 td_count = 0; 1065 qhdb_reset(&qhdb); 1066 qhdb_insert(&qhdb, link); 1067 } 1068 } 1069 1070 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1071 le32_to_cpus(&qh.link); 1072 le32_to_cpus(&qh.el_link); 1073 1074 if (!is_valid(qh.el_link)) { 1075 /* QH w/o elements */ 1076 curr_qh = 0; 1077 link = qh.link; 1078 } else { 1079 /* QH with elements */ 1080 curr_qh = link; 1081 link = qh.el_link; 1082 } 1083 continue; 1084 } 1085 1086 /* TD */ 1087 uhci_read_td(s, &td, link); 1088 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1089 1090 old_td_ctrl = td.ctrl; 1091 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1092 if (old_td_ctrl != td.ctrl) { 1093 /* update the status bits of the TD */ 1094 val = cpu_to_le32(td.ctrl); 1095 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1096 } 1097 1098 switch (ret) { 1099 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1100 goto out; 1101 1102 case TD_RESULT_NEXT_QH: 1103 case TD_RESULT_ASYNC_CONT: 1104 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1105 link = curr_qh ? qh.link : td.link; 1106 continue; 1107 1108 case TD_RESULT_ASYNC_START: 1109 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1110 link = curr_qh ? qh.link : td.link; 1111 continue; 1112 1113 case TD_RESULT_COMPLETE: 1114 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1115 link = td.link; 1116 td_count++; 1117 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1118 1119 if (curr_qh) { 1120 /* update QH element link */ 1121 qh.el_link = link; 1122 val = cpu_to_le32(qh.el_link); 1123 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1124 1125 if (!depth_first(link)) { 1126 /* done with this QH */ 1127 curr_qh = 0; 1128 link = qh.link; 1129 } 1130 } 1131 break; 1132 1133 default: 1134 assert(!"unknown return code"); 1135 } 1136 1137 /* go to the next entry */ 1138 } 1139 1140 out: 1141 s->pending_int_mask |= int_mask; 1142 } 1143 1144 static void uhci_bh(void *opaque) 1145 { 1146 UHCIState *s = opaque; 1147 uhci_process_frame(s); 1148 } 1149 1150 static void uhci_frame_timer(void *opaque) 1151 { 1152 UHCIState *s = opaque; 1153 uint64_t t_now, t_last_run; 1154 int i, frames; 1155 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1156 1157 s->completions_only = false; 1158 qemu_bh_cancel(s->bh); 1159 1160 if (!(s->cmd & UHCI_CMD_RS)) { 1161 /* Full stop */ 1162 trace_usb_uhci_schedule_stop(); 1163 timer_del(s->frame_timer); 1164 uhci_async_cancel_all(s); 1165 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1166 s->status |= UHCI_STS_HCHALTED; 1167 return; 1168 } 1169 1170 /* We still store expire_time in our state, for migration */ 1171 t_last_run = s->expire_time - frame_t; 1172 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1173 1174 /* Process up to MAX_FRAMES_PER_TICK frames */ 1175 frames = (t_now - t_last_run) / frame_t; 1176 if (frames > s->maxframes) { 1177 int skipped = frames - s->maxframes; 1178 s->expire_time += skipped * frame_t; 1179 s->frnum = (s->frnum + skipped) & 0x7ff; 1180 frames -= skipped; 1181 } 1182 if (frames > MAX_FRAMES_PER_TICK) { 1183 frames = MAX_FRAMES_PER_TICK; 1184 } 1185 1186 for (i = 0; i < frames; i++) { 1187 s->frame_bytes = 0; 1188 trace_usb_uhci_frame_start(s->frnum); 1189 uhci_async_validate_begin(s); 1190 uhci_process_frame(s); 1191 uhci_async_validate_end(s); 1192 /* The spec says frnum is the frame currently being processed, and 1193 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1194 s->frnum = (s->frnum + 1) & 0x7ff; 1195 s->expire_time += frame_t; 1196 } 1197 1198 /* Complete the previous frame(s) */ 1199 if (s->pending_int_mask) { 1200 s->status2 |= s->pending_int_mask; 1201 s->status |= UHCI_STS_USBINT; 1202 uhci_update_irq(s); 1203 } 1204 s->pending_int_mask = 0; 1205 1206 timer_mod(s->frame_timer, t_now + frame_t); 1207 } 1208 1209 static const MemoryRegionOps uhci_ioport_ops = { 1210 .read = uhci_port_read, 1211 .write = uhci_port_write, 1212 .valid.min_access_size = 1, 1213 .valid.max_access_size = 4, 1214 .impl.min_access_size = 2, 1215 .impl.max_access_size = 2, 1216 .endianness = DEVICE_LITTLE_ENDIAN, 1217 }; 1218 1219 static USBPortOps uhci_port_ops = { 1220 .attach = uhci_attach, 1221 .detach = uhci_detach, 1222 .child_detach = uhci_child_detach, 1223 .wakeup = uhci_wakeup, 1224 .complete = uhci_async_complete, 1225 }; 1226 1227 static USBBusOps uhci_bus_ops = { 1228 }; 1229 1230 static int usb_uhci_common_initfn(PCIDevice *dev) 1231 { 1232 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1233 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1234 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1235 uint8_t *pci_conf = s->dev.config; 1236 int i; 1237 1238 pci_conf[PCI_CLASS_PROG] = 0x00; 1239 /* TODO: reset value should be 0. */ 1240 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1241 1242 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1243 1244 if (s->masterbus) { 1245 USBPort *ports[NB_PORTS]; 1246 for(i = 0; i < NB_PORTS; i++) { 1247 ports[i] = &s->ports[i].port; 1248 } 1249 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1250 s->firstport, s, &uhci_port_ops, 1251 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1252 return -1; 1253 } 1254 } else { 1255 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1256 for (i = 0; i < NB_PORTS; i++) { 1257 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1258 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1259 } 1260 } 1261 s->bh = qemu_bh_new(uhci_bh, s); 1262 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1263 s->num_ports_vmstate = NB_PORTS; 1264 QTAILQ_INIT(&s->queues); 1265 1266 qemu_register_reset(uhci_reset, s); 1267 1268 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1269 "uhci", 0x20); 1270 1271 /* Use region 4 for consistency with real hardware. BSD guests seem 1272 to rely on this. */ 1273 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1274 1275 return 0; 1276 } 1277 1278 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1279 { 1280 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1281 uint8_t *pci_conf = s->dev.config; 1282 1283 /* USB misc control 1/2 */ 1284 pci_set_long(pci_conf + 0x40,0x00001000); 1285 /* PM capability */ 1286 pci_set_long(pci_conf + 0x80,0x00020001); 1287 /* USB legacy support */ 1288 pci_set_long(pci_conf + 0xc0,0x00002000); 1289 1290 return usb_uhci_common_initfn(dev); 1291 } 1292 1293 static void usb_uhci_exit(PCIDevice *dev) 1294 { 1295 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1296 1297 memory_region_destroy(&s->io_bar); 1298 } 1299 1300 static Property uhci_properties[] = { 1301 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1302 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1303 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1304 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1305 DEFINE_PROP_END_OF_LIST(), 1306 }; 1307 1308 static void uhci_class_init(ObjectClass *klass, void *data) 1309 { 1310 DeviceClass *dc = DEVICE_CLASS(klass); 1311 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1312 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1313 UHCIInfo *info = data; 1314 1315 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; 1316 k->exit = info->unplug ? usb_uhci_exit : NULL; 1317 k->vendor_id = info->vendor_id; 1318 k->device_id = info->device_id; 1319 k->revision = info->revision; 1320 k->class_id = PCI_CLASS_SERIAL_USB; 1321 k->no_hotplug = 1; 1322 dc->vmsd = &vmstate_uhci; 1323 dc->props = uhci_properties; 1324 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1325 u->info = *info; 1326 } 1327 1328 static UHCIInfo uhci_info[] = { 1329 { 1330 .name = "piix3-usb-uhci", 1331 .vendor_id = PCI_VENDOR_ID_INTEL, 1332 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1333 .revision = 0x01, 1334 .irq_pin = 3, 1335 .unplug = true, 1336 },{ 1337 .name = "piix4-usb-uhci", 1338 .vendor_id = PCI_VENDOR_ID_INTEL, 1339 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1340 .revision = 0x01, 1341 .irq_pin = 3, 1342 .unplug = true, 1343 },{ 1344 .name = "vt82c686b-usb-uhci", 1345 .vendor_id = PCI_VENDOR_ID_VIA, 1346 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1347 .revision = 0x01, 1348 .irq_pin = 3, 1349 .initfn = usb_uhci_vt82c686b_initfn, 1350 .unplug = true, 1351 },{ 1352 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1353 .vendor_id = PCI_VENDOR_ID_INTEL, 1354 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1355 .revision = 0x03, 1356 .irq_pin = 0, 1357 .unplug = false, 1358 },{ 1359 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1360 .vendor_id = PCI_VENDOR_ID_INTEL, 1361 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1362 .revision = 0x03, 1363 .irq_pin = 1, 1364 .unplug = false, 1365 },{ 1366 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1367 .vendor_id = PCI_VENDOR_ID_INTEL, 1368 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1369 .revision = 0x03, 1370 .irq_pin = 2, 1371 .unplug = false, 1372 },{ 1373 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1374 .vendor_id = PCI_VENDOR_ID_INTEL, 1375 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1376 .revision = 0x03, 1377 .irq_pin = 0, 1378 .unplug = false, 1379 },{ 1380 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1381 .vendor_id = PCI_VENDOR_ID_INTEL, 1382 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1383 .revision = 0x03, 1384 .irq_pin = 1, 1385 .unplug = false, 1386 },{ 1387 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1388 .vendor_id = PCI_VENDOR_ID_INTEL, 1389 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1390 .revision = 0x03, 1391 .irq_pin = 2, 1392 .unplug = false, 1393 } 1394 }; 1395 1396 static void uhci_register_types(void) 1397 { 1398 TypeInfo uhci_type_info = { 1399 .parent = TYPE_PCI_DEVICE, 1400 .instance_size = sizeof(UHCIState), 1401 .class_size = sizeof(UHCIPCIDeviceClass), 1402 .class_init = uhci_class_init, 1403 }; 1404 int i; 1405 1406 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1407 uhci_type_info.name = uhci_info[i].name; 1408 uhci_type_info.class_data = uhci_info + i; 1409 type_register(&uhci_type_info); 1410 } 1411 } 1412 1413 type_init(uhci_register_types) 1414