1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/usb.h" 31 #include "hw/usb/uhci-regs.h" 32 #include "migration/vmstate.h" 33 #include "hw/pci/pci.h" 34 #include "hw/irq.h" 35 #include "hw/qdev-properties.h" 36 #include "qapi/error.h" 37 #include "qemu/timer.h" 38 #include "qemu/iov.h" 39 #include "sysemu/dma.h" 40 #include "trace.h" 41 #include "qemu/main-loop.h" 42 #include "qemu/module.h" 43 #include "qom/object.h" 44 #include "hcd-uhci.h" 45 46 #define FRAME_TIMER_FREQ 1000 47 48 #define FRAME_MAX_LOOPS 256 49 50 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 51 #define QH_VALID 32 52 53 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 54 55 enum { 56 TD_RESULT_STOP_FRAME = 10, 57 TD_RESULT_COMPLETE, 58 TD_RESULT_NEXT_QH, 59 TD_RESULT_ASYNC_START, 60 TD_RESULT_ASYNC_CONT, 61 }; 62 63 typedef struct UHCIState UHCIState; 64 typedef struct UHCIAsync UHCIAsync; 65 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 66 67 struct UHCIPCIDeviceClass { 68 PCIDeviceClass parent_class; 69 UHCIInfo info; 70 }; 71 72 /* 73 * Pending async transaction. 74 * 'packet' must be the first field because completion 75 * handler does "(UHCIAsync *) pkt" cast. 76 */ 77 78 struct UHCIAsync { 79 USBPacket packet; 80 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 81 uint8_t *buf; 82 UHCIQueue *queue; 83 QTAILQ_ENTRY(UHCIAsync) next; 84 uint32_t td_addr; 85 uint8_t done; 86 }; 87 88 struct UHCIQueue { 89 uint32_t qh_addr; 90 uint32_t token; 91 UHCIState *uhci; 92 USBEndpoint *ep; 93 QTAILQ_ENTRY(UHCIQueue) next; 94 QTAILQ_HEAD(, UHCIAsync) asyncs; 95 int8_t valid; 96 }; 97 98 typedef struct UHCI_TD { 99 uint32_t link; 100 uint32_t ctrl; /* see TD_CTRL_xxx */ 101 uint32_t token; 102 uint32_t buffer; 103 } UHCI_TD; 104 105 typedef struct UHCI_QH { 106 uint32_t link; 107 uint32_t el_link; 108 } UHCI_QH; 109 110 static void uhci_async_cancel(UHCIAsync *async); 111 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 112 static void uhci_resume(void *opaque); 113 114 static inline int32_t uhci_queue_token(UHCI_TD *td) 115 { 116 if ((td->token & (0xf << 15)) == 0) { 117 /* ctrl ep, cover ep and dev, not pid! */ 118 return td->token & 0x7ff00; 119 } else { 120 /* covers ep, dev, pid -> identifies the endpoint */ 121 return td->token & 0x7ffff; 122 } 123 } 124 125 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 126 USBEndpoint *ep) 127 { 128 UHCIQueue *queue; 129 130 queue = g_new0(UHCIQueue, 1); 131 queue->uhci = s; 132 queue->qh_addr = qh_addr; 133 queue->token = uhci_queue_token(td); 134 queue->ep = ep; 135 QTAILQ_INIT(&queue->asyncs); 136 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 137 queue->valid = QH_VALID; 138 trace_usb_uhci_queue_add(queue->token); 139 return queue; 140 } 141 142 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 143 { 144 UHCIState *s = queue->uhci; 145 UHCIAsync *async; 146 147 while (!QTAILQ_EMPTY(&queue->asyncs)) { 148 async = QTAILQ_FIRST(&queue->asyncs); 149 uhci_async_cancel(async); 150 } 151 usb_device_ep_stopped(queue->ep->dev, queue->ep); 152 153 trace_usb_uhci_queue_del(queue->token, reason); 154 QTAILQ_REMOVE(&s->queues, queue, next); 155 g_free(queue); 156 } 157 158 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 159 { 160 uint32_t token = uhci_queue_token(td); 161 UHCIQueue *queue; 162 163 QTAILQ_FOREACH(queue, &s->queues, next) { 164 if (queue->token == token) { 165 return queue; 166 } 167 } 168 return NULL; 169 } 170 171 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 172 uint32_t td_addr, bool queuing) 173 { 174 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 175 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 176 177 return queue->qh_addr == qh_addr && 178 queue->token == uhci_queue_token(td) && 179 queue_token_addr == queue->ep->dev->addr && 180 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 181 first->td_addr == td_addr); 182 } 183 184 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 185 { 186 UHCIAsync *async = g_new0(UHCIAsync, 1); 187 188 async->queue = queue; 189 async->td_addr = td_addr; 190 usb_packet_init(&async->packet); 191 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 192 193 return async; 194 } 195 196 static void uhci_async_free(UHCIAsync *async) 197 { 198 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 199 usb_packet_cleanup(&async->packet); 200 if (async->buf != async->static_buf) { 201 g_free(async->buf); 202 } 203 g_free(async); 204 } 205 206 static void uhci_async_link(UHCIAsync *async) 207 { 208 UHCIQueue *queue = async->queue; 209 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 210 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 211 } 212 213 static void uhci_async_unlink(UHCIAsync *async) 214 { 215 UHCIQueue *queue = async->queue; 216 QTAILQ_REMOVE(&queue->asyncs, async, next); 217 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 218 } 219 220 static void uhci_async_cancel(UHCIAsync *async) 221 { 222 uhci_async_unlink(async); 223 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 224 async->done); 225 if (!async->done) 226 usb_cancel_packet(&async->packet); 227 uhci_async_free(async); 228 } 229 230 /* 231 * Mark all outstanding async packets as invalid. 232 * This is used for canceling them when TDs are removed by the HCD. 233 */ 234 static void uhci_async_validate_begin(UHCIState *s) 235 { 236 UHCIQueue *queue; 237 238 QTAILQ_FOREACH(queue, &s->queues, next) { 239 queue->valid--; 240 } 241 } 242 243 /* 244 * Cancel async packets that are no longer valid 245 */ 246 static void uhci_async_validate_end(UHCIState *s) 247 { 248 UHCIQueue *queue, *n; 249 250 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 251 if (!queue->valid) { 252 uhci_queue_free(queue, "validate-end"); 253 } 254 } 255 } 256 257 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 258 { 259 UHCIQueue *queue, *n; 260 261 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 262 if (queue->ep->dev == dev) { 263 uhci_queue_free(queue, "cancel-device"); 264 } 265 } 266 } 267 268 static void uhci_async_cancel_all(UHCIState *s) 269 { 270 UHCIQueue *queue, *nq; 271 272 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 273 uhci_queue_free(queue, "cancel-all"); 274 } 275 } 276 277 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 278 { 279 UHCIQueue *queue; 280 UHCIAsync *async; 281 282 QTAILQ_FOREACH(queue, &s->queues, next) { 283 QTAILQ_FOREACH(async, &queue->asyncs, next) { 284 if (async->td_addr == td_addr) { 285 return async; 286 } 287 } 288 } 289 return NULL; 290 } 291 292 static void uhci_update_irq(UHCIState *s) 293 { 294 int level = 0; 295 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 296 ((s->status2 & 2) && (s->intr & (1 << 3))) || 297 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 298 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 299 (s->status & UHCI_STS_HSERR) || 300 (s->status & UHCI_STS_HCPERR)) { 301 level = 1; 302 } 303 qemu_set_irq(s->irq, level); 304 } 305 306 static void uhci_reset(DeviceState *dev) 307 { 308 PCIDevice *d = PCI_DEVICE(dev); 309 UHCIState *s = UHCI(d); 310 uint8_t *pci_conf; 311 int i; 312 UHCIPort *port; 313 314 trace_usb_uhci_reset(); 315 316 pci_conf = s->dev.config; 317 318 pci_conf[0x6a] = 0x01; /* usb clock */ 319 pci_conf[0x6b] = 0x00; 320 s->cmd = 0; 321 s->status = UHCI_STS_HCHALTED; 322 s->status2 = 0; 323 s->intr = 0; 324 s->fl_base_addr = 0; 325 s->sof_timing = 64; 326 327 for(i = 0; i < NB_PORTS; i++) { 328 port = &s->ports[i]; 329 port->ctrl = 0x0080; 330 if (port->port.dev && port->port.dev->attached) { 331 usb_port_reset(&port->port); 332 } 333 } 334 335 uhci_async_cancel_all(s); 336 qemu_bh_cancel(s->bh); 337 uhci_update_irq(s); 338 } 339 340 static const VMStateDescription vmstate_uhci_port = { 341 .name = "uhci port", 342 .version_id = 1, 343 .minimum_version_id = 1, 344 .fields = (VMStateField[]) { 345 VMSTATE_UINT16(ctrl, UHCIPort), 346 VMSTATE_END_OF_LIST() 347 } 348 }; 349 350 static int uhci_post_load(void *opaque, int version_id) 351 { 352 UHCIState *s = opaque; 353 354 if (version_id < 2) { 355 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 356 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 357 } 358 return 0; 359 } 360 361 static const VMStateDescription vmstate_uhci = { 362 .name = "uhci", 363 .version_id = 3, 364 .minimum_version_id = 1, 365 .post_load = uhci_post_load, 366 .fields = (VMStateField[]) { 367 VMSTATE_PCI_DEVICE(dev, UHCIState), 368 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 369 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 370 vmstate_uhci_port, UHCIPort), 371 VMSTATE_UINT16(cmd, UHCIState), 372 VMSTATE_UINT16(status, UHCIState), 373 VMSTATE_UINT16(intr, UHCIState), 374 VMSTATE_UINT16(frnum, UHCIState), 375 VMSTATE_UINT32(fl_base_addr, UHCIState), 376 VMSTATE_UINT8(sof_timing, UHCIState), 377 VMSTATE_UINT8(status2, UHCIState), 378 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 379 VMSTATE_INT64_V(expire_time, UHCIState, 2), 380 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 381 VMSTATE_END_OF_LIST() 382 } 383 }; 384 385 static void uhci_port_write(void *opaque, hwaddr addr, 386 uint64_t val, unsigned size) 387 { 388 UHCIState *s = opaque; 389 390 trace_usb_uhci_mmio_writew(addr, val); 391 392 switch(addr) { 393 case 0x00: 394 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 395 /* start frame processing */ 396 trace_usb_uhci_schedule_start(); 397 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 398 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 399 timer_mod(s->frame_timer, s->expire_time); 400 s->status &= ~UHCI_STS_HCHALTED; 401 } else if (!(val & UHCI_CMD_RS)) { 402 s->status |= UHCI_STS_HCHALTED; 403 } 404 if (val & UHCI_CMD_GRESET) { 405 UHCIPort *port; 406 int i; 407 408 /* send reset on the USB bus */ 409 for(i = 0; i < NB_PORTS; i++) { 410 port = &s->ports[i]; 411 usb_device_reset(port->port.dev); 412 } 413 uhci_reset(DEVICE(s)); 414 return; 415 } 416 if (val & UHCI_CMD_HCRESET) { 417 uhci_reset(DEVICE(s)); 418 return; 419 } 420 s->cmd = val; 421 if (val & UHCI_CMD_EGSM) { 422 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 423 (s->ports[1].ctrl & UHCI_PORT_RD)) { 424 uhci_resume(s); 425 } 426 } 427 break; 428 case 0x02: 429 s->status &= ~val; 430 /* XXX: the chip spec is not coherent, so we add a hidden 431 register to distinguish between IOC and SPD */ 432 if (val & UHCI_STS_USBINT) 433 s->status2 = 0; 434 uhci_update_irq(s); 435 break; 436 case 0x04: 437 s->intr = val; 438 uhci_update_irq(s); 439 break; 440 case 0x06: 441 if (s->status & UHCI_STS_HCHALTED) 442 s->frnum = val & 0x7ff; 443 break; 444 case 0x08: 445 s->fl_base_addr &= 0xffff0000; 446 s->fl_base_addr |= val & ~0xfff; 447 break; 448 case 0x0a: 449 s->fl_base_addr &= 0x0000ffff; 450 s->fl_base_addr |= (val << 16); 451 break; 452 case 0x0c: 453 s->sof_timing = val & 0xff; 454 break; 455 case 0x10 ... 0x1f: 456 { 457 UHCIPort *port; 458 USBDevice *dev; 459 int n; 460 461 n = (addr >> 1) & 7; 462 if (n >= NB_PORTS) 463 return; 464 port = &s->ports[n]; 465 dev = port->port.dev; 466 if (dev && dev->attached) { 467 /* port reset */ 468 if ( (val & UHCI_PORT_RESET) && 469 !(port->ctrl & UHCI_PORT_RESET) ) { 470 usb_device_reset(dev); 471 } 472 } 473 port->ctrl &= UHCI_PORT_READ_ONLY; 474 /* enabled may only be set if a device is connected */ 475 if (!(port->ctrl & UHCI_PORT_CCS)) { 476 val &= ~UHCI_PORT_EN; 477 } 478 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 479 /* some bits are reset when a '1' is written to them */ 480 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 481 } 482 break; 483 } 484 } 485 486 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 487 { 488 UHCIState *s = opaque; 489 uint32_t val; 490 491 switch(addr) { 492 case 0x00: 493 val = s->cmd; 494 break; 495 case 0x02: 496 val = s->status; 497 break; 498 case 0x04: 499 val = s->intr; 500 break; 501 case 0x06: 502 val = s->frnum; 503 break; 504 case 0x08: 505 val = s->fl_base_addr & 0xffff; 506 break; 507 case 0x0a: 508 val = (s->fl_base_addr >> 16) & 0xffff; 509 break; 510 case 0x0c: 511 val = s->sof_timing; 512 break; 513 case 0x10 ... 0x1f: 514 { 515 UHCIPort *port; 516 int n; 517 n = (addr >> 1) & 7; 518 if (n >= NB_PORTS) 519 goto read_default; 520 port = &s->ports[n]; 521 val = port->ctrl; 522 } 523 break; 524 default: 525 read_default: 526 val = 0xff7f; /* disabled port */ 527 break; 528 } 529 530 trace_usb_uhci_mmio_readw(addr, val); 531 532 return val; 533 } 534 535 /* signal resume if controller suspended */ 536 static void uhci_resume (void *opaque) 537 { 538 UHCIState *s = (UHCIState *)opaque; 539 540 if (!s) 541 return; 542 543 if (s->cmd & UHCI_CMD_EGSM) { 544 s->cmd |= UHCI_CMD_FGR; 545 s->status |= UHCI_STS_RD; 546 uhci_update_irq(s); 547 } 548 } 549 550 static void uhci_attach(USBPort *port1) 551 { 552 UHCIState *s = port1->opaque; 553 UHCIPort *port = &s->ports[port1->index]; 554 555 /* set connect status */ 556 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 557 558 /* update speed */ 559 if (port->port.dev->speed == USB_SPEED_LOW) { 560 port->ctrl |= UHCI_PORT_LSDA; 561 } else { 562 port->ctrl &= ~UHCI_PORT_LSDA; 563 } 564 565 uhci_resume(s); 566 } 567 568 static void uhci_detach(USBPort *port1) 569 { 570 UHCIState *s = port1->opaque; 571 UHCIPort *port = &s->ports[port1->index]; 572 573 uhci_async_cancel_device(s, port1->dev); 574 575 /* set connect status */ 576 if (port->ctrl & UHCI_PORT_CCS) { 577 port->ctrl &= ~UHCI_PORT_CCS; 578 port->ctrl |= UHCI_PORT_CSC; 579 } 580 /* disable port */ 581 if (port->ctrl & UHCI_PORT_EN) { 582 port->ctrl &= ~UHCI_PORT_EN; 583 port->ctrl |= UHCI_PORT_ENC; 584 } 585 586 uhci_resume(s); 587 } 588 589 static void uhci_child_detach(USBPort *port1, USBDevice *child) 590 { 591 UHCIState *s = port1->opaque; 592 593 uhci_async_cancel_device(s, child); 594 } 595 596 static void uhci_wakeup(USBPort *port1) 597 { 598 UHCIState *s = port1->opaque; 599 UHCIPort *port = &s->ports[port1->index]; 600 601 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 602 port->ctrl |= UHCI_PORT_RD; 603 uhci_resume(s); 604 } 605 } 606 607 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 608 { 609 USBDevice *dev; 610 int i; 611 612 for (i = 0; i < NB_PORTS; i++) { 613 UHCIPort *port = &s->ports[i]; 614 if (!(port->ctrl & UHCI_PORT_EN)) { 615 continue; 616 } 617 dev = usb_find_device(&port->port, addr); 618 if (dev != NULL) { 619 return dev; 620 } 621 } 622 return NULL; 623 } 624 625 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 626 { 627 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 628 le32_to_cpus(&td->link); 629 le32_to_cpus(&td->ctrl); 630 le32_to_cpus(&td->token); 631 le32_to_cpus(&td->buffer); 632 } 633 634 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 635 int status, uint32_t *int_mask) 636 { 637 uint32_t queue_token = uhci_queue_token(td); 638 int ret; 639 640 switch (status) { 641 case USB_RET_NAK: 642 td->ctrl |= TD_CTRL_NAK; 643 return TD_RESULT_NEXT_QH; 644 645 case USB_RET_STALL: 646 td->ctrl |= TD_CTRL_STALL; 647 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 648 ret = TD_RESULT_NEXT_QH; 649 break; 650 651 case USB_RET_BABBLE: 652 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 653 /* frame interrupted */ 654 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 655 ret = TD_RESULT_STOP_FRAME; 656 break; 657 658 case USB_RET_IOERROR: 659 case USB_RET_NODEV: 660 default: 661 td->ctrl |= TD_CTRL_TIMEOUT; 662 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 663 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 664 ret = TD_RESULT_NEXT_QH; 665 break; 666 } 667 668 td->ctrl &= ~TD_CTRL_ACTIVE; 669 s->status |= UHCI_STS_USBERR; 670 if (td->ctrl & TD_CTRL_IOC) { 671 *int_mask |= 0x01; 672 } 673 uhci_update_irq(s); 674 return ret; 675 } 676 677 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 678 { 679 int len = 0, max_len; 680 uint8_t pid; 681 682 max_len = ((td->token >> 21) + 1) & 0x7ff; 683 pid = td->token & 0xff; 684 685 if (td->ctrl & TD_CTRL_IOS) 686 td->ctrl &= ~TD_CTRL_ACTIVE; 687 688 if (async->packet.status != USB_RET_SUCCESS) { 689 return uhci_handle_td_error(s, td, async->td_addr, 690 async->packet.status, int_mask); 691 } 692 693 len = async->packet.actual_length; 694 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 695 696 /* The NAK bit may have been set by a previous frame, so clear it 697 here. The docs are somewhat unclear, but win2k relies on this 698 behavior. */ 699 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 700 if (td->ctrl & TD_CTRL_IOC) 701 *int_mask |= 0x01; 702 703 if (pid == USB_TOKEN_IN) { 704 pci_dma_write(&s->dev, td->buffer, async->buf, len); 705 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 706 *int_mask |= 0x02; 707 /* short packet: do not update QH */ 708 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 709 async->td_addr); 710 return TD_RESULT_NEXT_QH; 711 } 712 } 713 714 /* success */ 715 trace_usb_uhci_packet_complete_success(async->queue->token, 716 async->td_addr); 717 return TD_RESULT_COMPLETE; 718 } 719 720 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 721 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 722 { 723 int ret, max_len; 724 bool spd; 725 bool queuing = (q != NULL); 726 uint8_t pid = td->token & 0xff; 727 UHCIAsync *async; 728 729 async = uhci_async_find_td(s, td_addr); 730 if (async) { 731 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 732 assert(q == NULL || q == async->queue); 733 q = async->queue; 734 } else { 735 uhci_queue_free(async->queue, "guest re-used pending td"); 736 async = NULL; 737 } 738 } 739 740 if (q == NULL) { 741 q = uhci_queue_find(s, td); 742 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 743 uhci_queue_free(q, "guest re-used qh"); 744 q = NULL; 745 } 746 } 747 748 if (q) { 749 q->valid = QH_VALID; 750 } 751 752 /* Is active ? */ 753 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 754 if (async) { 755 /* Guest marked a pending td non-active, cancel the queue */ 756 uhci_queue_free(async->queue, "pending td non-active"); 757 } 758 /* 759 * ehci11d spec page 22: "Even if the Active bit in the TD is already 760 * cleared when the TD is fetched ... an IOC interrupt is generated" 761 */ 762 if (td->ctrl & TD_CTRL_IOC) { 763 *int_mask |= 0x01; 764 } 765 return TD_RESULT_NEXT_QH; 766 } 767 768 switch (pid) { 769 case USB_TOKEN_OUT: 770 case USB_TOKEN_SETUP: 771 case USB_TOKEN_IN: 772 break; 773 default: 774 /* invalid pid : frame interrupted */ 775 s->status |= UHCI_STS_HCPERR; 776 s->cmd &= ~UHCI_CMD_RS; 777 uhci_update_irq(s); 778 return TD_RESULT_STOP_FRAME; 779 } 780 781 if (async) { 782 if (queuing) { 783 /* we are busy filling the queue, we are not prepared 784 to consume completed packages then, just leave them 785 in async state */ 786 return TD_RESULT_ASYNC_CONT; 787 } 788 if (!async->done) { 789 UHCI_TD last_td; 790 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); 791 /* 792 * While we are waiting for the current td to complete, the guest 793 * may have added more tds to the queue. Note we re-read the td 794 * rather then caching it, as we want to see guest made changes! 795 */ 796 uhci_read_td(s, &last_td, last->td_addr); 797 uhci_queue_fill(async->queue, &last_td); 798 799 return TD_RESULT_ASYNC_CONT; 800 } 801 uhci_async_unlink(async); 802 goto done; 803 } 804 805 if (s->completions_only) { 806 return TD_RESULT_ASYNC_CONT; 807 } 808 809 /* Allocate new packet */ 810 if (q == NULL) { 811 USBDevice *dev; 812 USBEndpoint *ep; 813 814 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 815 if (dev == NULL) { 816 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 817 int_mask); 818 } 819 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 820 q = uhci_queue_new(s, qh_addr, td, ep); 821 } 822 async = uhci_async_alloc(q, td_addr); 823 824 max_len = ((td->token >> 21) + 1) & 0x7ff; 825 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 826 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 827 (td->ctrl & TD_CTRL_IOC) != 0); 828 if (max_len <= sizeof(async->static_buf)) { 829 async->buf = async->static_buf; 830 } else { 831 async->buf = g_malloc(max_len); 832 } 833 usb_packet_addbuf(&async->packet, async->buf, max_len); 834 835 switch(pid) { 836 case USB_TOKEN_OUT: 837 case USB_TOKEN_SETUP: 838 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 839 usb_handle_packet(q->ep->dev, &async->packet); 840 if (async->packet.status == USB_RET_SUCCESS) { 841 async->packet.actual_length = max_len; 842 } 843 break; 844 845 case USB_TOKEN_IN: 846 usb_handle_packet(q->ep->dev, &async->packet); 847 break; 848 849 default: 850 abort(); /* Never to execute */ 851 } 852 853 if (async->packet.status == USB_RET_ASYNC) { 854 uhci_async_link(async); 855 if (!queuing) { 856 uhci_queue_fill(q, td); 857 } 858 return TD_RESULT_ASYNC_START; 859 } 860 861 done: 862 ret = uhci_complete_td(s, td, async, int_mask); 863 uhci_async_free(async); 864 return ret; 865 } 866 867 static void uhci_async_complete(USBPort *port, USBPacket *packet) 868 { 869 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 870 UHCIState *s = async->queue->uhci; 871 872 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 873 uhci_async_cancel(async); 874 return; 875 } 876 877 async->done = 1; 878 /* Force processing of this packet *now*, needed for migration */ 879 s->completions_only = true; 880 qemu_bh_schedule(s->bh); 881 } 882 883 static int is_valid(uint32_t link) 884 { 885 return (link & 1) == 0; 886 } 887 888 static int is_qh(uint32_t link) 889 { 890 return (link & 2) != 0; 891 } 892 893 static int depth_first(uint32_t link) 894 { 895 return (link & 4) != 0; 896 } 897 898 /* QH DB used for detecting QH loops */ 899 #define UHCI_MAX_QUEUES 128 900 typedef struct { 901 uint32_t addr[UHCI_MAX_QUEUES]; 902 int count; 903 } QhDb; 904 905 static void qhdb_reset(QhDb *db) 906 { 907 db->count = 0; 908 } 909 910 /* Add QH to DB. Returns 1 if already present or DB is full. */ 911 static int qhdb_insert(QhDb *db, uint32_t addr) 912 { 913 int i; 914 for (i = 0; i < db->count; i++) 915 if (db->addr[i] == addr) 916 return 1; 917 918 if (db->count >= UHCI_MAX_QUEUES) 919 return 1; 920 921 db->addr[db->count++] = addr; 922 return 0; 923 } 924 925 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 926 { 927 uint32_t int_mask = 0; 928 uint32_t plink = td->link; 929 UHCI_TD ptd; 930 int ret; 931 932 while (is_valid(plink)) { 933 uhci_read_td(q->uhci, &ptd, plink); 934 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 935 break; 936 } 937 if (uhci_queue_token(&ptd) != q->token) { 938 break; 939 } 940 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 941 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 942 if (ret == TD_RESULT_ASYNC_CONT) { 943 break; 944 } 945 assert(ret == TD_RESULT_ASYNC_START); 946 assert(int_mask == 0); 947 plink = ptd.link; 948 } 949 usb_device_flush_ep_queue(q->ep->dev, q->ep); 950 } 951 952 static void uhci_process_frame(UHCIState *s) 953 { 954 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 955 uint32_t curr_qh, td_count = 0; 956 int cnt, ret; 957 UHCI_TD td; 958 UHCI_QH qh; 959 QhDb qhdb; 960 961 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 962 963 pci_dma_read(&s->dev, frame_addr, &link, 4); 964 le32_to_cpus(&link); 965 966 int_mask = 0; 967 curr_qh = 0; 968 969 qhdb_reset(&qhdb); 970 971 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 972 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 973 /* We've reached the usb 1.1 bandwidth, which is 974 1280 bytes/frame, stop processing */ 975 trace_usb_uhci_frame_stop_bandwidth(); 976 break; 977 } 978 if (is_qh(link)) { 979 /* QH */ 980 trace_usb_uhci_qh_load(link & ~0xf); 981 982 if (qhdb_insert(&qhdb, link)) { 983 /* 984 * We're going in circles. Which is not a bug because 985 * HCD is allowed to do that as part of the BW management. 986 * 987 * Stop processing here if no transaction has been done 988 * since we've been here last time. 989 */ 990 if (td_count == 0) { 991 trace_usb_uhci_frame_loop_stop_idle(); 992 break; 993 } else { 994 trace_usb_uhci_frame_loop_continue(); 995 td_count = 0; 996 qhdb_reset(&qhdb); 997 qhdb_insert(&qhdb, link); 998 } 999 } 1000 1001 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1002 le32_to_cpus(&qh.link); 1003 le32_to_cpus(&qh.el_link); 1004 1005 if (!is_valid(qh.el_link)) { 1006 /* QH w/o elements */ 1007 curr_qh = 0; 1008 link = qh.link; 1009 } else { 1010 /* QH with elements */ 1011 curr_qh = link; 1012 link = qh.el_link; 1013 } 1014 continue; 1015 } 1016 1017 /* TD */ 1018 uhci_read_td(s, &td, link); 1019 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1020 1021 old_td_ctrl = td.ctrl; 1022 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1023 if (old_td_ctrl != td.ctrl) { 1024 /* update the status bits of the TD */ 1025 val = cpu_to_le32(td.ctrl); 1026 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1027 } 1028 1029 switch (ret) { 1030 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1031 goto out; 1032 1033 case TD_RESULT_NEXT_QH: 1034 case TD_RESULT_ASYNC_CONT: 1035 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1036 link = curr_qh ? qh.link : td.link; 1037 continue; 1038 1039 case TD_RESULT_ASYNC_START: 1040 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1041 link = curr_qh ? qh.link : td.link; 1042 continue; 1043 1044 case TD_RESULT_COMPLETE: 1045 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1046 link = td.link; 1047 td_count++; 1048 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1049 1050 if (curr_qh) { 1051 /* update QH element link */ 1052 qh.el_link = link; 1053 val = cpu_to_le32(qh.el_link); 1054 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1055 1056 if (!depth_first(link)) { 1057 /* done with this QH */ 1058 curr_qh = 0; 1059 link = qh.link; 1060 } 1061 } 1062 break; 1063 1064 default: 1065 assert(!"unknown return code"); 1066 } 1067 1068 /* go to the next entry */ 1069 } 1070 1071 out: 1072 s->pending_int_mask |= int_mask; 1073 } 1074 1075 static void uhci_bh(void *opaque) 1076 { 1077 UHCIState *s = opaque; 1078 uhci_process_frame(s); 1079 } 1080 1081 static void uhci_frame_timer(void *opaque) 1082 { 1083 UHCIState *s = opaque; 1084 uint64_t t_now, t_last_run; 1085 int i, frames; 1086 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1087 1088 s->completions_only = false; 1089 qemu_bh_cancel(s->bh); 1090 1091 if (!(s->cmd & UHCI_CMD_RS)) { 1092 /* Full stop */ 1093 trace_usb_uhci_schedule_stop(); 1094 timer_del(s->frame_timer); 1095 uhci_async_cancel_all(s); 1096 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1097 s->status |= UHCI_STS_HCHALTED; 1098 return; 1099 } 1100 1101 /* We still store expire_time in our state, for migration */ 1102 t_last_run = s->expire_time - frame_t; 1103 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1104 1105 /* Process up to MAX_FRAMES_PER_TICK frames */ 1106 frames = (t_now - t_last_run) / frame_t; 1107 if (frames > s->maxframes) { 1108 int skipped = frames - s->maxframes; 1109 s->expire_time += skipped * frame_t; 1110 s->frnum = (s->frnum + skipped) & 0x7ff; 1111 frames -= skipped; 1112 } 1113 if (frames > MAX_FRAMES_PER_TICK) { 1114 frames = MAX_FRAMES_PER_TICK; 1115 } 1116 1117 for (i = 0; i < frames; i++) { 1118 s->frame_bytes = 0; 1119 trace_usb_uhci_frame_start(s->frnum); 1120 uhci_async_validate_begin(s); 1121 uhci_process_frame(s); 1122 uhci_async_validate_end(s); 1123 /* The spec says frnum is the frame currently being processed, and 1124 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1125 s->frnum = (s->frnum + 1) & 0x7ff; 1126 s->expire_time += frame_t; 1127 } 1128 1129 /* Complete the previous frame(s) */ 1130 if (s->pending_int_mask) { 1131 s->status2 |= s->pending_int_mask; 1132 s->status |= UHCI_STS_USBINT; 1133 uhci_update_irq(s); 1134 } 1135 s->pending_int_mask = 0; 1136 1137 timer_mod(s->frame_timer, t_now + frame_t); 1138 } 1139 1140 static const MemoryRegionOps uhci_ioport_ops = { 1141 .read = uhci_port_read, 1142 .write = uhci_port_write, 1143 .valid.min_access_size = 1, 1144 .valid.max_access_size = 4, 1145 .impl.min_access_size = 2, 1146 .impl.max_access_size = 2, 1147 .endianness = DEVICE_LITTLE_ENDIAN, 1148 }; 1149 1150 static USBPortOps uhci_port_ops = { 1151 .attach = uhci_attach, 1152 .detach = uhci_detach, 1153 .child_detach = uhci_child_detach, 1154 .wakeup = uhci_wakeup, 1155 .complete = uhci_async_complete, 1156 }; 1157 1158 static USBBusOps uhci_bus_ops = { 1159 }; 1160 1161 void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1162 { 1163 Error *err = NULL; 1164 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1165 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1166 UHCIState *s = UHCI(dev); 1167 uint8_t *pci_conf = s->dev.config; 1168 int i; 1169 1170 pci_conf[PCI_CLASS_PROG] = 0x00; 1171 /* TODO: reset value should be 0. */ 1172 pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */ 1173 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1174 s->irq = pci_allocate_irq(dev); 1175 1176 if (s->masterbus) { 1177 USBPort *ports[NB_PORTS]; 1178 for(i = 0; i < NB_PORTS; i++) { 1179 ports[i] = &s->ports[i].port; 1180 } 1181 usb_register_companion(s->masterbus, ports, NB_PORTS, 1182 s->firstport, s, &uhci_port_ops, 1183 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1184 &err); 1185 if (err) { 1186 error_propagate(errp, err); 1187 return; 1188 } 1189 } else { 1190 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1191 for (i = 0; i < NB_PORTS; i++) { 1192 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1193 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1194 } 1195 } 1196 s->bh = qemu_bh_new(uhci_bh, s); 1197 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1198 s->num_ports_vmstate = NB_PORTS; 1199 QTAILQ_INIT(&s->queues); 1200 1201 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1202 "uhci", 0x20); 1203 1204 /* Use region 4 for consistency with real hardware. BSD guests seem 1205 to rely on this. */ 1206 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1207 } 1208 1209 static void usb_uhci_exit(PCIDevice *dev) 1210 { 1211 UHCIState *s = UHCI(dev); 1212 1213 trace_usb_uhci_exit(); 1214 1215 if (s->frame_timer) { 1216 timer_free(s->frame_timer); 1217 s->frame_timer = NULL; 1218 } 1219 1220 if (s->bh) { 1221 qemu_bh_delete(s->bh); 1222 } 1223 1224 uhci_async_cancel_all(s); 1225 1226 if (!s->masterbus) { 1227 usb_bus_release(&s->bus); 1228 } 1229 } 1230 1231 static Property uhci_properties_companion[] = { 1232 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1233 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1234 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1235 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1236 DEFINE_PROP_END_OF_LIST(), 1237 }; 1238 static Property uhci_properties_standalone[] = { 1239 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1240 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1241 DEFINE_PROP_END_OF_LIST(), 1242 }; 1243 1244 static void uhci_class_init(ObjectClass *klass, void *data) 1245 { 1246 DeviceClass *dc = DEVICE_CLASS(klass); 1247 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1248 1249 k->class_id = PCI_CLASS_SERIAL_USB; 1250 dc->vmsd = &vmstate_uhci; 1251 dc->reset = uhci_reset; 1252 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1253 } 1254 1255 static const TypeInfo uhci_pci_type_info = { 1256 .name = TYPE_UHCI, 1257 .parent = TYPE_PCI_DEVICE, 1258 .instance_size = sizeof(UHCIState), 1259 .class_size = sizeof(UHCIPCIDeviceClass), 1260 .abstract = true, 1261 .class_init = uhci_class_init, 1262 .interfaces = (InterfaceInfo[]) { 1263 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1264 { }, 1265 }, 1266 }; 1267 1268 void uhci_data_class_init(ObjectClass *klass, void *data) 1269 { 1270 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1271 DeviceClass *dc = DEVICE_CLASS(klass); 1272 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1273 UHCIInfo *info = data; 1274 1275 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1276 k->exit = info->unplug ? usb_uhci_exit : NULL; 1277 k->vendor_id = info->vendor_id; 1278 k->device_id = info->device_id; 1279 k->revision = info->revision; 1280 if (!info->unplug) { 1281 /* uhci controllers in companion setups can't be hotplugged */ 1282 dc->hotpluggable = false; 1283 device_class_set_props(dc, uhci_properties_companion); 1284 } else { 1285 device_class_set_props(dc, uhci_properties_standalone); 1286 } 1287 if (info->notuser) { 1288 dc->user_creatable = false; 1289 } 1290 u->info = *info; 1291 } 1292 1293 static UHCIInfo uhci_info[] = { 1294 { 1295 .name = TYPE_PIIX3_USB_UHCI, 1296 .vendor_id = PCI_VENDOR_ID_INTEL, 1297 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1298 .revision = 0x01, 1299 .irq_pin = 3, 1300 .unplug = true, 1301 },{ 1302 .name = TYPE_PIIX4_USB_UHCI, 1303 .vendor_id = PCI_VENDOR_ID_INTEL, 1304 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1305 .revision = 0x01, 1306 .irq_pin = 3, 1307 .unplug = true, 1308 },{ 1309 .name = TYPE_ICH9_USB_UHCI(1), /* 00:1d.0 */ 1310 .vendor_id = PCI_VENDOR_ID_INTEL, 1311 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1312 .revision = 0x03, 1313 .irq_pin = 0, 1314 .unplug = false, 1315 },{ 1316 .name = TYPE_ICH9_USB_UHCI(2), /* 00:1d.1 */ 1317 .vendor_id = PCI_VENDOR_ID_INTEL, 1318 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1319 .revision = 0x03, 1320 .irq_pin = 1, 1321 .unplug = false, 1322 },{ 1323 .name = TYPE_ICH9_USB_UHCI(3), /* 00:1d.2 */ 1324 .vendor_id = PCI_VENDOR_ID_INTEL, 1325 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1326 .revision = 0x03, 1327 .irq_pin = 2, 1328 .unplug = false, 1329 },{ 1330 .name = TYPE_ICH9_USB_UHCI(4), /* 00:1a.0 */ 1331 .vendor_id = PCI_VENDOR_ID_INTEL, 1332 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1333 .revision = 0x03, 1334 .irq_pin = 0, 1335 .unplug = false, 1336 },{ 1337 .name = TYPE_ICH9_USB_UHCI(5), /* 00:1a.1 */ 1338 .vendor_id = PCI_VENDOR_ID_INTEL, 1339 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1340 .revision = 0x03, 1341 .irq_pin = 1, 1342 .unplug = false, 1343 },{ 1344 .name = TYPE_ICH9_USB_UHCI(6), /* 00:1a.2 */ 1345 .vendor_id = PCI_VENDOR_ID_INTEL, 1346 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1347 .revision = 0x03, 1348 .irq_pin = 2, 1349 .unplug = false, 1350 } 1351 }; 1352 1353 static void uhci_register_types(void) 1354 { 1355 TypeInfo uhci_type_info = { 1356 .parent = TYPE_UHCI, 1357 .class_init = uhci_data_class_init, 1358 }; 1359 int i; 1360 1361 type_register_static(&uhci_pci_type_info); 1362 1363 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1364 uhci_type_info.name = uhci_info[i].name; 1365 uhci_type_info.class_data = uhci_info + i; 1366 type_register(&uhci_type_info); 1367 } 1368 } 1369 1370 type_init(uhci_register_types) 1371