1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "hw/usb.h" 31 #include "hw/usb/uhci-regs.h" 32 #include "migration/vmstate.h" 33 #include "hw/pci/pci.h" 34 #include "hw/qdev-properties.h" 35 #include "qapi/error.h" 36 #include "qemu/timer.h" 37 #include "qemu/iov.h" 38 #include "sysemu/dma.h" 39 #include "trace.h" 40 #include "qemu/main-loop.h" 41 #include "qemu/module.h" 42 #include "qom/object.h" 43 44 #define FRAME_TIMER_FREQ 1000 45 46 #define FRAME_MAX_LOOPS 256 47 48 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 49 #define QH_VALID 32 50 51 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 52 53 #define NB_PORTS 2 54 55 enum { 56 TD_RESULT_STOP_FRAME = 10, 57 TD_RESULT_COMPLETE, 58 TD_RESULT_NEXT_QH, 59 TD_RESULT_ASYNC_START, 60 TD_RESULT_ASYNC_CONT, 61 }; 62 63 typedef struct UHCIState UHCIState; 64 typedef struct UHCIAsync UHCIAsync; 65 typedef struct UHCIQueue UHCIQueue; 66 typedef struct UHCIInfo UHCIInfo; 67 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 68 69 struct UHCIInfo { 70 const char *name; 71 uint16_t vendor_id; 72 uint16_t device_id; 73 uint8_t revision; 74 uint8_t irq_pin; 75 void (*realize)(PCIDevice *dev, Error **errp); 76 bool unplug; 77 }; 78 79 struct UHCIPCIDeviceClass { 80 PCIDeviceClass parent_class; 81 UHCIInfo info; 82 }; 83 84 /* 85 * Pending async transaction. 86 * 'packet' must be the first field because completion 87 * handler does "(UHCIAsync *) pkt" cast. 88 */ 89 90 struct UHCIAsync { 91 USBPacket packet; 92 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 93 uint8_t *buf; 94 UHCIQueue *queue; 95 QTAILQ_ENTRY(UHCIAsync) next; 96 uint32_t td_addr; 97 uint8_t done; 98 }; 99 100 struct UHCIQueue { 101 uint32_t qh_addr; 102 uint32_t token; 103 UHCIState *uhci; 104 USBEndpoint *ep; 105 QTAILQ_ENTRY(UHCIQueue) next; 106 QTAILQ_HEAD(, UHCIAsync) asyncs; 107 int8_t valid; 108 }; 109 110 typedef struct UHCIPort { 111 USBPort port; 112 uint16_t ctrl; 113 } UHCIPort; 114 115 struct UHCIState { 116 PCIDevice dev; 117 MemoryRegion io_bar; 118 USBBus bus; /* Note unused when we're a companion controller */ 119 uint16_t cmd; /* cmd register */ 120 uint16_t status; 121 uint16_t intr; /* interrupt enable register */ 122 uint16_t frnum; /* frame number */ 123 uint32_t fl_base_addr; /* frame list base address */ 124 uint8_t sof_timing; 125 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 126 int64_t expire_time; 127 QEMUTimer *frame_timer; 128 QEMUBH *bh; 129 uint32_t frame_bytes; 130 uint32_t frame_bandwidth; 131 bool completions_only; 132 UHCIPort ports[NB_PORTS]; 133 134 /* Interrupts that should be raised at the end of the current frame. */ 135 uint32_t pending_int_mask; 136 137 /* Active packets */ 138 QTAILQ_HEAD(, UHCIQueue) queues; 139 uint8_t num_ports_vmstate; 140 141 /* Properties */ 142 char *masterbus; 143 uint32_t firstport; 144 uint32_t maxframes; 145 }; 146 147 typedef struct UHCI_TD { 148 uint32_t link; 149 uint32_t ctrl; /* see TD_CTRL_xxx */ 150 uint32_t token; 151 uint32_t buffer; 152 } UHCI_TD; 153 154 typedef struct UHCI_QH { 155 uint32_t link; 156 uint32_t el_link; 157 } UHCI_QH; 158 159 static void uhci_async_cancel(UHCIAsync *async); 160 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 161 static void uhci_resume(void *opaque); 162 163 #define TYPE_UHCI "pci-uhci-usb" 164 DECLARE_INSTANCE_CHECKER(UHCIState, UHCI, 165 TYPE_UHCI) 166 167 static inline int32_t uhci_queue_token(UHCI_TD *td) 168 { 169 if ((td->token & (0xf << 15)) == 0) { 170 /* ctrl ep, cover ep and dev, not pid! */ 171 return td->token & 0x7ff00; 172 } else { 173 /* covers ep, dev, pid -> identifies the endpoint */ 174 return td->token & 0x7ffff; 175 } 176 } 177 178 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 179 USBEndpoint *ep) 180 { 181 UHCIQueue *queue; 182 183 queue = g_new0(UHCIQueue, 1); 184 queue->uhci = s; 185 queue->qh_addr = qh_addr; 186 queue->token = uhci_queue_token(td); 187 queue->ep = ep; 188 QTAILQ_INIT(&queue->asyncs); 189 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 190 queue->valid = QH_VALID; 191 trace_usb_uhci_queue_add(queue->token); 192 return queue; 193 } 194 195 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 196 { 197 UHCIState *s = queue->uhci; 198 UHCIAsync *async; 199 200 while (!QTAILQ_EMPTY(&queue->asyncs)) { 201 async = QTAILQ_FIRST(&queue->asyncs); 202 uhci_async_cancel(async); 203 } 204 usb_device_ep_stopped(queue->ep->dev, queue->ep); 205 206 trace_usb_uhci_queue_del(queue->token, reason); 207 QTAILQ_REMOVE(&s->queues, queue, next); 208 g_free(queue); 209 } 210 211 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 212 { 213 uint32_t token = uhci_queue_token(td); 214 UHCIQueue *queue; 215 216 QTAILQ_FOREACH(queue, &s->queues, next) { 217 if (queue->token == token) { 218 return queue; 219 } 220 } 221 return NULL; 222 } 223 224 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 225 uint32_t td_addr, bool queuing) 226 { 227 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 228 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 229 230 return queue->qh_addr == qh_addr && 231 queue->token == uhci_queue_token(td) && 232 queue_token_addr == queue->ep->dev->addr && 233 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 234 first->td_addr == td_addr); 235 } 236 237 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 238 { 239 UHCIAsync *async = g_new0(UHCIAsync, 1); 240 241 async->queue = queue; 242 async->td_addr = td_addr; 243 usb_packet_init(&async->packet); 244 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 245 246 return async; 247 } 248 249 static void uhci_async_free(UHCIAsync *async) 250 { 251 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 252 usb_packet_cleanup(&async->packet); 253 if (async->buf != async->static_buf) { 254 g_free(async->buf); 255 } 256 g_free(async); 257 } 258 259 static void uhci_async_link(UHCIAsync *async) 260 { 261 UHCIQueue *queue = async->queue; 262 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 263 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 264 } 265 266 static void uhci_async_unlink(UHCIAsync *async) 267 { 268 UHCIQueue *queue = async->queue; 269 QTAILQ_REMOVE(&queue->asyncs, async, next); 270 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 271 } 272 273 static void uhci_async_cancel(UHCIAsync *async) 274 { 275 uhci_async_unlink(async); 276 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 277 async->done); 278 if (!async->done) 279 usb_cancel_packet(&async->packet); 280 uhci_async_free(async); 281 } 282 283 /* 284 * Mark all outstanding async packets as invalid. 285 * This is used for canceling them when TDs are removed by the HCD. 286 */ 287 static void uhci_async_validate_begin(UHCIState *s) 288 { 289 UHCIQueue *queue; 290 291 QTAILQ_FOREACH(queue, &s->queues, next) { 292 queue->valid--; 293 } 294 } 295 296 /* 297 * Cancel async packets that are no longer valid 298 */ 299 static void uhci_async_validate_end(UHCIState *s) 300 { 301 UHCIQueue *queue, *n; 302 303 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 304 if (!queue->valid) { 305 uhci_queue_free(queue, "validate-end"); 306 } 307 } 308 } 309 310 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 311 { 312 UHCIQueue *queue, *n; 313 314 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 315 if (queue->ep->dev == dev) { 316 uhci_queue_free(queue, "cancel-device"); 317 } 318 } 319 } 320 321 static void uhci_async_cancel_all(UHCIState *s) 322 { 323 UHCIQueue *queue, *nq; 324 325 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 326 uhci_queue_free(queue, "cancel-all"); 327 } 328 } 329 330 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 331 { 332 UHCIQueue *queue; 333 UHCIAsync *async; 334 335 QTAILQ_FOREACH(queue, &s->queues, next) { 336 QTAILQ_FOREACH(async, &queue->asyncs, next) { 337 if (async->td_addr == td_addr) { 338 return async; 339 } 340 } 341 } 342 return NULL; 343 } 344 345 static void uhci_update_irq(UHCIState *s) 346 { 347 int level; 348 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 349 ((s->status2 & 2) && (s->intr & (1 << 3))) || 350 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 351 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 352 (s->status & UHCI_STS_HSERR) || 353 (s->status & UHCI_STS_HCPERR)) { 354 level = 1; 355 } else { 356 level = 0; 357 } 358 pci_set_irq(&s->dev, level); 359 } 360 361 static void uhci_reset(DeviceState *dev) 362 { 363 PCIDevice *d = PCI_DEVICE(dev); 364 UHCIState *s = UHCI(d); 365 uint8_t *pci_conf; 366 int i; 367 UHCIPort *port; 368 369 trace_usb_uhci_reset(); 370 371 pci_conf = s->dev.config; 372 373 pci_conf[0x6a] = 0x01; /* usb clock */ 374 pci_conf[0x6b] = 0x00; 375 s->cmd = 0; 376 s->status = UHCI_STS_HCHALTED; 377 s->status2 = 0; 378 s->intr = 0; 379 s->fl_base_addr = 0; 380 s->sof_timing = 64; 381 382 for(i = 0; i < NB_PORTS; i++) { 383 port = &s->ports[i]; 384 port->ctrl = 0x0080; 385 if (port->port.dev && port->port.dev->attached) { 386 usb_port_reset(&port->port); 387 } 388 } 389 390 uhci_async_cancel_all(s); 391 qemu_bh_cancel(s->bh); 392 uhci_update_irq(s); 393 } 394 395 static const VMStateDescription vmstate_uhci_port = { 396 .name = "uhci port", 397 .version_id = 1, 398 .minimum_version_id = 1, 399 .fields = (VMStateField[]) { 400 VMSTATE_UINT16(ctrl, UHCIPort), 401 VMSTATE_END_OF_LIST() 402 } 403 }; 404 405 static int uhci_post_load(void *opaque, int version_id) 406 { 407 UHCIState *s = opaque; 408 409 if (version_id < 2) { 410 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 411 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 412 } 413 return 0; 414 } 415 416 static const VMStateDescription vmstate_uhci = { 417 .name = "uhci", 418 .version_id = 3, 419 .minimum_version_id = 1, 420 .post_load = uhci_post_load, 421 .fields = (VMStateField[]) { 422 VMSTATE_PCI_DEVICE(dev, UHCIState), 423 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 424 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 425 vmstate_uhci_port, UHCIPort), 426 VMSTATE_UINT16(cmd, UHCIState), 427 VMSTATE_UINT16(status, UHCIState), 428 VMSTATE_UINT16(intr, UHCIState), 429 VMSTATE_UINT16(frnum, UHCIState), 430 VMSTATE_UINT32(fl_base_addr, UHCIState), 431 VMSTATE_UINT8(sof_timing, UHCIState), 432 VMSTATE_UINT8(status2, UHCIState), 433 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 434 VMSTATE_INT64_V(expire_time, UHCIState, 2), 435 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 436 VMSTATE_END_OF_LIST() 437 } 438 }; 439 440 static void uhci_port_write(void *opaque, hwaddr addr, 441 uint64_t val, unsigned size) 442 { 443 UHCIState *s = opaque; 444 445 trace_usb_uhci_mmio_writew(addr, val); 446 447 switch(addr) { 448 case 0x00: 449 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 450 /* start frame processing */ 451 trace_usb_uhci_schedule_start(); 452 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 453 (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 454 timer_mod(s->frame_timer, s->expire_time); 455 s->status &= ~UHCI_STS_HCHALTED; 456 } else if (!(val & UHCI_CMD_RS)) { 457 s->status |= UHCI_STS_HCHALTED; 458 } 459 if (val & UHCI_CMD_GRESET) { 460 UHCIPort *port; 461 int i; 462 463 /* send reset on the USB bus */ 464 for(i = 0; i < NB_PORTS; i++) { 465 port = &s->ports[i]; 466 usb_device_reset(port->port.dev); 467 } 468 uhci_reset(DEVICE(s)); 469 return; 470 } 471 if (val & UHCI_CMD_HCRESET) { 472 uhci_reset(DEVICE(s)); 473 return; 474 } 475 s->cmd = val; 476 if (val & UHCI_CMD_EGSM) { 477 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 478 (s->ports[1].ctrl & UHCI_PORT_RD)) { 479 uhci_resume(s); 480 } 481 } 482 break; 483 case 0x02: 484 s->status &= ~val; 485 /* XXX: the chip spec is not coherent, so we add a hidden 486 register to distinguish between IOC and SPD */ 487 if (val & UHCI_STS_USBINT) 488 s->status2 = 0; 489 uhci_update_irq(s); 490 break; 491 case 0x04: 492 s->intr = val; 493 uhci_update_irq(s); 494 break; 495 case 0x06: 496 if (s->status & UHCI_STS_HCHALTED) 497 s->frnum = val & 0x7ff; 498 break; 499 case 0x08: 500 s->fl_base_addr &= 0xffff0000; 501 s->fl_base_addr |= val & ~0xfff; 502 break; 503 case 0x0a: 504 s->fl_base_addr &= 0x0000ffff; 505 s->fl_base_addr |= (val << 16); 506 break; 507 case 0x0c: 508 s->sof_timing = val & 0xff; 509 break; 510 case 0x10 ... 0x1f: 511 { 512 UHCIPort *port; 513 USBDevice *dev; 514 int n; 515 516 n = (addr >> 1) & 7; 517 if (n >= NB_PORTS) 518 return; 519 port = &s->ports[n]; 520 dev = port->port.dev; 521 if (dev && dev->attached) { 522 /* port reset */ 523 if ( (val & UHCI_PORT_RESET) && 524 !(port->ctrl & UHCI_PORT_RESET) ) { 525 usb_device_reset(dev); 526 } 527 } 528 port->ctrl &= UHCI_PORT_READ_ONLY; 529 /* enabled may only be set if a device is connected */ 530 if (!(port->ctrl & UHCI_PORT_CCS)) { 531 val &= ~UHCI_PORT_EN; 532 } 533 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 534 /* some bits are reset when a '1' is written to them */ 535 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 536 } 537 break; 538 } 539 } 540 541 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 542 { 543 UHCIState *s = opaque; 544 uint32_t val; 545 546 switch(addr) { 547 case 0x00: 548 val = s->cmd; 549 break; 550 case 0x02: 551 val = s->status; 552 break; 553 case 0x04: 554 val = s->intr; 555 break; 556 case 0x06: 557 val = s->frnum; 558 break; 559 case 0x08: 560 val = s->fl_base_addr & 0xffff; 561 break; 562 case 0x0a: 563 val = (s->fl_base_addr >> 16) & 0xffff; 564 break; 565 case 0x0c: 566 val = s->sof_timing; 567 break; 568 case 0x10 ... 0x1f: 569 { 570 UHCIPort *port; 571 int n; 572 n = (addr >> 1) & 7; 573 if (n >= NB_PORTS) 574 goto read_default; 575 port = &s->ports[n]; 576 val = port->ctrl; 577 } 578 break; 579 default: 580 read_default: 581 val = 0xff7f; /* disabled port */ 582 break; 583 } 584 585 trace_usb_uhci_mmio_readw(addr, val); 586 587 return val; 588 } 589 590 /* signal resume if controller suspended */ 591 static void uhci_resume (void *opaque) 592 { 593 UHCIState *s = (UHCIState *)opaque; 594 595 if (!s) 596 return; 597 598 if (s->cmd & UHCI_CMD_EGSM) { 599 s->cmd |= UHCI_CMD_FGR; 600 s->status |= UHCI_STS_RD; 601 uhci_update_irq(s); 602 } 603 } 604 605 static void uhci_attach(USBPort *port1) 606 { 607 UHCIState *s = port1->opaque; 608 UHCIPort *port = &s->ports[port1->index]; 609 610 /* set connect status */ 611 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 612 613 /* update speed */ 614 if (port->port.dev->speed == USB_SPEED_LOW) { 615 port->ctrl |= UHCI_PORT_LSDA; 616 } else { 617 port->ctrl &= ~UHCI_PORT_LSDA; 618 } 619 620 uhci_resume(s); 621 } 622 623 static void uhci_detach(USBPort *port1) 624 { 625 UHCIState *s = port1->opaque; 626 UHCIPort *port = &s->ports[port1->index]; 627 628 uhci_async_cancel_device(s, port1->dev); 629 630 /* set connect status */ 631 if (port->ctrl & UHCI_PORT_CCS) { 632 port->ctrl &= ~UHCI_PORT_CCS; 633 port->ctrl |= UHCI_PORT_CSC; 634 } 635 /* disable port */ 636 if (port->ctrl & UHCI_PORT_EN) { 637 port->ctrl &= ~UHCI_PORT_EN; 638 port->ctrl |= UHCI_PORT_ENC; 639 } 640 641 uhci_resume(s); 642 } 643 644 static void uhci_child_detach(USBPort *port1, USBDevice *child) 645 { 646 UHCIState *s = port1->opaque; 647 648 uhci_async_cancel_device(s, child); 649 } 650 651 static void uhci_wakeup(USBPort *port1) 652 { 653 UHCIState *s = port1->opaque; 654 UHCIPort *port = &s->ports[port1->index]; 655 656 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 657 port->ctrl |= UHCI_PORT_RD; 658 uhci_resume(s); 659 } 660 } 661 662 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 663 { 664 USBDevice *dev; 665 int i; 666 667 for (i = 0; i < NB_PORTS; i++) { 668 UHCIPort *port = &s->ports[i]; 669 if (!(port->ctrl & UHCI_PORT_EN)) { 670 continue; 671 } 672 dev = usb_find_device(&port->port, addr); 673 if (dev != NULL) { 674 return dev; 675 } 676 } 677 return NULL; 678 } 679 680 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 681 { 682 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 683 le32_to_cpus(&td->link); 684 le32_to_cpus(&td->ctrl); 685 le32_to_cpus(&td->token); 686 le32_to_cpus(&td->buffer); 687 } 688 689 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 690 int status, uint32_t *int_mask) 691 { 692 uint32_t queue_token = uhci_queue_token(td); 693 int ret; 694 695 switch (status) { 696 case USB_RET_NAK: 697 td->ctrl |= TD_CTRL_NAK; 698 return TD_RESULT_NEXT_QH; 699 700 case USB_RET_STALL: 701 td->ctrl |= TD_CTRL_STALL; 702 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 703 ret = TD_RESULT_NEXT_QH; 704 break; 705 706 case USB_RET_BABBLE: 707 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 708 /* frame interrupted */ 709 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 710 ret = TD_RESULT_STOP_FRAME; 711 break; 712 713 case USB_RET_IOERROR: 714 case USB_RET_NODEV: 715 default: 716 td->ctrl |= TD_CTRL_TIMEOUT; 717 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 718 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 719 ret = TD_RESULT_NEXT_QH; 720 break; 721 } 722 723 td->ctrl &= ~TD_CTRL_ACTIVE; 724 s->status |= UHCI_STS_USBERR; 725 if (td->ctrl & TD_CTRL_IOC) { 726 *int_mask |= 0x01; 727 } 728 uhci_update_irq(s); 729 return ret; 730 } 731 732 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 733 { 734 int len = 0, max_len; 735 uint8_t pid; 736 737 max_len = ((td->token >> 21) + 1) & 0x7ff; 738 pid = td->token & 0xff; 739 740 if (td->ctrl & TD_CTRL_IOS) 741 td->ctrl &= ~TD_CTRL_ACTIVE; 742 743 if (async->packet.status != USB_RET_SUCCESS) { 744 return uhci_handle_td_error(s, td, async->td_addr, 745 async->packet.status, int_mask); 746 } 747 748 len = async->packet.actual_length; 749 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 750 751 /* The NAK bit may have been set by a previous frame, so clear it 752 here. The docs are somewhat unclear, but win2k relies on this 753 behavior. */ 754 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 755 if (td->ctrl & TD_CTRL_IOC) 756 *int_mask |= 0x01; 757 758 if (pid == USB_TOKEN_IN) { 759 pci_dma_write(&s->dev, td->buffer, async->buf, len); 760 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 761 *int_mask |= 0x02; 762 /* short packet: do not update QH */ 763 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 764 async->td_addr); 765 return TD_RESULT_NEXT_QH; 766 } 767 } 768 769 /* success */ 770 trace_usb_uhci_packet_complete_success(async->queue->token, 771 async->td_addr); 772 return TD_RESULT_COMPLETE; 773 } 774 775 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 776 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 777 { 778 int ret, max_len; 779 bool spd; 780 bool queuing = (q != NULL); 781 uint8_t pid = td->token & 0xff; 782 UHCIAsync *async; 783 784 async = uhci_async_find_td(s, td_addr); 785 if (async) { 786 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 787 assert(q == NULL || q == async->queue); 788 q = async->queue; 789 } else { 790 uhci_queue_free(async->queue, "guest re-used pending td"); 791 async = NULL; 792 } 793 } 794 795 if (q == NULL) { 796 q = uhci_queue_find(s, td); 797 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 798 uhci_queue_free(q, "guest re-used qh"); 799 q = NULL; 800 } 801 } 802 803 if (q) { 804 q->valid = QH_VALID; 805 } 806 807 /* Is active ? */ 808 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 809 if (async) { 810 /* Guest marked a pending td non-active, cancel the queue */ 811 uhci_queue_free(async->queue, "pending td non-active"); 812 } 813 /* 814 * ehci11d spec page 22: "Even if the Active bit in the TD is already 815 * cleared when the TD is fetched ... an IOC interrupt is generated" 816 */ 817 if (td->ctrl & TD_CTRL_IOC) { 818 *int_mask |= 0x01; 819 } 820 return TD_RESULT_NEXT_QH; 821 } 822 823 switch (pid) { 824 case USB_TOKEN_OUT: 825 case USB_TOKEN_SETUP: 826 case USB_TOKEN_IN: 827 break; 828 default: 829 /* invalid pid : frame interrupted */ 830 s->status |= UHCI_STS_HCPERR; 831 s->cmd &= ~UHCI_CMD_RS; 832 uhci_update_irq(s); 833 return TD_RESULT_STOP_FRAME; 834 } 835 836 if (async) { 837 if (queuing) { 838 /* we are busy filling the queue, we are not prepared 839 to consume completed packages then, just leave them 840 in async state */ 841 return TD_RESULT_ASYNC_CONT; 842 } 843 if (!async->done) { 844 UHCI_TD last_td; 845 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); 846 /* 847 * While we are waiting for the current td to complete, the guest 848 * may have added more tds to the queue. Note we re-read the td 849 * rather then caching it, as we want to see guest made changes! 850 */ 851 uhci_read_td(s, &last_td, last->td_addr); 852 uhci_queue_fill(async->queue, &last_td); 853 854 return TD_RESULT_ASYNC_CONT; 855 } 856 uhci_async_unlink(async); 857 goto done; 858 } 859 860 if (s->completions_only) { 861 return TD_RESULT_ASYNC_CONT; 862 } 863 864 /* Allocate new packet */ 865 if (q == NULL) { 866 USBDevice *dev; 867 USBEndpoint *ep; 868 869 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 870 if (dev == NULL) { 871 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 872 int_mask); 873 } 874 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 875 q = uhci_queue_new(s, qh_addr, td, ep); 876 } 877 async = uhci_async_alloc(q, td_addr); 878 879 max_len = ((td->token >> 21) + 1) & 0x7ff; 880 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 881 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 882 (td->ctrl & TD_CTRL_IOC) != 0); 883 if (max_len <= sizeof(async->static_buf)) { 884 async->buf = async->static_buf; 885 } else { 886 async->buf = g_malloc(max_len); 887 } 888 usb_packet_addbuf(&async->packet, async->buf, max_len); 889 890 switch(pid) { 891 case USB_TOKEN_OUT: 892 case USB_TOKEN_SETUP: 893 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 894 usb_handle_packet(q->ep->dev, &async->packet); 895 if (async->packet.status == USB_RET_SUCCESS) { 896 async->packet.actual_length = max_len; 897 } 898 break; 899 900 case USB_TOKEN_IN: 901 usb_handle_packet(q->ep->dev, &async->packet); 902 break; 903 904 default: 905 abort(); /* Never to execute */ 906 } 907 908 if (async->packet.status == USB_RET_ASYNC) { 909 uhci_async_link(async); 910 if (!queuing) { 911 uhci_queue_fill(q, td); 912 } 913 return TD_RESULT_ASYNC_START; 914 } 915 916 done: 917 ret = uhci_complete_td(s, td, async, int_mask); 918 uhci_async_free(async); 919 return ret; 920 } 921 922 static void uhci_async_complete(USBPort *port, USBPacket *packet) 923 { 924 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 925 UHCIState *s = async->queue->uhci; 926 927 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 928 uhci_async_cancel(async); 929 return; 930 } 931 932 async->done = 1; 933 /* Force processing of this packet *now*, needed for migration */ 934 s->completions_only = true; 935 qemu_bh_schedule(s->bh); 936 } 937 938 static int is_valid(uint32_t link) 939 { 940 return (link & 1) == 0; 941 } 942 943 static int is_qh(uint32_t link) 944 { 945 return (link & 2) != 0; 946 } 947 948 static int depth_first(uint32_t link) 949 { 950 return (link & 4) != 0; 951 } 952 953 /* QH DB used for detecting QH loops */ 954 #define UHCI_MAX_QUEUES 128 955 typedef struct { 956 uint32_t addr[UHCI_MAX_QUEUES]; 957 int count; 958 } QhDb; 959 960 static void qhdb_reset(QhDb *db) 961 { 962 db->count = 0; 963 } 964 965 /* Add QH to DB. Returns 1 if already present or DB is full. */ 966 static int qhdb_insert(QhDb *db, uint32_t addr) 967 { 968 int i; 969 for (i = 0; i < db->count; i++) 970 if (db->addr[i] == addr) 971 return 1; 972 973 if (db->count >= UHCI_MAX_QUEUES) 974 return 1; 975 976 db->addr[db->count++] = addr; 977 return 0; 978 } 979 980 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 981 { 982 uint32_t int_mask = 0; 983 uint32_t plink = td->link; 984 UHCI_TD ptd; 985 int ret; 986 987 while (is_valid(plink)) { 988 uhci_read_td(q->uhci, &ptd, plink); 989 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 990 break; 991 } 992 if (uhci_queue_token(&ptd) != q->token) { 993 break; 994 } 995 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 996 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 997 if (ret == TD_RESULT_ASYNC_CONT) { 998 break; 999 } 1000 assert(ret == TD_RESULT_ASYNC_START); 1001 assert(int_mask == 0); 1002 plink = ptd.link; 1003 } 1004 usb_device_flush_ep_queue(q->ep->dev, q->ep); 1005 } 1006 1007 static void uhci_process_frame(UHCIState *s) 1008 { 1009 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 1010 uint32_t curr_qh, td_count = 0; 1011 int cnt, ret; 1012 UHCI_TD td; 1013 UHCI_QH qh; 1014 QhDb qhdb; 1015 1016 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 1017 1018 pci_dma_read(&s->dev, frame_addr, &link, 4); 1019 le32_to_cpus(&link); 1020 1021 int_mask = 0; 1022 curr_qh = 0; 1023 1024 qhdb_reset(&qhdb); 1025 1026 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1027 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1028 /* We've reached the usb 1.1 bandwidth, which is 1029 1280 bytes/frame, stop processing */ 1030 trace_usb_uhci_frame_stop_bandwidth(); 1031 break; 1032 } 1033 if (is_qh(link)) { 1034 /* QH */ 1035 trace_usb_uhci_qh_load(link & ~0xf); 1036 1037 if (qhdb_insert(&qhdb, link)) { 1038 /* 1039 * We're going in circles. Which is not a bug because 1040 * HCD is allowed to do that as part of the BW management. 1041 * 1042 * Stop processing here if no transaction has been done 1043 * since we've been here last time. 1044 */ 1045 if (td_count == 0) { 1046 trace_usb_uhci_frame_loop_stop_idle(); 1047 break; 1048 } else { 1049 trace_usb_uhci_frame_loop_continue(); 1050 td_count = 0; 1051 qhdb_reset(&qhdb); 1052 qhdb_insert(&qhdb, link); 1053 } 1054 } 1055 1056 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1057 le32_to_cpus(&qh.link); 1058 le32_to_cpus(&qh.el_link); 1059 1060 if (!is_valid(qh.el_link)) { 1061 /* QH w/o elements */ 1062 curr_qh = 0; 1063 link = qh.link; 1064 } else { 1065 /* QH with elements */ 1066 curr_qh = link; 1067 link = qh.el_link; 1068 } 1069 continue; 1070 } 1071 1072 /* TD */ 1073 uhci_read_td(s, &td, link); 1074 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1075 1076 old_td_ctrl = td.ctrl; 1077 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1078 if (old_td_ctrl != td.ctrl) { 1079 /* update the status bits of the TD */ 1080 val = cpu_to_le32(td.ctrl); 1081 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1082 } 1083 1084 switch (ret) { 1085 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1086 goto out; 1087 1088 case TD_RESULT_NEXT_QH: 1089 case TD_RESULT_ASYNC_CONT: 1090 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1091 link = curr_qh ? qh.link : td.link; 1092 continue; 1093 1094 case TD_RESULT_ASYNC_START: 1095 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1096 link = curr_qh ? qh.link : td.link; 1097 continue; 1098 1099 case TD_RESULT_COMPLETE: 1100 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1101 link = td.link; 1102 td_count++; 1103 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1104 1105 if (curr_qh) { 1106 /* update QH element link */ 1107 qh.el_link = link; 1108 val = cpu_to_le32(qh.el_link); 1109 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1110 1111 if (!depth_first(link)) { 1112 /* done with this QH */ 1113 curr_qh = 0; 1114 link = qh.link; 1115 } 1116 } 1117 break; 1118 1119 default: 1120 assert(!"unknown return code"); 1121 } 1122 1123 /* go to the next entry */ 1124 } 1125 1126 out: 1127 s->pending_int_mask |= int_mask; 1128 } 1129 1130 static void uhci_bh(void *opaque) 1131 { 1132 UHCIState *s = opaque; 1133 uhci_process_frame(s); 1134 } 1135 1136 static void uhci_frame_timer(void *opaque) 1137 { 1138 UHCIState *s = opaque; 1139 uint64_t t_now, t_last_run; 1140 int i, frames; 1141 const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1142 1143 s->completions_only = false; 1144 qemu_bh_cancel(s->bh); 1145 1146 if (!(s->cmd & UHCI_CMD_RS)) { 1147 /* Full stop */ 1148 trace_usb_uhci_schedule_stop(); 1149 timer_del(s->frame_timer); 1150 uhci_async_cancel_all(s); 1151 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1152 s->status |= UHCI_STS_HCHALTED; 1153 return; 1154 } 1155 1156 /* We still store expire_time in our state, for migration */ 1157 t_last_run = s->expire_time - frame_t; 1158 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1159 1160 /* Process up to MAX_FRAMES_PER_TICK frames */ 1161 frames = (t_now - t_last_run) / frame_t; 1162 if (frames > s->maxframes) { 1163 int skipped = frames - s->maxframes; 1164 s->expire_time += skipped * frame_t; 1165 s->frnum = (s->frnum + skipped) & 0x7ff; 1166 frames -= skipped; 1167 } 1168 if (frames > MAX_FRAMES_PER_TICK) { 1169 frames = MAX_FRAMES_PER_TICK; 1170 } 1171 1172 for (i = 0; i < frames; i++) { 1173 s->frame_bytes = 0; 1174 trace_usb_uhci_frame_start(s->frnum); 1175 uhci_async_validate_begin(s); 1176 uhci_process_frame(s); 1177 uhci_async_validate_end(s); 1178 /* The spec says frnum is the frame currently being processed, and 1179 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1180 s->frnum = (s->frnum + 1) & 0x7ff; 1181 s->expire_time += frame_t; 1182 } 1183 1184 /* Complete the previous frame(s) */ 1185 if (s->pending_int_mask) { 1186 s->status2 |= s->pending_int_mask; 1187 s->status |= UHCI_STS_USBINT; 1188 uhci_update_irq(s); 1189 } 1190 s->pending_int_mask = 0; 1191 1192 timer_mod(s->frame_timer, t_now + frame_t); 1193 } 1194 1195 static const MemoryRegionOps uhci_ioport_ops = { 1196 .read = uhci_port_read, 1197 .write = uhci_port_write, 1198 .valid.min_access_size = 1, 1199 .valid.max_access_size = 4, 1200 .impl.min_access_size = 2, 1201 .impl.max_access_size = 2, 1202 .endianness = DEVICE_LITTLE_ENDIAN, 1203 }; 1204 1205 static USBPortOps uhci_port_ops = { 1206 .attach = uhci_attach, 1207 .detach = uhci_detach, 1208 .child_detach = uhci_child_detach, 1209 .wakeup = uhci_wakeup, 1210 .complete = uhci_async_complete, 1211 }; 1212 1213 static USBBusOps uhci_bus_ops = { 1214 }; 1215 1216 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1217 { 1218 Error *err = NULL; 1219 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1220 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1221 UHCIState *s = UHCI(dev); 1222 uint8_t *pci_conf = s->dev.config; 1223 int i; 1224 1225 pci_conf[PCI_CLASS_PROG] = 0x00; 1226 /* TODO: reset value should be 0. */ 1227 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1228 1229 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1230 1231 if (s->masterbus) { 1232 USBPort *ports[NB_PORTS]; 1233 for(i = 0; i < NB_PORTS; i++) { 1234 ports[i] = &s->ports[i].port; 1235 } 1236 usb_register_companion(s->masterbus, ports, NB_PORTS, 1237 s->firstport, s, &uhci_port_ops, 1238 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1239 &err); 1240 if (err) { 1241 error_propagate(errp, err); 1242 return; 1243 } 1244 } else { 1245 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1246 for (i = 0; i < NB_PORTS; i++) { 1247 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1248 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1249 } 1250 } 1251 s->bh = qemu_bh_new(uhci_bh, s); 1252 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1253 s->num_ports_vmstate = NB_PORTS; 1254 QTAILQ_INIT(&s->queues); 1255 1256 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1257 "uhci", 0x20); 1258 1259 /* Use region 4 for consistency with real hardware. BSD guests seem 1260 to rely on this. */ 1261 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1262 } 1263 1264 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) 1265 { 1266 UHCIState *s = UHCI(dev); 1267 uint8_t *pci_conf = s->dev.config; 1268 1269 /* USB misc control 1/2 */ 1270 pci_set_long(pci_conf + 0x40,0x00001000); 1271 /* PM capability */ 1272 pci_set_long(pci_conf + 0x80,0x00020001); 1273 /* USB legacy support */ 1274 pci_set_long(pci_conf + 0xc0,0x00002000); 1275 1276 usb_uhci_common_realize(dev, errp); 1277 } 1278 1279 static void usb_uhci_exit(PCIDevice *dev) 1280 { 1281 UHCIState *s = UHCI(dev); 1282 1283 trace_usb_uhci_exit(); 1284 1285 if (s->frame_timer) { 1286 timer_free(s->frame_timer); 1287 s->frame_timer = NULL; 1288 } 1289 1290 if (s->bh) { 1291 qemu_bh_delete(s->bh); 1292 } 1293 1294 uhci_async_cancel_all(s); 1295 1296 if (!s->masterbus) { 1297 usb_bus_release(&s->bus); 1298 } 1299 } 1300 1301 static Property uhci_properties_companion[] = { 1302 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1303 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1304 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1305 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1306 DEFINE_PROP_END_OF_LIST(), 1307 }; 1308 static Property uhci_properties_standalone[] = { 1309 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1310 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1311 DEFINE_PROP_END_OF_LIST(), 1312 }; 1313 1314 static void uhci_class_init(ObjectClass *klass, void *data) 1315 { 1316 DeviceClass *dc = DEVICE_CLASS(klass); 1317 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1318 1319 k->class_id = PCI_CLASS_SERIAL_USB; 1320 dc->vmsd = &vmstate_uhci; 1321 dc->reset = uhci_reset; 1322 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1323 } 1324 1325 static const TypeInfo uhci_pci_type_info = { 1326 .name = TYPE_UHCI, 1327 .parent = TYPE_PCI_DEVICE, 1328 .instance_size = sizeof(UHCIState), 1329 .class_size = sizeof(UHCIPCIDeviceClass), 1330 .abstract = true, 1331 .class_init = uhci_class_init, 1332 .interfaces = (InterfaceInfo[]) { 1333 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1334 { }, 1335 }, 1336 }; 1337 1338 static void uhci_data_class_init(ObjectClass *klass, void *data) 1339 { 1340 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1341 DeviceClass *dc = DEVICE_CLASS(klass); 1342 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1343 UHCIInfo *info = data; 1344 1345 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1346 k->exit = info->unplug ? usb_uhci_exit : NULL; 1347 k->vendor_id = info->vendor_id; 1348 k->device_id = info->device_id; 1349 k->revision = info->revision; 1350 if (!info->unplug) { 1351 /* uhci controllers in companion setups can't be hotplugged */ 1352 dc->hotpluggable = false; 1353 device_class_set_props(dc, uhci_properties_companion); 1354 } else { 1355 device_class_set_props(dc, uhci_properties_standalone); 1356 } 1357 u->info = *info; 1358 } 1359 1360 static UHCIInfo uhci_info[] = { 1361 { 1362 .name = "piix3-usb-uhci", 1363 .vendor_id = PCI_VENDOR_ID_INTEL, 1364 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1365 .revision = 0x01, 1366 .irq_pin = 3, 1367 .unplug = true, 1368 },{ 1369 .name = "piix4-usb-uhci", 1370 .vendor_id = PCI_VENDOR_ID_INTEL, 1371 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1372 .revision = 0x01, 1373 .irq_pin = 3, 1374 .unplug = true, 1375 },{ 1376 .name = "vt82c686b-usb-uhci", 1377 .vendor_id = PCI_VENDOR_ID_VIA, 1378 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1379 .revision = 0x01, 1380 .irq_pin = 3, 1381 .realize = usb_uhci_vt82c686b_realize, 1382 .unplug = true, 1383 },{ 1384 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1385 .vendor_id = PCI_VENDOR_ID_INTEL, 1386 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1387 .revision = 0x03, 1388 .irq_pin = 0, 1389 .unplug = false, 1390 },{ 1391 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1392 .vendor_id = PCI_VENDOR_ID_INTEL, 1393 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1394 .revision = 0x03, 1395 .irq_pin = 1, 1396 .unplug = false, 1397 },{ 1398 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1399 .vendor_id = PCI_VENDOR_ID_INTEL, 1400 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1401 .revision = 0x03, 1402 .irq_pin = 2, 1403 .unplug = false, 1404 },{ 1405 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1406 .vendor_id = PCI_VENDOR_ID_INTEL, 1407 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1408 .revision = 0x03, 1409 .irq_pin = 0, 1410 .unplug = false, 1411 },{ 1412 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1413 .vendor_id = PCI_VENDOR_ID_INTEL, 1414 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1415 .revision = 0x03, 1416 .irq_pin = 1, 1417 .unplug = false, 1418 },{ 1419 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1420 .vendor_id = PCI_VENDOR_ID_INTEL, 1421 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1422 .revision = 0x03, 1423 .irq_pin = 2, 1424 .unplug = false, 1425 } 1426 }; 1427 1428 static void uhci_register_types(void) 1429 { 1430 TypeInfo uhci_type_info = { 1431 .parent = TYPE_UHCI, 1432 .class_init = uhci_data_class_init, 1433 }; 1434 int i; 1435 1436 type_register_static(&uhci_pci_type_info); 1437 1438 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1439 uhci_type_info.name = uhci_info[i].name; 1440 uhci_type_info.class_data = uhci_info + i; 1441 type_register(&uhci_type_info); 1442 } 1443 } 1444 1445 type_init(uhci_register_types) 1446