1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/usb/uhci-regs.h" 31 #include "hw/pci/pci.h" 32 #include "qemu/timer.h" 33 #include "qemu/iov.h" 34 #include "sysemu/dma.h" 35 #include "trace.h" 36 #include "qemu/main-loop.h" 37 38 #define FRAME_TIMER_FREQ 1000 39 40 #define FRAME_MAX_LOOPS 256 41 42 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 43 #define QH_VALID 32 44 45 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 46 47 #define NB_PORTS 2 48 49 enum { 50 TD_RESULT_STOP_FRAME = 10, 51 TD_RESULT_COMPLETE, 52 TD_RESULT_NEXT_QH, 53 TD_RESULT_ASYNC_START, 54 TD_RESULT_ASYNC_CONT, 55 }; 56 57 typedef struct UHCIState UHCIState; 58 typedef struct UHCIAsync UHCIAsync; 59 typedef struct UHCIQueue UHCIQueue; 60 typedef struct UHCIInfo UHCIInfo; 61 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 62 63 struct UHCIInfo { 64 const char *name; 65 uint16_t vendor_id; 66 uint16_t device_id; 67 uint8_t revision; 68 uint8_t irq_pin; 69 void (*realize)(PCIDevice *dev, Error **errp); 70 bool unplug; 71 }; 72 73 struct UHCIPCIDeviceClass { 74 PCIDeviceClass parent_class; 75 UHCIInfo info; 76 }; 77 78 /* 79 * Pending async transaction. 80 * 'packet' must be the first field because completion 81 * handler does "(UHCIAsync *) pkt" cast. 82 */ 83 84 struct UHCIAsync { 85 USBPacket packet; 86 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 87 uint8_t *buf; 88 UHCIQueue *queue; 89 QTAILQ_ENTRY(UHCIAsync) next; 90 uint32_t td_addr; 91 uint8_t done; 92 }; 93 94 struct UHCIQueue { 95 uint32_t qh_addr; 96 uint32_t token; 97 UHCIState *uhci; 98 USBEndpoint *ep; 99 QTAILQ_ENTRY(UHCIQueue) next; 100 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 101 int8_t valid; 102 }; 103 104 typedef struct UHCIPort { 105 USBPort port; 106 uint16_t ctrl; 107 } UHCIPort; 108 109 struct UHCIState { 110 PCIDevice dev; 111 MemoryRegion io_bar; 112 USBBus bus; /* Note unused when we're a companion controller */ 113 uint16_t cmd; /* cmd register */ 114 uint16_t status; 115 uint16_t intr; /* interrupt enable register */ 116 uint16_t frnum; /* frame number */ 117 uint32_t fl_base_addr; /* frame list base address */ 118 uint8_t sof_timing; 119 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 120 int64_t expire_time; 121 QEMUTimer *frame_timer; 122 QEMUBH *bh; 123 uint32_t frame_bytes; 124 uint32_t frame_bandwidth; 125 bool completions_only; 126 UHCIPort ports[NB_PORTS]; 127 128 /* Interrupts that should be raised at the end of the current frame. */ 129 uint32_t pending_int_mask; 130 131 /* Active packets */ 132 QTAILQ_HEAD(, UHCIQueue) queues; 133 uint8_t num_ports_vmstate; 134 135 /* Properties */ 136 char *masterbus; 137 uint32_t firstport; 138 uint32_t maxframes; 139 }; 140 141 typedef struct UHCI_TD { 142 uint32_t link; 143 uint32_t ctrl; /* see TD_CTRL_xxx */ 144 uint32_t token; 145 uint32_t buffer; 146 } UHCI_TD; 147 148 typedef struct UHCI_QH { 149 uint32_t link; 150 uint32_t el_link; 151 } UHCI_QH; 152 153 static void uhci_async_cancel(UHCIAsync *async); 154 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 155 static void uhci_resume(void *opaque); 156 157 #define TYPE_UHCI "pci-uhci-usb" 158 #define UHCI(obj) OBJECT_CHECK(UHCIState, (obj), TYPE_UHCI) 159 160 static inline int32_t uhci_queue_token(UHCI_TD *td) 161 { 162 if ((td->token & (0xf << 15)) == 0) { 163 /* ctrl ep, cover ep and dev, not pid! */ 164 return td->token & 0x7ff00; 165 } else { 166 /* covers ep, dev, pid -> identifies the endpoint */ 167 return td->token & 0x7ffff; 168 } 169 } 170 171 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 172 USBEndpoint *ep) 173 { 174 UHCIQueue *queue; 175 176 queue = g_new0(UHCIQueue, 1); 177 queue->uhci = s; 178 queue->qh_addr = qh_addr; 179 queue->token = uhci_queue_token(td); 180 queue->ep = ep; 181 QTAILQ_INIT(&queue->asyncs); 182 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 183 queue->valid = QH_VALID; 184 trace_usb_uhci_queue_add(queue->token); 185 return queue; 186 } 187 188 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 189 { 190 UHCIState *s = queue->uhci; 191 UHCIAsync *async; 192 193 while (!QTAILQ_EMPTY(&queue->asyncs)) { 194 async = QTAILQ_FIRST(&queue->asyncs); 195 uhci_async_cancel(async); 196 } 197 usb_device_ep_stopped(queue->ep->dev, queue->ep); 198 199 trace_usb_uhci_queue_del(queue->token, reason); 200 QTAILQ_REMOVE(&s->queues, queue, next); 201 g_free(queue); 202 } 203 204 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 205 { 206 uint32_t token = uhci_queue_token(td); 207 UHCIQueue *queue; 208 209 QTAILQ_FOREACH(queue, &s->queues, next) { 210 if (queue->token == token) { 211 return queue; 212 } 213 } 214 return NULL; 215 } 216 217 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 218 uint32_t td_addr, bool queuing) 219 { 220 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 221 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 222 223 return queue->qh_addr == qh_addr && 224 queue->token == uhci_queue_token(td) && 225 queue_token_addr == queue->ep->dev->addr && 226 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 227 first->td_addr == td_addr); 228 } 229 230 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 231 { 232 UHCIAsync *async = g_new0(UHCIAsync, 1); 233 234 async->queue = queue; 235 async->td_addr = td_addr; 236 usb_packet_init(&async->packet); 237 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 238 239 return async; 240 } 241 242 static void uhci_async_free(UHCIAsync *async) 243 { 244 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 245 usb_packet_cleanup(&async->packet); 246 if (async->buf != async->static_buf) { 247 g_free(async->buf); 248 } 249 g_free(async); 250 } 251 252 static void uhci_async_link(UHCIAsync *async) 253 { 254 UHCIQueue *queue = async->queue; 255 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 256 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 257 } 258 259 static void uhci_async_unlink(UHCIAsync *async) 260 { 261 UHCIQueue *queue = async->queue; 262 QTAILQ_REMOVE(&queue->asyncs, async, next); 263 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 264 } 265 266 static void uhci_async_cancel(UHCIAsync *async) 267 { 268 uhci_async_unlink(async); 269 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 270 async->done); 271 if (!async->done) 272 usb_cancel_packet(&async->packet); 273 uhci_async_free(async); 274 } 275 276 /* 277 * Mark all outstanding async packets as invalid. 278 * This is used for canceling them when TDs are removed by the HCD. 279 */ 280 static void uhci_async_validate_begin(UHCIState *s) 281 { 282 UHCIQueue *queue; 283 284 QTAILQ_FOREACH(queue, &s->queues, next) { 285 queue->valid--; 286 } 287 } 288 289 /* 290 * Cancel async packets that are no longer valid 291 */ 292 static void uhci_async_validate_end(UHCIState *s) 293 { 294 UHCIQueue *queue, *n; 295 296 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 297 if (!queue->valid) { 298 uhci_queue_free(queue, "validate-end"); 299 } 300 } 301 } 302 303 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 304 { 305 UHCIQueue *queue, *n; 306 307 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 308 if (queue->ep->dev == dev) { 309 uhci_queue_free(queue, "cancel-device"); 310 } 311 } 312 } 313 314 static void uhci_async_cancel_all(UHCIState *s) 315 { 316 UHCIQueue *queue, *nq; 317 318 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 319 uhci_queue_free(queue, "cancel-all"); 320 } 321 } 322 323 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 324 { 325 UHCIQueue *queue; 326 UHCIAsync *async; 327 328 QTAILQ_FOREACH(queue, &s->queues, next) { 329 QTAILQ_FOREACH(async, &queue->asyncs, next) { 330 if (async->td_addr == td_addr) { 331 return async; 332 } 333 } 334 } 335 return NULL; 336 } 337 338 static void uhci_update_irq(UHCIState *s) 339 { 340 int level; 341 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 342 ((s->status2 & 2) && (s->intr & (1 << 3))) || 343 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 344 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 345 (s->status & UHCI_STS_HSERR) || 346 (s->status & UHCI_STS_HCPERR)) { 347 level = 1; 348 } else { 349 level = 0; 350 } 351 pci_set_irq(&s->dev, level); 352 } 353 354 static void uhci_reset(DeviceState *dev) 355 { 356 PCIDevice *d = PCI_DEVICE(dev); 357 UHCIState *s = UHCI(d); 358 uint8_t *pci_conf; 359 int i; 360 UHCIPort *port; 361 362 trace_usb_uhci_reset(); 363 364 pci_conf = s->dev.config; 365 366 pci_conf[0x6a] = 0x01; /* usb clock */ 367 pci_conf[0x6b] = 0x00; 368 s->cmd = 0; 369 s->status = UHCI_STS_HCHALTED; 370 s->status2 = 0; 371 s->intr = 0; 372 s->fl_base_addr = 0; 373 s->sof_timing = 64; 374 375 for(i = 0; i < NB_PORTS; i++) { 376 port = &s->ports[i]; 377 port->ctrl = 0x0080; 378 if (port->port.dev && port->port.dev->attached) { 379 usb_port_reset(&port->port); 380 } 381 } 382 383 uhci_async_cancel_all(s); 384 qemu_bh_cancel(s->bh); 385 uhci_update_irq(s); 386 } 387 388 static const VMStateDescription vmstate_uhci_port = { 389 .name = "uhci port", 390 .version_id = 1, 391 .minimum_version_id = 1, 392 .fields = (VMStateField[]) { 393 VMSTATE_UINT16(ctrl, UHCIPort), 394 VMSTATE_END_OF_LIST() 395 } 396 }; 397 398 static int uhci_post_load(void *opaque, int version_id) 399 { 400 UHCIState *s = opaque; 401 402 if (version_id < 2) { 403 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 404 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 405 } 406 return 0; 407 } 408 409 static const VMStateDescription vmstate_uhci = { 410 .name = "uhci", 411 .version_id = 3, 412 .minimum_version_id = 1, 413 .post_load = uhci_post_load, 414 .fields = (VMStateField[]) { 415 VMSTATE_PCI_DEVICE(dev, UHCIState), 416 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 417 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 418 vmstate_uhci_port, UHCIPort), 419 VMSTATE_UINT16(cmd, UHCIState), 420 VMSTATE_UINT16(status, UHCIState), 421 VMSTATE_UINT16(intr, UHCIState), 422 VMSTATE_UINT16(frnum, UHCIState), 423 VMSTATE_UINT32(fl_base_addr, UHCIState), 424 VMSTATE_UINT8(sof_timing, UHCIState), 425 VMSTATE_UINT8(status2, UHCIState), 426 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 427 VMSTATE_INT64_V(expire_time, UHCIState, 2), 428 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 429 VMSTATE_END_OF_LIST() 430 } 431 }; 432 433 static void uhci_port_write(void *opaque, hwaddr addr, 434 uint64_t val, unsigned size) 435 { 436 UHCIState *s = opaque; 437 438 trace_usb_uhci_mmio_writew(addr, val); 439 440 switch(addr) { 441 case 0x00: 442 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 443 /* start frame processing */ 444 trace_usb_uhci_schedule_start(); 445 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 446 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 447 timer_mod(s->frame_timer, s->expire_time); 448 s->status &= ~UHCI_STS_HCHALTED; 449 } else if (!(val & UHCI_CMD_RS)) { 450 s->status |= UHCI_STS_HCHALTED; 451 } 452 if (val & UHCI_CMD_GRESET) { 453 UHCIPort *port; 454 int i; 455 456 /* send reset on the USB bus */ 457 for(i = 0; i < NB_PORTS; i++) { 458 port = &s->ports[i]; 459 usb_device_reset(port->port.dev); 460 } 461 uhci_reset(DEVICE(s)); 462 return; 463 } 464 if (val & UHCI_CMD_HCRESET) { 465 uhci_reset(DEVICE(s)); 466 return; 467 } 468 s->cmd = val; 469 if (val & UHCI_CMD_EGSM) { 470 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 471 (s->ports[1].ctrl & UHCI_PORT_RD)) { 472 uhci_resume(s); 473 } 474 } 475 break; 476 case 0x02: 477 s->status &= ~val; 478 /* XXX: the chip spec is not coherent, so we add a hidden 479 register to distinguish between IOC and SPD */ 480 if (val & UHCI_STS_USBINT) 481 s->status2 = 0; 482 uhci_update_irq(s); 483 break; 484 case 0x04: 485 s->intr = val; 486 uhci_update_irq(s); 487 break; 488 case 0x06: 489 if (s->status & UHCI_STS_HCHALTED) 490 s->frnum = val & 0x7ff; 491 break; 492 case 0x08: 493 s->fl_base_addr &= 0xffff0000; 494 s->fl_base_addr |= val & ~0xfff; 495 break; 496 case 0x0a: 497 s->fl_base_addr &= 0x0000ffff; 498 s->fl_base_addr |= (val << 16); 499 break; 500 case 0x0c: 501 s->sof_timing = val & 0xff; 502 break; 503 case 0x10 ... 0x1f: 504 { 505 UHCIPort *port; 506 USBDevice *dev; 507 int n; 508 509 n = (addr >> 1) & 7; 510 if (n >= NB_PORTS) 511 return; 512 port = &s->ports[n]; 513 dev = port->port.dev; 514 if (dev && dev->attached) { 515 /* port reset */ 516 if ( (val & UHCI_PORT_RESET) && 517 !(port->ctrl & UHCI_PORT_RESET) ) { 518 usb_device_reset(dev); 519 } 520 } 521 port->ctrl &= UHCI_PORT_READ_ONLY; 522 /* enabled may only be set if a device is connected */ 523 if (!(port->ctrl & UHCI_PORT_CCS)) { 524 val &= ~UHCI_PORT_EN; 525 } 526 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 527 /* some bits are reset when a '1' is written to them */ 528 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 529 } 530 break; 531 } 532 } 533 534 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 535 { 536 UHCIState *s = opaque; 537 uint32_t val; 538 539 switch(addr) { 540 case 0x00: 541 val = s->cmd; 542 break; 543 case 0x02: 544 val = s->status; 545 break; 546 case 0x04: 547 val = s->intr; 548 break; 549 case 0x06: 550 val = s->frnum; 551 break; 552 case 0x08: 553 val = s->fl_base_addr & 0xffff; 554 break; 555 case 0x0a: 556 val = (s->fl_base_addr >> 16) & 0xffff; 557 break; 558 case 0x0c: 559 val = s->sof_timing; 560 break; 561 case 0x10 ... 0x1f: 562 { 563 UHCIPort *port; 564 int n; 565 n = (addr >> 1) & 7; 566 if (n >= NB_PORTS) 567 goto read_default; 568 port = &s->ports[n]; 569 val = port->ctrl; 570 } 571 break; 572 default: 573 read_default: 574 val = 0xff7f; /* disabled port */ 575 break; 576 } 577 578 trace_usb_uhci_mmio_readw(addr, val); 579 580 return val; 581 } 582 583 /* signal resume if controller suspended */ 584 static void uhci_resume (void *opaque) 585 { 586 UHCIState *s = (UHCIState *)opaque; 587 588 if (!s) 589 return; 590 591 if (s->cmd & UHCI_CMD_EGSM) { 592 s->cmd |= UHCI_CMD_FGR; 593 s->status |= UHCI_STS_RD; 594 uhci_update_irq(s); 595 } 596 } 597 598 static void uhci_attach(USBPort *port1) 599 { 600 UHCIState *s = port1->opaque; 601 UHCIPort *port = &s->ports[port1->index]; 602 603 /* set connect status */ 604 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 605 606 /* update speed */ 607 if (port->port.dev->speed == USB_SPEED_LOW) { 608 port->ctrl |= UHCI_PORT_LSDA; 609 } else { 610 port->ctrl &= ~UHCI_PORT_LSDA; 611 } 612 613 uhci_resume(s); 614 } 615 616 static void uhci_detach(USBPort *port1) 617 { 618 UHCIState *s = port1->opaque; 619 UHCIPort *port = &s->ports[port1->index]; 620 621 uhci_async_cancel_device(s, port1->dev); 622 623 /* set connect status */ 624 if (port->ctrl & UHCI_PORT_CCS) { 625 port->ctrl &= ~UHCI_PORT_CCS; 626 port->ctrl |= UHCI_PORT_CSC; 627 } 628 /* disable port */ 629 if (port->ctrl & UHCI_PORT_EN) { 630 port->ctrl &= ~UHCI_PORT_EN; 631 port->ctrl |= UHCI_PORT_ENC; 632 } 633 634 uhci_resume(s); 635 } 636 637 static void uhci_child_detach(USBPort *port1, USBDevice *child) 638 { 639 UHCIState *s = port1->opaque; 640 641 uhci_async_cancel_device(s, child); 642 } 643 644 static void uhci_wakeup(USBPort *port1) 645 { 646 UHCIState *s = port1->opaque; 647 UHCIPort *port = &s->ports[port1->index]; 648 649 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 650 port->ctrl |= UHCI_PORT_RD; 651 uhci_resume(s); 652 } 653 } 654 655 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 656 { 657 USBDevice *dev; 658 int i; 659 660 for (i = 0; i < NB_PORTS; i++) { 661 UHCIPort *port = &s->ports[i]; 662 if (!(port->ctrl & UHCI_PORT_EN)) { 663 continue; 664 } 665 dev = usb_find_device(&port->port, addr); 666 if (dev != NULL) { 667 return dev; 668 } 669 } 670 return NULL; 671 } 672 673 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 674 { 675 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 676 le32_to_cpus(&td->link); 677 le32_to_cpus(&td->ctrl); 678 le32_to_cpus(&td->token); 679 le32_to_cpus(&td->buffer); 680 } 681 682 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 683 int status, uint32_t *int_mask) 684 { 685 uint32_t queue_token = uhci_queue_token(td); 686 int ret; 687 688 switch (status) { 689 case USB_RET_NAK: 690 td->ctrl |= TD_CTRL_NAK; 691 return TD_RESULT_NEXT_QH; 692 693 case USB_RET_STALL: 694 td->ctrl |= TD_CTRL_STALL; 695 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 696 ret = TD_RESULT_NEXT_QH; 697 break; 698 699 case USB_RET_BABBLE: 700 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 701 /* frame interrupted */ 702 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 703 ret = TD_RESULT_STOP_FRAME; 704 break; 705 706 case USB_RET_IOERROR: 707 case USB_RET_NODEV: 708 default: 709 td->ctrl |= TD_CTRL_TIMEOUT; 710 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 711 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 712 ret = TD_RESULT_NEXT_QH; 713 break; 714 } 715 716 td->ctrl &= ~TD_CTRL_ACTIVE; 717 s->status |= UHCI_STS_USBERR; 718 if (td->ctrl & TD_CTRL_IOC) { 719 *int_mask |= 0x01; 720 } 721 uhci_update_irq(s); 722 return ret; 723 } 724 725 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 726 { 727 int len = 0, max_len; 728 uint8_t pid; 729 730 max_len = ((td->token >> 21) + 1) & 0x7ff; 731 pid = td->token & 0xff; 732 733 if (td->ctrl & TD_CTRL_IOS) 734 td->ctrl &= ~TD_CTRL_ACTIVE; 735 736 if (async->packet.status != USB_RET_SUCCESS) { 737 return uhci_handle_td_error(s, td, async->td_addr, 738 async->packet.status, int_mask); 739 } 740 741 len = async->packet.actual_length; 742 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 743 744 /* The NAK bit may have been set by a previous frame, so clear it 745 here. The docs are somewhat unclear, but win2k relies on this 746 behavior. */ 747 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 748 if (td->ctrl & TD_CTRL_IOC) 749 *int_mask |= 0x01; 750 751 if (pid == USB_TOKEN_IN) { 752 pci_dma_write(&s->dev, td->buffer, async->buf, len); 753 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 754 *int_mask |= 0x02; 755 /* short packet: do not update QH */ 756 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 757 async->td_addr); 758 return TD_RESULT_NEXT_QH; 759 } 760 } 761 762 /* success */ 763 trace_usb_uhci_packet_complete_success(async->queue->token, 764 async->td_addr); 765 return TD_RESULT_COMPLETE; 766 } 767 768 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 769 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 770 { 771 int ret, max_len; 772 bool spd; 773 bool queuing = (q != NULL); 774 uint8_t pid = td->token & 0xff; 775 UHCIAsync *async = uhci_async_find_td(s, td_addr); 776 777 if (async) { 778 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 779 assert(q == NULL || q == async->queue); 780 q = async->queue; 781 } else { 782 uhci_queue_free(async->queue, "guest re-used pending td"); 783 async = NULL; 784 } 785 } 786 787 if (q == NULL) { 788 q = uhci_queue_find(s, td); 789 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 790 uhci_queue_free(q, "guest re-used qh"); 791 q = NULL; 792 } 793 } 794 795 if (q) { 796 q->valid = QH_VALID; 797 } 798 799 /* Is active ? */ 800 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 801 if (async) { 802 /* Guest marked a pending td non-active, cancel the queue */ 803 uhci_queue_free(async->queue, "pending td non-active"); 804 } 805 /* 806 * ehci11d spec page 22: "Even if the Active bit in the TD is already 807 * cleared when the TD is fetched ... an IOC interrupt is generated" 808 */ 809 if (td->ctrl & TD_CTRL_IOC) { 810 *int_mask |= 0x01; 811 } 812 return TD_RESULT_NEXT_QH; 813 } 814 815 if (async) { 816 if (queuing) { 817 /* we are busy filling the queue, we are not prepared 818 to consume completed packages then, just leave them 819 in async state */ 820 return TD_RESULT_ASYNC_CONT; 821 } 822 if (!async->done) { 823 UHCI_TD last_td; 824 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 825 /* 826 * While we are waiting for the current td to complete, the guest 827 * may have added more tds to the queue. Note we re-read the td 828 * rather then caching it, as we want to see guest made changes! 829 */ 830 uhci_read_td(s, &last_td, last->td_addr); 831 uhci_queue_fill(async->queue, &last_td); 832 833 return TD_RESULT_ASYNC_CONT; 834 } 835 uhci_async_unlink(async); 836 goto done; 837 } 838 839 if (s->completions_only) { 840 return TD_RESULT_ASYNC_CONT; 841 } 842 843 /* Allocate new packet */ 844 if (q == NULL) { 845 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 846 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 847 848 if (ep == NULL) { 849 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 850 int_mask); 851 } 852 q = uhci_queue_new(s, qh_addr, td, ep); 853 } 854 async = uhci_async_alloc(q, td_addr); 855 856 max_len = ((td->token >> 21) + 1) & 0x7ff; 857 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 858 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 859 (td->ctrl & TD_CTRL_IOC) != 0); 860 if (max_len <= sizeof(async->static_buf)) { 861 async->buf = async->static_buf; 862 } else { 863 async->buf = g_malloc(max_len); 864 } 865 usb_packet_addbuf(&async->packet, async->buf, max_len); 866 867 switch(pid) { 868 case USB_TOKEN_OUT: 869 case USB_TOKEN_SETUP: 870 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 871 usb_handle_packet(q->ep->dev, &async->packet); 872 if (async->packet.status == USB_RET_SUCCESS) { 873 async->packet.actual_length = max_len; 874 } 875 break; 876 877 case USB_TOKEN_IN: 878 usb_handle_packet(q->ep->dev, &async->packet); 879 break; 880 881 default: 882 /* invalid pid : frame interrupted */ 883 uhci_async_free(async); 884 s->status |= UHCI_STS_HCPERR; 885 uhci_update_irq(s); 886 return TD_RESULT_STOP_FRAME; 887 } 888 889 if (async->packet.status == USB_RET_ASYNC) { 890 uhci_async_link(async); 891 if (!queuing) { 892 uhci_queue_fill(q, td); 893 } 894 return TD_RESULT_ASYNC_START; 895 } 896 897 done: 898 ret = uhci_complete_td(s, td, async, int_mask); 899 uhci_async_free(async); 900 return ret; 901 } 902 903 static void uhci_async_complete(USBPort *port, USBPacket *packet) 904 { 905 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 906 UHCIState *s = async->queue->uhci; 907 908 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 909 uhci_async_cancel(async); 910 return; 911 } 912 913 async->done = 1; 914 /* Force processing of this packet *now*, needed for migration */ 915 s->completions_only = true; 916 qemu_bh_schedule(s->bh); 917 } 918 919 static int is_valid(uint32_t link) 920 { 921 return (link & 1) == 0; 922 } 923 924 static int is_qh(uint32_t link) 925 { 926 return (link & 2) != 0; 927 } 928 929 static int depth_first(uint32_t link) 930 { 931 return (link & 4) != 0; 932 } 933 934 /* QH DB used for detecting QH loops */ 935 #define UHCI_MAX_QUEUES 128 936 typedef struct { 937 uint32_t addr[UHCI_MAX_QUEUES]; 938 int count; 939 } QhDb; 940 941 static void qhdb_reset(QhDb *db) 942 { 943 db->count = 0; 944 } 945 946 /* Add QH to DB. Returns 1 if already present or DB is full. */ 947 static int qhdb_insert(QhDb *db, uint32_t addr) 948 { 949 int i; 950 for (i = 0; i < db->count; i++) 951 if (db->addr[i] == addr) 952 return 1; 953 954 if (db->count >= UHCI_MAX_QUEUES) 955 return 1; 956 957 db->addr[db->count++] = addr; 958 return 0; 959 } 960 961 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 962 { 963 uint32_t int_mask = 0; 964 uint32_t plink = td->link; 965 UHCI_TD ptd; 966 int ret; 967 968 while (is_valid(plink)) { 969 uhci_read_td(q->uhci, &ptd, plink); 970 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 971 break; 972 } 973 if (uhci_queue_token(&ptd) != q->token) { 974 break; 975 } 976 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 977 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 978 if (ret == TD_RESULT_ASYNC_CONT) { 979 break; 980 } 981 assert(ret == TD_RESULT_ASYNC_START); 982 assert(int_mask == 0); 983 plink = ptd.link; 984 } 985 usb_device_flush_ep_queue(q->ep->dev, q->ep); 986 } 987 988 static void uhci_process_frame(UHCIState *s) 989 { 990 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 991 uint32_t curr_qh, td_count = 0; 992 int cnt, ret; 993 UHCI_TD td; 994 UHCI_QH qh; 995 QhDb qhdb; 996 997 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 998 999 pci_dma_read(&s->dev, frame_addr, &link, 4); 1000 le32_to_cpus(&link); 1001 1002 int_mask = 0; 1003 curr_qh = 0; 1004 1005 qhdb_reset(&qhdb); 1006 1007 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1008 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1009 /* We've reached the usb 1.1 bandwidth, which is 1010 1280 bytes/frame, stop processing */ 1011 trace_usb_uhci_frame_stop_bandwidth(); 1012 break; 1013 } 1014 if (is_qh(link)) { 1015 /* QH */ 1016 trace_usb_uhci_qh_load(link & ~0xf); 1017 1018 if (qhdb_insert(&qhdb, link)) { 1019 /* 1020 * We're going in circles. Which is not a bug because 1021 * HCD is allowed to do that as part of the BW management. 1022 * 1023 * Stop processing here if no transaction has been done 1024 * since we've been here last time. 1025 */ 1026 if (td_count == 0) { 1027 trace_usb_uhci_frame_loop_stop_idle(); 1028 break; 1029 } else { 1030 trace_usb_uhci_frame_loop_continue(); 1031 td_count = 0; 1032 qhdb_reset(&qhdb); 1033 qhdb_insert(&qhdb, link); 1034 } 1035 } 1036 1037 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1038 le32_to_cpus(&qh.link); 1039 le32_to_cpus(&qh.el_link); 1040 1041 if (!is_valid(qh.el_link)) { 1042 /* QH w/o elements */ 1043 curr_qh = 0; 1044 link = qh.link; 1045 } else { 1046 /* QH with elements */ 1047 curr_qh = link; 1048 link = qh.el_link; 1049 } 1050 continue; 1051 } 1052 1053 /* TD */ 1054 uhci_read_td(s, &td, link); 1055 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1056 1057 old_td_ctrl = td.ctrl; 1058 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1059 if (old_td_ctrl != td.ctrl) { 1060 /* update the status bits of the TD */ 1061 val = cpu_to_le32(td.ctrl); 1062 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1063 } 1064 1065 switch (ret) { 1066 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1067 goto out; 1068 1069 case TD_RESULT_NEXT_QH: 1070 case TD_RESULT_ASYNC_CONT: 1071 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1072 link = curr_qh ? qh.link : td.link; 1073 continue; 1074 1075 case TD_RESULT_ASYNC_START: 1076 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1077 link = curr_qh ? qh.link : td.link; 1078 continue; 1079 1080 case TD_RESULT_COMPLETE: 1081 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1082 link = td.link; 1083 td_count++; 1084 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1085 1086 if (curr_qh) { 1087 /* update QH element link */ 1088 qh.el_link = link; 1089 val = cpu_to_le32(qh.el_link); 1090 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1091 1092 if (!depth_first(link)) { 1093 /* done with this QH */ 1094 curr_qh = 0; 1095 link = qh.link; 1096 } 1097 } 1098 break; 1099 1100 default: 1101 assert(!"unknown return code"); 1102 } 1103 1104 /* go to the next entry */ 1105 } 1106 1107 out: 1108 s->pending_int_mask |= int_mask; 1109 } 1110 1111 static void uhci_bh(void *opaque) 1112 { 1113 UHCIState *s = opaque; 1114 uhci_process_frame(s); 1115 } 1116 1117 static void uhci_frame_timer(void *opaque) 1118 { 1119 UHCIState *s = opaque; 1120 uint64_t t_now, t_last_run; 1121 int i, frames; 1122 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1123 1124 s->completions_only = false; 1125 qemu_bh_cancel(s->bh); 1126 1127 if (!(s->cmd & UHCI_CMD_RS)) { 1128 /* Full stop */ 1129 trace_usb_uhci_schedule_stop(); 1130 timer_del(s->frame_timer); 1131 uhci_async_cancel_all(s); 1132 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1133 s->status |= UHCI_STS_HCHALTED; 1134 return; 1135 } 1136 1137 /* We still store expire_time in our state, for migration */ 1138 t_last_run = s->expire_time - frame_t; 1139 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1140 1141 /* Process up to MAX_FRAMES_PER_TICK frames */ 1142 frames = (t_now - t_last_run) / frame_t; 1143 if (frames > s->maxframes) { 1144 int skipped = frames - s->maxframes; 1145 s->expire_time += skipped * frame_t; 1146 s->frnum = (s->frnum + skipped) & 0x7ff; 1147 frames -= skipped; 1148 } 1149 if (frames > MAX_FRAMES_PER_TICK) { 1150 frames = MAX_FRAMES_PER_TICK; 1151 } 1152 1153 for (i = 0; i < frames; i++) { 1154 s->frame_bytes = 0; 1155 trace_usb_uhci_frame_start(s->frnum); 1156 uhci_async_validate_begin(s); 1157 uhci_process_frame(s); 1158 uhci_async_validate_end(s); 1159 /* The spec says frnum is the frame currently being processed, and 1160 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1161 s->frnum = (s->frnum + 1) & 0x7ff; 1162 s->expire_time += frame_t; 1163 } 1164 1165 /* Complete the previous frame(s) */ 1166 if (s->pending_int_mask) { 1167 s->status2 |= s->pending_int_mask; 1168 s->status |= UHCI_STS_USBINT; 1169 uhci_update_irq(s); 1170 } 1171 s->pending_int_mask = 0; 1172 1173 timer_mod(s->frame_timer, t_now + frame_t); 1174 } 1175 1176 static const MemoryRegionOps uhci_ioport_ops = { 1177 .read = uhci_port_read, 1178 .write = uhci_port_write, 1179 .valid.min_access_size = 1, 1180 .valid.max_access_size = 4, 1181 .impl.min_access_size = 2, 1182 .impl.max_access_size = 2, 1183 .endianness = DEVICE_LITTLE_ENDIAN, 1184 }; 1185 1186 static USBPortOps uhci_port_ops = { 1187 .attach = uhci_attach, 1188 .detach = uhci_detach, 1189 .child_detach = uhci_child_detach, 1190 .wakeup = uhci_wakeup, 1191 .complete = uhci_async_complete, 1192 }; 1193 1194 static USBBusOps uhci_bus_ops = { 1195 }; 1196 1197 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1198 { 1199 Error *err = NULL; 1200 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1201 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1202 UHCIState *s = UHCI(dev); 1203 uint8_t *pci_conf = s->dev.config; 1204 int i; 1205 1206 pci_conf[PCI_CLASS_PROG] = 0x00; 1207 /* TODO: reset value should be 0. */ 1208 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1209 1210 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1211 1212 if (s->masterbus) { 1213 USBPort *ports[NB_PORTS]; 1214 for(i = 0; i < NB_PORTS; i++) { 1215 ports[i] = &s->ports[i].port; 1216 } 1217 usb_register_companion(s->masterbus, ports, NB_PORTS, 1218 s->firstport, s, &uhci_port_ops, 1219 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1220 &err); 1221 if (err) { 1222 error_propagate(errp, err); 1223 return; 1224 } 1225 } else { 1226 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1227 for (i = 0; i < NB_PORTS; i++) { 1228 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1229 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1230 } 1231 } 1232 s->bh = qemu_bh_new(uhci_bh, s); 1233 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1234 s->num_ports_vmstate = NB_PORTS; 1235 QTAILQ_INIT(&s->queues); 1236 1237 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1238 "uhci", 0x20); 1239 1240 /* Use region 4 for consistency with real hardware. BSD guests seem 1241 to rely on this. */ 1242 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1243 } 1244 1245 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) 1246 { 1247 UHCIState *s = UHCI(dev); 1248 uint8_t *pci_conf = s->dev.config; 1249 1250 /* USB misc control 1/2 */ 1251 pci_set_long(pci_conf + 0x40,0x00001000); 1252 /* PM capability */ 1253 pci_set_long(pci_conf + 0x80,0x00020001); 1254 /* USB legacy support */ 1255 pci_set_long(pci_conf + 0xc0,0x00002000); 1256 1257 usb_uhci_common_realize(dev, errp); 1258 } 1259 1260 static void usb_uhci_exit(PCIDevice *dev) 1261 { 1262 UHCIState *s = UHCI(dev); 1263 1264 trace_usb_uhci_exit(); 1265 1266 if (s->frame_timer) { 1267 timer_del(s->frame_timer); 1268 timer_free(s->frame_timer); 1269 s->frame_timer = NULL; 1270 } 1271 1272 if (s->bh) { 1273 qemu_bh_delete(s->bh); 1274 } 1275 1276 uhci_async_cancel_all(s); 1277 1278 if (!s->masterbus) { 1279 usb_bus_release(&s->bus); 1280 } 1281 } 1282 1283 static Property uhci_properties_companion[] = { 1284 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1285 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1286 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1287 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1288 DEFINE_PROP_END_OF_LIST(), 1289 }; 1290 static Property uhci_properties_standalone[] = { 1291 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1292 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1293 DEFINE_PROP_END_OF_LIST(), 1294 }; 1295 1296 static void uhci_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1300 1301 k->class_id = PCI_CLASS_SERIAL_USB; 1302 dc->vmsd = &vmstate_uhci; 1303 dc->reset = uhci_reset; 1304 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1305 } 1306 1307 static const TypeInfo uhci_pci_type_info = { 1308 .name = TYPE_UHCI, 1309 .parent = TYPE_PCI_DEVICE, 1310 .instance_size = sizeof(UHCIState), 1311 .class_size = sizeof(UHCIPCIDeviceClass), 1312 .abstract = true, 1313 .class_init = uhci_class_init, 1314 }; 1315 1316 static void uhci_data_class_init(ObjectClass *klass, void *data) 1317 { 1318 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1319 DeviceClass *dc = DEVICE_CLASS(klass); 1320 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1321 UHCIInfo *info = data; 1322 1323 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1324 k->exit = info->unplug ? usb_uhci_exit : NULL; 1325 k->vendor_id = info->vendor_id; 1326 k->device_id = info->device_id; 1327 k->revision = info->revision; 1328 if (!info->unplug) { 1329 /* uhci controllers in companion setups can't be hotplugged */ 1330 dc->hotpluggable = false; 1331 dc->props = uhci_properties_companion; 1332 } else { 1333 dc->props = uhci_properties_standalone; 1334 } 1335 u->info = *info; 1336 } 1337 1338 static UHCIInfo uhci_info[] = { 1339 { 1340 .name = "piix3-usb-uhci", 1341 .vendor_id = PCI_VENDOR_ID_INTEL, 1342 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1343 .revision = 0x01, 1344 .irq_pin = 3, 1345 .unplug = true, 1346 },{ 1347 .name = "piix4-usb-uhci", 1348 .vendor_id = PCI_VENDOR_ID_INTEL, 1349 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1350 .revision = 0x01, 1351 .irq_pin = 3, 1352 .unplug = true, 1353 },{ 1354 .name = "vt82c686b-usb-uhci", 1355 .vendor_id = PCI_VENDOR_ID_VIA, 1356 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1357 .revision = 0x01, 1358 .irq_pin = 3, 1359 .realize = usb_uhci_vt82c686b_realize, 1360 .unplug = true, 1361 },{ 1362 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1363 .vendor_id = PCI_VENDOR_ID_INTEL, 1364 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1365 .revision = 0x03, 1366 .irq_pin = 0, 1367 .unplug = false, 1368 },{ 1369 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1370 .vendor_id = PCI_VENDOR_ID_INTEL, 1371 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1372 .revision = 0x03, 1373 .irq_pin = 1, 1374 .unplug = false, 1375 },{ 1376 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1377 .vendor_id = PCI_VENDOR_ID_INTEL, 1378 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1379 .revision = 0x03, 1380 .irq_pin = 2, 1381 .unplug = false, 1382 },{ 1383 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1384 .vendor_id = PCI_VENDOR_ID_INTEL, 1385 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1386 .revision = 0x03, 1387 .irq_pin = 0, 1388 .unplug = false, 1389 },{ 1390 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1391 .vendor_id = PCI_VENDOR_ID_INTEL, 1392 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1393 .revision = 0x03, 1394 .irq_pin = 1, 1395 .unplug = false, 1396 },{ 1397 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1398 .vendor_id = PCI_VENDOR_ID_INTEL, 1399 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1400 .revision = 0x03, 1401 .irq_pin = 2, 1402 .unplug = false, 1403 } 1404 }; 1405 1406 static void uhci_register_types(void) 1407 { 1408 TypeInfo uhci_type_info = { 1409 .parent = TYPE_UHCI, 1410 .class_init = uhci_data_class_init, 1411 }; 1412 int i; 1413 1414 type_register_static(&uhci_pci_type_info); 1415 1416 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1417 uhci_type_info.name = uhci_info[i].name; 1418 uhci_type_info.class_data = uhci_info + i; 1419 type_register(&uhci_type_info); 1420 } 1421 } 1422 1423 type_init(uhci_register_types) 1424