1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/usb/uhci-regs.h" 31 #include "hw/pci/pci.h" 32 #include "qemu/timer.h" 33 #include "qemu/iov.h" 34 #include "sysemu/dma.h" 35 #include "trace.h" 36 #include "qemu/main-loop.h" 37 38 #define FRAME_TIMER_FREQ 1000 39 40 #define FRAME_MAX_LOOPS 256 41 42 /* Must be large enough to handle 10 frame delay for initial isoc requests */ 43 #define QH_VALID 32 44 45 #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 46 47 #define NB_PORTS 2 48 49 enum { 50 TD_RESULT_STOP_FRAME = 10, 51 TD_RESULT_COMPLETE, 52 TD_RESULT_NEXT_QH, 53 TD_RESULT_ASYNC_START, 54 TD_RESULT_ASYNC_CONT, 55 }; 56 57 typedef struct UHCIState UHCIState; 58 typedef struct UHCIAsync UHCIAsync; 59 typedef struct UHCIQueue UHCIQueue; 60 typedef struct UHCIInfo UHCIInfo; 61 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 62 63 struct UHCIInfo { 64 const char *name; 65 uint16_t vendor_id; 66 uint16_t device_id; 67 uint8_t revision; 68 uint8_t irq_pin; 69 void (*realize)(PCIDevice *dev, Error **errp); 70 bool unplug; 71 }; 72 73 struct UHCIPCIDeviceClass { 74 PCIDeviceClass parent_class; 75 UHCIInfo info; 76 }; 77 78 /* 79 * Pending async transaction. 80 * 'packet' must be the first field because completion 81 * handler does "(UHCIAsync *) pkt" cast. 82 */ 83 84 struct UHCIAsync { 85 USBPacket packet; 86 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 87 uint8_t *buf; 88 UHCIQueue *queue; 89 QTAILQ_ENTRY(UHCIAsync) next; 90 uint32_t td_addr; 91 uint8_t done; 92 }; 93 94 struct UHCIQueue { 95 uint32_t qh_addr; 96 uint32_t token; 97 UHCIState *uhci; 98 USBEndpoint *ep; 99 QTAILQ_ENTRY(UHCIQueue) next; 100 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs; 101 int8_t valid; 102 }; 103 104 typedef struct UHCIPort { 105 USBPort port; 106 uint16_t ctrl; 107 } UHCIPort; 108 109 struct UHCIState { 110 PCIDevice dev; 111 MemoryRegion io_bar; 112 USBBus bus; /* Note unused when we're a companion controller */ 113 uint16_t cmd; /* cmd register */ 114 uint16_t status; 115 uint16_t intr; /* interrupt enable register */ 116 uint16_t frnum; /* frame number */ 117 uint32_t fl_base_addr; /* frame list base address */ 118 uint8_t sof_timing; 119 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 120 int64_t expire_time; 121 QEMUTimer *frame_timer; 122 QEMUBH *bh; 123 uint32_t frame_bytes; 124 uint32_t frame_bandwidth; 125 bool completions_only; 126 UHCIPort ports[NB_PORTS]; 127 128 /* Interrupts that should be raised at the end of the current frame. */ 129 uint32_t pending_int_mask; 130 131 /* Active packets */ 132 QTAILQ_HEAD(, UHCIQueue) queues; 133 uint8_t num_ports_vmstate; 134 135 /* Properties */ 136 char *masterbus; 137 uint32_t firstport; 138 uint32_t maxframes; 139 }; 140 141 typedef struct UHCI_TD { 142 uint32_t link; 143 uint32_t ctrl; /* see TD_CTRL_xxx */ 144 uint32_t token; 145 uint32_t buffer; 146 } UHCI_TD; 147 148 typedef struct UHCI_QH { 149 uint32_t link; 150 uint32_t el_link; 151 } UHCI_QH; 152 153 static void uhci_async_cancel(UHCIAsync *async); 154 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 155 static void uhci_resume(void *opaque); 156 157 static inline int32_t uhci_queue_token(UHCI_TD *td) 158 { 159 if ((td->token & (0xf << 15)) == 0) { 160 /* ctrl ep, cover ep and dev, not pid! */ 161 return td->token & 0x7ff00; 162 } else { 163 /* covers ep, dev, pid -> identifies the endpoint */ 164 return td->token & 0x7ffff; 165 } 166 } 167 168 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 169 USBEndpoint *ep) 170 { 171 UHCIQueue *queue; 172 173 queue = g_new0(UHCIQueue, 1); 174 queue->uhci = s; 175 queue->qh_addr = qh_addr; 176 queue->token = uhci_queue_token(td); 177 queue->ep = ep; 178 QTAILQ_INIT(&queue->asyncs); 179 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 180 queue->valid = QH_VALID; 181 trace_usb_uhci_queue_add(queue->token); 182 return queue; 183 } 184 185 static void uhci_queue_free(UHCIQueue *queue, const char *reason) 186 { 187 UHCIState *s = queue->uhci; 188 UHCIAsync *async; 189 190 while (!QTAILQ_EMPTY(&queue->asyncs)) { 191 async = QTAILQ_FIRST(&queue->asyncs); 192 uhci_async_cancel(async); 193 } 194 usb_device_ep_stopped(queue->ep->dev, queue->ep); 195 196 trace_usb_uhci_queue_del(queue->token, reason); 197 QTAILQ_REMOVE(&s->queues, queue, next); 198 g_free(queue); 199 } 200 201 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 202 { 203 uint32_t token = uhci_queue_token(td); 204 UHCIQueue *queue; 205 206 QTAILQ_FOREACH(queue, &s->queues, next) { 207 if (queue->token == token) { 208 return queue; 209 } 210 } 211 return NULL; 212 } 213 214 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 215 uint32_t td_addr, bool queuing) 216 { 217 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 218 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 219 220 return queue->qh_addr == qh_addr && 221 queue->token == uhci_queue_token(td) && 222 queue_token_addr == queue->ep->dev->addr && 223 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 224 first->td_addr == td_addr); 225 } 226 227 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 228 { 229 UHCIAsync *async = g_new0(UHCIAsync, 1); 230 231 async->queue = queue; 232 async->td_addr = td_addr; 233 usb_packet_init(&async->packet); 234 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 235 236 return async; 237 } 238 239 static void uhci_async_free(UHCIAsync *async) 240 { 241 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 242 usb_packet_cleanup(&async->packet); 243 if (async->buf != async->static_buf) { 244 g_free(async->buf); 245 } 246 g_free(async); 247 } 248 249 static void uhci_async_link(UHCIAsync *async) 250 { 251 UHCIQueue *queue = async->queue; 252 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 253 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 254 } 255 256 static void uhci_async_unlink(UHCIAsync *async) 257 { 258 UHCIQueue *queue = async->queue; 259 QTAILQ_REMOVE(&queue->asyncs, async, next); 260 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 261 } 262 263 static void uhci_async_cancel(UHCIAsync *async) 264 { 265 uhci_async_unlink(async); 266 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 267 async->done); 268 if (!async->done) 269 usb_cancel_packet(&async->packet); 270 uhci_async_free(async); 271 } 272 273 /* 274 * Mark all outstanding async packets as invalid. 275 * This is used for canceling them when TDs are removed by the HCD. 276 */ 277 static void uhci_async_validate_begin(UHCIState *s) 278 { 279 UHCIQueue *queue; 280 281 QTAILQ_FOREACH(queue, &s->queues, next) { 282 queue->valid--; 283 } 284 } 285 286 /* 287 * Cancel async packets that are no longer valid 288 */ 289 static void uhci_async_validate_end(UHCIState *s) 290 { 291 UHCIQueue *queue, *n; 292 293 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 294 if (!queue->valid) { 295 uhci_queue_free(queue, "validate-end"); 296 } 297 } 298 } 299 300 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 301 { 302 UHCIQueue *queue, *n; 303 304 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 305 if (queue->ep->dev == dev) { 306 uhci_queue_free(queue, "cancel-device"); 307 } 308 } 309 } 310 311 static void uhci_async_cancel_all(UHCIState *s) 312 { 313 UHCIQueue *queue, *nq; 314 315 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 316 uhci_queue_free(queue, "cancel-all"); 317 } 318 } 319 320 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 321 { 322 UHCIQueue *queue; 323 UHCIAsync *async; 324 325 QTAILQ_FOREACH(queue, &s->queues, next) { 326 QTAILQ_FOREACH(async, &queue->asyncs, next) { 327 if (async->td_addr == td_addr) { 328 return async; 329 } 330 } 331 } 332 return NULL; 333 } 334 335 static void uhci_update_irq(UHCIState *s) 336 { 337 int level; 338 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 339 ((s->status2 & 2) && (s->intr & (1 << 3))) || 340 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 341 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 342 (s->status & UHCI_STS_HSERR) || 343 (s->status & UHCI_STS_HCPERR)) { 344 level = 1; 345 } else { 346 level = 0; 347 } 348 pci_set_irq(&s->dev, level); 349 } 350 351 static void uhci_reset(DeviceState *dev) 352 { 353 PCIDevice *d = PCI_DEVICE(dev); 354 UHCIState *s = DO_UPCAST(UHCIState, dev, d); 355 uint8_t *pci_conf; 356 int i; 357 UHCIPort *port; 358 359 trace_usb_uhci_reset(); 360 361 pci_conf = s->dev.config; 362 363 pci_conf[0x6a] = 0x01; /* usb clock */ 364 pci_conf[0x6b] = 0x00; 365 s->cmd = 0; 366 s->status = 0; 367 s->status2 = 0; 368 s->intr = 0; 369 s->fl_base_addr = 0; 370 s->sof_timing = 64; 371 372 for(i = 0; i < NB_PORTS; i++) { 373 port = &s->ports[i]; 374 port->ctrl = 0x0080; 375 if (port->port.dev && port->port.dev->attached) { 376 usb_port_reset(&port->port); 377 } 378 } 379 380 uhci_async_cancel_all(s); 381 qemu_bh_cancel(s->bh); 382 uhci_update_irq(s); 383 } 384 385 static const VMStateDescription vmstate_uhci_port = { 386 .name = "uhci port", 387 .version_id = 1, 388 .minimum_version_id = 1, 389 .fields = (VMStateField[]) { 390 VMSTATE_UINT16(ctrl, UHCIPort), 391 VMSTATE_END_OF_LIST() 392 } 393 }; 394 395 static int uhci_post_load(void *opaque, int version_id) 396 { 397 UHCIState *s = opaque; 398 399 if (version_id < 2) { 400 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 401 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 402 } 403 return 0; 404 } 405 406 static const VMStateDescription vmstate_uhci = { 407 .name = "uhci", 408 .version_id = 3, 409 .minimum_version_id = 1, 410 .post_load = uhci_post_load, 411 .fields = (VMStateField[]) { 412 VMSTATE_PCI_DEVICE(dev, UHCIState), 413 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 414 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 415 vmstate_uhci_port, UHCIPort), 416 VMSTATE_UINT16(cmd, UHCIState), 417 VMSTATE_UINT16(status, UHCIState), 418 VMSTATE_UINT16(intr, UHCIState), 419 VMSTATE_UINT16(frnum, UHCIState), 420 VMSTATE_UINT32(fl_base_addr, UHCIState), 421 VMSTATE_UINT8(sof_timing, UHCIState), 422 VMSTATE_UINT8(status2, UHCIState), 423 VMSTATE_TIMER_PTR(frame_timer, UHCIState), 424 VMSTATE_INT64_V(expire_time, UHCIState, 2), 425 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 426 VMSTATE_END_OF_LIST() 427 } 428 }; 429 430 static void uhci_port_write(void *opaque, hwaddr addr, 431 uint64_t val, unsigned size) 432 { 433 UHCIState *s = opaque; 434 435 trace_usb_uhci_mmio_writew(addr, val); 436 437 switch(addr) { 438 case 0x00: 439 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 440 /* start frame processing */ 441 trace_usb_uhci_schedule_start(); 442 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 443 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 444 timer_mod(s->frame_timer, s->expire_time); 445 s->status &= ~UHCI_STS_HCHALTED; 446 } else if (!(val & UHCI_CMD_RS)) { 447 s->status |= UHCI_STS_HCHALTED; 448 } 449 if (val & UHCI_CMD_GRESET) { 450 UHCIPort *port; 451 int i; 452 453 /* send reset on the USB bus */ 454 for(i = 0; i < NB_PORTS; i++) { 455 port = &s->ports[i]; 456 usb_device_reset(port->port.dev); 457 } 458 uhci_reset(DEVICE(s)); 459 return; 460 } 461 if (val & UHCI_CMD_HCRESET) { 462 uhci_reset(DEVICE(s)); 463 return; 464 } 465 s->cmd = val; 466 if (val & UHCI_CMD_EGSM) { 467 if ((s->ports[0].ctrl & UHCI_PORT_RD) || 468 (s->ports[1].ctrl & UHCI_PORT_RD)) { 469 uhci_resume(s); 470 } 471 } 472 break; 473 case 0x02: 474 s->status &= ~val; 475 /* XXX: the chip spec is not coherent, so we add a hidden 476 register to distinguish between IOC and SPD */ 477 if (val & UHCI_STS_USBINT) 478 s->status2 = 0; 479 uhci_update_irq(s); 480 break; 481 case 0x04: 482 s->intr = val; 483 uhci_update_irq(s); 484 break; 485 case 0x06: 486 if (s->status & UHCI_STS_HCHALTED) 487 s->frnum = val & 0x7ff; 488 break; 489 case 0x08: 490 s->fl_base_addr &= 0xffff0000; 491 s->fl_base_addr |= val & ~0xfff; 492 break; 493 case 0x0a: 494 s->fl_base_addr &= 0x0000ffff; 495 s->fl_base_addr |= (val << 16); 496 break; 497 case 0x0c: 498 s->sof_timing = val & 0xff; 499 break; 500 case 0x10 ... 0x1f: 501 { 502 UHCIPort *port; 503 USBDevice *dev; 504 int n; 505 506 n = (addr >> 1) & 7; 507 if (n >= NB_PORTS) 508 return; 509 port = &s->ports[n]; 510 dev = port->port.dev; 511 if (dev && dev->attached) { 512 /* port reset */ 513 if ( (val & UHCI_PORT_RESET) && 514 !(port->ctrl & UHCI_PORT_RESET) ) { 515 usb_device_reset(dev); 516 } 517 } 518 port->ctrl &= UHCI_PORT_READ_ONLY; 519 /* enabled may only be set if a device is connected */ 520 if (!(port->ctrl & UHCI_PORT_CCS)) { 521 val &= ~UHCI_PORT_EN; 522 } 523 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 524 /* some bits are reset when a '1' is written to them */ 525 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 526 } 527 break; 528 } 529 } 530 531 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 532 { 533 UHCIState *s = opaque; 534 uint32_t val; 535 536 switch(addr) { 537 case 0x00: 538 val = s->cmd; 539 break; 540 case 0x02: 541 val = s->status; 542 break; 543 case 0x04: 544 val = s->intr; 545 break; 546 case 0x06: 547 val = s->frnum; 548 break; 549 case 0x08: 550 val = s->fl_base_addr & 0xffff; 551 break; 552 case 0x0a: 553 val = (s->fl_base_addr >> 16) & 0xffff; 554 break; 555 case 0x0c: 556 val = s->sof_timing; 557 break; 558 case 0x10 ... 0x1f: 559 { 560 UHCIPort *port; 561 int n; 562 n = (addr >> 1) & 7; 563 if (n >= NB_PORTS) 564 goto read_default; 565 port = &s->ports[n]; 566 val = port->ctrl; 567 } 568 break; 569 default: 570 read_default: 571 val = 0xff7f; /* disabled port */ 572 break; 573 } 574 575 trace_usb_uhci_mmio_readw(addr, val); 576 577 return val; 578 } 579 580 /* signal resume if controller suspended */ 581 static void uhci_resume (void *opaque) 582 { 583 UHCIState *s = (UHCIState *)opaque; 584 585 if (!s) 586 return; 587 588 if (s->cmd & UHCI_CMD_EGSM) { 589 s->cmd |= UHCI_CMD_FGR; 590 s->status |= UHCI_STS_RD; 591 uhci_update_irq(s); 592 } 593 } 594 595 static void uhci_attach(USBPort *port1) 596 { 597 UHCIState *s = port1->opaque; 598 UHCIPort *port = &s->ports[port1->index]; 599 600 /* set connect status */ 601 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 602 603 /* update speed */ 604 if (port->port.dev->speed == USB_SPEED_LOW) { 605 port->ctrl |= UHCI_PORT_LSDA; 606 } else { 607 port->ctrl &= ~UHCI_PORT_LSDA; 608 } 609 610 uhci_resume(s); 611 } 612 613 static void uhci_detach(USBPort *port1) 614 { 615 UHCIState *s = port1->opaque; 616 UHCIPort *port = &s->ports[port1->index]; 617 618 uhci_async_cancel_device(s, port1->dev); 619 620 /* set connect status */ 621 if (port->ctrl & UHCI_PORT_CCS) { 622 port->ctrl &= ~UHCI_PORT_CCS; 623 port->ctrl |= UHCI_PORT_CSC; 624 } 625 /* disable port */ 626 if (port->ctrl & UHCI_PORT_EN) { 627 port->ctrl &= ~UHCI_PORT_EN; 628 port->ctrl |= UHCI_PORT_ENC; 629 } 630 631 uhci_resume(s); 632 } 633 634 static void uhci_child_detach(USBPort *port1, USBDevice *child) 635 { 636 UHCIState *s = port1->opaque; 637 638 uhci_async_cancel_device(s, child); 639 } 640 641 static void uhci_wakeup(USBPort *port1) 642 { 643 UHCIState *s = port1->opaque; 644 UHCIPort *port = &s->ports[port1->index]; 645 646 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 647 port->ctrl |= UHCI_PORT_RD; 648 uhci_resume(s); 649 } 650 } 651 652 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 653 { 654 USBDevice *dev; 655 int i; 656 657 for (i = 0; i < NB_PORTS; i++) { 658 UHCIPort *port = &s->ports[i]; 659 if (!(port->ctrl & UHCI_PORT_EN)) { 660 continue; 661 } 662 dev = usb_find_device(&port->port, addr); 663 if (dev != NULL) { 664 return dev; 665 } 666 } 667 return NULL; 668 } 669 670 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 671 { 672 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 673 le32_to_cpus(&td->link); 674 le32_to_cpus(&td->ctrl); 675 le32_to_cpus(&td->token); 676 le32_to_cpus(&td->buffer); 677 } 678 679 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 680 int status, uint32_t *int_mask) 681 { 682 uint32_t queue_token = uhci_queue_token(td); 683 int ret; 684 685 switch (status) { 686 case USB_RET_NAK: 687 td->ctrl |= TD_CTRL_NAK; 688 return TD_RESULT_NEXT_QH; 689 690 case USB_RET_STALL: 691 td->ctrl |= TD_CTRL_STALL; 692 trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 693 ret = TD_RESULT_NEXT_QH; 694 break; 695 696 case USB_RET_BABBLE: 697 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 698 /* frame interrupted */ 699 trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 700 ret = TD_RESULT_STOP_FRAME; 701 break; 702 703 case USB_RET_IOERROR: 704 case USB_RET_NODEV: 705 default: 706 td->ctrl |= TD_CTRL_TIMEOUT; 707 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 708 trace_usb_uhci_packet_complete_error(queue_token, td_addr); 709 ret = TD_RESULT_NEXT_QH; 710 break; 711 } 712 713 td->ctrl &= ~TD_CTRL_ACTIVE; 714 s->status |= UHCI_STS_USBERR; 715 if (td->ctrl & TD_CTRL_IOC) { 716 *int_mask |= 0x01; 717 } 718 uhci_update_irq(s); 719 return ret; 720 } 721 722 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 723 { 724 int len = 0, max_len; 725 uint8_t pid; 726 727 max_len = ((td->token >> 21) + 1) & 0x7ff; 728 pid = td->token & 0xff; 729 730 if (td->ctrl & TD_CTRL_IOS) 731 td->ctrl &= ~TD_CTRL_ACTIVE; 732 733 if (async->packet.status != USB_RET_SUCCESS) { 734 return uhci_handle_td_error(s, td, async->td_addr, 735 async->packet.status, int_mask); 736 } 737 738 len = async->packet.actual_length; 739 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 740 741 /* The NAK bit may have been set by a previous frame, so clear it 742 here. The docs are somewhat unclear, but win2k relies on this 743 behavior. */ 744 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 745 if (td->ctrl & TD_CTRL_IOC) 746 *int_mask |= 0x01; 747 748 if (pid == USB_TOKEN_IN) { 749 pci_dma_write(&s->dev, td->buffer, async->buf, len); 750 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 751 *int_mask |= 0x02; 752 /* short packet: do not update QH */ 753 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 754 async->td_addr); 755 return TD_RESULT_NEXT_QH; 756 } 757 } 758 759 /* success */ 760 trace_usb_uhci_packet_complete_success(async->queue->token, 761 async->td_addr); 762 return TD_RESULT_COMPLETE; 763 } 764 765 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 766 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 767 { 768 int ret, max_len; 769 bool spd; 770 bool queuing = (q != NULL); 771 uint8_t pid = td->token & 0xff; 772 UHCIAsync *async = uhci_async_find_td(s, td_addr); 773 774 if (async) { 775 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 776 assert(q == NULL || q == async->queue); 777 q = async->queue; 778 } else { 779 uhci_queue_free(async->queue, "guest re-used pending td"); 780 async = NULL; 781 } 782 } 783 784 if (q == NULL) { 785 q = uhci_queue_find(s, td); 786 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 787 uhci_queue_free(q, "guest re-used qh"); 788 q = NULL; 789 } 790 } 791 792 if (q) { 793 q->valid = QH_VALID; 794 } 795 796 /* Is active ? */ 797 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 798 if (async) { 799 /* Guest marked a pending td non-active, cancel the queue */ 800 uhci_queue_free(async->queue, "pending td non-active"); 801 } 802 /* 803 * ehci11d spec page 22: "Even if the Active bit in the TD is already 804 * cleared when the TD is fetched ... an IOC interrupt is generated" 805 */ 806 if (td->ctrl & TD_CTRL_IOC) { 807 *int_mask |= 0x01; 808 } 809 return TD_RESULT_NEXT_QH; 810 } 811 812 if (async) { 813 if (queuing) { 814 /* we are busy filling the queue, we are not prepared 815 to consume completed packages then, just leave them 816 in async state */ 817 return TD_RESULT_ASYNC_CONT; 818 } 819 if (!async->done) { 820 UHCI_TD last_td; 821 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head); 822 /* 823 * While we are waiting for the current td to complete, the guest 824 * may have added more tds to the queue. Note we re-read the td 825 * rather then caching it, as we want to see guest made changes! 826 */ 827 uhci_read_td(s, &last_td, last->td_addr); 828 uhci_queue_fill(async->queue, &last_td); 829 830 return TD_RESULT_ASYNC_CONT; 831 } 832 uhci_async_unlink(async); 833 goto done; 834 } 835 836 if (s->completions_only) { 837 return TD_RESULT_ASYNC_CONT; 838 } 839 840 /* Allocate new packet */ 841 if (q == NULL) { 842 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 843 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 844 845 if (ep == NULL) { 846 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 847 int_mask); 848 } 849 q = uhci_queue_new(s, qh_addr, td, ep); 850 } 851 async = uhci_async_alloc(q, td_addr); 852 853 max_len = ((td->token >> 21) + 1) & 0x7ff; 854 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 855 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 856 (td->ctrl & TD_CTRL_IOC) != 0); 857 if (max_len <= sizeof(async->static_buf)) { 858 async->buf = async->static_buf; 859 } else { 860 async->buf = g_malloc(max_len); 861 } 862 usb_packet_addbuf(&async->packet, async->buf, max_len); 863 864 switch(pid) { 865 case USB_TOKEN_OUT: 866 case USB_TOKEN_SETUP: 867 pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 868 usb_handle_packet(q->ep->dev, &async->packet); 869 if (async->packet.status == USB_RET_SUCCESS) { 870 async->packet.actual_length = max_len; 871 } 872 break; 873 874 case USB_TOKEN_IN: 875 usb_handle_packet(q->ep->dev, &async->packet); 876 break; 877 878 default: 879 /* invalid pid : frame interrupted */ 880 uhci_async_free(async); 881 s->status |= UHCI_STS_HCPERR; 882 uhci_update_irq(s); 883 return TD_RESULT_STOP_FRAME; 884 } 885 886 if (async->packet.status == USB_RET_ASYNC) { 887 uhci_async_link(async); 888 if (!queuing) { 889 uhci_queue_fill(q, td); 890 } 891 return TD_RESULT_ASYNC_START; 892 } 893 894 done: 895 ret = uhci_complete_td(s, td, async, int_mask); 896 uhci_async_free(async); 897 return ret; 898 } 899 900 static void uhci_async_complete(USBPort *port, USBPacket *packet) 901 { 902 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 903 UHCIState *s = async->queue->uhci; 904 905 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 906 uhci_async_cancel(async); 907 return; 908 } 909 910 async->done = 1; 911 /* Force processing of this packet *now*, needed for migration */ 912 s->completions_only = true; 913 qemu_bh_schedule(s->bh); 914 } 915 916 static int is_valid(uint32_t link) 917 { 918 return (link & 1) == 0; 919 } 920 921 static int is_qh(uint32_t link) 922 { 923 return (link & 2) != 0; 924 } 925 926 static int depth_first(uint32_t link) 927 { 928 return (link & 4) != 0; 929 } 930 931 /* QH DB used for detecting QH loops */ 932 #define UHCI_MAX_QUEUES 128 933 typedef struct { 934 uint32_t addr[UHCI_MAX_QUEUES]; 935 int count; 936 } QhDb; 937 938 static void qhdb_reset(QhDb *db) 939 { 940 db->count = 0; 941 } 942 943 /* Add QH to DB. Returns 1 if already present or DB is full. */ 944 static int qhdb_insert(QhDb *db, uint32_t addr) 945 { 946 int i; 947 for (i = 0; i < db->count; i++) 948 if (db->addr[i] == addr) 949 return 1; 950 951 if (db->count >= UHCI_MAX_QUEUES) 952 return 1; 953 954 db->addr[db->count++] = addr; 955 return 0; 956 } 957 958 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 959 { 960 uint32_t int_mask = 0; 961 uint32_t plink = td->link; 962 UHCI_TD ptd; 963 int ret; 964 965 while (is_valid(plink)) { 966 uhci_read_td(q->uhci, &ptd, plink); 967 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 968 break; 969 } 970 if (uhci_queue_token(&ptd) != q->token) { 971 break; 972 } 973 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 974 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 975 if (ret == TD_RESULT_ASYNC_CONT) { 976 break; 977 } 978 assert(ret == TD_RESULT_ASYNC_START); 979 assert(int_mask == 0); 980 plink = ptd.link; 981 } 982 usb_device_flush_ep_queue(q->ep->dev, q->ep); 983 } 984 985 static void uhci_process_frame(UHCIState *s) 986 { 987 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 988 uint32_t curr_qh, td_count = 0; 989 int cnt, ret; 990 UHCI_TD td; 991 UHCI_QH qh; 992 QhDb qhdb; 993 994 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 995 996 pci_dma_read(&s->dev, frame_addr, &link, 4); 997 le32_to_cpus(&link); 998 999 int_mask = 0; 1000 curr_qh = 0; 1001 1002 qhdb_reset(&qhdb); 1003 1004 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 1005 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 1006 /* We've reached the usb 1.1 bandwidth, which is 1007 1280 bytes/frame, stop processing */ 1008 trace_usb_uhci_frame_stop_bandwidth(); 1009 break; 1010 } 1011 if (is_qh(link)) { 1012 /* QH */ 1013 trace_usb_uhci_qh_load(link & ~0xf); 1014 1015 if (qhdb_insert(&qhdb, link)) { 1016 /* 1017 * We're going in circles. Which is not a bug because 1018 * HCD is allowed to do that as part of the BW management. 1019 * 1020 * Stop processing here if no transaction has been done 1021 * since we've been here last time. 1022 */ 1023 if (td_count == 0) { 1024 trace_usb_uhci_frame_loop_stop_idle(); 1025 break; 1026 } else { 1027 trace_usb_uhci_frame_loop_continue(); 1028 td_count = 0; 1029 qhdb_reset(&qhdb); 1030 qhdb_insert(&qhdb, link); 1031 } 1032 } 1033 1034 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1035 le32_to_cpus(&qh.link); 1036 le32_to_cpus(&qh.el_link); 1037 1038 if (!is_valid(qh.el_link)) { 1039 /* QH w/o elements */ 1040 curr_qh = 0; 1041 link = qh.link; 1042 } else { 1043 /* QH with elements */ 1044 curr_qh = link; 1045 link = qh.el_link; 1046 } 1047 continue; 1048 } 1049 1050 /* TD */ 1051 uhci_read_td(s, &td, link); 1052 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1053 1054 old_td_ctrl = td.ctrl; 1055 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1056 if (old_td_ctrl != td.ctrl) { 1057 /* update the status bits of the TD */ 1058 val = cpu_to_le32(td.ctrl); 1059 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1060 } 1061 1062 switch (ret) { 1063 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1064 goto out; 1065 1066 case TD_RESULT_NEXT_QH: 1067 case TD_RESULT_ASYNC_CONT: 1068 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1069 link = curr_qh ? qh.link : td.link; 1070 continue; 1071 1072 case TD_RESULT_ASYNC_START: 1073 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1074 link = curr_qh ? qh.link : td.link; 1075 continue; 1076 1077 case TD_RESULT_COMPLETE: 1078 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1079 link = td.link; 1080 td_count++; 1081 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1082 1083 if (curr_qh) { 1084 /* update QH element link */ 1085 qh.el_link = link; 1086 val = cpu_to_le32(qh.el_link); 1087 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1088 1089 if (!depth_first(link)) { 1090 /* done with this QH */ 1091 curr_qh = 0; 1092 link = qh.link; 1093 } 1094 } 1095 break; 1096 1097 default: 1098 assert(!"unknown return code"); 1099 } 1100 1101 /* go to the next entry */ 1102 } 1103 1104 out: 1105 s->pending_int_mask |= int_mask; 1106 } 1107 1108 static void uhci_bh(void *opaque) 1109 { 1110 UHCIState *s = opaque; 1111 uhci_process_frame(s); 1112 } 1113 1114 static void uhci_frame_timer(void *opaque) 1115 { 1116 UHCIState *s = opaque; 1117 uint64_t t_now, t_last_run; 1118 int i, frames; 1119 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ; 1120 1121 s->completions_only = false; 1122 qemu_bh_cancel(s->bh); 1123 1124 if (!(s->cmd & UHCI_CMD_RS)) { 1125 /* Full stop */ 1126 trace_usb_uhci_schedule_stop(); 1127 timer_del(s->frame_timer); 1128 uhci_async_cancel_all(s); 1129 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1130 s->status |= UHCI_STS_HCHALTED; 1131 return; 1132 } 1133 1134 /* We still store expire_time in our state, for migration */ 1135 t_last_run = s->expire_time - frame_t; 1136 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1137 1138 /* Process up to MAX_FRAMES_PER_TICK frames */ 1139 frames = (t_now - t_last_run) / frame_t; 1140 if (frames > s->maxframes) { 1141 int skipped = frames - s->maxframes; 1142 s->expire_time += skipped * frame_t; 1143 s->frnum = (s->frnum + skipped) & 0x7ff; 1144 frames -= skipped; 1145 } 1146 if (frames > MAX_FRAMES_PER_TICK) { 1147 frames = MAX_FRAMES_PER_TICK; 1148 } 1149 1150 for (i = 0; i < frames; i++) { 1151 s->frame_bytes = 0; 1152 trace_usb_uhci_frame_start(s->frnum); 1153 uhci_async_validate_begin(s); 1154 uhci_process_frame(s); 1155 uhci_async_validate_end(s); 1156 /* The spec says frnum is the frame currently being processed, and 1157 * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1158 s->frnum = (s->frnum + 1) & 0x7ff; 1159 s->expire_time += frame_t; 1160 } 1161 1162 /* Complete the previous frame(s) */ 1163 if (s->pending_int_mask) { 1164 s->status2 |= s->pending_int_mask; 1165 s->status |= UHCI_STS_USBINT; 1166 uhci_update_irq(s); 1167 } 1168 s->pending_int_mask = 0; 1169 1170 timer_mod(s->frame_timer, t_now + frame_t); 1171 } 1172 1173 static const MemoryRegionOps uhci_ioport_ops = { 1174 .read = uhci_port_read, 1175 .write = uhci_port_write, 1176 .valid.min_access_size = 1, 1177 .valid.max_access_size = 4, 1178 .impl.min_access_size = 2, 1179 .impl.max_access_size = 2, 1180 .endianness = DEVICE_LITTLE_ENDIAN, 1181 }; 1182 1183 static USBPortOps uhci_port_ops = { 1184 .attach = uhci_attach, 1185 .detach = uhci_detach, 1186 .child_detach = uhci_child_detach, 1187 .wakeup = uhci_wakeup, 1188 .complete = uhci_async_complete, 1189 }; 1190 1191 static USBBusOps uhci_bus_ops = { 1192 }; 1193 1194 static void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1195 { 1196 Error *err = NULL; 1197 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1198 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 1199 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1200 uint8_t *pci_conf = s->dev.config; 1201 int i; 1202 1203 pci_conf[PCI_CLASS_PROG] = 0x00; 1204 /* TODO: reset value should be 0. */ 1205 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1206 1207 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1208 1209 if (s->masterbus) { 1210 USBPort *ports[NB_PORTS]; 1211 for(i = 0; i < NB_PORTS; i++) { 1212 ports[i] = &s->ports[i].port; 1213 } 1214 usb_register_companion(s->masterbus, ports, NB_PORTS, 1215 s->firstport, s, &uhci_port_ops, 1216 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1217 &err); 1218 if (err) { 1219 error_propagate(errp, err); 1220 return; 1221 } 1222 } else { 1223 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1224 for (i = 0; i < NB_PORTS; i++) { 1225 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1226 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1227 } 1228 } 1229 s->bh = qemu_bh_new(uhci_bh, s); 1230 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1231 s->num_ports_vmstate = NB_PORTS; 1232 QTAILQ_INIT(&s->queues); 1233 1234 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 1235 "uhci", 0x20); 1236 1237 /* Use region 4 for consistency with real hardware. BSD guests seem 1238 to rely on this. */ 1239 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1240 } 1241 1242 static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) 1243 { 1244 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1245 uint8_t *pci_conf = s->dev.config; 1246 1247 /* USB misc control 1/2 */ 1248 pci_set_long(pci_conf + 0x40,0x00001000); 1249 /* PM capability */ 1250 pci_set_long(pci_conf + 0x80,0x00020001); 1251 /* USB legacy support */ 1252 pci_set_long(pci_conf + 0xc0,0x00002000); 1253 1254 usb_uhci_common_realize(dev, errp); 1255 } 1256 1257 static void usb_uhci_exit(PCIDevice *dev) 1258 { 1259 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1260 1261 trace_usb_uhci_exit(); 1262 1263 if (s->frame_timer) { 1264 timer_del(s->frame_timer); 1265 timer_free(s->frame_timer); 1266 s->frame_timer = NULL; 1267 } 1268 1269 if (s->bh) { 1270 qemu_bh_delete(s->bh); 1271 } 1272 1273 uhci_async_cancel_all(s); 1274 1275 if (!s->masterbus) { 1276 usb_bus_release(&s->bus); 1277 } 1278 } 1279 1280 static Property uhci_properties_companion[] = { 1281 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1282 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1283 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1284 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1285 DEFINE_PROP_END_OF_LIST(), 1286 }; 1287 static Property uhci_properties_standalone[] = { 1288 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1289 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1290 DEFINE_PROP_END_OF_LIST(), 1291 }; 1292 1293 static void uhci_class_init(ObjectClass *klass, void *data) 1294 { 1295 DeviceClass *dc = DEVICE_CLASS(klass); 1296 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1297 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 1298 UHCIInfo *info = data; 1299 1300 k->realize = info->realize ? info->realize : usb_uhci_common_realize; 1301 k->exit = info->unplug ? usb_uhci_exit : NULL; 1302 k->vendor_id = info->vendor_id; 1303 k->device_id = info->device_id; 1304 k->revision = info->revision; 1305 k->class_id = PCI_CLASS_SERIAL_USB; 1306 dc->vmsd = &vmstate_uhci; 1307 dc->reset = uhci_reset; 1308 if (!info->unplug) { 1309 /* uhci controllers in companion setups can't be hotplugged */ 1310 dc->hotpluggable = false; 1311 dc->props = uhci_properties_companion; 1312 } else { 1313 dc->props = uhci_properties_standalone; 1314 } 1315 set_bit(DEVICE_CATEGORY_USB, dc->categories); 1316 u->info = *info; 1317 } 1318 1319 static UHCIInfo uhci_info[] = { 1320 { 1321 .name = "piix3-usb-uhci", 1322 .vendor_id = PCI_VENDOR_ID_INTEL, 1323 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 1324 .revision = 0x01, 1325 .irq_pin = 3, 1326 .unplug = true, 1327 },{ 1328 .name = "piix4-usb-uhci", 1329 .vendor_id = PCI_VENDOR_ID_INTEL, 1330 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 1331 .revision = 0x01, 1332 .irq_pin = 3, 1333 .unplug = true, 1334 },{ 1335 .name = "vt82c686b-usb-uhci", 1336 .vendor_id = PCI_VENDOR_ID_VIA, 1337 .device_id = PCI_DEVICE_ID_VIA_UHCI, 1338 .revision = 0x01, 1339 .irq_pin = 3, 1340 .realize = usb_uhci_vt82c686b_realize, 1341 .unplug = true, 1342 },{ 1343 .name = "ich9-usb-uhci1", /* 00:1d.0 */ 1344 .vendor_id = PCI_VENDOR_ID_INTEL, 1345 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 1346 .revision = 0x03, 1347 .irq_pin = 0, 1348 .unplug = false, 1349 },{ 1350 .name = "ich9-usb-uhci2", /* 00:1d.1 */ 1351 .vendor_id = PCI_VENDOR_ID_INTEL, 1352 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 1353 .revision = 0x03, 1354 .irq_pin = 1, 1355 .unplug = false, 1356 },{ 1357 .name = "ich9-usb-uhci3", /* 00:1d.2 */ 1358 .vendor_id = PCI_VENDOR_ID_INTEL, 1359 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 1360 .revision = 0x03, 1361 .irq_pin = 2, 1362 .unplug = false, 1363 },{ 1364 .name = "ich9-usb-uhci4", /* 00:1a.0 */ 1365 .vendor_id = PCI_VENDOR_ID_INTEL, 1366 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 1367 .revision = 0x03, 1368 .irq_pin = 0, 1369 .unplug = false, 1370 },{ 1371 .name = "ich9-usb-uhci5", /* 00:1a.1 */ 1372 .vendor_id = PCI_VENDOR_ID_INTEL, 1373 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 1374 .revision = 0x03, 1375 .irq_pin = 1, 1376 .unplug = false, 1377 },{ 1378 .name = "ich9-usb-uhci6", /* 00:1a.2 */ 1379 .vendor_id = PCI_VENDOR_ID_INTEL, 1380 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 1381 .revision = 0x03, 1382 .irq_pin = 2, 1383 .unplug = false, 1384 } 1385 }; 1386 1387 static void uhci_register_types(void) 1388 { 1389 TypeInfo uhci_type_info = { 1390 .parent = TYPE_PCI_DEVICE, 1391 .instance_size = sizeof(UHCIState), 1392 .class_size = sizeof(UHCIPCIDeviceClass), 1393 .class_init = uhci_class_init, 1394 }; 1395 int i; 1396 1397 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 1398 uhci_type_info.name = uhci_info[i].name; 1399 uhci_type_info.class_data = uhci_info + i; 1400 type_register(&uhci_type_info); 1401 } 1402 } 1403 1404 type_init(uhci_register_types) 1405