1f1ae32a1SGerd Hoffmann /* 2f1ae32a1SGerd Hoffmann * USB UHCI controller emulation 3f1ae32a1SGerd Hoffmann * 4f1ae32a1SGerd Hoffmann * Copyright (c) 2005 Fabrice Bellard 5f1ae32a1SGerd Hoffmann * 6f1ae32a1SGerd Hoffmann * Copyright (c) 2008 Max Krasnyansky 7f1ae32a1SGerd Hoffmann * Magor rewrite of the UHCI data structures parser and frame processor 8f1ae32a1SGerd Hoffmann * Support for fully async operation and multiple outstanding transactions 9f1ae32a1SGerd Hoffmann * 10f1ae32a1SGerd Hoffmann * Permission is hereby granted, free of charge, to any person obtaining a copy 11f1ae32a1SGerd Hoffmann * of this software and associated documentation files (the "Software"), to deal 12f1ae32a1SGerd Hoffmann * in the Software without restriction, including without limitation the rights 13f1ae32a1SGerd Hoffmann * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14f1ae32a1SGerd Hoffmann * copies of the Software, and to permit persons to whom the Software is 15f1ae32a1SGerd Hoffmann * furnished to do so, subject to the following conditions: 16f1ae32a1SGerd Hoffmann * 17f1ae32a1SGerd Hoffmann * The above copyright notice and this permission notice shall be included in 18f1ae32a1SGerd Hoffmann * all copies or substantial portions of the Software. 19f1ae32a1SGerd Hoffmann * 20f1ae32a1SGerd Hoffmann * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21f1ae32a1SGerd Hoffmann * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22f1ae32a1SGerd Hoffmann * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23f1ae32a1SGerd Hoffmann * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24f1ae32a1SGerd Hoffmann * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25f1ae32a1SGerd Hoffmann * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26f1ae32a1SGerd Hoffmann * THE SOFTWARE. 27f1ae32a1SGerd Hoffmann */ 280b8fa32fSMarkus Armbruster 29e532b2e0SPeter Maydell #include "qemu/osdep.h" 30f1ae32a1SGerd Hoffmann #include "hw/usb.h" 319a1d111eSGerd Hoffmann #include "hw/usb/uhci-regs.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 33a2cb15b0SMichael S. Tsirkin #include "hw/pci/pci.h" 34a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 35da34e65cSMarkus Armbruster #include "qapi/error.h" 361de7afc9SPaolo Bonzini #include "qemu/timer.h" 371de7afc9SPaolo Bonzini #include "qemu/iov.h" 389c17d615SPaolo Bonzini #include "sysemu/dma.h" 3950dcc0f8SGerd Hoffmann #include "trace.h" 406a1751b7SAlex Bligh #include "qemu/main-loop.h" 410b8fa32fSMarkus Armbruster #include "qemu/module.h" 42db1015e9SEduardo Habkost #include "qom/object.h" 439a4e12a6SPhilippe Mathieu-Daudé #include "hcd-uhci.h" 44f1ae32a1SGerd Hoffmann 45f1ae32a1SGerd Hoffmann #define FRAME_TIMER_FREQ 1000 46f1ae32a1SGerd Hoffmann 47f1ae32a1SGerd Hoffmann #define FRAME_MAX_LOOPS 256 48f1ae32a1SGerd Hoffmann 49475443cfSHans de Goede /* Must be large enough to handle 10 frame delay for initial isoc requests */ 50475443cfSHans de Goede #define QH_VALID 32 51475443cfSHans de Goede 52f8f48b69SHans de Goede #define MAX_FRAMES_PER_TICK (QH_VALID / 2) 53f8f48b69SHans de Goede 5460e1b2a6SGerd Hoffmann enum { 550cd178caSGerd Hoffmann TD_RESULT_STOP_FRAME = 10, 560cd178caSGerd Hoffmann TD_RESULT_COMPLETE, 570cd178caSGerd Hoffmann TD_RESULT_NEXT_QH, 584efe4ef3SGerd Hoffmann TD_RESULT_ASYNC_START, 594efe4ef3SGerd Hoffmann TD_RESULT_ASYNC_CONT, 6060e1b2a6SGerd Hoffmann }; 6160e1b2a6SGerd Hoffmann 62f1ae32a1SGerd Hoffmann typedef struct UHCIState UHCIState; 63f1ae32a1SGerd Hoffmann typedef struct UHCIAsync UHCIAsync; 648f3f90b0SGerd Hoffmann typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; 652c2e8525SGerd Hoffmann 668f3f90b0SGerd Hoffmann struct UHCIPCIDeviceClass { 678f3f90b0SGerd Hoffmann PCIDeviceClass parent_class; 688f3f90b0SGerd Hoffmann UHCIInfo info; 698f3f90b0SGerd Hoffmann }; 708f3f90b0SGerd Hoffmann 71f1ae32a1SGerd Hoffmann /* 72f1ae32a1SGerd Hoffmann * Pending async transaction. 73f1ae32a1SGerd Hoffmann * 'packet' must be the first field because completion 74f1ae32a1SGerd Hoffmann * handler does "(UHCIAsync *) pkt" cast. 75f1ae32a1SGerd Hoffmann */ 76f1ae32a1SGerd Hoffmann 77f1ae32a1SGerd Hoffmann struct UHCIAsync { 78f1ae32a1SGerd Hoffmann USBPacket packet; 799822261cSHans de Goede uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */ 809822261cSHans de Goede uint8_t *buf; 81f1ae32a1SGerd Hoffmann UHCIQueue *queue; 82f1ae32a1SGerd Hoffmann QTAILQ_ENTRY(UHCIAsync) next; 831f250cc7SHans de Goede uint32_t td_addr; 84f1ae32a1SGerd Hoffmann uint8_t done; 85f1ae32a1SGerd Hoffmann }; 86f1ae32a1SGerd Hoffmann 87f1ae32a1SGerd Hoffmann struct UHCIQueue { 8866a08cbeSHans de Goede uint32_t qh_addr; 89f1ae32a1SGerd Hoffmann uint32_t token; 90f1ae32a1SGerd Hoffmann UHCIState *uhci; 9111d15e40SHans de Goede USBEndpoint *ep; 92f1ae32a1SGerd Hoffmann QTAILQ_ENTRY(UHCIQueue) next; 93eae3eb3eSPaolo Bonzini QTAILQ_HEAD(, UHCIAsync) asyncs; 94f1ae32a1SGerd Hoffmann int8_t valid; 95f1ae32a1SGerd Hoffmann }; 96f1ae32a1SGerd Hoffmann 97f1ae32a1SGerd Hoffmann typedef struct UHCI_TD { 98f1ae32a1SGerd Hoffmann uint32_t link; 99f1ae32a1SGerd Hoffmann uint32_t ctrl; /* see TD_CTRL_xxx */ 100f1ae32a1SGerd Hoffmann uint32_t token; 101f1ae32a1SGerd Hoffmann uint32_t buffer; 102f1ae32a1SGerd Hoffmann } UHCI_TD; 103f1ae32a1SGerd Hoffmann 104f1ae32a1SGerd Hoffmann typedef struct UHCI_QH { 105f1ae32a1SGerd Hoffmann uint32_t link; 106f1ae32a1SGerd Hoffmann uint32_t el_link; 107f1ae32a1SGerd Hoffmann } UHCI_QH; 108f1ae32a1SGerd Hoffmann 10940507377SHans de Goede static void uhci_async_cancel(UHCIAsync *async); 11011d15e40SHans de Goede static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 1119f0f1a0cSGerd Hoffmann static void uhci_resume(void *opaque); 11240507377SHans de Goede 113f1ae32a1SGerd Hoffmann static inline int32_t uhci_queue_token(UHCI_TD *td) 114f1ae32a1SGerd Hoffmann { 1156fe30910SHans de Goede if ((td->token & (0xf << 15)) == 0) { 1166fe30910SHans de Goede /* ctrl ep, cover ep and dev, not pid! */ 1176fe30910SHans de Goede return td->token & 0x7ff00; 1186fe30910SHans de Goede } else { 119f1ae32a1SGerd Hoffmann /* covers ep, dev, pid -> identifies the endpoint */ 120f1ae32a1SGerd Hoffmann return td->token & 0x7ffff; 121f1ae32a1SGerd Hoffmann } 1226fe30910SHans de Goede } 123f1ae32a1SGerd Hoffmann 12466a08cbeSHans de Goede static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td, 12566a08cbeSHans de Goede USBEndpoint *ep) 126f1ae32a1SGerd Hoffmann { 127f1ae32a1SGerd Hoffmann UHCIQueue *queue; 128f1ae32a1SGerd Hoffmann 129f1ae32a1SGerd Hoffmann queue = g_new0(UHCIQueue, 1); 130f1ae32a1SGerd Hoffmann queue->uhci = s; 13166a08cbeSHans de Goede queue->qh_addr = qh_addr; 13266a08cbeSHans de Goede queue->token = uhci_queue_token(td); 13311d15e40SHans de Goede queue->ep = ep; 134f1ae32a1SGerd Hoffmann QTAILQ_INIT(&queue->asyncs); 135f1ae32a1SGerd Hoffmann QTAILQ_INSERT_HEAD(&s->queues, queue, next); 136475443cfSHans de Goede queue->valid = QH_VALID; 13750dcc0f8SGerd Hoffmann trace_usb_uhci_queue_add(queue->token); 138f1ae32a1SGerd Hoffmann return queue; 139f1ae32a1SGerd Hoffmann } 140f1ae32a1SGerd Hoffmann 14166a08cbeSHans de Goede static void uhci_queue_free(UHCIQueue *queue, const char *reason) 142f1ae32a1SGerd Hoffmann { 143f1ae32a1SGerd Hoffmann UHCIState *s = queue->uhci; 14440507377SHans de Goede UHCIAsync *async; 14540507377SHans de Goede 14640507377SHans de Goede while (!QTAILQ_EMPTY(&queue->asyncs)) { 14740507377SHans de Goede async = QTAILQ_FIRST(&queue->asyncs); 14840507377SHans de Goede uhci_async_cancel(async); 14940507377SHans de Goede } 150f79738b0SHans de Goede usb_device_ep_stopped(queue->ep->dev, queue->ep); 151f1ae32a1SGerd Hoffmann 15266a08cbeSHans de Goede trace_usb_uhci_queue_del(queue->token, reason); 153f1ae32a1SGerd Hoffmann QTAILQ_REMOVE(&s->queues, queue, next); 154f1ae32a1SGerd Hoffmann g_free(queue); 155f1ae32a1SGerd Hoffmann } 156f1ae32a1SGerd Hoffmann 15766a08cbeSHans de Goede static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td) 15866a08cbeSHans de Goede { 15966a08cbeSHans de Goede uint32_t token = uhci_queue_token(td); 16066a08cbeSHans de Goede UHCIQueue *queue; 16166a08cbeSHans de Goede 16266a08cbeSHans de Goede QTAILQ_FOREACH(queue, &s->queues, next) { 16366a08cbeSHans de Goede if (queue->token == token) { 16466a08cbeSHans de Goede return queue; 16566a08cbeSHans de Goede } 16666a08cbeSHans de Goede } 16766a08cbeSHans de Goede return NULL; 16866a08cbeSHans de Goede } 16966a08cbeSHans de Goede 17066a08cbeSHans de Goede static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td, 17166a08cbeSHans de Goede uint32_t td_addr, bool queuing) 17266a08cbeSHans de Goede { 17366a08cbeSHans de Goede UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs); 174c348e481SGerd Hoffmann uint32_t queue_token_addr = (queue->token >> 8) & 0x7f; 17566a08cbeSHans de Goede 17666a08cbeSHans de Goede return queue->qh_addr == qh_addr && 17766a08cbeSHans de Goede queue->token == uhci_queue_token(td) && 178c348e481SGerd Hoffmann queue_token_addr == queue->ep->dev->addr && 17966a08cbeSHans de Goede (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL || 18066a08cbeSHans de Goede first->td_addr == td_addr); 18166a08cbeSHans de Goede } 18266a08cbeSHans de Goede 1831f250cc7SHans de Goede static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 184f1ae32a1SGerd Hoffmann { 185f1ae32a1SGerd Hoffmann UHCIAsync *async = g_new0(UHCIAsync, 1); 186f1ae32a1SGerd Hoffmann 187f1ae32a1SGerd Hoffmann async->queue = queue; 1881f250cc7SHans de Goede async->td_addr = td_addr; 189f1ae32a1SGerd Hoffmann usb_packet_init(&async->packet); 1901f250cc7SHans de Goede trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 191f1ae32a1SGerd Hoffmann 192f1ae32a1SGerd Hoffmann return async; 193f1ae32a1SGerd Hoffmann } 194f1ae32a1SGerd Hoffmann 195f1ae32a1SGerd Hoffmann static void uhci_async_free(UHCIAsync *async) 196f1ae32a1SGerd Hoffmann { 1971f250cc7SHans de Goede trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 198f1ae32a1SGerd Hoffmann usb_packet_cleanup(&async->packet); 1999822261cSHans de Goede if (async->buf != async->static_buf) { 2009822261cSHans de Goede g_free(async->buf); 2019822261cSHans de Goede } 202f1ae32a1SGerd Hoffmann g_free(async); 203f1ae32a1SGerd Hoffmann } 204f1ae32a1SGerd Hoffmann 205f1ae32a1SGerd Hoffmann static void uhci_async_link(UHCIAsync *async) 206f1ae32a1SGerd Hoffmann { 207f1ae32a1SGerd Hoffmann UHCIQueue *queue = async->queue; 208f1ae32a1SGerd Hoffmann QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 2091f250cc7SHans de Goede trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 210f1ae32a1SGerd Hoffmann } 211f1ae32a1SGerd Hoffmann 212f1ae32a1SGerd Hoffmann static void uhci_async_unlink(UHCIAsync *async) 213f1ae32a1SGerd Hoffmann { 214f1ae32a1SGerd Hoffmann UHCIQueue *queue = async->queue; 215f1ae32a1SGerd Hoffmann QTAILQ_REMOVE(&queue->asyncs, async, next); 2161f250cc7SHans de Goede trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 217f1ae32a1SGerd Hoffmann } 218f1ae32a1SGerd Hoffmann 219f1ae32a1SGerd Hoffmann static void uhci_async_cancel(UHCIAsync *async) 220f1ae32a1SGerd Hoffmann { 2212f2ee268SHans de Goede uhci_async_unlink(async); 2221f250cc7SHans de Goede trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 2231f250cc7SHans de Goede async->done); 224f1ae32a1SGerd Hoffmann if (!async->done) 225f1ae32a1SGerd Hoffmann usb_cancel_packet(&async->packet); 226f1ae32a1SGerd Hoffmann uhci_async_free(async); 227f1ae32a1SGerd Hoffmann } 228f1ae32a1SGerd Hoffmann 229f1ae32a1SGerd Hoffmann /* 230f1ae32a1SGerd Hoffmann * Mark all outstanding async packets as invalid. 231f1ae32a1SGerd Hoffmann * This is used for canceling them when TDs are removed by the HCD. 232f1ae32a1SGerd Hoffmann */ 233f1ae32a1SGerd Hoffmann static void uhci_async_validate_begin(UHCIState *s) 234f1ae32a1SGerd Hoffmann { 235f1ae32a1SGerd Hoffmann UHCIQueue *queue; 236f1ae32a1SGerd Hoffmann 237f1ae32a1SGerd Hoffmann QTAILQ_FOREACH(queue, &s->queues, next) { 238f1ae32a1SGerd Hoffmann queue->valid--; 239f1ae32a1SGerd Hoffmann } 240f1ae32a1SGerd Hoffmann } 241f1ae32a1SGerd Hoffmann 242f1ae32a1SGerd Hoffmann /* 243f1ae32a1SGerd Hoffmann * Cancel async packets that are no longer valid 244f1ae32a1SGerd Hoffmann */ 245f1ae32a1SGerd Hoffmann static void uhci_async_validate_end(UHCIState *s) 246f1ae32a1SGerd Hoffmann { 247f1ae32a1SGerd Hoffmann UHCIQueue *queue, *n; 248f1ae32a1SGerd Hoffmann 249f1ae32a1SGerd Hoffmann QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 25040507377SHans de Goede if (!queue->valid) { 25166a08cbeSHans de Goede uhci_queue_free(queue, "validate-end"); 252f1ae32a1SGerd Hoffmann } 253f1ae32a1SGerd Hoffmann } 25440507377SHans de Goede } 255f1ae32a1SGerd Hoffmann 256f1ae32a1SGerd Hoffmann static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 257f1ae32a1SGerd Hoffmann { 2585ad23e87SHans de Goede UHCIQueue *queue, *n; 259f1ae32a1SGerd Hoffmann 2605ad23e87SHans de Goede QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 2615ad23e87SHans de Goede if (queue->ep->dev == dev) { 2625ad23e87SHans de Goede uhci_queue_free(queue, "cancel-device"); 263f1ae32a1SGerd Hoffmann } 264f1ae32a1SGerd Hoffmann } 265f1ae32a1SGerd Hoffmann } 266f1ae32a1SGerd Hoffmann 267f1ae32a1SGerd Hoffmann static void uhci_async_cancel_all(UHCIState *s) 268f1ae32a1SGerd Hoffmann { 26977fa9aeeSGerd Hoffmann UHCIQueue *queue, *nq; 270f1ae32a1SGerd Hoffmann 27177fa9aeeSGerd Hoffmann QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 27266a08cbeSHans de Goede uhci_queue_free(queue, "cancel-all"); 273f1ae32a1SGerd Hoffmann } 274f1ae32a1SGerd Hoffmann } 275f1ae32a1SGerd Hoffmann 2768c75a899SHans de Goede static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr) 277f1ae32a1SGerd Hoffmann { 278f1ae32a1SGerd Hoffmann UHCIQueue *queue; 279f1ae32a1SGerd Hoffmann UHCIAsync *async; 280f1ae32a1SGerd Hoffmann 281f1ae32a1SGerd Hoffmann QTAILQ_FOREACH(queue, &s->queues, next) { 282f1ae32a1SGerd Hoffmann QTAILQ_FOREACH(async, &queue->asyncs, next) { 2831f250cc7SHans de Goede if (async->td_addr == td_addr) { 284f1ae32a1SGerd Hoffmann return async; 285f1ae32a1SGerd Hoffmann } 286f1ae32a1SGerd Hoffmann } 2878c75a899SHans de Goede } 288f1ae32a1SGerd Hoffmann return NULL; 289f1ae32a1SGerd Hoffmann } 290f1ae32a1SGerd Hoffmann 291f1ae32a1SGerd Hoffmann static void uhci_update_irq(UHCIState *s) 292f1ae32a1SGerd Hoffmann { 293*d3647ef1SBALATON Zoltan int level = 0; 294f1ae32a1SGerd Hoffmann if (((s->status2 & 1) && (s->intr & (1 << 2))) || 295f1ae32a1SGerd Hoffmann ((s->status2 & 2) && (s->intr & (1 << 3))) || 296f1ae32a1SGerd Hoffmann ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 297f1ae32a1SGerd Hoffmann ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 298f1ae32a1SGerd Hoffmann (s->status & UHCI_STS_HSERR) || 299f1ae32a1SGerd Hoffmann (s->status & UHCI_STS_HCPERR)) { 300f1ae32a1SGerd Hoffmann level = 1; 301f1ae32a1SGerd Hoffmann } 3029e64f8a3SMarcel Apfelbaum pci_set_irq(&s->dev, level); 303f1ae32a1SGerd Hoffmann } 304f1ae32a1SGerd Hoffmann 305537e572aSGonglei static void uhci_reset(DeviceState *dev) 306f1ae32a1SGerd Hoffmann { 307537e572aSGonglei PCIDevice *d = PCI_DEVICE(dev); 30849184b62SGonglei UHCIState *s = UHCI(d); 309f1ae32a1SGerd Hoffmann uint8_t *pci_conf; 310f1ae32a1SGerd Hoffmann int i; 311f1ae32a1SGerd Hoffmann UHCIPort *port; 312f1ae32a1SGerd Hoffmann 31350dcc0f8SGerd Hoffmann trace_usb_uhci_reset(); 314f1ae32a1SGerd Hoffmann 315f1ae32a1SGerd Hoffmann pci_conf = s->dev.config; 316f1ae32a1SGerd Hoffmann 317f1ae32a1SGerd Hoffmann pci_conf[0x6a] = 0x01; /* usb clock */ 318f1ae32a1SGerd Hoffmann pci_conf[0x6b] = 0x00; 319f1ae32a1SGerd Hoffmann s->cmd = 0; 320ca5a21c4SGerd Hoffmann s->status = UHCI_STS_HCHALTED; 321f1ae32a1SGerd Hoffmann s->status2 = 0; 322f1ae32a1SGerd Hoffmann s->intr = 0; 323f1ae32a1SGerd Hoffmann s->fl_base_addr = 0; 324f1ae32a1SGerd Hoffmann s->sof_timing = 64; 325f1ae32a1SGerd Hoffmann 326f1ae32a1SGerd Hoffmann for(i = 0; i < NB_PORTS; i++) { 327f1ae32a1SGerd Hoffmann port = &s->ports[i]; 328f1ae32a1SGerd Hoffmann port->ctrl = 0x0080; 329f1ae32a1SGerd Hoffmann if (port->port.dev && port->port.dev->attached) { 330f1ae32a1SGerd Hoffmann usb_port_reset(&port->port); 331f1ae32a1SGerd Hoffmann } 332f1ae32a1SGerd Hoffmann } 333f1ae32a1SGerd Hoffmann 334f1ae32a1SGerd Hoffmann uhci_async_cancel_all(s); 3359a16c595SGerd Hoffmann qemu_bh_cancel(s->bh); 336aba1f242SGerd Hoffmann uhci_update_irq(s); 337f1ae32a1SGerd Hoffmann } 338f1ae32a1SGerd Hoffmann 339f1ae32a1SGerd Hoffmann static const VMStateDescription vmstate_uhci_port = { 340f1ae32a1SGerd Hoffmann .name = "uhci port", 341f1ae32a1SGerd Hoffmann .version_id = 1, 342f1ae32a1SGerd Hoffmann .minimum_version_id = 1, 343f1ae32a1SGerd Hoffmann .fields = (VMStateField[]) { 344f1ae32a1SGerd Hoffmann VMSTATE_UINT16(ctrl, UHCIPort), 345f1ae32a1SGerd Hoffmann VMSTATE_END_OF_LIST() 346f1ae32a1SGerd Hoffmann } 347f1ae32a1SGerd Hoffmann }; 348f1ae32a1SGerd Hoffmann 34975f151cdSGerd Hoffmann static int uhci_post_load(void *opaque, int version_id) 35075f151cdSGerd Hoffmann { 35175f151cdSGerd Hoffmann UHCIState *s = opaque; 35275f151cdSGerd Hoffmann 35375f151cdSGerd Hoffmann if (version_id < 2) { 354bc72ad67SAlex Bligh s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 35573bcb24dSRutuja Shah (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 35675f151cdSGerd Hoffmann } 35775f151cdSGerd Hoffmann return 0; 35875f151cdSGerd Hoffmann } 35975f151cdSGerd Hoffmann 360f1ae32a1SGerd Hoffmann static const VMStateDescription vmstate_uhci = { 361f1ae32a1SGerd Hoffmann .name = "uhci", 362ecfdc15fSHans de Goede .version_id = 3, 363f1ae32a1SGerd Hoffmann .minimum_version_id = 1, 36475f151cdSGerd Hoffmann .post_load = uhci_post_load, 365f1ae32a1SGerd Hoffmann .fields = (VMStateField[]) { 366f1ae32a1SGerd Hoffmann VMSTATE_PCI_DEVICE(dev, UHCIState), 367d2164ad3SHalil Pasic VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState, NULL), 368f1ae32a1SGerd Hoffmann VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 369f1ae32a1SGerd Hoffmann vmstate_uhci_port, UHCIPort), 370f1ae32a1SGerd Hoffmann VMSTATE_UINT16(cmd, UHCIState), 371f1ae32a1SGerd Hoffmann VMSTATE_UINT16(status, UHCIState), 372f1ae32a1SGerd Hoffmann VMSTATE_UINT16(intr, UHCIState), 373f1ae32a1SGerd Hoffmann VMSTATE_UINT16(frnum, UHCIState), 374f1ae32a1SGerd Hoffmann VMSTATE_UINT32(fl_base_addr, UHCIState), 375f1ae32a1SGerd Hoffmann VMSTATE_UINT8(sof_timing, UHCIState), 376f1ae32a1SGerd Hoffmann VMSTATE_UINT8(status2, UHCIState), 377e720677eSPaolo Bonzini VMSTATE_TIMER_PTR(frame_timer, UHCIState), 378f1ae32a1SGerd Hoffmann VMSTATE_INT64_V(expire_time, UHCIState, 2), 379ecfdc15fSHans de Goede VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3), 380f1ae32a1SGerd Hoffmann VMSTATE_END_OF_LIST() 381f1ae32a1SGerd Hoffmann } 382f1ae32a1SGerd Hoffmann }; 383f1ae32a1SGerd Hoffmann 38489eb147cSGerd Hoffmann static void uhci_port_write(void *opaque, hwaddr addr, 38589eb147cSGerd Hoffmann uint64_t val, unsigned size) 386f1ae32a1SGerd Hoffmann { 387f1ae32a1SGerd Hoffmann UHCIState *s = opaque; 388f1ae32a1SGerd Hoffmann 38950dcc0f8SGerd Hoffmann trace_usb_uhci_mmio_writew(addr, val); 390f1ae32a1SGerd Hoffmann 391f1ae32a1SGerd Hoffmann switch(addr) { 392f1ae32a1SGerd Hoffmann case 0x00: 393f1ae32a1SGerd Hoffmann if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 394f1ae32a1SGerd Hoffmann /* start frame processing */ 39550dcc0f8SGerd Hoffmann trace_usb_uhci_schedule_start(); 396bc72ad67SAlex Bligh s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 39773bcb24dSRutuja Shah (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ); 398bc72ad67SAlex Bligh timer_mod(s->frame_timer, s->expire_time); 399f1ae32a1SGerd Hoffmann s->status &= ~UHCI_STS_HCHALTED; 400f1ae32a1SGerd Hoffmann } else if (!(val & UHCI_CMD_RS)) { 401f1ae32a1SGerd Hoffmann s->status |= UHCI_STS_HCHALTED; 402f1ae32a1SGerd Hoffmann } 403f1ae32a1SGerd Hoffmann if (val & UHCI_CMD_GRESET) { 404f1ae32a1SGerd Hoffmann UHCIPort *port; 405f1ae32a1SGerd Hoffmann int i; 406f1ae32a1SGerd Hoffmann 407f1ae32a1SGerd Hoffmann /* send reset on the USB bus */ 408f1ae32a1SGerd Hoffmann for(i = 0; i < NB_PORTS; i++) { 409f1ae32a1SGerd Hoffmann port = &s->ports[i]; 410f1ae32a1SGerd Hoffmann usb_device_reset(port->port.dev); 411f1ae32a1SGerd Hoffmann } 412537e572aSGonglei uhci_reset(DEVICE(s)); 413f1ae32a1SGerd Hoffmann return; 414f1ae32a1SGerd Hoffmann } 415f1ae32a1SGerd Hoffmann if (val & UHCI_CMD_HCRESET) { 416537e572aSGonglei uhci_reset(DEVICE(s)); 417f1ae32a1SGerd Hoffmann return; 418f1ae32a1SGerd Hoffmann } 419f1ae32a1SGerd Hoffmann s->cmd = val; 4209f0f1a0cSGerd Hoffmann if (val & UHCI_CMD_EGSM) { 4219f0f1a0cSGerd Hoffmann if ((s->ports[0].ctrl & UHCI_PORT_RD) || 4229f0f1a0cSGerd Hoffmann (s->ports[1].ctrl & UHCI_PORT_RD)) { 4239f0f1a0cSGerd Hoffmann uhci_resume(s); 4249f0f1a0cSGerd Hoffmann } 4259f0f1a0cSGerd Hoffmann } 426f1ae32a1SGerd Hoffmann break; 427f1ae32a1SGerd Hoffmann case 0x02: 428f1ae32a1SGerd Hoffmann s->status &= ~val; 429f1ae32a1SGerd Hoffmann /* XXX: the chip spec is not coherent, so we add a hidden 430f1ae32a1SGerd Hoffmann register to distinguish between IOC and SPD */ 431f1ae32a1SGerd Hoffmann if (val & UHCI_STS_USBINT) 432f1ae32a1SGerd Hoffmann s->status2 = 0; 433f1ae32a1SGerd Hoffmann uhci_update_irq(s); 434f1ae32a1SGerd Hoffmann break; 435f1ae32a1SGerd Hoffmann case 0x04: 436f1ae32a1SGerd Hoffmann s->intr = val; 437f1ae32a1SGerd Hoffmann uhci_update_irq(s); 438f1ae32a1SGerd Hoffmann break; 439f1ae32a1SGerd Hoffmann case 0x06: 440f1ae32a1SGerd Hoffmann if (s->status & UHCI_STS_HCHALTED) 441f1ae32a1SGerd Hoffmann s->frnum = val & 0x7ff; 442f1ae32a1SGerd Hoffmann break; 44389eb147cSGerd Hoffmann case 0x08: 44489eb147cSGerd Hoffmann s->fl_base_addr &= 0xffff0000; 44589eb147cSGerd Hoffmann s->fl_base_addr |= val & ~0xfff; 44689eb147cSGerd Hoffmann break; 44789eb147cSGerd Hoffmann case 0x0a: 44889eb147cSGerd Hoffmann s->fl_base_addr &= 0x0000ffff; 44989eb147cSGerd Hoffmann s->fl_base_addr |= (val << 16); 45089eb147cSGerd Hoffmann break; 45189eb147cSGerd Hoffmann case 0x0c: 45289eb147cSGerd Hoffmann s->sof_timing = val & 0xff; 45389eb147cSGerd Hoffmann break; 454f1ae32a1SGerd Hoffmann case 0x10 ... 0x1f: 455f1ae32a1SGerd Hoffmann { 456f1ae32a1SGerd Hoffmann UHCIPort *port; 457f1ae32a1SGerd Hoffmann USBDevice *dev; 458f1ae32a1SGerd Hoffmann int n; 459f1ae32a1SGerd Hoffmann 460f1ae32a1SGerd Hoffmann n = (addr >> 1) & 7; 461f1ae32a1SGerd Hoffmann if (n >= NB_PORTS) 462f1ae32a1SGerd Hoffmann return; 463f1ae32a1SGerd Hoffmann port = &s->ports[n]; 464f1ae32a1SGerd Hoffmann dev = port->port.dev; 465f1ae32a1SGerd Hoffmann if (dev && dev->attached) { 466f1ae32a1SGerd Hoffmann /* port reset */ 467f1ae32a1SGerd Hoffmann if ( (val & UHCI_PORT_RESET) && 468f1ae32a1SGerd Hoffmann !(port->ctrl & UHCI_PORT_RESET) ) { 469f1ae32a1SGerd Hoffmann usb_device_reset(dev); 470f1ae32a1SGerd Hoffmann } 471f1ae32a1SGerd Hoffmann } 472f1ae32a1SGerd Hoffmann port->ctrl &= UHCI_PORT_READ_ONLY; 4731cbdde90SHans de Goede /* enabled may only be set if a device is connected */ 4741cbdde90SHans de Goede if (!(port->ctrl & UHCI_PORT_CCS)) { 4751cbdde90SHans de Goede val &= ~UHCI_PORT_EN; 4761cbdde90SHans de Goede } 477f1ae32a1SGerd Hoffmann port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 478f1ae32a1SGerd Hoffmann /* some bits are reset when a '1' is written to them */ 479f1ae32a1SGerd Hoffmann port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 480f1ae32a1SGerd Hoffmann } 481f1ae32a1SGerd Hoffmann break; 482f1ae32a1SGerd Hoffmann } 483f1ae32a1SGerd Hoffmann } 484f1ae32a1SGerd Hoffmann 48589eb147cSGerd Hoffmann static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size) 486f1ae32a1SGerd Hoffmann { 487f1ae32a1SGerd Hoffmann UHCIState *s = opaque; 488f1ae32a1SGerd Hoffmann uint32_t val; 489f1ae32a1SGerd Hoffmann 490f1ae32a1SGerd Hoffmann switch(addr) { 491f1ae32a1SGerd Hoffmann case 0x00: 492f1ae32a1SGerd Hoffmann val = s->cmd; 493f1ae32a1SGerd Hoffmann break; 494f1ae32a1SGerd Hoffmann case 0x02: 495f1ae32a1SGerd Hoffmann val = s->status; 496f1ae32a1SGerd Hoffmann break; 497f1ae32a1SGerd Hoffmann case 0x04: 498f1ae32a1SGerd Hoffmann val = s->intr; 499f1ae32a1SGerd Hoffmann break; 500f1ae32a1SGerd Hoffmann case 0x06: 501f1ae32a1SGerd Hoffmann val = s->frnum; 502f1ae32a1SGerd Hoffmann break; 50389eb147cSGerd Hoffmann case 0x08: 50489eb147cSGerd Hoffmann val = s->fl_base_addr & 0xffff; 50589eb147cSGerd Hoffmann break; 50689eb147cSGerd Hoffmann case 0x0a: 50789eb147cSGerd Hoffmann val = (s->fl_base_addr >> 16) & 0xffff; 50889eb147cSGerd Hoffmann break; 50989eb147cSGerd Hoffmann case 0x0c: 51089eb147cSGerd Hoffmann val = s->sof_timing; 51189eb147cSGerd Hoffmann break; 512f1ae32a1SGerd Hoffmann case 0x10 ... 0x1f: 513f1ae32a1SGerd Hoffmann { 514f1ae32a1SGerd Hoffmann UHCIPort *port; 515f1ae32a1SGerd Hoffmann int n; 516f1ae32a1SGerd Hoffmann n = (addr >> 1) & 7; 517f1ae32a1SGerd Hoffmann if (n >= NB_PORTS) 518f1ae32a1SGerd Hoffmann goto read_default; 519f1ae32a1SGerd Hoffmann port = &s->ports[n]; 520f1ae32a1SGerd Hoffmann val = port->ctrl; 521f1ae32a1SGerd Hoffmann } 522f1ae32a1SGerd Hoffmann break; 523f1ae32a1SGerd Hoffmann default: 524f1ae32a1SGerd Hoffmann read_default: 525f1ae32a1SGerd Hoffmann val = 0xff7f; /* disabled port */ 526f1ae32a1SGerd Hoffmann break; 527f1ae32a1SGerd Hoffmann } 528f1ae32a1SGerd Hoffmann 52950dcc0f8SGerd Hoffmann trace_usb_uhci_mmio_readw(addr, val); 530f1ae32a1SGerd Hoffmann 531f1ae32a1SGerd Hoffmann return val; 532f1ae32a1SGerd Hoffmann } 533f1ae32a1SGerd Hoffmann 534f1ae32a1SGerd Hoffmann /* signal resume if controller suspended */ 535f1ae32a1SGerd Hoffmann static void uhci_resume (void *opaque) 536f1ae32a1SGerd Hoffmann { 537f1ae32a1SGerd Hoffmann UHCIState *s = (UHCIState *)opaque; 538f1ae32a1SGerd Hoffmann 539f1ae32a1SGerd Hoffmann if (!s) 540f1ae32a1SGerd Hoffmann return; 541f1ae32a1SGerd Hoffmann 542f1ae32a1SGerd Hoffmann if (s->cmd & UHCI_CMD_EGSM) { 543f1ae32a1SGerd Hoffmann s->cmd |= UHCI_CMD_FGR; 544f1ae32a1SGerd Hoffmann s->status |= UHCI_STS_RD; 545f1ae32a1SGerd Hoffmann uhci_update_irq(s); 546f1ae32a1SGerd Hoffmann } 547f1ae32a1SGerd Hoffmann } 548f1ae32a1SGerd Hoffmann 549f1ae32a1SGerd Hoffmann static void uhci_attach(USBPort *port1) 550f1ae32a1SGerd Hoffmann { 551f1ae32a1SGerd Hoffmann UHCIState *s = port1->opaque; 552f1ae32a1SGerd Hoffmann UHCIPort *port = &s->ports[port1->index]; 553f1ae32a1SGerd Hoffmann 554f1ae32a1SGerd Hoffmann /* set connect status */ 555f1ae32a1SGerd Hoffmann port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 556f1ae32a1SGerd Hoffmann 557f1ae32a1SGerd Hoffmann /* update speed */ 558f1ae32a1SGerd Hoffmann if (port->port.dev->speed == USB_SPEED_LOW) { 559f1ae32a1SGerd Hoffmann port->ctrl |= UHCI_PORT_LSDA; 560f1ae32a1SGerd Hoffmann } else { 561f1ae32a1SGerd Hoffmann port->ctrl &= ~UHCI_PORT_LSDA; 562f1ae32a1SGerd Hoffmann } 563f1ae32a1SGerd Hoffmann 564f1ae32a1SGerd Hoffmann uhci_resume(s); 565f1ae32a1SGerd Hoffmann } 566f1ae32a1SGerd Hoffmann 567f1ae32a1SGerd Hoffmann static void uhci_detach(USBPort *port1) 568f1ae32a1SGerd Hoffmann { 569f1ae32a1SGerd Hoffmann UHCIState *s = port1->opaque; 570f1ae32a1SGerd Hoffmann UHCIPort *port = &s->ports[port1->index]; 571f1ae32a1SGerd Hoffmann 572f1ae32a1SGerd Hoffmann uhci_async_cancel_device(s, port1->dev); 573f1ae32a1SGerd Hoffmann 574f1ae32a1SGerd Hoffmann /* set connect status */ 575f1ae32a1SGerd Hoffmann if (port->ctrl & UHCI_PORT_CCS) { 576f1ae32a1SGerd Hoffmann port->ctrl &= ~UHCI_PORT_CCS; 577f1ae32a1SGerd Hoffmann port->ctrl |= UHCI_PORT_CSC; 578f1ae32a1SGerd Hoffmann } 579f1ae32a1SGerd Hoffmann /* disable port */ 580f1ae32a1SGerd Hoffmann if (port->ctrl & UHCI_PORT_EN) { 581f1ae32a1SGerd Hoffmann port->ctrl &= ~UHCI_PORT_EN; 582f1ae32a1SGerd Hoffmann port->ctrl |= UHCI_PORT_ENC; 583f1ae32a1SGerd Hoffmann } 584f1ae32a1SGerd Hoffmann 585f1ae32a1SGerd Hoffmann uhci_resume(s); 586f1ae32a1SGerd Hoffmann } 587f1ae32a1SGerd Hoffmann 588f1ae32a1SGerd Hoffmann static void uhci_child_detach(USBPort *port1, USBDevice *child) 589f1ae32a1SGerd Hoffmann { 590f1ae32a1SGerd Hoffmann UHCIState *s = port1->opaque; 591f1ae32a1SGerd Hoffmann 592f1ae32a1SGerd Hoffmann uhci_async_cancel_device(s, child); 593f1ae32a1SGerd Hoffmann } 594f1ae32a1SGerd Hoffmann 595f1ae32a1SGerd Hoffmann static void uhci_wakeup(USBPort *port1) 596f1ae32a1SGerd Hoffmann { 597f1ae32a1SGerd Hoffmann UHCIState *s = port1->opaque; 598f1ae32a1SGerd Hoffmann UHCIPort *port = &s->ports[port1->index]; 599f1ae32a1SGerd Hoffmann 600f1ae32a1SGerd Hoffmann if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 601f1ae32a1SGerd Hoffmann port->ctrl |= UHCI_PORT_RD; 602f1ae32a1SGerd Hoffmann uhci_resume(s); 603f1ae32a1SGerd Hoffmann } 604f1ae32a1SGerd Hoffmann } 605f1ae32a1SGerd Hoffmann 606f1ae32a1SGerd Hoffmann static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 607f1ae32a1SGerd Hoffmann { 608f1ae32a1SGerd Hoffmann USBDevice *dev; 609f1ae32a1SGerd Hoffmann int i; 610f1ae32a1SGerd Hoffmann 611f1ae32a1SGerd Hoffmann for (i = 0; i < NB_PORTS; i++) { 612f1ae32a1SGerd Hoffmann UHCIPort *port = &s->ports[i]; 613f1ae32a1SGerd Hoffmann if (!(port->ctrl & UHCI_PORT_EN)) { 614f1ae32a1SGerd Hoffmann continue; 615f1ae32a1SGerd Hoffmann } 616f1ae32a1SGerd Hoffmann dev = usb_find_device(&port->port, addr); 617f1ae32a1SGerd Hoffmann if (dev != NULL) { 618f1ae32a1SGerd Hoffmann return dev; 619f1ae32a1SGerd Hoffmann } 620f1ae32a1SGerd Hoffmann } 621f1ae32a1SGerd Hoffmann return NULL; 622f1ae32a1SGerd Hoffmann } 623f1ae32a1SGerd Hoffmann 624963a68b5SHans de Goede static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 625963a68b5SHans de Goede { 626963a68b5SHans de Goede pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 627963a68b5SHans de Goede le32_to_cpus(&td->link); 628963a68b5SHans de Goede le32_to_cpus(&td->ctrl); 629963a68b5SHans de Goede le32_to_cpus(&td->token); 630963a68b5SHans de Goede le32_to_cpus(&td->buffer); 631963a68b5SHans de Goede } 632963a68b5SHans de Goede 633faccca00SHans de Goede static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, 634faccca00SHans de Goede int status, uint32_t *int_mask) 635faccca00SHans de Goede { 636faccca00SHans de Goede uint32_t queue_token = uhci_queue_token(td); 637faccca00SHans de Goede int ret; 638faccca00SHans de Goede 639faccca00SHans de Goede switch (status) { 640faccca00SHans de Goede case USB_RET_NAK: 641faccca00SHans de Goede td->ctrl |= TD_CTRL_NAK; 642faccca00SHans de Goede return TD_RESULT_NEXT_QH; 643faccca00SHans de Goede 644faccca00SHans de Goede case USB_RET_STALL: 645faccca00SHans de Goede td->ctrl |= TD_CTRL_STALL; 646faccca00SHans de Goede trace_usb_uhci_packet_complete_stall(queue_token, td_addr); 647faccca00SHans de Goede ret = TD_RESULT_NEXT_QH; 648faccca00SHans de Goede break; 649faccca00SHans de Goede 650faccca00SHans de Goede case USB_RET_BABBLE: 651faccca00SHans de Goede td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 652faccca00SHans de Goede /* frame interrupted */ 653faccca00SHans de Goede trace_usb_uhci_packet_complete_babble(queue_token, td_addr); 654faccca00SHans de Goede ret = TD_RESULT_STOP_FRAME; 655faccca00SHans de Goede break; 656faccca00SHans de Goede 657faccca00SHans de Goede case USB_RET_IOERROR: 658faccca00SHans de Goede case USB_RET_NODEV: 659faccca00SHans de Goede default: 660faccca00SHans de Goede td->ctrl |= TD_CTRL_TIMEOUT; 661faccca00SHans de Goede td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 662faccca00SHans de Goede trace_usb_uhci_packet_complete_error(queue_token, td_addr); 663faccca00SHans de Goede ret = TD_RESULT_NEXT_QH; 664faccca00SHans de Goede break; 665faccca00SHans de Goede } 666faccca00SHans de Goede 667faccca00SHans de Goede td->ctrl &= ~TD_CTRL_ACTIVE; 668faccca00SHans de Goede s->status |= UHCI_STS_USBERR; 669faccca00SHans de Goede if (td->ctrl & TD_CTRL_IOC) { 670faccca00SHans de Goede *int_mask |= 0x01; 671faccca00SHans de Goede } 672faccca00SHans de Goede uhci_update_irq(s); 673faccca00SHans de Goede return ret; 674faccca00SHans de Goede } 675faccca00SHans de Goede 676f1ae32a1SGerd Hoffmann static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 677f1ae32a1SGerd Hoffmann { 6789a77a0f5SHans de Goede int len = 0, max_len; 679f1ae32a1SGerd Hoffmann uint8_t pid; 680f1ae32a1SGerd Hoffmann 681f1ae32a1SGerd Hoffmann max_len = ((td->token >> 21) + 1) & 0x7ff; 682f1ae32a1SGerd Hoffmann pid = td->token & 0xff; 683f1ae32a1SGerd Hoffmann 684f1ae32a1SGerd Hoffmann if (td->ctrl & TD_CTRL_IOS) 685f1ae32a1SGerd Hoffmann td->ctrl &= ~TD_CTRL_ACTIVE; 686f1ae32a1SGerd Hoffmann 6879a77a0f5SHans de Goede if (async->packet.status != USB_RET_SUCCESS) { 6889a77a0f5SHans de Goede return uhci_handle_td_error(s, td, async->td_addr, 6899a77a0f5SHans de Goede async->packet.status, int_mask); 690faccca00SHans de Goede } 691f1ae32a1SGerd Hoffmann 6929a77a0f5SHans de Goede len = async->packet.actual_length; 693f1ae32a1SGerd Hoffmann td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 694f1ae32a1SGerd Hoffmann 695f1ae32a1SGerd Hoffmann /* The NAK bit may have been set by a previous frame, so clear it 696f1ae32a1SGerd Hoffmann here. The docs are somewhat unclear, but win2k relies on this 697f1ae32a1SGerd Hoffmann behavior. */ 698f1ae32a1SGerd Hoffmann td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 699f1ae32a1SGerd Hoffmann if (td->ctrl & TD_CTRL_IOC) 700f1ae32a1SGerd Hoffmann *int_mask |= 0x01; 701f1ae32a1SGerd Hoffmann 702f1ae32a1SGerd Hoffmann if (pid == USB_TOKEN_IN) { 7039822261cSHans de Goede pci_dma_write(&s->dev, td->buffer, async->buf, len); 704f1ae32a1SGerd Hoffmann if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 705f1ae32a1SGerd Hoffmann *int_mask |= 0x02; 706f1ae32a1SGerd Hoffmann /* short packet: do not update QH */ 70750dcc0f8SGerd Hoffmann trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 7081f250cc7SHans de Goede async->td_addr); 70960e1b2a6SGerd Hoffmann return TD_RESULT_NEXT_QH; 710f1ae32a1SGerd Hoffmann } 711f1ae32a1SGerd Hoffmann } 712f1ae32a1SGerd Hoffmann 713f1ae32a1SGerd Hoffmann /* success */ 7141f250cc7SHans de Goede trace_usb_uhci_packet_complete_success(async->queue->token, 7151f250cc7SHans de Goede async->td_addr); 71660e1b2a6SGerd Hoffmann return TD_RESULT_COMPLETE; 717f1ae32a1SGerd Hoffmann } 718f1ae32a1SGerd Hoffmann 71966a08cbeSHans de Goede static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, 720a4f30cd7SHans de Goede UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 721f1ae32a1SGerd Hoffmann { 7229a77a0f5SHans de Goede int ret, max_len; 7236ba43f1fSHans de Goede bool spd; 724a4f30cd7SHans de Goede bool queuing = (q != NULL); 72511d15e40SHans de Goede uint8_t pid = td->token & 0xff; 7265f77e06bSGonglei UHCIAsync *async; 7278c75a899SHans de Goede 7285f77e06bSGonglei async = uhci_async_find_td(s, td_addr); 7298c75a899SHans de Goede if (async) { 7308c75a899SHans de Goede if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) { 7318c75a899SHans de Goede assert(q == NULL || q == async->queue); 7328c75a899SHans de Goede q = async->queue; 7338c75a899SHans de Goede } else { 7348c75a899SHans de Goede uhci_queue_free(async->queue, "guest re-used pending td"); 7358c75a899SHans de Goede async = NULL; 7368c75a899SHans de Goede } 7378c75a899SHans de Goede } 738f1ae32a1SGerd Hoffmann 73966a08cbeSHans de Goede if (q == NULL) { 74066a08cbeSHans de Goede q = uhci_queue_find(s, td); 74166a08cbeSHans de Goede if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) { 74266a08cbeSHans de Goede uhci_queue_free(q, "guest re-used qh"); 74366a08cbeSHans de Goede q = NULL; 74466a08cbeSHans de Goede } 74566a08cbeSHans de Goede } 74666a08cbeSHans de Goede 7473905097eSHans de Goede if (q) { 748475443cfSHans de Goede q->valid = QH_VALID; 7493905097eSHans de Goede } 7503905097eSHans de Goede 751f1ae32a1SGerd Hoffmann /* Is active ? */ 752883bca77SHans de Goede if (!(td->ctrl & TD_CTRL_ACTIVE)) { 753420ca987SHans de Goede if (async) { 754420ca987SHans de Goede /* Guest marked a pending td non-active, cancel the queue */ 755420ca987SHans de Goede uhci_queue_free(async->queue, "pending td non-active"); 756420ca987SHans de Goede } 757883bca77SHans de Goede /* 758883bca77SHans de Goede * ehci11d spec page 22: "Even if the Active bit in the TD is already 759883bca77SHans de Goede * cleared when the TD is fetched ... an IOC interrupt is generated" 760883bca77SHans de Goede */ 761883bca77SHans de Goede if (td->ctrl & TD_CTRL_IOC) { 762883bca77SHans de Goede *int_mask |= 0x01; 763883bca77SHans de Goede } 76460e1b2a6SGerd Hoffmann return TD_RESULT_NEXT_QH; 765883bca77SHans de Goede } 766f1ae32a1SGerd Hoffmann 767f419a626SGerd Hoffmann switch (pid) { 768f419a626SGerd Hoffmann case USB_TOKEN_OUT: 769f419a626SGerd Hoffmann case USB_TOKEN_SETUP: 770f419a626SGerd Hoffmann case USB_TOKEN_IN: 771f419a626SGerd Hoffmann break; 772f419a626SGerd Hoffmann default: 773f419a626SGerd Hoffmann /* invalid pid : frame interrupted */ 774f419a626SGerd Hoffmann s->status |= UHCI_STS_HCPERR; 775f419a626SGerd Hoffmann s->cmd &= ~UHCI_CMD_RS; 776f419a626SGerd Hoffmann uhci_update_irq(s); 777f419a626SGerd Hoffmann return TD_RESULT_STOP_FRAME; 778f419a626SGerd Hoffmann } 779f419a626SGerd Hoffmann 780f1ae32a1SGerd Hoffmann if (async) { 781ee008ba6SGerd Hoffmann if (queuing) { 782ee008ba6SGerd Hoffmann /* we are busy filling the queue, we are not prepared 783ee008ba6SGerd Hoffmann to consume completed packages then, just leave them 784ee008ba6SGerd Hoffmann in async state */ 785ee008ba6SGerd Hoffmann return TD_RESULT_ASYNC_CONT; 786ee008ba6SGerd Hoffmann } 7878928c9c4SHans de Goede if (!async->done) { 7888928c9c4SHans de Goede UHCI_TD last_td; 789eae3eb3eSPaolo Bonzini UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs); 7908928c9c4SHans de Goede /* 7918928c9c4SHans de Goede * While we are waiting for the current td to complete, the guest 7928928c9c4SHans de Goede * may have added more tds to the queue. Note we re-read the td 7938928c9c4SHans de Goede * rather then caching it, as we want to see guest made changes! 7948928c9c4SHans de Goede */ 7958928c9c4SHans de Goede uhci_read_td(s, &last_td, last->td_addr); 7968928c9c4SHans de Goede uhci_queue_fill(async->queue, &last_td); 797f1ae32a1SGerd Hoffmann 7988928c9c4SHans de Goede return TD_RESULT_ASYNC_CONT; 7998928c9c4SHans de Goede } 800f1ae32a1SGerd Hoffmann uhci_async_unlink(async); 801f1ae32a1SGerd Hoffmann goto done; 802f1ae32a1SGerd Hoffmann } 803f1ae32a1SGerd Hoffmann 80488793816SHans de Goede if (s->completions_only) { 80588793816SHans de Goede return TD_RESULT_ASYNC_CONT; 80688793816SHans de Goede } 80788793816SHans de Goede 808f1ae32a1SGerd Hoffmann /* Allocate new packet */ 809a4f30cd7SHans de Goede if (q == NULL) { 810ff668537SLiam Merwick USBDevice *dev; 811ff668537SLiam Merwick USBEndpoint *ep; 8127f102ebeSHans de Goede 813ff668537SLiam Merwick dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 814ff668537SLiam Merwick if (dev == NULL) { 8157f102ebeSHans de Goede return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, 8167f102ebeSHans de Goede int_mask); 8177f102ebeSHans de Goede } 818ff668537SLiam Merwick ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 81966a08cbeSHans de Goede q = uhci_queue_new(s, qh_addr, td, ep); 820a4f30cd7SHans de Goede } 821a4f30cd7SHans de Goede async = uhci_async_alloc(q, td_addr); 822f1ae32a1SGerd Hoffmann 823f1ae32a1SGerd Hoffmann max_len = ((td->token >> 21) + 1) & 0x7ff; 8246ba43f1fSHans de Goede spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 8258550a02dSGerd Hoffmann usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd, 826a6fb2ddbSHans de Goede (td->ctrl & TD_CTRL_IOC) != 0); 8279822261cSHans de Goede if (max_len <= sizeof(async->static_buf)) { 8289822261cSHans de Goede async->buf = async->static_buf; 8299822261cSHans de Goede } else { 8309822261cSHans de Goede async->buf = g_malloc(max_len); 8319822261cSHans de Goede } 8329822261cSHans de Goede usb_packet_addbuf(&async->packet, async->buf, max_len); 833f1ae32a1SGerd Hoffmann 834f1ae32a1SGerd Hoffmann switch(pid) { 835f1ae32a1SGerd Hoffmann case USB_TOKEN_OUT: 836f1ae32a1SGerd Hoffmann case USB_TOKEN_SETUP: 8379822261cSHans de Goede pci_dma_read(&s->dev, td->buffer, async->buf, max_len); 8389a77a0f5SHans de Goede usb_handle_packet(q->ep->dev, &async->packet); 8399a77a0f5SHans de Goede if (async->packet.status == USB_RET_SUCCESS) { 8409a77a0f5SHans de Goede async->packet.actual_length = max_len; 8419a77a0f5SHans de Goede } 842f1ae32a1SGerd Hoffmann break; 843f1ae32a1SGerd Hoffmann 844f1ae32a1SGerd Hoffmann case USB_TOKEN_IN: 8459a77a0f5SHans de Goede usb_handle_packet(q->ep->dev, &async->packet); 846f1ae32a1SGerd Hoffmann break; 847f1ae32a1SGerd Hoffmann 848f1ae32a1SGerd Hoffmann default: 8495f77e06bSGonglei abort(); /* Never to execute */ 850f1ae32a1SGerd Hoffmann } 851f1ae32a1SGerd Hoffmann 8529a77a0f5SHans de Goede if (async->packet.status == USB_RET_ASYNC) { 853f1ae32a1SGerd Hoffmann uhci_async_link(async); 854a4f30cd7SHans de Goede if (!queuing) { 85511d15e40SHans de Goede uhci_queue_fill(q, td); 856a4f30cd7SHans de Goede } 8574efe4ef3SGerd Hoffmann return TD_RESULT_ASYNC_START; 858f1ae32a1SGerd Hoffmann } 859f1ae32a1SGerd Hoffmann 860f1ae32a1SGerd Hoffmann done: 8619a77a0f5SHans de Goede ret = uhci_complete_td(s, td, async, int_mask); 862f1ae32a1SGerd Hoffmann uhci_async_free(async); 8639a77a0f5SHans de Goede return ret; 864f1ae32a1SGerd Hoffmann } 865f1ae32a1SGerd Hoffmann 866f1ae32a1SGerd Hoffmann static void uhci_async_complete(USBPort *port, USBPacket *packet) 867f1ae32a1SGerd Hoffmann { 868f1ae32a1SGerd Hoffmann UHCIAsync *async = container_of(packet, UHCIAsync, packet); 869f1ae32a1SGerd Hoffmann UHCIState *s = async->queue->uhci; 870f1ae32a1SGerd Hoffmann 8719a77a0f5SHans de Goede if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 8720cae7b1aSHans de Goede uhci_async_cancel(async); 8730cae7b1aSHans de Goede return; 8740cae7b1aSHans de Goede } 8750cae7b1aSHans de Goede 876f1ae32a1SGerd Hoffmann async->done = 1; 87788793816SHans de Goede /* Force processing of this packet *now*, needed for migration */ 87888793816SHans de Goede s->completions_only = true; 8799a16c595SGerd Hoffmann qemu_bh_schedule(s->bh); 8809a16c595SGerd Hoffmann } 881f1ae32a1SGerd Hoffmann 882f1ae32a1SGerd Hoffmann static int is_valid(uint32_t link) 883f1ae32a1SGerd Hoffmann { 884f1ae32a1SGerd Hoffmann return (link & 1) == 0; 885f1ae32a1SGerd Hoffmann } 886f1ae32a1SGerd Hoffmann 887f1ae32a1SGerd Hoffmann static int is_qh(uint32_t link) 888f1ae32a1SGerd Hoffmann { 889f1ae32a1SGerd Hoffmann return (link & 2) != 0; 890f1ae32a1SGerd Hoffmann } 891f1ae32a1SGerd Hoffmann 892f1ae32a1SGerd Hoffmann static int depth_first(uint32_t link) 893f1ae32a1SGerd Hoffmann { 894f1ae32a1SGerd Hoffmann return (link & 4) != 0; 895f1ae32a1SGerd Hoffmann } 896f1ae32a1SGerd Hoffmann 897f1ae32a1SGerd Hoffmann /* QH DB used for detecting QH loops */ 898f1ae32a1SGerd Hoffmann #define UHCI_MAX_QUEUES 128 899f1ae32a1SGerd Hoffmann typedef struct { 900f1ae32a1SGerd Hoffmann uint32_t addr[UHCI_MAX_QUEUES]; 901f1ae32a1SGerd Hoffmann int count; 902f1ae32a1SGerd Hoffmann } QhDb; 903f1ae32a1SGerd Hoffmann 904f1ae32a1SGerd Hoffmann static void qhdb_reset(QhDb *db) 905f1ae32a1SGerd Hoffmann { 906f1ae32a1SGerd Hoffmann db->count = 0; 907f1ae32a1SGerd Hoffmann } 908f1ae32a1SGerd Hoffmann 909f1ae32a1SGerd Hoffmann /* Add QH to DB. Returns 1 if already present or DB is full. */ 910f1ae32a1SGerd Hoffmann static int qhdb_insert(QhDb *db, uint32_t addr) 911f1ae32a1SGerd Hoffmann { 912f1ae32a1SGerd Hoffmann int i; 913f1ae32a1SGerd Hoffmann for (i = 0; i < db->count; i++) 914f1ae32a1SGerd Hoffmann if (db->addr[i] == addr) 915f1ae32a1SGerd Hoffmann return 1; 916f1ae32a1SGerd Hoffmann 917f1ae32a1SGerd Hoffmann if (db->count >= UHCI_MAX_QUEUES) 918f1ae32a1SGerd Hoffmann return 1; 919f1ae32a1SGerd Hoffmann 920f1ae32a1SGerd Hoffmann db->addr[db->count++] = addr; 921f1ae32a1SGerd Hoffmann return 0; 922f1ae32a1SGerd Hoffmann } 923f1ae32a1SGerd Hoffmann 92411d15e40SHans de Goede static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 925f1ae32a1SGerd Hoffmann { 926f1ae32a1SGerd Hoffmann uint32_t int_mask = 0; 927f1ae32a1SGerd Hoffmann uint32_t plink = td->link; 928f1ae32a1SGerd Hoffmann UHCI_TD ptd; 929f1ae32a1SGerd Hoffmann int ret; 930f1ae32a1SGerd Hoffmann 9316ba43f1fSHans de Goede while (is_valid(plink)) { 932a4f30cd7SHans de Goede uhci_read_td(q->uhci, &ptd, plink); 933f1ae32a1SGerd Hoffmann if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 934f1ae32a1SGerd Hoffmann break; 935f1ae32a1SGerd Hoffmann } 936a4f30cd7SHans de Goede if (uhci_queue_token(&ptd) != q->token) { 937f1ae32a1SGerd Hoffmann break; 938f1ae32a1SGerd Hoffmann } 93950dcc0f8SGerd Hoffmann trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 94066a08cbeSHans de Goede ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask); 94152b0fecdSGerd Hoffmann if (ret == TD_RESULT_ASYNC_CONT) { 94252b0fecdSGerd Hoffmann break; 94352b0fecdSGerd Hoffmann } 9444efe4ef3SGerd Hoffmann assert(ret == TD_RESULT_ASYNC_START); 945f1ae32a1SGerd Hoffmann assert(int_mask == 0); 946f1ae32a1SGerd Hoffmann plink = ptd.link; 947f1ae32a1SGerd Hoffmann } 94811d15e40SHans de Goede usb_device_flush_ep_queue(q->ep->dev, q->ep); 949f1ae32a1SGerd Hoffmann } 950f1ae32a1SGerd Hoffmann 951f1ae32a1SGerd Hoffmann static void uhci_process_frame(UHCIState *s) 952f1ae32a1SGerd Hoffmann { 953f1ae32a1SGerd Hoffmann uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 9544aed20e2SGerd Hoffmann uint32_t curr_qh, td_count = 0; 955f1ae32a1SGerd Hoffmann int cnt, ret; 956f1ae32a1SGerd Hoffmann UHCI_TD td; 957f1ae32a1SGerd Hoffmann UHCI_QH qh; 958f1ae32a1SGerd Hoffmann QhDb qhdb; 959f1ae32a1SGerd Hoffmann 960f1ae32a1SGerd Hoffmann frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 961f1ae32a1SGerd Hoffmann 962f1ae32a1SGerd Hoffmann pci_dma_read(&s->dev, frame_addr, &link, 4); 963f1ae32a1SGerd Hoffmann le32_to_cpus(&link); 964f1ae32a1SGerd Hoffmann 965f1ae32a1SGerd Hoffmann int_mask = 0; 966f1ae32a1SGerd Hoffmann curr_qh = 0; 967f1ae32a1SGerd Hoffmann 968f1ae32a1SGerd Hoffmann qhdb_reset(&qhdb); 969f1ae32a1SGerd Hoffmann 970f1ae32a1SGerd Hoffmann for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 97188793816SHans de Goede if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) { 9724aed20e2SGerd Hoffmann /* We've reached the usb 1.1 bandwidth, which is 9734aed20e2SGerd Hoffmann 1280 bytes/frame, stop processing */ 9744aed20e2SGerd Hoffmann trace_usb_uhci_frame_stop_bandwidth(); 9754aed20e2SGerd Hoffmann break; 9764aed20e2SGerd Hoffmann } 977f1ae32a1SGerd Hoffmann if (is_qh(link)) { 978f1ae32a1SGerd Hoffmann /* QH */ 97950dcc0f8SGerd Hoffmann trace_usb_uhci_qh_load(link & ~0xf); 980f1ae32a1SGerd Hoffmann 981f1ae32a1SGerd Hoffmann if (qhdb_insert(&qhdb, link)) { 982f1ae32a1SGerd Hoffmann /* 983f1ae32a1SGerd Hoffmann * We're going in circles. Which is not a bug because 984f1ae32a1SGerd Hoffmann * HCD is allowed to do that as part of the BW management. 985f1ae32a1SGerd Hoffmann * 9864aed20e2SGerd Hoffmann * Stop processing here if no transaction has been done 9874aed20e2SGerd Hoffmann * since we've been here last time. 988f1ae32a1SGerd Hoffmann */ 989f1ae32a1SGerd Hoffmann if (td_count == 0) { 99050dcc0f8SGerd Hoffmann trace_usb_uhci_frame_loop_stop_idle(); 991f1ae32a1SGerd Hoffmann break; 992f1ae32a1SGerd Hoffmann } else { 99350dcc0f8SGerd Hoffmann trace_usb_uhci_frame_loop_continue(); 994f1ae32a1SGerd Hoffmann td_count = 0; 995f1ae32a1SGerd Hoffmann qhdb_reset(&qhdb); 996f1ae32a1SGerd Hoffmann qhdb_insert(&qhdb, link); 997f1ae32a1SGerd Hoffmann } 998f1ae32a1SGerd Hoffmann } 999f1ae32a1SGerd Hoffmann 1000f1ae32a1SGerd Hoffmann pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1001f1ae32a1SGerd Hoffmann le32_to_cpus(&qh.link); 1002f1ae32a1SGerd Hoffmann le32_to_cpus(&qh.el_link); 1003f1ae32a1SGerd Hoffmann 1004f1ae32a1SGerd Hoffmann if (!is_valid(qh.el_link)) { 1005f1ae32a1SGerd Hoffmann /* QH w/o elements */ 1006f1ae32a1SGerd Hoffmann curr_qh = 0; 1007f1ae32a1SGerd Hoffmann link = qh.link; 1008f1ae32a1SGerd Hoffmann } else { 1009f1ae32a1SGerd Hoffmann /* QH with elements */ 1010f1ae32a1SGerd Hoffmann curr_qh = link; 1011f1ae32a1SGerd Hoffmann link = qh.el_link; 1012f1ae32a1SGerd Hoffmann } 1013f1ae32a1SGerd Hoffmann continue; 1014f1ae32a1SGerd Hoffmann } 1015f1ae32a1SGerd Hoffmann 1016f1ae32a1SGerd Hoffmann /* TD */ 1017963a68b5SHans de Goede uhci_read_td(s, &td, link); 101850dcc0f8SGerd Hoffmann trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1019f1ae32a1SGerd Hoffmann 1020f1ae32a1SGerd Hoffmann old_td_ctrl = td.ctrl; 102166a08cbeSHans de Goede ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask); 1022f1ae32a1SGerd Hoffmann if (old_td_ctrl != td.ctrl) { 1023f1ae32a1SGerd Hoffmann /* update the status bits of the TD */ 1024f1ae32a1SGerd Hoffmann val = cpu_to_le32(td.ctrl); 1025f1ae32a1SGerd Hoffmann pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1026f1ae32a1SGerd Hoffmann } 1027f1ae32a1SGerd Hoffmann 1028f1ae32a1SGerd Hoffmann switch (ret) { 102960e1b2a6SGerd Hoffmann case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1030f1ae32a1SGerd Hoffmann goto out; 1031f1ae32a1SGerd Hoffmann 103260e1b2a6SGerd Hoffmann case TD_RESULT_NEXT_QH: 10334efe4ef3SGerd Hoffmann case TD_RESULT_ASYNC_CONT: 103450dcc0f8SGerd Hoffmann trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1035f1ae32a1SGerd Hoffmann link = curr_qh ? qh.link : td.link; 1036f1ae32a1SGerd Hoffmann continue; 1037f1ae32a1SGerd Hoffmann 10384efe4ef3SGerd Hoffmann case TD_RESULT_ASYNC_START: 103950dcc0f8SGerd Hoffmann trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1040f1ae32a1SGerd Hoffmann link = curr_qh ? qh.link : td.link; 1041f1ae32a1SGerd Hoffmann continue; 1042f1ae32a1SGerd Hoffmann 104360e1b2a6SGerd Hoffmann case TD_RESULT_COMPLETE: 104450dcc0f8SGerd Hoffmann trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1045f1ae32a1SGerd Hoffmann link = td.link; 1046f1ae32a1SGerd Hoffmann td_count++; 10474aed20e2SGerd Hoffmann s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1048f1ae32a1SGerd Hoffmann 1049f1ae32a1SGerd Hoffmann if (curr_qh) { 1050f1ae32a1SGerd Hoffmann /* update QH element link */ 1051f1ae32a1SGerd Hoffmann qh.el_link = link; 1052f1ae32a1SGerd Hoffmann val = cpu_to_le32(qh.el_link); 1053f1ae32a1SGerd Hoffmann pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1054f1ae32a1SGerd Hoffmann 1055f1ae32a1SGerd Hoffmann if (!depth_first(link)) { 1056f1ae32a1SGerd Hoffmann /* done with this QH */ 1057f1ae32a1SGerd Hoffmann curr_qh = 0; 1058f1ae32a1SGerd Hoffmann link = qh.link; 1059f1ae32a1SGerd Hoffmann } 1060f1ae32a1SGerd Hoffmann } 1061f1ae32a1SGerd Hoffmann break; 1062f1ae32a1SGerd Hoffmann 1063f1ae32a1SGerd Hoffmann default: 1064f1ae32a1SGerd Hoffmann assert(!"unknown return code"); 1065f1ae32a1SGerd Hoffmann } 1066f1ae32a1SGerd Hoffmann 1067f1ae32a1SGerd Hoffmann /* go to the next entry */ 1068f1ae32a1SGerd Hoffmann } 1069f1ae32a1SGerd Hoffmann 1070f1ae32a1SGerd Hoffmann out: 1071f1ae32a1SGerd Hoffmann s->pending_int_mask |= int_mask; 1072f1ae32a1SGerd Hoffmann } 1073f1ae32a1SGerd Hoffmann 10749a16c595SGerd Hoffmann static void uhci_bh(void *opaque) 10759a16c595SGerd Hoffmann { 10769a16c595SGerd Hoffmann UHCIState *s = opaque; 10779a16c595SGerd Hoffmann uhci_process_frame(s); 10789a16c595SGerd Hoffmann } 10799a16c595SGerd Hoffmann 1080f1ae32a1SGerd Hoffmann static void uhci_frame_timer(void *opaque) 1081f1ae32a1SGerd Hoffmann { 1082f1ae32a1SGerd Hoffmann UHCIState *s = opaque; 1083f8f48b69SHans de Goede uint64_t t_now, t_last_run; 1084f8f48b69SHans de Goede int i, frames; 108573bcb24dSRutuja Shah const uint64_t frame_t = NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ; 1086f1ae32a1SGerd Hoffmann 108788793816SHans de Goede s->completions_only = false; 10889a16c595SGerd Hoffmann qemu_bh_cancel(s->bh); 1089f1ae32a1SGerd Hoffmann 1090f1ae32a1SGerd Hoffmann if (!(s->cmd & UHCI_CMD_RS)) { 1091f1ae32a1SGerd Hoffmann /* Full stop */ 109250dcc0f8SGerd Hoffmann trace_usb_uhci_schedule_stop(); 1093bc72ad67SAlex Bligh timer_del(s->frame_timer); 1094d9a528dbSGerd Hoffmann uhci_async_cancel_all(s); 1095f1ae32a1SGerd Hoffmann /* set hchalted bit in status - UHCI11D 2.1.2 */ 1096f1ae32a1SGerd Hoffmann s->status |= UHCI_STS_HCHALTED; 1097f1ae32a1SGerd Hoffmann return; 1098f1ae32a1SGerd Hoffmann } 1099f1ae32a1SGerd Hoffmann 1100f8f48b69SHans de Goede /* We still store expire_time in our state, for migration */ 1101f8f48b69SHans de Goede t_last_run = s->expire_time - frame_t; 1102bc72ad67SAlex Bligh t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1103f8f48b69SHans de Goede 1104f8f48b69SHans de Goede /* Process up to MAX_FRAMES_PER_TICK frames */ 1105f8f48b69SHans de Goede frames = (t_now - t_last_run) / frame_t; 11069fdf7027SHans de Goede if (frames > s->maxframes) { 11079fdf7027SHans de Goede int skipped = frames - s->maxframes; 11089fdf7027SHans de Goede s->expire_time += skipped * frame_t; 11099fdf7027SHans de Goede s->frnum = (s->frnum + skipped) & 0x7ff; 11109fdf7027SHans de Goede frames -= skipped; 11119fdf7027SHans de Goede } 1112f8f48b69SHans de Goede if (frames > MAX_FRAMES_PER_TICK) { 1113f8f48b69SHans de Goede frames = MAX_FRAMES_PER_TICK; 1114f8f48b69SHans de Goede } 1115f8f48b69SHans de Goede 1116f8f48b69SHans de Goede for (i = 0; i < frames; i++) { 1117f8f48b69SHans de Goede s->frame_bytes = 0; 111850dcc0f8SGerd Hoffmann trace_usb_uhci_frame_start(s->frnum); 1119f1ae32a1SGerd Hoffmann uhci_async_validate_begin(s); 1120f1ae32a1SGerd Hoffmann uhci_process_frame(s); 1121f1ae32a1SGerd Hoffmann uhci_async_validate_end(s); 1122f8f48b69SHans de Goede /* The spec says frnum is the frame currently being processed, and 1123f8f48b69SHans de Goede * the guest must look at frnum - 1 on interrupt, so inc frnum now */ 1124719c130dSHans de Goede s->frnum = (s->frnum + 1) & 0x7ff; 1125f8f48b69SHans de Goede s->expire_time += frame_t; 1126f8f48b69SHans de Goede } 1127719c130dSHans de Goede 1128f8f48b69SHans de Goede /* Complete the previous frame(s) */ 1129719c130dSHans de Goede if (s->pending_int_mask) { 1130719c130dSHans de Goede s->status2 |= s->pending_int_mask; 1131719c130dSHans de Goede s->status |= UHCI_STS_USBINT; 1132719c130dSHans de Goede uhci_update_irq(s); 1133719c130dSHans de Goede } 1134719c130dSHans de Goede s->pending_int_mask = 0; 1135719c130dSHans de Goede 1136bc72ad67SAlex Bligh timer_mod(s->frame_timer, t_now + frame_t); 1137f1ae32a1SGerd Hoffmann } 1138f1ae32a1SGerd Hoffmann 1139f1ae32a1SGerd Hoffmann static const MemoryRegionOps uhci_ioport_ops = { 114089eb147cSGerd Hoffmann .read = uhci_port_read, 114189eb147cSGerd Hoffmann .write = uhci_port_write, 114289eb147cSGerd Hoffmann .valid.min_access_size = 1, 114389eb147cSGerd Hoffmann .valid.max_access_size = 4, 114489eb147cSGerd Hoffmann .impl.min_access_size = 2, 114589eb147cSGerd Hoffmann .impl.max_access_size = 2, 114689eb147cSGerd Hoffmann .endianness = DEVICE_LITTLE_ENDIAN, 1147f1ae32a1SGerd Hoffmann }; 1148f1ae32a1SGerd Hoffmann 1149f1ae32a1SGerd Hoffmann static USBPortOps uhci_port_ops = { 1150f1ae32a1SGerd Hoffmann .attach = uhci_attach, 1151f1ae32a1SGerd Hoffmann .detach = uhci_detach, 1152f1ae32a1SGerd Hoffmann .child_detach = uhci_child_detach, 1153f1ae32a1SGerd Hoffmann .wakeup = uhci_wakeup, 1154f1ae32a1SGerd Hoffmann .complete = uhci_async_complete, 1155f1ae32a1SGerd Hoffmann }; 1156f1ae32a1SGerd Hoffmann 1157f1ae32a1SGerd Hoffmann static USBBusOps uhci_bus_ops = { 1158f1ae32a1SGerd Hoffmann }; 1159f1ae32a1SGerd Hoffmann 11609a4e12a6SPhilippe Mathieu-Daudé void usb_uhci_common_realize(PCIDevice *dev, Error **errp) 1161f1ae32a1SGerd Hoffmann { 1162f4bbaaf5SMarkus Armbruster Error *err = NULL; 1163973002c1SGerd Hoffmann PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 11648f3f90b0SGerd Hoffmann UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); 116549184b62SGonglei UHCIState *s = UHCI(dev); 1166f1ae32a1SGerd Hoffmann uint8_t *pci_conf = s->dev.config; 1167f1ae32a1SGerd Hoffmann int i; 1168f1ae32a1SGerd Hoffmann 1169f1ae32a1SGerd Hoffmann pci_conf[PCI_CLASS_PROG] = 0x00; 1170f1ae32a1SGerd Hoffmann /* TODO: reset value should be 0. */ 1171*d3647ef1SBALATON Zoltan pci_conf[USB_SBRN] = USB_RELEASE_1; /* release number */ 11729e64f8a3SMarcel Apfelbaum pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1); 1173973002c1SGerd Hoffmann 1174f1ae32a1SGerd Hoffmann if (s->masterbus) { 1175f1ae32a1SGerd Hoffmann USBPort *ports[NB_PORTS]; 1176f1ae32a1SGerd Hoffmann for(i = 0; i < NB_PORTS; i++) { 1177f1ae32a1SGerd Hoffmann ports[i] = &s->ports[i].port; 1178f1ae32a1SGerd Hoffmann } 1179f4bbaaf5SMarkus Armbruster usb_register_companion(s->masterbus, ports, NB_PORTS, 1180f1ae32a1SGerd Hoffmann s->firstport, s, &uhci_port_ops, 1181f4bbaaf5SMarkus Armbruster USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1182f4bbaaf5SMarkus Armbruster &err); 1183f4bbaaf5SMarkus Armbruster if (err) { 118463216dc7SMarkus Armbruster error_propagate(errp, err); 118563216dc7SMarkus Armbruster return; 1186f1ae32a1SGerd Hoffmann } 1187f1ae32a1SGerd Hoffmann } else { 1188c889b3a5SAndreas Färber usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev)); 1189f1ae32a1SGerd Hoffmann for (i = 0; i < NB_PORTS; i++) { 1190f1ae32a1SGerd Hoffmann usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1191f1ae32a1SGerd Hoffmann USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1192f1ae32a1SGerd Hoffmann } 1193f1ae32a1SGerd Hoffmann } 11949a16c595SGerd Hoffmann s->bh = qemu_bh_new(uhci_bh, s); 1195bc72ad67SAlex Bligh s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s); 1196f1ae32a1SGerd Hoffmann s->num_ports_vmstate = NB_PORTS; 1197f1ae32a1SGerd Hoffmann QTAILQ_INIT(&s->queues); 1198f1ae32a1SGerd Hoffmann 119922fc860bSPaolo Bonzini memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s, 120022fc860bSPaolo Bonzini "uhci", 0x20); 120122fc860bSPaolo Bonzini 1202f1ae32a1SGerd Hoffmann /* Use region 4 for consistency with real hardware. BSD guests seem 1203f1ae32a1SGerd Hoffmann to rely on this. */ 1204f1ae32a1SGerd Hoffmann pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1205f1ae32a1SGerd Hoffmann } 1206f1ae32a1SGerd Hoffmann 12073a3464b0SGonglei static void usb_uhci_exit(PCIDevice *dev) 12083a3464b0SGonglei { 120949184b62SGonglei UHCIState *s = UHCI(dev); 12103a3464b0SGonglei 1211d733f74cSGonglei trace_usb_uhci_exit(); 1212d733f74cSGonglei 12133a3464b0SGonglei if (s->frame_timer) { 12143a3464b0SGonglei timer_free(s->frame_timer); 12153a3464b0SGonglei s->frame_timer = NULL; 12163a3464b0SGonglei } 12173a3464b0SGonglei 12183a3464b0SGonglei if (s->bh) { 12193a3464b0SGonglei qemu_bh_delete(s->bh); 12203a3464b0SGonglei } 12213a3464b0SGonglei 12223a3464b0SGonglei uhci_async_cancel_all(s); 12233a3464b0SGonglei 12243a3464b0SGonglei if (!s->masterbus) { 12253a3464b0SGonglei usb_bus_release(&s->bus); 12263a3464b0SGonglei } 12273a3464b0SGonglei } 12283a3464b0SGonglei 1229638ca939SGerd Hoffmann static Property uhci_properties_companion[] = { 1230f1ae32a1SGerd Hoffmann DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1231f1ae32a1SGerd Hoffmann DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 123240141d12SGerd Hoffmann DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 12339fdf7027SHans de Goede DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1234f1ae32a1SGerd Hoffmann DEFINE_PROP_END_OF_LIST(), 1235f1ae32a1SGerd Hoffmann }; 1236638ca939SGerd Hoffmann static Property uhci_properties_standalone[] = { 1237638ca939SGerd Hoffmann DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1238638ca939SGerd Hoffmann DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), 1239638ca939SGerd Hoffmann DEFINE_PROP_END_OF_LIST(), 1240638ca939SGerd Hoffmann }; 1241f1ae32a1SGerd Hoffmann 12422c2e8525SGerd Hoffmann static void uhci_class_init(ObjectClass *klass, void *data) 1243f1ae32a1SGerd Hoffmann { 1244f1ae32a1SGerd Hoffmann DeviceClass *dc = DEVICE_CLASS(klass); 1245f1ae32a1SGerd Hoffmann PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 124649184b62SGonglei 124749184b62SGonglei k->class_id = PCI_CLASS_SERIAL_USB; 124849184b62SGonglei dc->vmsd = &vmstate_uhci; 124949184b62SGonglei dc->reset = uhci_reset; 125049184b62SGonglei set_bit(DEVICE_CATEGORY_USB, dc->categories); 125149184b62SGonglei } 125249184b62SGonglei 125349184b62SGonglei static const TypeInfo uhci_pci_type_info = { 125449184b62SGonglei .name = TYPE_UHCI, 125549184b62SGonglei .parent = TYPE_PCI_DEVICE, 125649184b62SGonglei .instance_size = sizeof(UHCIState), 125749184b62SGonglei .class_size = sizeof(UHCIPCIDeviceClass), 125849184b62SGonglei .abstract = true, 125949184b62SGonglei .class_init = uhci_class_init, 1260fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 1261fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1262fd3b02c8SEduardo Habkost { }, 1263fd3b02c8SEduardo Habkost }, 126449184b62SGonglei }; 126549184b62SGonglei 12669a4e12a6SPhilippe Mathieu-Daudé void uhci_data_class_init(ObjectClass *klass, void *data) 126749184b62SGonglei { 126849184b62SGonglei PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 126949184b62SGonglei DeviceClass *dc = DEVICE_CLASS(klass); 12708f3f90b0SGerd Hoffmann UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); 12712c2e8525SGerd Hoffmann UHCIInfo *info = data; 1272f1ae32a1SGerd Hoffmann 127363216dc7SMarkus Armbruster k->realize = info->realize ? info->realize : usb_uhci_common_realize; 12743a3464b0SGonglei k->exit = info->unplug ? usb_uhci_exit : NULL; 12752c2e8525SGerd Hoffmann k->vendor_id = info->vendor_id; 12762c2e8525SGerd Hoffmann k->device_id = info->device_id; 12772c2e8525SGerd Hoffmann k->revision = info->revision; 1278638ca939SGerd Hoffmann if (!info->unplug) { 1279638ca939SGerd Hoffmann /* uhci controllers in companion setups can't be hotplugged */ 1280638ca939SGerd Hoffmann dc->hotpluggable = false; 12814f67d30bSMarc-André Lureau device_class_set_props(dc, uhci_properties_companion); 1282638ca939SGerd Hoffmann } else { 12834f67d30bSMarc-André Lureau device_class_set_props(dc, uhci_properties_standalone); 1284638ca939SGerd Hoffmann } 12858f3f90b0SGerd Hoffmann u->info = *info; 1286f1ae32a1SGerd Hoffmann } 1287f1ae32a1SGerd Hoffmann 12882c2e8525SGerd Hoffmann static UHCIInfo uhci_info[] = { 12892c2e8525SGerd Hoffmann { 1290f1ae32a1SGerd Hoffmann .name = "piix3-usb-uhci", 12912c2e8525SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 12922c2e8525SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, 12932c2e8525SGerd Hoffmann .revision = 0x01, 12948f3f90b0SGerd Hoffmann .irq_pin = 3, 12952c2e8525SGerd Hoffmann .unplug = true, 12962c2e8525SGerd Hoffmann },{ 1297f1ae32a1SGerd Hoffmann .name = "piix4-usb-uhci", 12982c2e8525SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 12992c2e8525SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, 13002c2e8525SGerd Hoffmann .revision = 0x01, 13018f3f90b0SGerd Hoffmann .irq_pin = 3, 13022c2e8525SGerd Hoffmann .unplug = true, 13032c2e8525SGerd Hoffmann },{ 130474625ea2SGerd Hoffmann .name = "ich9-usb-uhci1", /* 00:1d.0 */ 13052c2e8525SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 13062c2e8525SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, 13072c2e8525SGerd Hoffmann .revision = 0x03, 13088f3f90b0SGerd Hoffmann .irq_pin = 0, 13092c2e8525SGerd Hoffmann .unplug = false, 13102c2e8525SGerd Hoffmann },{ 131174625ea2SGerd Hoffmann .name = "ich9-usb-uhci2", /* 00:1d.1 */ 13122c2e8525SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 13132c2e8525SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, 13142c2e8525SGerd Hoffmann .revision = 0x03, 13158f3f90b0SGerd Hoffmann .irq_pin = 1, 13162c2e8525SGerd Hoffmann .unplug = false, 13172c2e8525SGerd Hoffmann },{ 131874625ea2SGerd Hoffmann .name = "ich9-usb-uhci3", /* 00:1d.2 */ 13192c2e8525SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 13202c2e8525SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, 13212c2e8525SGerd Hoffmann .revision = 0x03, 13228f3f90b0SGerd Hoffmann .irq_pin = 2, 13232c2e8525SGerd Hoffmann .unplug = false, 132474625ea2SGerd Hoffmann },{ 132574625ea2SGerd Hoffmann .name = "ich9-usb-uhci4", /* 00:1a.0 */ 132674625ea2SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 132774625ea2SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, 132874625ea2SGerd Hoffmann .revision = 0x03, 132974625ea2SGerd Hoffmann .irq_pin = 0, 133074625ea2SGerd Hoffmann .unplug = false, 133174625ea2SGerd Hoffmann },{ 133274625ea2SGerd Hoffmann .name = "ich9-usb-uhci5", /* 00:1a.1 */ 133374625ea2SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 133474625ea2SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, 133574625ea2SGerd Hoffmann .revision = 0x03, 133674625ea2SGerd Hoffmann .irq_pin = 1, 133774625ea2SGerd Hoffmann .unplug = false, 133874625ea2SGerd Hoffmann },{ 133974625ea2SGerd Hoffmann .name = "ich9-usb-uhci6", /* 00:1a.2 */ 134074625ea2SGerd Hoffmann .vendor_id = PCI_VENDOR_ID_INTEL, 134174625ea2SGerd Hoffmann .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, 134274625ea2SGerd Hoffmann .revision = 0x03, 134374625ea2SGerd Hoffmann .irq_pin = 2, 134474625ea2SGerd Hoffmann .unplug = false, 13452c2e8525SGerd Hoffmann } 1346f1ae32a1SGerd Hoffmann }; 1347f1ae32a1SGerd Hoffmann 1348f1ae32a1SGerd Hoffmann static void uhci_register_types(void) 1349f1ae32a1SGerd Hoffmann { 13502c2e8525SGerd Hoffmann TypeInfo uhci_type_info = { 135149184b62SGonglei .parent = TYPE_UHCI, 135249184b62SGonglei .class_init = uhci_data_class_init, 13532c2e8525SGerd Hoffmann }; 13542c2e8525SGerd Hoffmann int i; 13552c2e8525SGerd Hoffmann 135649184b62SGonglei type_register_static(&uhci_pci_type_info); 135749184b62SGonglei 13582c2e8525SGerd Hoffmann for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { 13592c2e8525SGerd Hoffmann uhci_type_info.name = uhci_info[i].name; 13602c2e8525SGerd Hoffmann uhci_type_info.class_data = uhci_info + i; 13612c2e8525SGerd Hoffmann type_register(&uhci_type_info); 13622c2e8525SGerd Hoffmann } 1363f1ae32a1SGerd Hoffmann } 1364f1ae32a1SGerd Hoffmann 1365f1ae32a1SGerd Hoffmann type_init(uhci_register_types) 1366