1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o Handle unrecoverable errors properly 26 * o BIOS work to boot from USB storage 27 */ 28 29 #include "hw/hw.h" 30 #include "qemu-timer.h" 31 #include "hw/usb.h" 32 #include "hw/pci.h" 33 #include "hw/sysbus.h" 34 #include "hw/qdev-dma.h" 35 36 //#define DEBUG_OHCI 37 /* Dump packet contents. */ 38 //#define DEBUG_PACKET 39 //#define DEBUG_ISOCH 40 /* This causes frames to occur 1000x slower */ 41 //#define OHCI_TIME_WARP 1 42 43 #ifdef DEBUG_OHCI 44 #define DPRINTF printf 45 #else 46 #define DPRINTF(...) 47 #endif 48 49 /* Number of Downstream Ports on the root hub. */ 50 51 #define OHCI_MAX_PORTS 15 52 53 static int64_t usb_frame_time; 54 static int64_t usb_bit_time; 55 56 typedef struct OHCIPort { 57 USBPort port; 58 uint32_t ctrl; 59 } OHCIPort; 60 61 typedef struct { 62 USBBus bus; 63 qemu_irq irq; 64 MemoryRegion mem; 65 DMAContext *dma; 66 int num_ports; 67 const char *name; 68 69 QEMUTimer *eof_timer; 70 int64_t sof_time; 71 72 /* OHCI state */ 73 /* Control partition */ 74 uint32_t ctl, status; 75 uint32_t intr_status; 76 uint32_t intr; 77 78 /* memory pointer partition */ 79 uint32_t hcca; 80 uint32_t ctrl_head, ctrl_cur; 81 uint32_t bulk_head, bulk_cur; 82 uint32_t per_cur; 83 uint32_t done; 84 int done_count; 85 86 /* Frame counter partition */ 87 uint32_t fsmps:15; 88 uint32_t fit:1; 89 uint32_t fi:14; 90 uint32_t frt:1; 91 uint16_t frame_number; 92 uint16_t padding; 93 uint32_t pstart; 94 uint32_t lst; 95 96 /* Root Hub partition */ 97 uint32_t rhdesc_a, rhdesc_b; 98 uint32_t rhstatus; 99 OHCIPort rhport[OHCI_MAX_PORTS]; 100 101 /* PXA27x Non-OHCI events */ 102 uint32_t hstatus; 103 uint32_t hmask; 104 uint32_t hreset; 105 uint32_t htest; 106 107 /* SM501 local memory offset */ 108 dma_addr_t localmem_base; 109 110 /* Active packets. */ 111 uint32_t old_ctl; 112 USBPacket usb_packet; 113 uint8_t usb_buf[8192]; 114 uint32_t async_td; 115 int async_complete; 116 117 } OHCIState; 118 119 /* Host Controller Communications Area */ 120 struct ohci_hcca { 121 uint32_t intr[32]; 122 uint16_t frame, pad; 123 uint32_t done; 124 }; 125 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 126 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 127 128 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 129 #define ED_WBACK_SIZE 4 130 131 static void ohci_bus_stop(OHCIState *ohci); 132 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); 133 134 /* Bitfields for the first word of an Endpoint Desciptor. */ 135 #define OHCI_ED_FA_SHIFT 0 136 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 137 #define OHCI_ED_EN_SHIFT 7 138 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 139 #define OHCI_ED_D_SHIFT 11 140 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 141 #define OHCI_ED_S (1<<13) 142 #define OHCI_ED_K (1<<14) 143 #define OHCI_ED_F (1<<15) 144 #define OHCI_ED_MPS_SHIFT 16 145 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 146 147 /* Flags in the head field of an Endpoint Desciptor. */ 148 #define OHCI_ED_H 1 149 #define OHCI_ED_C 2 150 151 /* Bitfields for the first word of a Transfer Desciptor. */ 152 #define OHCI_TD_R (1<<18) 153 #define OHCI_TD_DP_SHIFT 19 154 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 155 #define OHCI_TD_DI_SHIFT 21 156 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 157 #define OHCI_TD_T0 (1<<24) 158 #define OHCI_TD_T1 (1<<25) 159 #define OHCI_TD_EC_SHIFT 26 160 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 161 #define OHCI_TD_CC_SHIFT 28 162 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 163 164 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 165 /* CC & DI - same as in the General Transfer Desciptor */ 166 #define OHCI_TD_SF_SHIFT 0 167 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 168 #define OHCI_TD_FC_SHIFT 24 169 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 170 171 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 172 #define OHCI_TD_PSW_CC_SHIFT 12 173 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 174 #define OHCI_TD_PSW_SIZE_SHIFT 0 175 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 176 177 #define OHCI_PAGE_MASK 0xfffff000 178 #define OHCI_OFFSET_MASK 0xfff 179 180 #define OHCI_DPTR_MASK 0xfffffff0 181 182 #define OHCI_BM(val, field) \ 183 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 184 185 #define OHCI_SET_BM(val, field, newval) do { \ 186 val &= ~OHCI_##field##_MASK; \ 187 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 188 } while(0) 189 190 /* endpoint descriptor */ 191 struct ohci_ed { 192 uint32_t flags; 193 uint32_t tail; 194 uint32_t head; 195 uint32_t next; 196 }; 197 198 /* General transfer descriptor */ 199 struct ohci_td { 200 uint32_t flags; 201 uint32_t cbp; 202 uint32_t next; 203 uint32_t be; 204 }; 205 206 /* Isochronous transfer descriptor */ 207 struct ohci_iso_td { 208 uint32_t flags; 209 uint32_t bp; 210 uint32_t next; 211 uint32_t be; 212 uint16_t offset[8]; 213 }; 214 215 #define USB_HZ 12000000 216 217 /* OHCI Local stuff */ 218 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 219 #define OHCI_CTL_PLE (1<<2) 220 #define OHCI_CTL_IE (1<<3) 221 #define OHCI_CTL_CLE (1<<4) 222 #define OHCI_CTL_BLE (1<<5) 223 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 224 #define OHCI_USB_RESET 0x00 225 #define OHCI_USB_RESUME 0x40 226 #define OHCI_USB_OPERATIONAL 0x80 227 #define OHCI_USB_SUSPEND 0xc0 228 #define OHCI_CTL_IR (1<<8) 229 #define OHCI_CTL_RWC (1<<9) 230 #define OHCI_CTL_RWE (1<<10) 231 232 #define OHCI_STATUS_HCR (1<<0) 233 #define OHCI_STATUS_CLF (1<<1) 234 #define OHCI_STATUS_BLF (1<<2) 235 #define OHCI_STATUS_OCR (1<<3) 236 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 237 238 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ 239 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ 240 #define OHCI_INTR_SF (1<<2) /* Start of frame */ 241 #define OHCI_INTR_RD (1<<3) /* Resume detect */ 242 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ 243 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ 244 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ 245 #define OHCI_INTR_OC (1<<30) /* Ownership change */ 246 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ 247 248 #define OHCI_HCCA_SIZE 0x100 249 #define OHCI_HCCA_MASK 0xffffff00 250 251 #define OHCI_EDPTR_MASK 0xfffffff0 252 253 #define OHCI_FMI_FI 0x00003fff 254 #define OHCI_FMI_FSMPS 0xffff0000 255 #define OHCI_FMI_FIT 0x80000000 256 257 #define OHCI_FR_RT (1<<31) 258 259 #define OHCI_LS_THRESH 0x628 260 261 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 262 #define OHCI_RHA_PSM (1<<8) 263 #define OHCI_RHA_NPS (1<<9) 264 #define OHCI_RHA_DT (1<<10) 265 #define OHCI_RHA_OCPM (1<<11) 266 #define OHCI_RHA_NOCP (1<<12) 267 #define OHCI_RHA_POTPGT_MASK 0xff000000 268 269 #define OHCI_RHS_LPS (1<<0) 270 #define OHCI_RHS_OCI (1<<1) 271 #define OHCI_RHS_DRWE (1<<15) 272 #define OHCI_RHS_LPSC (1<<16) 273 #define OHCI_RHS_OCIC (1<<17) 274 #define OHCI_RHS_CRWE (1<<31) 275 276 #define OHCI_PORT_CCS (1<<0) 277 #define OHCI_PORT_PES (1<<1) 278 #define OHCI_PORT_PSS (1<<2) 279 #define OHCI_PORT_POCI (1<<3) 280 #define OHCI_PORT_PRS (1<<4) 281 #define OHCI_PORT_PPS (1<<8) 282 #define OHCI_PORT_LSDA (1<<9) 283 #define OHCI_PORT_CSC (1<<16) 284 #define OHCI_PORT_PESC (1<<17) 285 #define OHCI_PORT_PSSC (1<<18) 286 #define OHCI_PORT_OCIC (1<<19) 287 #define OHCI_PORT_PRSC (1<<20) 288 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 289 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 290 291 #define OHCI_TD_DIR_SETUP 0x0 292 #define OHCI_TD_DIR_OUT 0x1 293 #define OHCI_TD_DIR_IN 0x2 294 #define OHCI_TD_DIR_RESERVED 0x3 295 296 #define OHCI_CC_NOERROR 0x0 297 #define OHCI_CC_CRC 0x1 298 #define OHCI_CC_BITSTUFFING 0x2 299 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 300 #define OHCI_CC_STALL 0x4 301 #define OHCI_CC_DEVICENOTRESPONDING 0x5 302 #define OHCI_CC_PIDCHECKFAILURE 0x6 303 #define OHCI_CC_UNDEXPETEDPID 0x7 304 #define OHCI_CC_DATAOVERRUN 0x8 305 #define OHCI_CC_DATAUNDERRUN 0x9 306 #define OHCI_CC_BUFFEROVERRUN 0xc 307 #define OHCI_CC_BUFFERUNDERRUN 0xd 308 309 #define OHCI_HRESET_FSBIR (1 << 0) 310 311 /* Update IRQ levels */ 312 static inline void ohci_intr_update(OHCIState *ohci) 313 { 314 int level = 0; 315 316 if ((ohci->intr & OHCI_INTR_MIE) && 317 (ohci->intr_status & ohci->intr)) 318 level = 1; 319 320 qemu_set_irq(ohci->irq, level); 321 } 322 323 /* Set an interrupt */ 324 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 325 { 326 ohci->intr_status |= intr; 327 ohci_intr_update(ohci); 328 } 329 330 /* Attach or detach a device on a root hub port. */ 331 static void ohci_attach(USBPort *port1) 332 { 333 OHCIState *s = port1->opaque; 334 OHCIPort *port = &s->rhport[port1->index]; 335 uint32_t old_state = port->ctrl; 336 337 /* set connect status */ 338 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 339 340 /* update speed */ 341 if (port->port.dev->speed == USB_SPEED_LOW) { 342 port->ctrl |= OHCI_PORT_LSDA; 343 } else { 344 port->ctrl &= ~OHCI_PORT_LSDA; 345 } 346 347 /* notify of remote-wakeup */ 348 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 349 ohci_set_interrupt(s, OHCI_INTR_RD); 350 } 351 352 DPRINTF("usb-ohci: Attached port %d\n", port1->index); 353 354 if (old_state != port->ctrl) { 355 ohci_set_interrupt(s, OHCI_INTR_RHSC); 356 } 357 } 358 359 static void ohci_detach(USBPort *port1) 360 { 361 OHCIState *s = port1->opaque; 362 OHCIPort *port = &s->rhport[port1->index]; 363 uint32_t old_state = port->ctrl; 364 365 ohci_async_cancel_device(s, port1->dev); 366 367 /* set connect status */ 368 if (port->ctrl & OHCI_PORT_CCS) { 369 port->ctrl &= ~OHCI_PORT_CCS; 370 port->ctrl |= OHCI_PORT_CSC; 371 } 372 /* disable port */ 373 if (port->ctrl & OHCI_PORT_PES) { 374 port->ctrl &= ~OHCI_PORT_PES; 375 port->ctrl |= OHCI_PORT_PESC; 376 } 377 DPRINTF("usb-ohci: Detached port %d\n", port1->index); 378 379 if (old_state != port->ctrl) { 380 ohci_set_interrupt(s, OHCI_INTR_RHSC); 381 } 382 } 383 384 static void ohci_wakeup(USBPort *port1) 385 { 386 OHCIState *s = port1->opaque; 387 OHCIPort *port = &s->rhport[port1->index]; 388 uint32_t intr = 0; 389 if (port->ctrl & OHCI_PORT_PSS) { 390 DPRINTF("usb-ohci: port %d: wakeup\n", port1->index); 391 port->ctrl |= OHCI_PORT_PSSC; 392 port->ctrl &= ~OHCI_PORT_PSS; 393 intr = OHCI_INTR_RHSC; 394 } 395 /* Note that the controller can be suspended even if this port is not */ 396 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 397 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n"); 398 /* This is the one state transition the controller can do by itself */ 399 s->ctl &= ~OHCI_CTL_HCFS; 400 s->ctl |= OHCI_USB_RESUME; 401 /* In suspend mode only ResumeDetected is possible, not RHSC: 402 * see the OHCI spec 5.1.2.3. 403 */ 404 intr = OHCI_INTR_RD; 405 } 406 ohci_set_interrupt(s, intr); 407 } 408 409 static void ohci_child_detach(USBPort *port1, USBDevice *child) 410 { 411 OHCIState *s = port1->opaque; 412 413 ohci_async_cancel_device(s, child); 414 } 415 416 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 417 { 418 USBDevice *dev; 419 int i; 420 421 for (i = 0; i < ohci->num_ports; i++) { 422 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 423 continue; 424 } 425 dev = usb_find_device(&ohci->rhport[i].port, addr); 426 if (dev != NULL) { 427 return dev; 428 } 429 } 430 return NULL; 431 } 432 433 /* Reset the controller */ 434 static void ohci_reset(void *opaque) 435 { 436 OHCIState *ohci = opaque; 437 OHCIPort *port; 438 int i; 439 440 ohci_bus_stop(ohci); 441 ohci->ctl = 0; 442 ohci->old_ctl = 0; 443 ohci->status = 0; 444 ohci->intr_status = 0; 445 ohci->intr = OHCI_INTR_MIE; 446 447 ohci->hcca = 0; 448 ohci->ctrl_head = ohci->ctrl_cur = 0; 449 ohci->bulk_head = ohci->bulk_cur = 0; 450 ohci->per_cur = 0; 451 ohci->done = 0; 452 ohci->done_count = 7; 453 454 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 455 * I took the value linux sets ... 456 */ 457 ohci->fsmps = 0x2778; 458 ohci->fi = 0x2edf; 459 ohci->fit = 0; 460 ohci->frt = 0; 461 ohci->frame_number = 0; 462 ohci->pstart = 0; 463 ohci->lst = OHCI_LS_THRESH; 464 465 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 466 ohci->rhdesc_b = 0x0; /* Impl. specific */ 467 ohci->rhstatus = 0; 468 469 for (i = 0; i < ohci->num_ports; i++) 470 { 471 port = &ohci->rhport[i]; 472 port->ctrl = 0; 473 if (port->port.dev && port->port.dev->attached) { 474 usb_port_reset(&port->port); 475 } 476 } 477 if (ohci->async_td) { 478 usb_cancel_packet(&ohci->usb_packet); 479 ohci->async_td = 0; 480 } 481 DPRINTF("usb-ohci: Reset %s\n", ohci->name); 482 } 483 484 /* Get an array of dwords from main memory */ 485 static inline int get_dwords(OHCIState *ohci, 486 dma_addr_t addr, uint32_t *buf, int num) 487 { 488 int i; 489 490 addr += ohci->localmem_base; 491 492 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 493 dma_memory_read(ohci->dma, addr, buf, sizeof(*buf)); 494 *buf = le32_to_cpu(*buf); 495 } 496 497 return 1; 498 } 499 500 /* Put an array of dwords in to main memory */ 501 static inline int put_dwords(OHCIState *ohci, 502 dma_addr_t addr, uint32_t *buf, int num) 503 { 504 int i; 505 506 addr += ohci->localmem_base; 507 508 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 509 uint32_t tmp = cpu_to_le32(*buf); 510 dma_memory_write(ohci->dma, addr, &tmp, sizeof(tmp)); 511 } 512 513 return 1; 514 } 515 516 /* Get an array of words from main memory */ 517 static inline int get_words(OHCIState *ohci, 518 dma_addr_t addr, uint16_t *buf, int num) 519 { 520 int i; 521 522 addr += ohci->localmem_base; 523 524 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 525 dma_memory_read(ohci->dma, addr, buf, sizeof(*buf)); 526 *buf = le16_to_cpu(*buf); 527 } 528 529 return 1; 530 } 531 532 /* Put an array of words in to main memory */ 533 static inline int put_words(OHCIState *ohci, 534 dma_addr_t addr, uint16_t *buf, int num) 535 { 536 int i; 537 538 addr += ohci->localmem_base; 539 540 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 541 uint16_t tmp = cpu_to_le16(*buf); 542 dma_memory_write(ohci->dma, addr, &tmp, sizeof(tmp)); 543 } 544 545 return 1; 546 } 547 548 static inline int ohci_read_ed(OHCIState *ohci, 549 dma_addr_t addr, struct ohci_ed *ed) 550 { 551 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 552 } 553 554 static inline int ohci_read_td(OHCIState *ohci, 555 dma_addr_t addr, struct ohci_td *td) 556 { 557 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 558 } 559 560 static inline int ohci_read_iso_td(OHCIState *ohci, 561 dma_addr_t addr, struct ohci_iso_td *td) 562 { 563 return (get_dwords(ohci, addr, (uint32_t *)td, 4) && 564 get_words(ohci, addr + 16, td->offset, 8)); 565 } 566 567 static inline int ohci_read_hcca(OHCIState *ohci, 568 dma_addr_t addr, struct ohci_hcca *hcca) 569 { 570 dma_memory_read(ohci->dma, addr + ohci->localmem_base, hcca, sizeof(*hcca)); 571 return 1; 572 } 573 574 static inline int ohci_put_ed(OHCIState *ohci, 575 dma_addr_t addr, struct ohci_ed *ed) 576 { 577 /* ed->tail is under control of the HCD. 578 * Since just ed->head is changed by HC, just write back this 579 */ 580 581 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 582 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 583 ED_WBACK_SIZE >> 2); 584 } 585 586 static inline int ohci_put_td(OHCIState *ohci, 587 dma_addr_t addr, struct ohci_td *td) 588 { 589 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 590 } 591 592 static inline int ohci_put_iso_td(OHCIState *ohci, 593 dma_addr_t addr, struct ohci_iso_td *td) 594 { 595 return (put_dwords(ohci, addr, (uint32_t *)td, 4) && 596 put_words(ohci, addr + 16, td->offset, 8)); 597 } 598 599 static inline int ohci_put_hcca(OHCIState *ohci, 600 dma_addr_t addr, struct ohci_hcca *hcca) 601 { 602 dma_memory_write(ohci->dma, 603 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 604 (char *)hcca + HCCA_WRITEBACK_OFFSET, 605 HCCA_WRITEBACK_SIZE); 606 return 1; 607 } 608 609 /* Read/Write the contents of a TD from/to main memory. */ 610 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 611 uint8_t *buf, int len, DMADirection dir) 612 { 613 dma_addr_t ptr, n; 614 615 ptr = td->cbp; 616 n = 0x1000 - (ptr & 0xfff); 617 if (n > len) 618 n = len; 619 dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, n, dir); 620 if (n == len) 621 return; 622 ptr = td->be & ~0xfffu; 623 buf += n; 624 dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, len - n, dir); 625 } 626 627 /* Read/Write the contents of an ISO TD from/to main memory. */ 628 static void ohci_copy_iso_td(OHCIState *ohci, 629 uint32_t start_addr, uint32_t end_addr, 630 uint8_t *buf, int len, DMADirection dir) 631 { 632 dma_addr_t ptr, n; 633 634 ptr = start_addr; 635 n = 0x1000 - (ptr & 0xfff); 636 if (n > len) 637 n = len; 638 dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, n, dir); 639 if (n == len) 640 return; 641 ptr = end_addr & ~0xfffu; 642 buf += n; 643 dma_memory_rw(ohci->dma, ptr + ohci->localmem_base, buf, len - n, dir); 644 } 645 646 static void ohci_process_lists(OHCIState *ohci, int completion); 647 648 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 649 { 650 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 651 #ifdef DEBUG_PACKET 652 DPRINTF("Async packet complete\n"); 653 #endif 654 ohci->async_complete = 1; 655 ohci_process_lists(ohci, 1); 656 } 657 658 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 659 660 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, 661 int completion) 662 { 663 int dir; 664 size_t len = 0; 665 #ifdef DEBUG_ISOCH 666 const char *str = NULL; 667 #endif 668 int pid; 669 int ret; 670 int i; 671 USBDevice *dev; 672 USBEndpoint *ep; 673 struct ohci_iso_td iso_td; 674 uint32_t addr; 675 uint16_t starting_frame; 676 int16_t relative_frame_number; 677 int frame_count; 678 uint32_t start_offset, next_offset, end_offset = 0; 679 uint32_t start_addr, end_addr; 680 681 addr = ed->head & OHCI_DPTR_MASK; 682 683 if (!ohci_read_iso_td(ohci, addr, &iso_td)) { 684 printf("usb-ohci: ISO_TD read error at %x\n", addr); 685 return 0; 686 } 687 688 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 689 frame_count = OHCI_BM(iso_td.flags, TD_FC); 690 relative_frame_number = USUB(ohci->frame_number, starting_frame); 691 692 #ifdef DEBUG_ISOCH 693 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n" 694 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" 695 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" 696 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n" 697 "frame_number 0x%.8x starting_frame 0x%.8x\n" 698 "frame_count 0x%.8x relative %d\n" 699 "di 0x%.8x cc 0x%.8x\n", 700 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 701 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 702 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], 703 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], 704 ohci->frame_number, starting_frame, 705 frame_count, relative_frame_number, 706 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); 707 #endif 708 709 if (relative_frame_number < 0) { 710 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number); 711 return 1; 712 } else if (relative_frame_number > frame_count) { 713 /* ISO TD expired - retire the TD to the Done Queue and continue with 714 the next ISO TD of the same ED */ 715 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number, 716 frame_count); 717 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 718 ed->head &= ~OHCI_DPTR_MASK; 719 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 720 iso_td.next = ohci->done; 721 ohci->done = addr; 722 i = OHCI_BM(iso_td.flags, TD_DI); 723 if (i < ohci->done_count) 724 ohci->done_count = i; 725 ohci_put_iso_td(ohci, addr, &iso_td); 726 return 0; 727 } 728 729 dir = OHCI_BM(ed->flags, ED_D); 730 switch (dir) { 731 case OHCI_TD_DIR_IN: 732 #ifdef DEBUG_ISOCH 733 str = "in"; 734 #endif 735 pid = USB_TOKEN_IN; 736 break; 737 case OHCI_TD_DIR_OUT: 738 #ifdef DEBUG_ISOCH 739 str = "out"; 740 #endif 741 pid = USB_TOKEN_OUT; 742 break; 743 case OHCI_TD_DIR_SETUP: 744 #ifdef DEBUG_ISOCH 745 str = "setup"; 746 #endif 747 pid = USB_TOKEN_SETUP; 748 break; 749 default: 750 printf("usb-ohci: Bad direction %d\n", dir); 751 return 1; 752 } 753 754 if (!iso_td.bp || !iso_td.be) { 755 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be); 756 return 1; 757 } 758 759 start_offset = iso_td.offset[relative_frame_number]; 760 next_offset = iso_td.offset[relative_frame_number + 1]; 761 762 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 763 ((relative_frame_number < frame_count) && 764 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 765 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n", 766 start_offset, next_offset); 767 return 1; 768 } 769 770 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 771 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n", 772 start_offset, next_offset); 773 return 1; 774 } 775 776 if ((start_offset & 0x1000) == 0) { 777 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 778 (start_offset & OHCI_OFFSET_MASK); 779 } else { 780 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 781 (start_offset & OHCI_OFFSET_MASK); 782 } 783 784 if (relative_frame_number < frame_count) { 785 end_offset = next_offset - 1; 786 if ((end_offset & 0x1000) == 0) { 787 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 788 (end_offset & OHCI_OFFSET_MASK); 789 } else { 790 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 791 (end_offset & OHCI_OFFSET_MASK); 792 } 793 } else { 794 /* Last packet in the ISO TD */ 795 end_addr = iso_td.be; 796 } 797 798 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 799 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 800 - (start_addr & OHCI_OFFSET_MASK); 801 } else { 802 len = end_addr - start_addr + 1; 803 } 804 805 if (len && dir != OHCI_TD_DIR_IN) { 806 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 807 DMA_DIRECTION_TO_DEVICE); 808 } 809 810 if (completion) { 811 ret = ohci->usb_packet.result; 812 } else { 813 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 814 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 815 usb_packet_setup(&ohci->usb_packet, pid, ep); 816 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); 817 ret = usb_handle_packet(dev, &ohci->usb_packet); 818 if (ret == USB_RET_ASYNC) { 819 return 1; 820 } 821 } 822 823 #ifdef DEBUG_ISOCH 824 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n", 825 start_offset, end_offset, start_addr, end_addr, str, len, ret); 826 #endif 827 828 /* Writeback */ 829 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 830 /* IN transfer succeeded */ 831 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 832 DMA_DIRECTION_FROM_DEVICE); 833 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 834 OHCI_CC_NOERROR); 835 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 836 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 837 /* OUT transfer succeeded */ 838 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 839 OHCI_CC_NOERROR); 840 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 841 } else { 842 if (ret > (ssize_t) len) { 843 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len); 844 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 845 OHCI_CC_DATAOVERRUN); 846 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 847 len); 848 } else if (ret >= 0) { 849 printf("usb-ohci: DataUnderrun %d\n", ret); 850 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 851 OHCI_CC_DATAUNDERRUN); 852 } else { 853 switch (ret) { 854 case USB_RET_IOERROR: 855 case USB_RET_NODEV: 856 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 857 OHCI_CC_DEVICENOTRESPONDING); 858 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 859 0); 860 break; 861 case USB_RET_NAK: 862 case USB_RET_STALL: 863 printf("usb-ohci: got NAK/STALL %d\n", ret); 864 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 865 OHCI_CC_STALL); 866 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 867 0); 868 break; 869 default: 870 printf("usb-ohci: Bad device response %d\n", ret); 871 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 872 OHCI_CC_UNDEXPETEDPID); 873 break; 874 } 875 } 876 } 877 878 if (relative_frame_number == frame_count) { 879 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 880 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 881 ed->head &= ~OHCI_DPTR_MASK; 882 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 883 iso_td.next = ohci->done; 884 ohci->done = addr; 885 i = OHCI_BM(iso_td.flags, TD_DI); 886 if (i < ohci->done_count) 887 ohci->done_count = i; 888 } 889 ohci_put_iso_td(ohci, addr, &iso_td); 890 return 1; 891 } 892 893 /* Service a transport descriptor. 894 Returns nonzero to terminate processing of this endpoint. */ 895 896 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 897 { 898 int dir; 899 size_t len = 0, pktlen = 0; 900 #ifdef DEBUG_PACKET 901 const char *str = NULL; 902 #endif 903 int pid; 904 int ret; 905 int i; 906 USBDevice *dev; 907 USBEndpoint *ep; 908 struct ohci_td td; 909 uint32_t addr; 910 int flag_r; 911 int completion; 912 913 addr = ed->head & OHCI_DPTR_MASK; 914 /* See if this TD has already been submitted to the device. */ 915 completion = (addr == ohci->async_td); 916 if (completion && !ohci->async_complete) { 917 #ifdef DEBUG_PACKET 918 DPRINTF("Skipping async TD\n"); 919 #endif 920 return 1; 921 } 922 if (!ohci_read_td(ohci, addr, &td)) { 923 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr); 924 return 0; 925 } 926 927 dir = OHCI_BM(ed->flags, ED_D); 928 switch (dir) { 929 case OHCI_TD_DIR_OUT: 930 case OHCI_TD_DIR_IN: 931 /* Same value. */ 932 break; 933 default: 934 dir = OHCI_BM(td.flags, TD_DP); 935 break; 936 } 937 938 switch (dir) { 939 case OHCI_TD_DIR_IN: 940 #ifdef DEBUG_PACKET 941 str = "in"; 942 #endif 943 pid = USB_TOKEN_IN; 944 break; 945 case OHCI_TD_DIR_OUT: 946 #ifdef DEBUG_PACKET 947 str = "out"; 948 #endif 949 pid = USB_TOKEN_OUT; 950 break; 951 case OHCI_TD_DIR_SETUP: 952 #ifdef DEBUG_PACKET 953 str = "setup"; 954 #endif 955 pid = USB_TOKEN_SETUP; 956 break; 957 default: 958 fprintf(stderr, "usb-ohci: Bad direction\n"); 959 return 1; 960 } 961 if (td.cbp && td.be) { 962 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 963 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 964 } else { 965 len = (td.be - td.cbp) + 1; 966 } 967 968 pktlen = len; 969 if (len && dir != OHCI_TD_DIR_IN) { 970 /* The endpoint may not allow us to transfer it all now */ 971 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 972 if (pktlen > len) { 973 pktlen = len; 974 } 975 if (!completion) { 976 ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 977 DMA_DIRECTION_TO_DEVICE); 978 } 979 } 980 } 981 982 flag_r = (td.flags & OHCI_TD_R) != 0; 983 #ifdef DEBUG_PACKET 984 DPRINTF(" TD @ 0x%.8x %" PRId64 " of %" PRId64 985 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", 986 addr, (int64_t)pktlen, (int64_t)len, str, flag_r, td.cbp, td.be); 987 988 if (pktlen > 0 && dir != OHCI_TD_DIR_IN) { 989 DPRINTF(" data:"); 990 for (i = 0; i < pktlen; i++) { 991 printf(" %.2x", ohci->usb_buf[i]); 992 } 993 DPRINTF("\n"); 994 } 995 #endif 996 if (completion) { 997 ret = ohci->usb_packet.result; 998 ohci->async_td = 0; 999 ohci->async_complete = 0; 1000 } else { 1001 if (ohci->async_td) { 1002 /* ??? The hardware should allow one active packet per 1003 endpoint. We only allow one active packet per controller. 1004 This should be sufficient as long as devices respond in a 1005 timely manner. 1006 */ 1007 #ifdef DEBUG_PACKET 1008 DPRINTF("Too many pending packets\n"); 1009 #endif 1010 return 1; 1011 } 1012 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 1013 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 1014 usb_packet_setup(&ohci->usb_packet, pid, ep); 1015 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 1016 ret = usb_handle_packet(dev, &ohci->usb_packet); 1017 #ifdef DEBUG_PACKET 1018 DPRINTF("ret=%d\n", ret); 1019 #endif 1020 if (ret == USB_RET_ASYNC) { 1021 ohci->async_td = addr; 1022 return 1; 1023 } 1024 } 1025 if (ret >= 0) { 1026 if (dir == OHCI_TD_DIR_IN) { 1027 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1028 DMA_DIRECTION_FROM_DEVICE); 1029 #ifdef DEBUG_PACKET 1030 DPRINTF(" data:"); 1031 for (i = 0; i < ret; i++) 1032 printf(" %.2x", ohci->usb_buf[i]); 1033 DPRINTF("\n"); 1034 #endif 1035 } else { 1036 ret = pktlen; 1037 } 1038 } 1039 1040 /* Writeback */ 1041 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 1042 /* Transmission succeeded. */ 1043 if (ret == len) { 1044 td.cbp = 0; 1045 } else { 1046 if ((td.cbp & 0xfff) + ret > 0xfff) { 1047 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 1048 } else { 1049 td.cbp += ret; 1050 } 1051 } 1052 td.flags |= OHCI_TD_T1; 1053 td.flags ^= OHCI_TD_T0; 1054 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1055 OHCI_SET_BM(td.flags, TD_EC, 0); 1056 1057 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1058 /* Partial packet transfer: TD not ready to retire yet */ 1059 goto exit_no_retire; 1060 } 1061 1062 /* Setting ED_C is part of the TD retirement process */ 1063 ed->head &= ~OHCI_ED_C; 1064 if (td.flags & OHCI_TD_T0) 1065 ed->head |= OHCI_ED_C; 1066 } else { 1067 if (ret >= 0) { 1068 DPRINTF("usb-ohci: Underrun\n"); 1069 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1070 } else { 1071 switch (ret) { 1072 case USB_RET_IOERROR: 1073 case USB_RET_NODEV: 1074 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1075 case USB_RET_NAK: 1076 DPRINTF("usb-ohci: got NAK\n"); 1077 return 1; 1078 case USB_RET_STALL: 1079 DPRINTF("usb-ohci: got STALL\n"); 1080 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1081 break; 1082 case USB_RET_BABBLE: 1083 DPRINTF("usb-ohci: got BABBLE\n"); 1084 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1085 break; 1086 default: 1087 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret); 1088 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1089 OHCI_SET_BM(td.flags, TD_EC, 3); 1090 break; 1091 } 1092 } 1093 ed->head |= OHCI_ED_H; 1094 } 1095 1096 /* Retire this TD */ 1097 ed->head &= ~OHCI_DPTR_MASK; 1098 ed->head |= td.next & OHCI_DPTR_MASK; 1099 td.next = ohci->done; 1100 ohci->done = addr; 1101 i = OHCI_BM(td.flags, TD_DI); 1102 if (i < ohci->done_count) 1103 ohci->done_count = i; 1104 exit_no_retire: 1105 ohci_put_td(ohci, addr, &td); 1106 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1107 } 1108 1109 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1110 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) 1111 { 1112 struct ohci_ed ed; 1113 uint32_t next_ed; 1114 uint32_t cur; 1115 int active; 1116 1117 active = 0; 1118 1119 if (head == 0) 1120 return 0; 1121 1122 for (cur = head; cur; cur = next_ed) { 1123 if (!ohci_read_ed(ohci, cur, &ed)) { 1124 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur); 1125 return 0; 1126 } 1127 1128 next_ed = ed.next & OHCI_DPTR_MASK; 1129 1130 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1131 uint32_t addr; 1132 /* Cancel pending packets for ED that have been paused. */ 1133 addr = ed.head & OHCI_DPTR_MASK; 1134 if (ohci->async_td && addr == ohci->async_td) { 1135 usb_cancel_packet(&ohci->usb_packet); 1136 ohci->async_td = 0; 1137 } 1138 continue; 1139 } 1140 1141 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1142 #ifdef DEBUG_PACKET 1143 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u " 1144 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur, 1145 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1146 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1147 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1148 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0, 1149 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1150 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1151 #endif 1152 active = 1; 1153 1154 if ((ed.flags & OHCI_ED_F) == 0) { 1155 if (ohci_service_td(ohci, &ed)) 1156 break; 1157 } else { 1158 /* Handle isochronous endpoints */ 1159 if (ohci_service_iso_td(ohci, &ed, completion)) 1160 break; 1161 } 1162 } 1163 1164 ohci_put_ed(ohci, cur, &ed); 1165 } 1166 1167 return active; 1168 } 1169 1170 /* Generate a SOF event, and set a timer for EOF */ 1171 static void ohci_sof(OHCIState *ohci) 1172 { 1173 ohci->sof_time = qemu_get_clock_ns(vm_clock); 1174 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1175 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1176 } 1177 1178 /* Process Control and Bulk lists. */ 1179 static void ohci_process_lists(OHCIState *ohci, int completion) 1180 { 1181 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1182 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1183 DPRINTF("usb-ohci: head %x, cur %x\n", 1184 ohci->ctrl_head, ohci->ctrl_cur); 1185 } 1186 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { 1187 ohci->ctrl_cur = 0; 1188 ohci->status &= ~OHCI_STATUS_CLF; 1189 } 1190 } 1191 1192 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1193 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { 1194 ohci->bulk_cur = 0; 1195 ohci->status &= ~OHCI_STATUS_BLF; 1196 } 1197 } 1198 } 1199 1200 /* Do frame processing on frame boundary */ 1201 static void ohci_frame_boundary(void *opaque) 1202 { 1203 OHCIState *ohci = opaque; 1204 struct ohci_hcca hcca; 1205 1206 ohci_read_hcca(ohci, ohci->hcca, &hcca); 1207 1208 /* Process all the lists at the end of the frame */ 1209 if (ohci->ctl & OHCI_CTL_PLE) { 1210 int n; 1211 1212 n = ohci->frame_number & 0x1f; 1213 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); 1214 } 1215 1216 /* Cancel all pending packets if either of the lists has been disabled. */ 1217 if (ohci->async_td && 1218 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1219 usb_cancel_packet(&ohci->usb_packet); 1220 ohci->async_td = 0; 1221 } 1222 ohci->old_ctl = ohci->ctl; 1223 ohci_process_lists(ohci, 0); 1224 1225 /* Frame boundary, so do EOF stuf here */ 1226 ohci->frt = ohci->fit; 1227 1228 /* Increment frame number and take care of endianness. */ 1229 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1230 hcca.frame = cpu_to_le16(ohci->frame_number); 1231 1232 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1233 if (!ohci->done) 1234 abort(); 1235 if (ohci->intr & ohci->intr_status) 1236 ohci->done |= 1; 1237 hcca.done = cpu_to_le32(ohci->done); 1238 ohci->done = 0; 1239 ohci->done_count = 7; 1240 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1241 } 1242 1243 if (ohci->done_count != 7 && ohci->done_count != 0) 1244 ohci->done_count--; 1245 1246 /* Do SOF stuff here */ 1247 ohci_sof(ohci); 1248 1249 /* Writeback HCCA */ 1250 ohci_put_hcca(ohci, ohci->hcca, &hcca); 1251 } 1252 1253 /* Start sending SOF tokens across the USB bus, lists are processed in 1254 * next frame 1255 */ 1256 static int ohci_bus_start(OHCIState *ohci) 1257 { 1258 ohci->eof_timer = qemu_new_timer_ns(vm_clock, 1259 ohci_frame_boundary, 1260 ohci); 1261 1262 if (ohci->eof_timer == NULL) { 1263 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name); 1264 /* TODO: Signal unrecoverable error */ 1265 return 0; 1266 } 1267 1268 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name); 1269 1270 ohci_sof(ohci); 1271 1272 return 1; 1273 } 1274 1275 /* Stop sending SOF tokens on the bus */ 1276 static void ohci_bus_stop(OHCIState *ohci) 1277 { 1278 if (ohci->eof_timer) 1279 qemu_del_timer(ohci->eof_timer); 1280 ohci->eof_timer = NULL; 1281 } 1282 1283 /* Sets a flag in a port status register but only set it if the port is 1284 * connected, if not set ConnectStatusChange flag. If flag is enabled 1285 * return 1. 1286 */ 1287 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1288 { 1289 int ret = 1; 1290 1291 /* writing a 0 has no effect */ 1292 if (val == 0) 1293 return 0; 1294 1295 /* If CurrentConnectStatus is cleared we set 1296 * ConnectStatusChange 1297 */ 1298 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1299 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1300 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1301 /* TODO: CSC is a wakeup event */ 1302 } 1303 return 0; 1304 } 1305 1306 if (ohci->rhport[i].ctrl & val) 1307 ret = 0; 1308 1309 /* set the bit */ 1310 ohci->rhport[i].ctrl |= val; 1311 1312 return ret; 1313 } 1314 1315 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1316 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1317 { 1318 val &= OHCI_FMI_FI; 1319 1320 if (val != ohci->fi) { 1321 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n", 1322 ohci->name, ohci->fi, ohci->fi); 1323 } 1324 1325 ohci->fi = val; 1326 } 1327 1328 static void ohci_port_power(OHCIState *ohci, int i, int p) 1329 { 1330 if (p) { 1331 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1332 } else { 1333 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1334 OHCI_PORT_CCS| 1335 OHCI_PORT_PSS| 1336 OHCI_PORT_PRS); 1337 } 1338 } 1339 1340 /* Set HcControlRegister */ 1341 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1342 { 1343 uint32_t old_state; 1344 uint32_t new_state; 1345 1346 old_state = ohci->ctl & OHCI_CTL_HCFS; 1347 ohci->ctl = val; 1348 new_state = ohci->ctl & OHCI_CTL_HCFS; 1349 1350 /* no state change */ 1351 if (old_state == new_state) 1352 return; 1353 1354 switch (new_state) { 1355 case OHCI_USB_OPERATIONAL: 1356 ohci_bus_start(ohci); 1357 break; 1358 case OHCI_USB_SUSPEND: 1359 ohci_bus_stop(ohci); 1360 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name); 1361 break; 1362 case OHCI_USB_RESUME: 1363 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name); 1364 break; 1365 case OHCI_USB_RESET: 1366 ohci_reset(ohci); 1367 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name); 1368 break; 1369 } 1370 } 1371 1372 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1373 { 1374 uint16_t fr; 1375 int64_t tks; 1376 1377 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1378 return (ohci->frt << 31); 1379 1380 /* Being in USB operational state guarnatees sof_time was 1381 * set already. 1382 */ 1383 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time; 1384 1385 /* avoid muldiv if possible */ 1386 if (tks >= usb_frame_time) 1387 return (ohci->frt << 31); 1388 1389 tks = muldiv64(1, tks, usb_bit_time); 1390 fr = (uint16_t)(ohci->fi - tks); 1391 1392 return (ohci->frt << 31) | fr; 1393 } 1394 1395 1396 /* Set root hub status */ 1397 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1398 { 1399 uint32_t old_state; 1400 1401 old_state = ohci->rhstatus; 1402 1403 /* write 1 to clear OCIC */ 1404 if (val & OHCI_RHS_OCIC) 1405 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1406 1407 if (val & OHCI_RHS_LPS) { 1408 int i; 1409 1410 for (i = 0; i < ohci->num_ports; i++) 1411 ohci_port_power(ohci, i, 0); 1412 DPRINTF("usb-ohci: powered down all ports\n"); 1413 } 1414 1415 if (val & OHCI_RHS_LPSC) { 1416 int i; 1417 1418 for (i = 0; i < ohci->num_ports; i++) 1419 ohci_port_power(ohci, i, 1); 1420 DPRINTF("usb-ohci: powered up all ports\n"); 1421 } 1422 1423 if (val & OHCI_RHS_DRWE) 1424 ohci->rhstatus |= OHCI_RHS_DRWE; 1425 1426 if (val & OHCI_RHS_CRWE) 1427 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1428 1429 if (old_state != ohci->rhstatus) 1430 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1431 } 1432 1433 /* Set root hub port status */ 1434 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1435 { 1436 uint32_t old_state; 1437 OHCIPort *port; 1438 1439 port = &ohci->rhport[portnum]; 1440 old_state = port->ctrl; 1441 1442 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1443 if (val & OHCI_PORT_WTC) 1444 port->ctrl &= ~(val & OHCI_PORT_WTC); 1445 1446 if (val & OHCI_PORT_CCS) 1447 port->ctrl &= ~OHCI_PORT_PES; 1448 1449 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1450 1451 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1452 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum); 1453 } 1454 1455 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1456 DPRINTF("usb-ohci: port %d: RESET\n", portnum); 1457 usb_device_reset(port->port.dev); 1458 port->ctrl &= ~OHCI_PORT_PRS; 1459 /* ??? Should this also set OHCI_PORT_PESC. */ 1460 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1461 } 1462 1463 /* Invert order here to ensure in ambiguous case, device is 1464 * powered up... 1465 */ 1466 if (val & OHCI_PORT_LSDA) 1467 ohci_port_power(ohci, portnum, 0); 1468 if (val & OHCI_PORT_PPS) 1469 ohci_port_power(ohci, portnum, 1); 1470 1471 if (old_state != port->ctrl) 1472 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1473 1474 return; 1475 } 1476 1477 static uint64_t ohci_mem_read(void *opaque, 1478 target_phys_addr_t addr, 1479 unsigned size) 1480 { 1481 OHCIState *ohci = opaque; 1482 uint32_t retval; 1483 1484 /* Only aligned reads are allowed on OHCI */ 1485 if (addr & 3) { 1486 fprintf(stderr, "usb-ohci: Mis-aligned read\n"); 1487 return 0xffffffff; 1488 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1489 /* HcRhPortStatus */ 1490 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1491 } else { 1492 switch (addr >> 2) { 1493 case 0: /* HcRevision */ 1494 retval = 0x10; 1495 break; 1496 1497 case 1: /* HcControl */ 1498 retval = ohci->ctl; 1499 break; 1500 1501 case 2: /* HcCommandStatus */ 1502 retval = ohci->status; 1503 break; 1504 1505 case 3: /* HcInterruptStatus */ 1506 retval = ohci->intr_status; 1507 break; 1508 1509 case 4: /* HcInterruptEnable */ 1510 case 5: /* HcInterruptDisable */ 1511 retval = ohci->intr; 1512 break; 1513 1514 case 6: /* HcHCCA */ 1515 retval = ohci->hcca; 1516 break; 1517 1518 case 7: /* HcPeriodCurrentED */ 1519 retval = ohci->per_cur; 1520 break; 1521 1522 case 8: /* HcControlHeadED */ 1523 retval = ohci->ctrl_head; 1524 break; 1525 1526 case 9: /* HcControlCurrentED */ 1527 retval = ohci->ctrl_cur; 1528 break; 1529 1530 case 10: /* HcBulkHeadED */ 1531 retval = ohci->bulk_head; 1532 break; 1533 1534 case 11: /* HcBulkCurrentED */ 1535 retval = ohci->bulk_cur; 1536 break; 1537 1538 case 12: /* HcDoneHead */ 1539 retval = ohci->done; 1540 break; 1541 1542 case 13: /* HcFmInterretval */ 1543 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1544 break; 1545 1546 case 14: /* HcFmRemaining */ 1547 retval = ohci_get_frame_remaining(ohci); 1548 break; 1549 1550 case 15: /* HcFmNumber */ 1551 retval = ohci->frame_number; 1552 break; 1553 1554 case 16: /* HcPeriodicStart */ 1555 retval = ohci->pstart; 1556 break; 1557 1558 case 17: /* HcLSThreshold */ 1559 retval = ohci->lst; 1560 break; 1561 1562 case 18: /* HcRhDescriptorA */ 1563 retval = ohci->rhdesc_a; 1564 break; 1565 1566 case 19: /* HcRhDescriptorB */ 1567 retval = ohci->rhdesc_b; 1568 break; 1569 1570 case 20: /* HcRhStatus */ 1571 retval = ohci->rhstatus; 1572 break; 1573 1574 /* PXA27x specific registers */ 1575 case 24: /* HcStatus */ 1576 retval = ohci->hstatus & ohci->hmask; 1577 break; 1578 1579 case 25: /* HcHReset */ 1580 retval = ohci->hreset; 1581 break; 1582 1583 case 26: /* HcHInterruptEnable */ 1584 retval = ohci->hmask; 1585 break; 1586 1587 case 27: /* HcHInterruptTest */ 1588 retval = ohci->htest; 1589 break; 1590 1591 default: 1592 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); 1593 retval = 0xffffffff; 1594 } 1595 } 1596 1597 return retval; 1598 } 1599 1600 static void ohci_mem_write(void *opaque, 1601 target_phys_addr_t addr, 1602 uint64_t val, 1603 unsigned size) 1604 { 1605 OHCIState *ohci = opaque; 1606 1607 /* Only aligned reads are allowed on OHCI */ 1608 if (addr & 3) { 1609 fprintf(stderr, "usb-ohci: Mis-aligned write\n"); 1610 return; 1611 } 1612 1613 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1614 /* HcRhPortStatus */ 1615 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1616 return; 1617 } 1618 1619 switch (addr >> 2) { 1620 case 1: /* HcControl */ 1621 ohci_set_ctl(ohci, val); 1622 break; 1623 1624 case 2: /* HcCommandStatus */ 1625 /* SOC is read-only */ 1626 val = (val & ~OHCI_STATUS_SOC); 1627 1628 /* Bits written as '0' remain unchanged in the register */ 1629 ohci->status |= val; 1630 1631 if (ohci->status & OHCI_STATUS_HCR) 1632 ohci_reset(ohci); 1633 break; 1634 1635 case 3: /* HcInterruptStatus */ 1636 ohci->intr_status &= ~val; 1637 ohci_intr_update(ohci); 1638 break; 1639 1640 case 4: /* HcInterruptEnable */ 1641 ohci->intr |= val; 1642 ohci_intr_update(ohci); 1643 break; 1644 1645 case 5: /* HcInterruptDisable */ 1646 ohci->intr &= ~val; 1647 ohci_intr_update(ohci); 1648 break; 1649 1650 case 6: /* HcHCCA */ 1651 ohci->hcca = val & OHCI_HCCA_MASK; 1652 break; 1653 1654 case 7: /* HcPeriodCurrentED */ 1655 /* Ignore writes to this read-only register, Linux does them */ 1656 break; 1657 1658 case 8: /* HcControlHeadED */ 1659 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1660 break; 1661 1662 case 9: /* HcControlCurrentED */ 1663 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1664 break; 1665 1666 case 10: /* HcBulkHeadED */ 1667 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1668 break; 1669 1670 case 11: /* HcBulkCurrentED */ 1671 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1672 break; 1673 1674 case 13: /* HcFmInterval */ 1675 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1676 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1677 ohci_set_frame_interval(ohci, val); 1678 break; 1679 1680 case 15: /* HcFmNumber */ 1681 break; 1682 1683 case 16: /* HcPeriodicStart */ 1684 ohci->pstart = val & 0xffff; 1685 break; 1686 1687 case 17: /* HcLSThreshold */ 1688 ohci->lst = val & 0xffff; 1689 break; 1690 1691 case 18: /* HcRhDescriptorA */ 1692 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1693 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1694 break; 1695 1696 case 19: /* HcRhDescriptorB */ 1697 break; 1698 1699 case 20: /* HcRhStatus */ 1700 ohci_set_hub_status(ohci, val); 1701 break; 1702 1703 /* PXA27x specific registers */ 1704 case 24: /* HcStatus */ 1705 ohci->hstatus &= ~(val & ohci->hmask); 1706 1707 case 25: /* HcHReset */ 1708 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1709 if (val & OHCI_HRESET_FSBIR) 1710 ohci_reset(ohci); 1711 break; 1712 1713 case 26: /* HcHInterruptEnable */ 1714 ohci->hmask = val; 1715 break; 1716 1717 case 27: /* HcHInterruptTest */ 1718 ohci->htest = val; 1719 break; 1720 1721 default: 1722 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); 1723 break; 1724 } 1725 } 1726 1727 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) 1728 { 1729 if (ohci->async_td && 1730 usb_packet_is_inflight(&ohci->usb_packet) && 1731 ohci->usb_packet.ep->dev == dev) { 1732 usb_cancel_packet(&ohci->usb_packet); 1733 ohci->async_td = 0; 1734 } 1735 } 1736 1737 static const MemoryRegionOps ohci_mem_ops = { 1738 .read = ohci_mem_read, 1739 .write = ohci_mem_write, 1740 .endianness = DEVICE_LITTLE_ENDIAN, 1741 }; 1742 1743 static USBPortOps ohci_port_ops = { 1744 .attach = ohci_attach, 1745 .detach = ohci_detach, 1746 .child_detach = ohci_child_detach, 1747 .wakeup = ohci_wakeup, 1748 .complete = ohci_async_complete_packet, 1749 }; 1750 1751 static USBBusOps ohci_bus_ops = { 1752 }; 1753 1754 static int usb_ohci_init(OHCIState *ohci, DeviceState *dev, 1755 int num_ports, dma_addr_t localmem_base, 1756 char *masterbus, uint32_t firstport, 1757 DMAContext *dma) 1758 { 1759 int i; 1760 1761 ohci->dma = dma; 1762 1763 if (usb_frame_time == 0) { 1764 #ifdef OHCI_TIME_WARP 1765 usb_frame_time = get_ticks_per_sec(); 1766 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); 1767 #else 1768 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); 1769 if (get_ticks_per_sec() >= USB_HZ) { 1770 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); 1771 } else { 1772 usb_bit_time = 1; 1773 } 1774 #endif 1775 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n", 1776 usb_frame_time, usb_bit_time); 1777 } 1778 1779 ohci->num_ports = num_ports; 1780 if (masterbus) { 1781 USBPort *ports[OHCI_MAX_PORTS]; 1782 for(i = 0; i < num_ports; i++) { 1783 ports[i] = &ohci->rhport[i].port; 1784 } 1785 if (usb_register_companion(masterbus, ports, num_ports, 1786 firstport, ohci, &ohci_port_ops, 1787 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1788 return -1; 1789 } 1790 } else { 1791 usb_bus_new(&ohci->bus, &ohci_bus_ops, dev); 1792 for (i = 0; i < num_ports; i++) { 1793 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1794 ohci, i, &ohci_port_ops, 1795 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1796 } 1797 } 1798 1799 memory_region_init_io(&ohci->mem, &ohci_mem_ops, ohci, "ohci", 256); 1800 ohci->localmem_base = localmem_base; 1801 1802 ohci->name = object_get_typename(OBJECT(dev)); 1803 usb_packet_init(&ohci->usb_packet); 1804 1805 ohci->async_td = 0; 1806 qemu_register_reset(ohci_reset, ohci); 1807 1808 return 0; 1809 } 1810 1811 typedef struct { 1812 PCIDevice pci_dev; 1813 OHCIState state; 1814 char *masterbus; 1815 uint32_t num_ports; 1816 uint32_t firstport; 1817 } OHCIPCIState; 1818 1819 static int usb_ohci_initfn_pci(struct PCIDevice *dev) 1820 { 1821 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); 1822 1823 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */ 1824 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1825 1826 if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0, 1827 ohci->masterbus, ohci->firstport, 1828 pci_dma_context(dev)) != 0) { 1829 return -1; 1830 } 1831 ohci->state.irq = ohci->pci_dev.irq[0]; 1832 1833 /* TODO: avoid cast below by using dev */ 1834 pci_register_bar(&ohci->pci_dev, 0, 0, &ohci->state.mem); 1835 return 0; 1836 } 1837 1838 typedef struct { 1839 SysBusDevice busdev; 1840 OHCIState ohci; 1841 uint32_t num_ports; 1842 dma_addr_t dma_offset; 1843 } OHCISysBusState; 1844 1845 static int ohci_init_pxa(SysBusDevice *dev) 1846 { 1847 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev); 1848 1849 /* Cannot fail as we pass NULL for masterbus */ 1850 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0, 1851 NULL); 1852 sysbus_init_irq(dev, &s->ohci.irq); 1853 sysbus_init_mmio(dev, &s->ohci.mem); 1854 1855 return 0; 1856 } 1857 1858 static Property ohci_pci_properties[] = { 1859 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), 1860 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), 1861 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), 1862 DEFINE_PROP_END_OF_LIST(), 1863 }; 1864 1865 static void ohci_pci_class_init(ObjectClass *klass, void *data) 1866 { 1867 DeviceClass *dc = DEVICE_CLASS(klass); 1868 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1869 1870 k->init = usb_ohci_initfn_pci; 1871 k->vendor_id = PCI_VENDOR_ID_APPLE; 1872 k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; 1873 k->class_id = PCI_CLASS_SERIAL_USB; 1874 dc->desc = "Apple USB Controller"; 1875 dc->props = ohci_pci_properties; 1876 } 1877 1878 static TypeInfo ohci_pci_info = { 1879 .name = "pci-ohci", 1880 .parent = TYPE_PCI_DEVICE, 1881 .instance_size = sizeof(OHCIPCIState), 1882 .class_init = ohci_pci_class_init, 1883 }; 1884 1885 static Property ohci_sysbus_properties[] = { 1886 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 1887 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), 1888 DEFINE_PROP_END_OF_LIST(), 1889 }; 1890 1891 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 1892 { 1893 DeviceClass *dc = DEVICE_CLASS(klass); 1894 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 1895 1896 sbc->init = ohci_init_pxa; 1897 dc->desc = "OHCI USB Controller"; 1898 dc->props = ohci_sysbus_properties; 1899 } 1900 1901 static TypeInfo ohci_sysbus_info = { 1902 .name = "sysbus-ohci", 1903 .parent = TYPE_SYS_BUS_DEVICE, 1904 .instance_size = sizeof(OHCISysBusState), 1905 .class_init = ohci_sysbus_class_init, 1906 }; 1907 1908 static void ohci_register_types(void) 1909 { 1910 type_register_static(&ohci_pci_info); 1911 type_register_static(&ohci_sysbus_info); 1912 } 1913 1914 type_init(ohci_register_types) 1915