1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o BIOS work to boot from USB storage 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/hw.h" 30 #include "qapi/error.h" 31 #include "qemu/timer.h" 32 #include "hw/usb.h" 33 #include "hw/pci/pci.h" 34 #include "hw/sysbus.h" 35 #include "hw/qdev-dma.h" 36 #include "trace.h" 37 38 /* This causes frames to occur 1000x slower */ 39 //#define OHCI_TIME_WARP 1 40 41 /* Number of Downstream Ports on the root hub. */ 42 43 #define OHCI_MAX_PORTS 15 44 45 static int64_t usb_frame_time; 46 static int64_t usb_bit_time; 47 48 typedef struct OHCIPort { 49 USBPort port; 50 uint32_t ctrl; 51 } OHCIPort; 52 53 typedef struct { 54 USBBus bus; 55 qemu_irq irq; 56 MemoryRegion mem; 57 AddressSpace *as; 58 int num_ports; 59 const char *name; 60 61 QEMUTimer *eof_timer; 62 int64_t sof_time; 63 64 /* OHCI state */ 65 /* Control partition */ 66 uint32_t ctl, status; 67 uint32_t intr_status; 68 uint32_t intr; 69 70 /* memory pointer partition */ 71 uint32_t hcca; 72 uint32_t ctrl_head, ctrl_cur; 73 uint32_t bulk_head, bulk_cur; 74 uint32_t per_cur; 75 uint32_t done; 76 int32_t done_count; 77 78 /* Frame counter partition */ 79 uint16_t fsmps; 80 uint8_t fit; 81 uint16_t fi; 82 uint8_t frt; 83 uint16_t frame_number; 84 uint16_t padding; 85 uint32_t pstart; 86 uint32_t lst; 87 88 /* Root Hub partition */ 89 uint32_t rhdesc_a, rhdesc_b; 90 uint32_t rhstatus; 91 OHCIPort rhport[OHCI_MAX_PORTS]; 92 93 /* PXA27x Non-OHCI events */ 94 uint32_t hstatus; 95 uint32_t hmask; 96 uint32_t hreset; 97 uint32_t htest; 98 99 /* SM501 local memory offset */ 100 dma_addr_t localmem_base; 101 102 /* Active packets. */ 103 uint32_t old_ctl; 104 USBPacket usb_packet; 105 uint8_t usb_buf[8192]; 106 uint32_t async_td; 107 bool async_complete; 108 109 } OHCIState; 110 111 /* Host Controller Communications Area */ 112 struct ohci_hcca { 113 uint32_t intr[32]; 114 uint16_t frame, pad; 115 uint32_t done; 116 }; 117 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 118 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 119 120 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 121 #define ED_WBACK_SIZE 4 122 123 static void ohci_bus_stop(OHCIState *ohci); 124 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); 125 126 /* Bitfields for the first word of an Endpoint Desciptor. */ 127 #define OHCI_ED_FA_SHIFT 0 128 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 129 #define OHCI_ED_EN_SHIFT 7 130 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 131 #define OHCI_ED_D_SHIFT 11 132 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 133 #define OHCI_ED_S (1<<13) 134 #define OHCI_ED_K (1<<14) 135 #define OHCI_ED_F (1<<15) 136 #define OHCI_ED_MPS_SHIFT 16 137 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 138 139 /* Flags in the head field of an Endpoint Desciptor. */ 140 #define OHCI_ED_H 1 141 #define OHCI_ED_C 2 142 143 /* Bitfields for the first word of a Transfer Desciptor. */ 144 #define OHCI_TD_R (1<<18) 145 #define OHCI_TD_DP_SHIFT 19 146 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 147 #define OHCI_TD_DI_SHIFT 21 148 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 149 #define OHCI_TD_T0 (1<<24) 150 #define OHCI_TD_T1 (1<<25) 151 #define OHCI_TD_EC_SHIFT 26 152 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 153 #define OHCI_TD_CC_SHIFT 28 154 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 155 156 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 157 /* CC & DI - same as in the General Transfer Desciptor */ 158 #define OHCI_TD_SF_SHIFT 0 159 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 160 #define OHCI_TD_FC_SHIFT 24 161 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 162 163 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 164 #define OHCI_TD_PSW_CC_SHIFT 12 165 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 166 #define OHCI_TD_PSW_SIZE_SHIFT 0 167 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 168 169 #define OHCI_PAGE_MASK 0xfffff000 170 #define OHCI_OFFSET_MASK 0xfff 171 172 #define OHCI_DPTR_MASK 0xfffffff0 173 174 #define OHCI_BM(val, field) \ 175 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 176 177 #define OHCI_SET_BM(val, field, newval) do { \ 178 val &= ~OHCI_##field##_MASK; \ 179 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 180 } while(0) 181 182 /* endpoint descriptor */ 183 struct ohci_ed { 184 uint32_t flags; 185 uint32_t tail; 186 uint32_t head; 187 uint32_t next; 188 }; 189 190 /* General transfer descriptor */ 191 struct ohci_td { 192 uint32_t flags; 193 uint32_t cbp; 194 uint32_t next; 195 uint32_t be; 196 }; 197 198 /* Isochronous transfer descriptor */ 199 struct ohci_iso_td { 200 uint32_t flags; 201 uint32_t bp; 202 uint32_t next; 203 uint32_t be; 204 uint16_t offset[8]; 205 }; 206 207 #define USB_HZ 12000000 208 209 /* OHCI Local stuff */ 210 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 211 #define OHCI_CTL_PLE (1<<2) 212 #define OHCI_CTL_IE (1<<3) 213 #define OHCI_CTL_CLE (1<<4) 214 #define OHCI_CTL_BLE (1<<5) 215 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 216 #define OHCI_USB_RESET 0x00 217 #define OHCI_USB_RESUME 0x40 218 #define OHCI_USB_OPERATIONAL 0x80 219 #define OHCI_USB_SUSPEND 0xc0 220 #define OHCI_CTL_IR (1<<8) 221 #define OHCI_CTL_RWC (1<<9) 222 #define OHCI_CTL_RWE (1<<10) 223 224 #define OHCI_STATUS_HCR (1<<0) 225 #define OHCI_STATUS_CLF (1<<1) 226 #define OHCI_STATUS_BLF (1<<2) 227 #define OHCI_STATUS_OCR (1<<3) 228 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 229 230 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ 231 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ 232 #define OHCI_INTR_SF (1U<<2) /* Start of frame */ 233 #define OHCI_INTR_RD (1U<<3) /* Resume detect */ 234 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ 235 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ 236 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ 237 #define OHCI_INTR_OC (1U<<30) /* Ownership change */ 238 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ 239 240 #define OHCI_HCCA_SIZE 0x100 241 #define OHCI_HCCA_MASK 0xffffff00 242 243 #define OHCI_EDPTR_MASK 0xfffffff0 244 245 #define OHCI_FMI_FI 0x00003fff 246 #define OHCI_FMI_FSMPS 0xffff0000 247 #define OHCI_FMI_FIT 0x80000000 248 249 #define OHCI_FR_RT (1U<<31) 250 251 #define OHCI_LS_THRESH 0x628 252 253 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 254 #define OHCI_RHA_PSM (1<<8) 255 #define OHCI_RHA_NPS (1<<9) 256 #define OHCI_RHA_DT (1<<10) 257 #define OHCI_RHA_OCPM (1<<11) 258 #define OHCI_RHA_NOCP (1<<12) 259 #define OHCI_RHA_POTPGT_MASK 0xff000000 260 261 #define OHCI_RHS_LPS (1U<<0) 262 #define OHCI_RHS_OCI (1U<<1) 263 #define OHCI_RHS_DRWE (1U<<15) 264 #define OHCI_RHS_LPSC (1U<<16) 265 #define OHCI_RHS_OCIC (1U<<17) 266 #define OHCI_RHS_CRWE (1U<<31) 267 268 #define OHCI_PORT_CCS (1<<0) 269 #define OHCI_PORT_PES (1<<1) 270 #define OHCI_PORT_PSS (1<<2) 271 #define OHCI_PORT_POCI (1<<3) 272 #define OHCI_PORT_PRS (1<<4) 273 #define OHCI_PORT_PPS (1<<8) 274 #define OHCI_PORT_LSDA (1<<9) 275 #define OHCI_PORT_CSC (1<<16) 276 #define OHCI_PORT_PESC (1<<17) 277 #define OHCI_PORT_PSSC (1<<18) 278 #define OHCI_PORT_OCIC (1<<19) 279 #define OHCI_PORT_PRSC (1<<20) 280 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 281 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 282 283 #define OHCI_TD_DIR_SETUP 0x0 284 #define OHCI_TD_DIR_OUT 0x1 285 #define OHCI_TD_DIR_IN 0x2 286 #define OHCI_TD_DIR_RESERVED 0x3 287 288 #define OHCI_CC_NOERROR 0x0 289 #define OHCI_CC_CRC 0x1 290 #define OHCI_CC_BITSTUFFING 0x2 291 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 292 #define OHCI_CC_STALL 0x4 293 #define OHCI_CC_DEVICENOTRESPONDING 0x5 294 #define OHCI_CC_PIDCHECKFAILURE 0x6 295 #define OHCI_CC_UNDEXPETEDPID 0x7 296 #define OHCI_CC_DATAOVERRUN 0x8 297 #define OHCI_CC_DATAUNDERRUN 0x9 298 #define OHCI_CC_BUFFEROVERRUN 0xc 299 #define OHCI_CC_BUFFERUNDERRUN 0xd 300 301 #define OHCI_HRESET_FSBIR (1 << 0) 302 303 static void ohci_die(OHCIState *ohci); 304 305 /* Update IRQ levels */ 306 static inline void ohci_intr_update(OHCIState *ohci) 307 { 308 int level = 0; 309 310 if ((ohci->intr & OHCI_INTR_MIE) && 311 (ohci->intr_status & ohci->intr)) 312 level = 1; 313 314 qemu_set_irq(ohci->irq, level); 315 } 316 317 /* Set an interrupt */ 318 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 319 { 320 ohci->intr_status |= intr; 321 ohci_intr_update(ohci); 322 } 323 324 /* Attach or detach a device on a root hub port. */ 325 static void ohci_attach(USBPort *port1) 326 { 327 OHCIState *s = port1->opaque; 328 OHCIPort *port = &s->rhport[port1->index]; 329 uint32_t old_state = port->ctrl; 330 331 /* set connect status */ 332 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 333 334 /* update speed */ 335 if (port->port.dev->speed == USB_SPEED_LOW) { 336 port->ctrl |= OHCI_PORT_LSDA; 337 } else { 338 port->ctrl &= ~OHCI_PORT_LSDA; 339 } 340 341 /* notify of remote-wakeup */ 342 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 343 ohci_set_interrupt(s, OHCI_INTR_RD); 344 } 345 346 trace_usb_ohci_port_attach(port1->index); 347 348 if (old_state != port->ctrl) { 349 ohci_set_interrupt(s, OHCI_INTR_RHSC); 350 } 351 } 352 353 static void ohci_detach(USBPort *port1) 354 { 355 OHCIState *s = port1->opaque; 356 OHCIPort *port = &s->rhport[port1->index]; 357 uint32_t old_state = port->ctrl; 358 359 ohci_async_cancel_device(s, port1->dev); 360 361 /* set connect status */ 362 if (port->ctrl & OHCI_PORT_CCS) { 363 port->ctrl &= ~OHCI_PORT_CCS; 364 port->ctrl |= OHCI_PORT_CSC; 365 } 366 /* disable port */ 367 if (port->ctrl & OHCI_PORT_PES) { 368 port->ctrl &= ~OHCI_PORT_PES; 369 port->ctrl |= OHCI_PORT_PESC; 370 } 371 trace_usb_ohci_port_detach(port1->index); 372 373 if (old_state != port->ctrl) { 374 ohci_set_interrupt(s, OHCI_INTR_RHSC); 375 } 376 } 377 378 static void ohci_wakeup(USBPort *port1) 379 { 380 OHCIState *s = port1->opaque; 381 OHCIPort *port = &s->rhport[port1->index]; 382 uint32_t intr = 0; 383 if (port->ctrl & OHCI_PORT_PSS) { 384 trace_usb_ohci_port_wakeup(port1->index); 385 port->ctrl |= OHCI_PORT_PSSC; 386 port->ctrl &= ~OHCI_PORT_PSS; 387 intr = OHCI_INTR_RHSC; 388 } 389 /* Note that the controller can be suspended even if this port is not */ 390 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 391 trace_usb_ohci_remote_wakeup(s->name); 392 /* This is the one state transition the controller can do by itself */ 393 s->ctl &= ~OHCI_CTL_HCFS; 394 s->ctl |= OHCI_USB_RESUME; 395 /* In suspend mode only ResumeDetected is possible, not RHSC: 396 * see the OHCI spec 5.1.2.3. 397 */ 398 intr = OHCI_INTR_RD; 399 } 400 ohci_set_interrupt(s, intr); 401 } 402 403 static void ohci_child_detach(USBPort *port1, USBDevice *child) 404 { 405 OHCIState *s = port1->opaque; 406 407 ohci_async_cancel_device(s, child); 408 } 409 410 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 411 { 412 USBDevice *dev; 413 int i; 414 415 for (i = 0; i < ohci->num_ports; i++) { 416 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 417 continue; 418 } 419 dev = usb_find_device(&ohci->rhport[i].port, addr); 420 if (dev != NULL) { 421 return dev; 422 } 423 } 424 return NULL; 425 } 426 427 static void ohci_stop_endpoints(OHCIState *ohci) 428 { 429 USBDevice *dev; 430 int i, j; 431 432 for (i = 0; i < ohci->num_ports; i++) { 433 dev = ohci->rhport[i].port.dev; 434 if (dev && dev->attached) { 435 usb_device_ep_stopped(dev, &dev->ep_ctl); 436 for (j = 0; j < USB_MAX_ENDPOINTS; j++) { 437 usb_device_ep_stopped(dev, &dev->ep_in[j]); 438 usb_device_ep_stopped(dev, &dev->ep_out[j]); 439 } 440 } 441 } 442 } 443 444 static void ohci_roothub_reset(OHCIState *ohci) 445 { 446 OHCIPort *port; 447 int i; 448 449 ohci_bus_stop(ohci); 450 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 451 ohci->rhdesc_b = 0x0; /* Impl. specific */ 452 ohci->rhstatus = 0; 453 454 for (i = 0; i < ohci->num_ports; i++) { 455 port = &ohci->rhport[i]; 456 port->ctrl = 0; 457 if (port->port.dev && port->port.dev->attached) { 458 usb_port_reset(&port->port); 459 } 460 } 461 if (ohci->async_td) { 462 usb_cancel_packet(&ohci->usb_packet); 463 ohci->async_td = 0; 464 } 465 ohci_stop_endpoints(ohci); 466 } 467 468 /* Reset the controller */ 469 static void ohci_soft_reset(OHCIState *ohci) 470 { 471 trace_usb_ohci_reset(ohci->name); 472 473 ohci_bus_stop(ohci); 474 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; 475 ohci->old_ctl = 0; 476 ohci->status = 0; 477 ohci->intr_status = 0; 478 ohci->intr = OHCI_INTR_MIE; 479 480 ohci->hcca = 0; 481 ohci->ctrl_head = ohci->ctrl_cur = 0; 482 ohci->bulk_head = ohci->bulk_cur = 0; 483 ohci->per_cur = 0; 484 ohci->done = 0; 485 ohci->done_count = 7; 486 487 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 488 * I took the value linux sets ... 489 */ 490 ohci->fsmps = 0x2778; 491 ohci->fi = 0x2edf; 492 ohci->fit = 0; 493 ohci->frt = 0; 494 ohci->frame_number = 0; 495 ohci->pstart = 0; 496 ohci->lst = OHCI_LS_THRESH; 497 } 498 499 static void ohci_hard_reset(OHCIState *ohci) 500 { 501 ohci_soft_reset(ohci); 502 ohci->ctl = 0; 503 ohci_roothub_reset(ohci); 504 } 505 506 /* Get an array of dwords from main memory */ 507 static inline int get_dwords(OHCIState *ohci, 508 dma_addr_t addr, uint32_t *buf, int num) 509 { 510 int i; 511 512 addr += ohci->localmem_base; 513 514 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 515 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 516 return -1; 517 } 518 *buf = le32_to_cpu(*buf); 519 } 520 521 return 0; 522 } 523 524 /* Put an array of dwords in to main memory */ 525 static inline int put_dwords(OHCIState *ohci, 526 dma_addr_t addr, uint32_t *buf, int num) 527 { 528 int i; 529 530 addr += ohci->localmem_base; 531 532 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 533 uint32_t tmp = cpu_to_le32(*buf); 534 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 535 return -1; 536 } 537 } 538 539 return 0; 540 } 541 542 /* Get an array of words from main memory */ 543 static inline int get_words(OHCIState *ohci, 544 dma_addr_t addr, uint16_t *buf, int num) 545 { 546 int i; 547 548 addr += ohci->localmem_base; 549 550 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 551 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 552 return -1; 553 } 554 *buf = le16_to_cpu(*buf); 555 } 556 557 return 0; 558 } 559 560 /* Put an array of words in to main memory */ 561 static inline int put_words(OHCIState *ohci, 562 dma_addr_t addr, uint16_t *buf, int num) 563 { 564 int i; 565 566 addr += ohci->localmem_base; 567 568 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 569 uint16_t tmp = cpu_to_le16(*buf); 570 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 571 return -1; 572 } 573 } 574 575 return 0; 576 } 577 578 static inline int ohci_read_ed(OHCIState *ohci, 579 dma_addr_t addr, struct ohci_ed *ed) 580 { 581 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 582 } 583 584 static inline int ohci_read_td(OHCIState *ohci, 585 dma_addr_t addr, struct ohci_td *td) 586 { 587 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 588 } 589 590 static inline int ohci_read_iso_td(OHCIState *ohci, 591 dma_addr_t addr, struct ohci_iso_td *td) 592 { 593 return get_dwords(ohci, addr, (uint32_t *)td, 4) || 594 get_words(ohci, addr + 16, td->offset, 8); 595 } 596 597 static inline int ohci_read_hcca(OHCIState *ohci, 598 dma_addr_t addr, struct ohci_hcca *hcca) 599 { 600 return dma_memory_read(ohci->as, addr + ohci->localmem_base, 601 hcca, sizeof(*hcca)); 602 } 603 604 static inline int ohci_put_ed(OHCIState *ohci, 605 dma_addr_t addr, struct ohci_ed *ed) 606 { 607 /* ed->tail is under control of the HCD. 608 * Since just ed->head is changed by HC, just write back this 609 */ 610 611 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 612 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 613 ED_WBACK_SIZE >> 2); 614 } 615 616 static inline int ohci_put_td(OHCIState *ohci, 617 dma_addr_t addr, struct ohci_td *td) 618 { 619 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 620 } 621 622 static inline int ohci_put_iso_td(OHCIState *ohci, 623 dma_addr_t addr, struct ohci_iso_td *td) 624 { 625 return put_dwords(ohci, addr, (uint32_t *)td, 4) || 626 put_words(ohci, addr + 16, td->offset, 8); 627 } 628 629 static inline int ohci_put_hcca(OHCIState *ohci, 630 dma_addr_t addr, struct ohci_hcca *hcca) 631 { 632 return dma_memory_write(ohci->as, 633 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 634 (char *)hcca + HCCA_WRITEBACK_OFFSET, 635 HCCA_WRITEBACK_SIZE); 636 } 637 638 /* Read/Write the contents of a TD from/to main memory. */ 639 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 640 uint8_t *buf, int len, DMADirection dir) 641 { 642 dma_addr_t ptr, n; 643 644 ptr = td->cbp; 645 n = 0x1000 - (ptr & 0xfff); 646 if (n > len) 647 n = len; 648 649 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 650 return -1; 651 } 652 if (n == len) { 653 return 0; 654 } 655 ptr = td->be & ~0xfffu; 656 buf += n; 657 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 658 len - n, dir)) { 659 return -1; 660 } 661 return 0; 662 } 663 664 /* Read/Write the contents of an ISO TD from/to main memory. */ 665 static int ohci_copy_iso_td(OHCIState *ohci, 666 uint32_t start_addr, uint32_t end_addr, 667 uint8_t *buf, int len, DMADirection dir) 668 { 669 dma_addr_t ptr, n; 670 671 ptr = start_addr; 672 n = 0x1000 - (ptr & 0xfff); 673 if (n > len) 674 n = len; 675 676 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 677 return -1; 678 } 679 if (n == len) { 680 return 0; 681 } 682 ptr = end_addr & ~0xfffu; 683 buf += n; 684 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 685 len - n, dir)) { 686 return -1; 687 } 688 return 0; 689 } 690 691 static void ohci_process_lists(OHCIState *ohci, int completion); 692 693 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 694 { 695 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 696 697 trace_usb_ohci_async_complete(); 698 ohci->async_complete = true; 699 ohci_process_lists(ohci, 1); 700 } 701 702 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 703 704 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, 705 int completion) 706 { 707 int dir; 708 size_t len = 0; 709 const char *str = NULL; 710 int pid; 711 int ret; 712 int i; 713 USBDevice *dev; 714 USBEndpoint *ep; 715 struct ohci_iso_td iso_td; 716 uint32_t addr; 717 uint16_t starting_frame; 718 int16_t relative_frame_number; 719 int frame_count; 720 uint32_t start_offset, next_offset, end_offset = 0; 721 uint32_t start_addr, end_addr; 722 723 addr = ed->head & OHCI_DPTR_MASK; 724 725 if (ohci_read_iso_td(ohci, addr, &iso_td)) { 726 trace_usb_ohci_iso_td_read_failed(addr); 727 ohci_die(ohci); 728 return 0; 729 } 730 731 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 732 frame_count = OHCI_BM(iso_td.flags, TD_FC); 733 relative_frame_number = USUB(ohci->frame_number, starting_frame); 734 735 trace_usb_ohci_iso_td_head( 736 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 737 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 738 ohci->frame_number, starting_frame, 739 frame_count, relative_frame_number); 740 trace_usb_ohci_iso_td_head_offset( 741 iso_td.offset[0], iso_td.offset[1], 742 iso_td.offset[2], iso_td.offset[3], 743 iso_td.offset[4], iso_td.offset[5], 744 iso_td.offset[6], iso_td.offset[7]); 745 746 if (relative_frame_number < 0) { 747 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); 748 return 1; 749 } else if (relative_frame_number > frame_count) { 750 /* ISO TD expired - retire the TD to the Done Queue and continue with 751 the next ISO TD of the same ED */ 752 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, 753 frame_count); 754 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 755 ed->head &= ~OHCI_DPTR_MASK; 756 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 757 iso_td.next = ohci->done; 758 ohci->done = addr; 759 i = OHCI_BM(iso_td.flags, TD_DI); 760 if (i < ohci->done_count) 761 ohci->done_count = i; 762 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 763 ohci_die(ohci); 764 return 1; 765 } 766 return 0; 767 } 768 769 dir = OHCI_BM(ed->flags, ED_D); 770 switch (dir) { 771 case OHCI_TD_DIR_IN: 772 str = "in"; 773 pid = USB_TOKEN_IN; 774 break; 775 case OHCI_TD_DIR_OUT: 776 str = "out"; 777 pid = USB_TOKEN_OUT; 778 break; 779 case OHCI_TD_DIR_SETUP: 780 str = "setup"; 781 pid = USB_TOKEN_SETUP; 782 break; 783 default: 784 trace_usb_ohci_iso_td_bad_direction(dir); 785 return 1; 786 } 787 788 if (!iso_td.bp || !iso_td.be) { 789 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); 790 return 1; 791 } 792 793 start_offset = iso_td.offset[relative_frame_number]; 794 next_offset = iso_td.offset[relative_frame_number + 1]; 795 796 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 797 ((relative_frame_number < frame_count) && 798 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 799 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); 800 return 1; 801 } 802 803 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 804 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); 805 return 1; 806 } 807 808 if ((start_offset & 0x1000) == 0) { 809 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 810 (start_offset & OHCI_OFFSET_MASK); 811 } else { 812 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 813 (start_offset & OHCI_OFFSET_MASK); 814 } 815 816 if (relative_frame_number < frame_count) { 817 end_offset = next_offset - 1; 818 if ((end_offset & 0x1000) == 0) { 819 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 820 (end_offset & OHCI_OFFSET_MASK); 821 } else { 822 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 823 (end_offset & OHCI_OFFSET_MASK); 824 } 825 } else { 826 /* Last packet in the ISO TD */ 827 end_addr = iso_td.be; 828 } 829 830 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 831 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 832 - (start_addr & OHCI_OFFSET_MASK); 833 } else { 834 len = end_addr - start_addr + 1; 835 } 836 837 if (len && dir != OHCI_TD_DIR_IN) { 838 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 839 DMA_DIRECTION_TO_DEVICE)) { 840 ohci_die(ohci); 841 return 1; 842 } 843 } 844 845 if (!completion) { 846 bool int_req = relative_frame_number == frame_count && 847 OHCI_BM(iso_td.flags, TD_DI) == 0; 848 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 849 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 850 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); 851 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); 852 usb_handle_packet(dev, &ohci->usb_packet); 853 if (ohci->usb_packet.status == USB_RET_ASYNC) { 854 usb_device_flush_ep_queue(dev, ep); 855 return 1; 856 } 857 } 858 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 859 ret = ohci->usb_packet.actual_length; 860 } else { 861 ret = ohci->usb_packet.status; 862 } 863 864 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, 865 str, len, ret); 866 867 /* Writeback */ 868 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 869 /* IN transfer succeeded */ 870 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 871 DMA_DIRECTION_FROM_DEVICE)) { 872 ohci_die(ohci); 873 return 1; 874 } 875 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 876 OHCI_CC_NOERROR); 877 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 878 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 879 /* OUT transfer succeeded */ 880 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 881 OHCI_CC_NOERROR); 882 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 883 } else { 884 if (ret > (ssize_t) len) { 885 trace_usb_ohci_iso_td_data_overrun(ret, len); 886 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 887 OHCI_CC_DATAOVERRUN); 888 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 889 len); 890 } else if (ret >= 0) { 891 trace_usb_ohci_iso_td_data_underrun(ret); 892 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 893 OHCI_CC_DATAUNDERRUN); 894 } else { 895 switch (ret) { 896 case USB_RET_IOERROR: 897 case USB_RET_NODEV: 898 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 899 OHCI_CC_DEVICENOTRESPONDING); 900 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 901 0); 902 break; 903 case USB_RET_NAK: 904 case USB_RET_STALL: 905 trace_usb_ohci_iso_td_nak(ret); 906 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 907 OHCI_CC_STALL); 908 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 909 0); 910 break; 911 default: 912 trace_usb_ohci_iso_td_bad_response(ret); 913 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 914 OHCI_CC_UNDEXPETEDPID); 915 break; 916 } 917 } 918 } 919 920 if (relative_frame_number == frame_count) { 921 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 922 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 923 ed->head &= ~OHCI_DPTR_MASK; 924 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 925 iso_td.next = ohci->done; 926 ohci->done = addr; 927 i = OHCI_BM(iso_td.flags, TD_DI); 928 if (i < ohci->done_count) 929 ohci->done_count = i; 930 } 931 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 932 ohci_die(ohci); 933 } 934 return 1; 935 } 936 937 #ifdef trace_event_get_state 938 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 939 { 940 bool print16 = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_SHORT); 941 bool printall = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_FULL); 942 const int width = 16; 943 int i; 944 char tmp[3 * width + 1]; 945 char *p = tmp; 946 947 if (!printall && !print16) { 948 return; 949 } 950 951 for (i = 0; ; i++) { 952 if (i && (!(i % width) || (i == len))) { 953 if (!printall) { 954 trace_usb_ohci_td_pkt_short(msg, tmp); 955 break; 956 } 957 trace_usb_ohci_td_pkt_full(msg, tmp); 958 p = tmp; 959 *p = 0; 960 } 961 if (i == len) { 962 break; 963 } 964 965 p += sprintf(p, " %.2x", buf[i]); 966 } 967 } 968 #else 969 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 970 { 971 } 972 #endif 973 974 /* Service a transport descriptor. 975 Returns nonzero to terminate processing of this endpoint. */ 976 977 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 978 { 979 int dir; 980 size_t len = 0, pktlen = 0; 981 const char *str = NULL; 982 int pid; 983 int ret; 984 int i; 985 USBDevice *dev; 986 USBEndpoint *ep; 987 struct ohci_td td; 988 uint32_t addr; 989 int flag_r; 990 int completion; 991 992 addr = ed->head & OHCI_DPTR_MASK; 993 /* See if this TD has already been submitted to the device. */ 994 completion = (addr == ohci->async_td); 995 if (completion && !ohci->async_complete) { 996 trace_usb_ohci_td_skip_async(); 997 return 1; 998 } 999 if (ohci_read_td(ohci, addr, &td)) { 1000 trace_usb_ohci_td_read_error(addr); 1001 ohci_die(ohci); 1002 return 0; 1003 } 1004 1005 dir = OHCI_BM(ed->flags, ED_D); 1006 switch (dir) { 1007 case OHCI_TD_DIR_OUT: 1008 case OHCI_TD_DIR_IN: 1009 /* Same value. */ 1010 break; 1011 default: 1012 dir = OHCI_BM(td.flags, TD_DP); 1013 break; 1014 } 1015 1016 switch (dir) { 1017 case OHCI_TD_DIR_IN: 1018 str = "in"; 1019 pid = USB_TOKEN_IN; 1020 break; 1021 case OHCI_TD_DIR_OUT: 1022 str = "out"; 1023 pid = USB_TOKEN_OUT; 1024 break; 1025 case OHCI_TD_DIR_SETUP: 1026 str = "setup"; 1027 pid = USB_TOKEN_SETUP; 1028 break; 1029 default: 1030 trace_usb_ohci_td_bad_direction(dir); 1031 return 1; 1032 } 1033 if (td.cbp && td.be) { 1034 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 1035 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 1036 } else { 1037 len = (td.be - td.cbp) + 1; 1038 } 1039 1040 pktlen = len; 1041 if (len && dir != OHCI_TD_DIR_IN) { 1042 /* The endpoint may not allow us to transfer it all now */ 1043 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 1044 if (pktlen > len) { 1045 pktlen = len; 1046 } 1047 if (!completion) { 1048 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 1049 DMA_DIRECTION_TO_DEVICE)) { 1050 ohci_die(ohci); 1051 } 1052 } 1053 } 1054 } 1055 1056 flag_r = (td.flags & OHCI_TD_R) != 0; 1057 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, 1058 flag_r, td.cbp, td.be); 1059 ohci_td_pkt("OUT", ohci->usb_buf, pktlen); 1060 1061 if (completion) { 1062 ohci->async_td = 0; 1063 ohci->async_complete = false; 1064 } else { 1065 if (ohci->async_td) { 1066 /* ??? The hardware should allow one active packet per 1067 endpoint. We only allow one active packet per controller. 1068 This should be sufficient as long as devices respond in a 1069 timely manner. 1070 */ 1071 trace_usb_ohci_td_too_many_pending(); 1072 return 1; 1073 } 1074 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 1075 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 1076 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, 1077 OHCI_BM(td.flags, TD_DI) == 0); 1078 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 1079 usb_handle_packet(dev, &ohci->usb_packet); 1080 trace_usb_ohci_td_packet_status(ohci->usb_packet.status); 1081 1082 if (ohci->usb_packet.status == USB_RET_ASYNC) { 1083 usb_device_flush_ep_queue(dev, ep); 1084 ohci->async_td = addr; 1085 return 1; 1086 } 1087 } 1088 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 1089 ret = ohci->usb_packet.actual_length; 1090 } else { 1091 ret = ohci->usb_packet.status; 1092 } 1093 1094 if (ret >= 0) { 1095 if (dir == OHCI_TD_DIR_IN) { 1096 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1097 DMA_DIRECTION_FROM_DEVICE)) { 1098 ohci_die(ohci); 1099 } 1100 ohci_td_pkt("IN", ohci->usb_buf, pktlen); 1101 } else { 1102 ret = pktlen; 1103 } 1104 } 1105 1106 /* Writeback */ 1107 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 1108 /* Transmission succeeded. */ 1109 if (ret == len) { 1110 td.cbp = 0; 1111 } else { 1112 if ((td.cbp & 0xfff) + ret > 0xfff) { 1113 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 1114 } else { 1115 td.cbp += ret; 1116 } 1117 } 1118 td.flags |= OHCI_TD_T1; 1119 td.flags ^= OHCI_TD_T0; 1120 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1121 OHCI_SET_BM(td.flags, TD_EC, 0); 1122 1123 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1124 /* Partial packet transfer: TD not ready to retire yet */ 1125 goto exit_no_retire; 1126 } 1127 1128 /* Setting ED_C is part of the TD retirement process */ 1129 ed->head &= ~OHCI_ED_C; 1130 if (td.flags & OHCI_TD_T0) 1131 ed->head |= OHCI_ED_C; 1132 } else { 1133 if (ret >= 0) { 1134 trace_usb_ohci_td_underrun(); 1135 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1136 } else { 1137 switch (ret) { 1138 case USB_RET_IOERROR: 1139 case USB_RET_NODEV: 1140 trace_usb_ohci_td_dev_error(); 1141 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1142 break; 1143 case USB_RET_NAK: 1144 trace_usb_ohci_td_nak(); 1145 return 1; 1146 case USB_RET_STALL: 1147 trace_usb_ohci_td_stall(); 1148 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1149 break; 1150 case USB_RET_BABBLE: 1151 trace_usb_ohci_td_babble(); 1152 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1153 break; 1154 default: 1155 trace_usb_ohci_td_bad_device_response(ret); 1156 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1157 OHCI_SET_BM(td.flags, TD_EC, 3); 1158 break; 1159 } 1160 } 1161 ed->head |= OHCI_ED_H; 1162 } 1163 1164 /* Retire this TD */ 1165 ed->head &= ~OHCI_DPTR_MASK; 1166 ed->head |= td.next & OHCI_DPTR_MASK; 1167 td.next = ohci->done; 1168 ohci->done = addr; 1169 i = OHCI_BM(td.flags, TD_DI); 1170 if (i < ohci->done_count) 1171 ohci->done_count = i; 1172 exit_no_retire: 1173 if (ohci_put_td(ohci, addr, &td)) { 1174 ohci_die(ohci); 1175 return 1; 1176 } 1177 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1178 } 1179 1180 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1181 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) 1182 { 1183 struct ohci_ed ed; 1184 uint32_t next_ed; 1185 uint32_t cur; 1186 int active; 1187 1188 active = 0; 1189 1190 if (head == 0) 1191 return 0; 1192 1193 for (cur = head; cur; cur = next_ed) { 1194 if (ohci_read_ed(ohci, cur, &ed)) { 1195 trace_usb_ohci_ed_read_error(cur); 1196 ohci_die(ohci); 1197 return 0; 1198 } 1199 1200 next_ed = ed.next & OHCI_DPTR_MASK; 1201 1202 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1203 uint32_t addr; 1204 /* Cancel pending packets for ED that have been paused. */ 1205 addr = ed.head & OHCI_DPTR_MASK; 1206 if (ohci->async_td && addr == ohci->async_td) { 1207 usb_cancel_packet(&ohci->usb_packet); 1208 ohci->async_td = 0; 1209 usb_device_ep_stopped(ohci->usb_packet.ep->dev, 1210 ohci->usb_packet.ep); 1211 } 1212 continue; 1213 } 1214 1215 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1216 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, 1217 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1218 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1219 trace_usb_ohci_ed_pkt_flags( 1220 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1221 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1222 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1223 OHCI_BM(ed.flags, ED_MPS)); 1224 1225 active = 1; 1226 1227 if ((ed.flags & OHCI_ED_F) == 0) { 1228 if (ohci_service_td(ohci, &ed)) 1229 break; 1230 } else { 1231 /* Handle isochronous endpoints */ 1232 if (ohci_service_iso_td(ohci, &ed, completion)) 1233 break; 1234 } 1235 } 1236 1237 if (ohci_put_ed(ohci, cur, &ed)) { 1238 ohci_die(ohci); 1239 return 0; 1240 } 1241 } 1242 1243 return active; 1244 } 1245 1246 /* set a timer for EOF */ 1247 static void ohci_eof_timer(OHCIState *ohci) 1248 { 1249 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1250 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1251 } 1252 /* Set a timer for EOF and generate a SOF event */ 1253 static void ohci_sof(OHCIState *ohci) 1254 { 1255 ohci_eof_timer(ohci); 1256 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1257 } 1258 1259 /* Process Control and Bulk lists. */ 1260 static void ohci_process_lists(OHCIState *ohci, int completion) 1261 { 1262 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1263 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1264 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); 1265 } 1266 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { 1267 ohci->ctrl_cur = 0; 1268 ohci->status &= ~OHCI_STATUS_CLF; 1269 } 1270 } 1271 1272 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1273 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { 1274 ohci->bulk_cur = 0; 1275 ohci->status &= ~OHCI_STATUS_BLF; 1276 } 1277 } 1278 } 1279 1280 /* Do frame processing on frame boundary */ 1281 static void ohci_frame_boundary(void *opaque) 1282 { 1283 OHCIState *ohci = opaque; 1284 struct ohci_hcca hcca; 1285 1286 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { 1287 trace_usb_ohci_hcca_read_error(ohci->hcca); 1288 ohci_die(ohci); 1289 return; 1290 } 1291 1292 /* Process all the lists at the end of the frame */ 1293 if (ohci->ctl & OHCI_CTL_PLE) { 1294 int n; 1295 1296 n = ohci->frame_number & 0x1f; 1297 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); 1298 } 1299 1300 /* Cancel all pending packets if either of the lists has been disabled. */ 1301 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1302 if (ohci->async_td) { 1303 usb_cancel_packet(&ohci->usb_packet); 1304 ohci->async_td = 0; 1305 } 1306 ohci_stop_endpoints(ohci); 1307 } 1308 ohci->old_ctl = ohci->ctl; 1309 ohci_process_lists(ohci, 0); 1310 1311 /* Stop if UnrecoverableError happened or ohci_sof will crash */ 1312 if (ohci->intr_status & OHCI_INTR_UE) { 1313 return; 1314 } 1315 1316 /* Frame boundary, so do EOF stuf here */ 1317 ohci->frt = ohci->fit; 1318 1319 /* Increment frame number and take care of endianness. */ 1320 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1321 hcca.frame = cpu_to_le16(ohci->frame_number); 1322 1323 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1324 if (!ohci->done) 1325 abort(); 1326 if (ohci->intr & ohci->intr_status) 1327 ohci->done |= 1; 1328 hcca.done = cpu_to_le32(ohci->done); 1329 ohci->done = 0; 1330 ohci->done_count = 7; 1331 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1332 } 1333 1334 if (ohci->done_count != 7 && ohci->done_count != 0) 1335 ohci->done_count--; 1336 1337 /* Do SOF stuff here */ 1338 ohci_sof(ohci); 1339 1340 /* Writeback HCCA */ 1341 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { 1342 ohci_die(ohci); 1343 } 1344 } 1345 1346 /* Start sending SOF tokens across the USB bus, lists are processed in 1347 * next frame 1348 */ 1349 static int ohci_bus_start(OHCIState *ohci) 1350 { 1351 trace_usb_ohci_start(ohci->name); 1352 1353 /* Delay the first SOF event by one frame time as 1354 * linux driver is not ready to receive it and 1355 * can meet some race conditions 1356 */ 1357 1358 ohci_eof_timer(ohci); 1359 1360 return 1; 1361 } 1362 1363 /* Stop sending SOF tokens on the bus */ 1364 static void ohci_bus_stop(OHCIState *ohci) 1365 { 1366 trace_usb_ohci_stop(ohci->name); 1367 timer_del(ohci->eof_timer); 1368 } 1369 1370 /* Sets a flag in a port status register but only set it if the port is 1371 * connected, if not set ConnectStatusChange flag. If flag is enabled 1372 * return 1. 1373 */ 1374 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1375 { 1376 int ret = 1; 1377 1378 /* writing a 0 has no effect */ 1379 if (val == 0) 1380 return 0; 1381 1382 /* If CurrentConnectStatus is cleared we set 1383 * ConnectStatusChange 1384 */ 1385 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1386 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1387 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1388 /* TODO: CSC is a wakeup event */ 1389 } 1390 return 0; 1391 } 1392 1393 if (ohci->rhport[i].ctrl & val) 1394 ret = 0; 1395 1396 /* set the bit */ 1397 ohci->rhport[i].ctrl |= val; 1398 1399 return ret; 1400 } 1401 1402 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1403 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1404 { 1405 val &= OHCI_FMI_FI; 1406 1407 if (val != ohci->fi) { 1408 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); 1409 } 1410 1411 ohci->fi = val; 1412 } 1413 1414 static void ohci_port_power(OHCIState *ohci, int i, int p) 1415 { 1416 if (p) { 1417 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1418 } else { 1419 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1420 OHCI_PORT_CCS| 1421 OHCI_PORT_PSS| 1422 OHCI_PORT_PRS); 1423 } 1424 } 1425 1426 /* Set HcControlRegister */ 1427 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1428 { 1429 uint32_t old_state; 1430 uint32_t new_state; 1431 1432 old_state = ohci->ctl & OHCI_CTL_HCFS; 1433 ohci->ctl = val; 1434 new_state = ohci->ctl & OHCI_CTL_HCFS; 1435 1436 /* no state change */ 1437 if (old_state == new_state) 1438 return; 1439 1440 trace_usb_ohci_set_ctl(ohci->name, new_state); 1441 switch (new_state) { 1442 case OHCI_USB_OPERATIONAL: 1443 ohci_bus_start(ohci); 1444 break; 1445 case OHCI_USB_SUSPEND: 1446 ohci_bus_stop(ohci); 1447 /* clear pending SF otherwise linux driver loops in ohci_irq() */ 1448 ohci->intr_status &= ~OHCI_INTR_SF; 1449 ohci_intr_update(ohci); 1450 break; 1451 case OHCI_USB_RESUME: 1452 trace_usb_ohci_resume(ohci->name); 1453 break; 1454 case OHCI_USB_RESET: 1455 ohci_roothub_reset(ohci); 1456 break; 1457 } 1458 } 1459 1460 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1461 { 1462 uint16_t fr; 1463 int64_t tks; 1464 1465 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1466 return (ohci->frt << 31); 1467 1468 /* Being in USB operational state guarnatees sof_time was 1469 * set already. 1470 */ 1471 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; 1472 1473 /* avoid muldiv if possible */ 1474 if (tks >= usb_frame_time) 1475 return (ohci->frt << 31); 1476 1477 tks = tks / usb_bit_time; 1478 fr = (uint16_t)(ohci->fi - tks); 1479 1480 return (ohci->frt << 31) | fr; 1481 } 1482 1483 1484 /* Set root hub status */ 1485 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1486 { 1487 uint32_t old_state; 1488 1489 old_state = ohci->rhstatus; 1490 1491 /* write 1 to clear OCIC */ 1492 if (val & OHCI_RHS_OCIC) 1493 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1494 1495 if (val & OHCI_RHS_LPS) { 1496 int i; 1497 1498 for (i = 0; i < ohci->num_ports; i++) 1499 ohci_port_power(ohci, i, 0); 1500 trace_usb_ohci_hub_power_down(); 1501 } 1502 1503 if (val & OHCI_RHS_LPSC) { 1504 int i; 1505 1506 for (i = 0; i < ohci->num_ports; i++) 1507 ohci_port_power(ohci, i, 1); 1508 trace_usb_ohci_hub_power_up(); 1509 } 1510 1511 if (val & OHCI_RHS_DRWE) 1512 ohci->rhstatus |= OHCI_RHS_DRWE; 1513 1514 if (val & OHCI_RHS_CRWE) 1515 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1516 1517 if (old_state != ohci->rhstatus) 1518 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1519 } 1520 1521 /* Set root hub port status */ 1522 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1523 { 1524 uint32_t old_state; 1525 OHCIPort *port; 1526 1527 port = &ohci->rhport[portnum]; 1528 old_state = port->ctrl; 1529 1530 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1531 if (val & OHCI_PORT_WTC) 1532 port->ctrl &= ~(val & OHCI_PORT_WTC); 1533 1534 if (val & OHCI_PORT_CCS) 1535 port->ctrl &= ~OHCI_PORT_PES; 1536 1537 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1538 1539 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1540 trace_usb_ohci_port_suspend(portnum); 1541 } 1542 1543 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1544 trace_usb_ohci_port_reset(portnum); 1545 usb_device_reset(port->port.dev); 1546 port->ctrl &= ~OHCI_PORT_PRS; 1547 /* ??? Should this also set OHCI_PORT_PESC. */ 1548 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1549 } 1550 1551 /* Invert order here to ensure in ambiguous case, device is 1552 * powered up... 1553 */ 1554 if (val & OHCI_PORT_LSDA) 1555 ohci_port_power(ohci, portnum, 0); 1556 if (val & OHCI_PORT_PPS) 1557 ohci_port_power(ohci, portnum, 1); 1558 1559 if (old_state != port->ctrl) 1560 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1561 } 1562 1563 static uint64_t ohci_mem_read(void *opaque, 1564 hwaddr addr, 1565 unsigned size) 1566 { 1567 OHCIState *ohci = opaque; 1568 uint32_t retval; 1569 1570 /* Only aligned reads are allowed on OHCI */ 1571 if (addr & 3) { 1572 trace_usb_ohci_mem_read_unaligned(addr); 1573 return 0xffffffff; 1574 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1575 /* HcRhPortStatus */ 1576 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1577 } else { 1578 switch (addr >> 2) { 1579 case 0: /* HcRevision */ 1580 retval = 0x10; 1581 break; 1582 1583 case 1: /* HcControl */ 1584 retval = ohci->ctl; 1585 break; 1586 1587 case 2: /* HcCommandStatus */ 1588 retval = ohci->status; 1589 break; 1590 1591 case 3: /* HcInterruptStatus */ 1592 retval = ohci->intr_status; 1593 break; 1594 1595 case 4: /* HcInterruptEnable */ 1596 case 5: /* HcInterruptDisable */ 1597 retval = ohci->intr; 1598 break; 1599 1600 case 6: /* HcHCCA */ 1601 retval = ohci->hcca; 1602 break; 1603 1604 case 7: /* HcPeriodCurrentED */ 1605 retval = ohci->per_cur; 1606 break; 1607 1608 case 8: /* HcControlHeadED */ 1609 retval = ohci->ctrl_head; 1610 break; 1611 1612 case 9: /* HcControlCurrentED */ 1613 retval = ohci->ctrl_cur; 1614 break; 1615 1616 case 10: /* HcBulkHeadED */ 1617 retval = ohci->bulk_head; 1618 break; 1619 1620 case 11: /* HcBulkCurrentED */ 1621 retval = ohci->bulk_cur; 1622 break; 1623 1624 case 12: /* HcDoneHead */ 1625 retval = ohci->done; 1626 break; 1627 1628 case 13: /* HcFmInterretval */ 1629 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1630 break; 1631 1632 case 14: /* HcFmRemaining */ 1633 retval = ohci_get_frame_remaining(ohci); 1634 break; 1635 1636 case 15: /* HcFmNumber */ 1637 retval = ohci->frame_number; 1638 break; 1639 1640 case 16: /* HcPeriodicStart */ 1641 retval = ohci->pstart; 1642 break; 1643 1644 case 17: /* HcLSThreshold */ 1645 retval = ohci->lst; 1646 break; 1647 1648 case 18: /* HcRhDescriptorA */ 1649 retval = ohci->rhdesc_a; 1650 break; 1651 1652 case 19: /* HcRhDescriptorB */ 1653 retval = ohci->rhdesc_b; 1654 break; 1655 1656 case 20: /* HcRhStatus */ 1657 retval = ohci->rhstatus; 1658 break; 1659 1660 /* PXA27x specific registers */ 1661 case 24: /* HcStatus */ 1662 retval = ohci->hstatus & ohci->hmask; 1663 break; 1664 1665 case 25: /* HcHReset */ 1666 retval = ohci->hreset; 1667 break; 1668 1669 case 26: /* HcHInterruptEnable */ 1670 retval = ohci->hmask; 1671 break; 1672 1673 case 27: /* HcHInterruptTest */ 1674 retval = ohci->htest; 1675 break; 1676 1677 default: 1678 trace_usb_ohci_mem_read_bad_offset(addr); 1679 retval = 0xffffffff; 1680 } 1681 } 1682 1683 return retval; 1684 } 1685 1686 static void ohci_mem_write(void *opaque, 1687 hwaddr addr, 1688 uint64_t val, 1689 unsigned size) 1690 { 1691 OHCIState *ohci = opaque; 1692 1693 /* Only aligned reads are allowed on OHCI */ 1694 if (addr & 3) { 1695 trace_usb_ohci_mem_write_unaligned(addr); 1696 return; 1697 } 1698 1699 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1700 /* HcRhPortStatus */ 1701 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1702 return; 1703 } 1704 1705 switch (addr >> 2) { 1706 case 1: /* HcControl */ 1707 ohci_set_ctl(ohci, val); 1708 break; 1709 1710 case 2: /* HcCommandStatus */ 1711 /* SOC is read-only */ 1712 val = (val & ~OHCI_STATUS_SOC); 1713 1714 /* Bits written as '0' remain unchanged in the register */ 1715 ohci->status |= val; 1716 1717 if (ohci->status & OHCI_STATUS_HCR) 1718 ohci_soft_reset(ohci); 1719 break; 1720 1721 case 3: /* HcInterruptStatus */ 1722 ohci->intr_status &= ~val; 1723 ohci_intr_update(ohci); 1724 break; 1725 1726 case 4: /* HcInterruptEnable */ 1727 ohci->intr |= val; 1728 ohci_intr_update(ohci); 1729 break; 1730 1731 case 5: /* HcInterruptDisable */ 1732 ohci->intr &= ~val; 1733 ohci_intr_update(ohci); 1734 break; 1735 1736 case 6: /* HcHCCA */ 1737 ohci->hcca = val & OHCI_HCCA_MASK; 1738 break; 1739 1740 case 7: /* HcPeriodCurrentED */ 1741 /* Ignore writes to this read-only register, Linux does them */ 1742 break; 1743 1744 case 8: /* HcControlHeadED */ 1745 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1746 break; 1747 1748 case 9: /* HcControlCurrentED */ 1749 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1750 break; 1751 1752 case 10: /* HcBulkHeadED */ 1753 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1754 break; 1755 1756 case 11: /* HcBulkCurrentED */ 1757 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1758 break; 1759 1760 case 13: /* HcFmInterval */ 1761 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1762 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1763 ohci_set_frame_interval(ohci, val); 1764 break; 1765 1766 case 15: /* HcFmNumber */ 1767 break; 1768 1769 case 16: /* HcPeriodicStart */ 1770 ohci->pstart = val & 0xffff; 1771 break; 1772 1773 case 17: /* HcLSThreshold */ 1774 ohci->lst = val & 0xffff; 1775 break; 1776 1777 case 18: /* HcRhDescriptorA */ 1778 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1779 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1780 break; 1781 1782 case 19: /* HcRhDescriptorB */ 1783 break; 1784 1785 case 20: /* HcRhStatus */ 1786 ohci_set_hub_status(ohci, val); 1787 break; 1788 1789 /* PXA27x specific registers */ 1790 case 24: /* HcStatus */ 1791 ohci->hstatus &= ~(val & ohci->hmask); 1792 break; 1793 1794 case 25: /* HcHReset */ 1795 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1796 if (val & OHCI_HRESET_FSBIR) 1797 ohci_hard_reset(ohci); 1798 break; 1799 1800 case 26: /* HcHInterruptEnable */ 1801 ohci->hmask = val; 1802 break; 1803 1804 case 27: /* HcHInterruptTest */ 1805 ohci->htest = val; 1806 break; 1807 1808 default: 1809 trace_usb_ohci_mem_write_bad_offset(addr); 1810 break; 1811 } 1812 } 1813 1814 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) 1815 { 1816 if (ohci->async_td && 1817 usb_packet_is_inflight(&ohci->usb_packet) && 1818 ohci->usb_packet.ep->dev == dev) { 1819 usb_cancel_packet(&ohci->usb_packet); 1820 ohci->async_td = 0; 1821 } 1822 } 1823 1824 static const MemoryRegionOps ohci_mem_ops = { 1825 .read = ohci_mem_read, 1826 .write = ohci_mem_write, 1827 .endianness = DEVICE_LITTLE_ENDIAN, 1828 }; 1829 1830 static USBPortOps ohci_port_ops = { 1831 .attach = ohci_attach, 1832 .detach = ohci_detach, 1833 .child_detach = ohci_child_detach, 1834 .wakeup = ohci_wakeup, 1835 .complete = ohci_async_complete_packet, 1836 }; 1837 1838 static USBBusOps ohci_bus_ops = { 1839 }; 1840 1841 static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, 1842 int num_ports, dma_addr_t localmem_base, 1843 char *masterbus, uint32_t firstport, 1844 AddressSpace *as, Error **errp) 1845 { 1846 Error *err = NULL; 1847 int i; 1848 1849 ohci->as = as; 1850 1851 if (num_ports > OHCI_MAX_PORTS) { 1852 error_setg(errp, "OHCI num-ports=%d is too big (limit is %d ports)", 1853 num_ports, OHCI_MAX_PORTS); 1854 return; 1855 } 1856 1857 if (usb_frame_time == 0) { 1858 #ifdef OHCI_TIME_WARP 1859 usb_frame_time = NANOSECONDS_PER_SECOND; 1860 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000); 1861 #else 1862 usb_frame_time = NANOSECONDS_PER_SECOND / 1000; 1863 if (NANOSECONDS_PER_SECOND >= USB_HZ) { 1864 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ; 1865 } else { 1866 usb_bit_time = 1; 1867 } 1868 #endif 1869 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); 1870 } 1871 1872 ohci->num_ports = num_ports; 1873 if (masterbus) { 1874 USBPort *ports[OHCI_MAX_PORTS]; 1875 for(i = 0; i < num_ports; i++) { 1876 ports[i] = &ohci->rhport[i].port; 1877 } 1878 usb_register_companion(masterbus, ports, num_ports, 1879 firstport, ohci, &ohci_port_ops, 1880 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1881 &err); 1882 if (err) { 1883 error_propagate(errp, err); 1884 return; 1885 } 1886 } else { 1887 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); 1888 for (i = 0; i < num_ports; i++) { 1889 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1890 ohci, i, &ohci_port_ops, 1891 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1892 } 1893 } 1894 1895 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, 1896 ohci, "ohci", 256); 1897 ohci->localmem_base = localmem_base; 1898 1899 ohci->name = object_get_typename(OBJECT(dev)); 1900 usb_packet_init(&ohci->usb_packet); 1901 1902 ohci->async_td = 0; 1903 1904 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1905 ohci_frame_boundary, ohci); 1906 } 1907 1908 #define TYPE_PCI_OHCI "pci-ohci" 1909 #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI) 1910 1911 typedef struct { 1912 /*< private >*/ 1913 PCIDevice parent_obj; 1914 /*< public >*/ 1915 1916 OHCIState state; 1917 char *masterbus; 1918 uint32_t num_ports; 1919 uint32_t firstport; 1920 } OHCIPCIState; 1921 1922 /** A typical O/EHCI will stop operating, set itself into error state 1923 * (which can be queried by MMIO) and will set PERR in its config 1924 * space to signal that it got an error 1925 */ 1926 static void ohci_die(OHCIState *ohci) 1927 { 1928 OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state); 1929 1930 trace_usb_ohci_die(); 1931 1932 ohci_set_interrupt(ohci, OHCI_INTR_UE); 1933 ohci_bus_stop(ohci); 1934 pci_set_word(dev->parent_obj.config + PCI_STATUS, 1935 PCI_STATUS_DETECTED_PARITY); 1936 } 1937 1938 static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp) 1939 { 1940 Error *err = NULL; 1941 OHCIPCIState *ohci = PCI_OHCI(dev); 1942 1943 dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */ 1944 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1945 1946 usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0, 1947 ohci->masterbus, ohci->firstport, 1948 pci_get_address_space(dev), &err); 1949 if (err) { 1950 error_propagate(errp, err); 1951 return; 1952 } 1953 1954 ohci->state.irq = pci_allocate_irq(dev); 1955 pci_register_bar(dev, 0, 0, &ohci->state.mem); 1956 } 1957 1958 static void usb_ohci_exit(PCIDevice *dev) 1959 { 1960 OHCIPCIState *ohci = PCI_OHCI(dev); 1961 OHCIState *s = &ohci->state; 1962 1963 trace_usb_ohci_exit(s->name); 1964 ohci_bus_stop(s); 1965 1966 if (s->async_td) { 1967 usb_cancel_packet(&s->usb_packet); 1968 s->async_td = 0; 1969 } 1970 ohci_stop_endpoints(s); 1971 1972 if (!ohci->masterbus) { 1973 usb_bus_release(&s->bus); 1974 } 1975 1976 timer_del(s->eof_timer); 1977 timer_free(s->eof_timer); 1978 } 1979 1980 static void usb_ohci_reset_pci(DeviceState *d) 1981 { 1982 PCIDevice *dev = PCI_DEVICE(d); 1983 OHCIPCIState *ohci = PCI_OHCI(dev); 1984 OHCIState *s = &ohci->state; 1985 1986 ohci_hard_reset(s); 1987 } 1988 1989 #define TYPE_SYSBUS_OHCI "sysbus-ohci" 1990 #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI) 1991 1992 typedef struct { 1993 /*< private >*/ 1994 SysBusDevice parent_obj; 1995 /*< public >*/ 1996 1997 OHCIState ohci; 1998 uint32_t num_ports; 1999 dma_addr_t dma_offset; 2000 } OHCISysBusState; 2001 2002 static void ohci_realize_pxa(DeviceState *dev, Error **errp) 2003 { 2004 OHCISysBusState *s = SYSBUS_OHCI(dev); 2005 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 2006 2007 /* Cannot fail as we pass NULL for masterbus */ 2008 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, NULL, 0, 2009 &address_space_memory, &error_abort); 2010 sysbus_init_irq(sbd, &s->ohci.irq); 2011 sysbus_init_mmio(sbd, &s->ohci.mem); 2012 } 2013 2014 static void usb_ohci_reset_sysbus(DeviceState *dev) 2015 { 2016 OHCISysBusState *s = SYSBUS_OHCI(dev); 2017 OHCIState *ohci = &s->ohci; 2018 2019 ohci_hard_reset(ohci); 2020 } 2021 2022 static Property ohci_pci_properties[] = { 2023 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), 2024 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), 2025 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), 2026 DEFINE_PROP_END_OF_LIST(), 2027 }; 2028 2029 static const VMStateDescription vmstate_ohci_state_port = { 2030 .name = "ohci-core/port", 2031 .version_id = 1, 2032 .minimum_version_id = 1, 2033 .fields = (VMStateField[]) { 2034 VMSTATE_UINT32(ctrl, OHCIPort), 2035 VMSTATE_END_OF_LIST() 2036 }, 2037 }; 2038 2039 static bool ohci_eof_timer_needed(void *opaque) 2040 { 2041 OHCIState *ohci = opaque; 2042 2043 return timer_pending(ohci->eof_timer); 2044 } 2045 2046 static const VMStateDescription vmstate_ohci_eof_timer = { 2047 .name = "ohci-core/eof-timer", 2048 .version_id = 1, 2049 .minimum_version_id = 1, 2050 .needed = ohci_eof_timer_needed, 2051 .fields = (VMStateField[]) { 2052 VMSTATE_TIMER_PTR(eof_timer, OHCIState), 2053 VMSTATE_END_OF_LIST() 2054 }, 2055 }; 2056 2057 static const VMStateDescription vmstate_ohci_state = { 2058 .name = "ohci-core", 2059 .version_id = 1, 2060 .minimum_version_id = 1, 2061 .fields = (VMStateField[]) { 2062 VMSTATE_INT64(sof_time, OHCIState), 2063 VMSTATE_UINT32(ctl, OHCIState), 2064 VMSTATE_UINT32(status, OHCIState), 2065 VMSTATE_UINT32(intr_status, OHCIState), 2066 VMSTATE_UINT32(intr, OHCIState), 2067 VMSTATE_UINT32(hcca, OHCIState), 2068 VMSTATE_UINT32(ctrl_head, OHCIState), 2069 VMSTATE_UINT32(ctrl_cur, OHCIState), 2070 VMSTATE_UINT32(bulk_head, OHCIState), 2071 VMSTATE_UINT32(bulk_cur, OHCIState), 2072 VMSTATE_UINT32(per_cur, OHCIState), 2073 VMSTATE_UINT32(done, OHCIState), 2074 VMSTATE_INT32(done_count, OHCIState), 2075 VMSTATE_UINT16(fsmps, OHCIState), 2076 VMSTATE_UINT8(fit, OHCIState), 2077 VMSTATE_UINT16(fi, OHCIState), 2078 VMSTATE_UINT8(frt, OHCIState), 2079 VMSTATE_UINT16(frame_number, OHCIState), 2080 VMSTATE_UINT16(padding, OHCIState), 2081 VMSTATE_UINT32(pstart, OHCIState), 2082 VMSTATE_UINT32(lst, OHCIState), 2083 VMSTATE_UINT32(rhdesc_a, OHCIState), 2084 VMSTATE_UINT32(rhdesc_b, OHCIState), 2085 VMSTATE_UINT32(rhstatus, OHCIState), 2086 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, 2087 vmstate_ohci_state_port, OHCIPort), 2088 VMSTATE_UINT32(hstatus, OHCIState), 2089 VMSTATE_UINT32(hmask, OHCIState), 2090 VMSTATE_UINT32(hreset, OHCIState), 2091 VMSTATE_UINT32(htest, OHCIState), 2092 VMSTATE_UINT32(old_ctl, OHCIState), 2093 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), 2094 VMSTATE_UINT32(async_td, OHCIState), 2095 VMSTATE_BOOL(async_complete, OHCIState), 2096 VMSTATE_END_OF_LIST() 2097 }, 2098 .subsections = (const VMStateDescription*[]) { 2099 &vmstate_ohci_eof_timer, 2100 NULL 2101 } 2102 }; 2103 2104 static const VMStateDescription vmstate_ohci = { 2105 .name = "ohci", 2106 .version_id = 1, 2107 .minimum_version_id = 1, 2108 .fields = (VMStateField[]) { 2109 VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState), 2110 VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState), 2111 VMSTATE_END_OF_LIST() 2112 } 2113 }; 2114 2115 static void ohci_pci_class_init(ObjectClass *klass, void *data) 2116 { 2117 DeviceClass *dc = DEVICE_CLASS(klass); 2118 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2119 2120 k->realize = usb_ohci_realize_pci; 2121 k->exit = usb_ohci_exit; 2122 k->vendor_id = PCI_VENDOR_ID_APPLE; 2123 k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; 2124 k->class_id = PCI_CLASS_SERIAL_USB; 2125 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2126 dc->desc = "Apple USB Controller"; 2127 dc->props = ohci_pci_properties; 2128 dc->hotpluggable = false; 2129 dc->vmsd = &vmstate_ohci; 2130 dc->reset = usb_ohci_reset_pci; 2131 } 2132 2133 static const TypeInfo ohci_pci_info = { 2134 .name = TYPE_PCI_OHCI, 2135 .parent = TYPE_PCI_DEVICE, 2136 .instance_size = sizeof(OHCIPCIState), 2137 .class_init = ohci_pci_class_init, 2138 }; 2139 2140 static Property ohci_sysbus_properties[] = { 2141 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 2142 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), 2143 DEFINE_PROP_END_OF_LIST(), 2144 }; 2145 2146 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 2147 { 2148 DeviceClass *dc = DEVICE_CLASS(klass); 2149 2150 dc->realize = ohci_realize_pxa; 2151 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2152 dc->desc = "OHCI USB Controller"; 2153 dc->props = ohci_sysbus_properties; 2154 dc->reset = usb_ohci_reset_sysbus; 2155 } 2156 2157 static const TypeInfo ohci_sysbus_info = { 2158 .name = TYPE_SYSBUS_OHCI, 2159 .parent = TYPE_SYS_BUS_DEVICE, 2160 .instance_size = sizeof(OHCISysBusState), 2161 .class_init = ohci_sysbus_class_init, 2162 }; 2163 2164 static void ohci_register_types(void) 2165 { 2166 type_register_static(&ohci_pci_info); 2167 type_register_static(&ohci_sysbus_info); 2168 } 2169 2170 type_init(ohci_register_types) 2171