1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o BIOS work to boot from USB storage 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/irq.h" 30 #include "qapi/error.h" 31 #include "qemu/module.h" 32 #include "qemu/timer.h" 33 #include "hw/usb.h" 34 #include "migration/vmstate.h" 35 #include "hw/sysbus.h" 36 #include "hw/qdev-dma.h" 37 #include "hw/qdev-properties.h" 38 #include "trace.h" 39 #include "hcd-ohci.h" 40 41 /* This causes frames to occur 1000x slower */ 42 //#define OHCI_TIME_WARP 1 43 44 #define ED_LINK_LIMIT 32 45 46 static int64_t usb_frame_time; 47 static int64_t usb_bit_time; 48 49 /* Host Controller Communications Area */ 50 struct ohci_hcca { 51 uint32_t intr[32]; 52 uint16_t frame, pad; 53 uint32_t done; 54 }; 55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 57 58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 59 #define ED_WBACK_SIZE 4 60 61 /* Bitfields for the first word of an Endpoint Desciptor. */ 62 #define OHCI_ED_FA_SHIFT 0 63 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 64 #define OHCI_ED_EN_SHIFT 7 65 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 66 #define OHCI_ED_D_SHIFT 11 67 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 68 #define OHCI_ED_S (1<<13) 69 #define OHCI_ED_K (1<<14) 70 #define OHCI_ED_F (1<<15) 71 #define OHCI_ED_MPS_SHIFT 16 72 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 73 74 /* Flags in the head field of an Endpoint Desciptor. */ 75 #define OHCI_ED_H 1 76 #define OHCI_ED_C 2 77 78 /* Bitfields for the first word of a Transfer Desciptor. */ 79 #define OHCI_TD_R (1<<18) 80 #define OHCI_TD_DP_SHIFT 19 81 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 82 #define OHCI_TD_DI_SHIFT 21 83 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 84 #define OHCI_TD_T0 (1<<24) 85 #define OHCI_TD_T1 (1<<25) 86 #define OHCI_TD_EC_SHIFT 26 87 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 88 #define OHCI_TD_CC_SHIFT 28 89 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 90 91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 92 /* CC & DI - same as in the General Transfer Desciptor */ 93 #define OHCI_TD_SF_SHIFT 0 94 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 95 #define OHCI_TD_FC_SHIFT 24 96 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 97 98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 99 #define OHCI_TD_PSW_CC_SHIFT 12 100 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 101 #define OHCI_TD_PSW_SIZE_SHIFT 0 102 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 103 104 #define OHCI_PAGE_MASK 0xfffff000 105 #define OHCI_OFFSET_MASK 0xfff 106 107 #define OHCI_DPTR_MASK 0xfffffff0 108 109 #define OHCI_BM(val, field) \ 110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 111 112 #define OHCI_SET_BM(val, field, newval) do { \ 113 val &= ~OHCI_##field##_MASK; \ 114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 115 } while(0) 116 117 /* endpoint descriptor */ 118 struct ohci_ed { 119 uint32_t flags; 120 uint32_t tail; 121 uint32_t head; 122 uint32_t next; 123 }; 124 125 /* General transfer descriptor */ 126 struct ohci_td { 127 uint32_t flags; 128 uint32_t cbp; 129 uint32_t next; 130 uint32_t be; 131 }; 132 133 /* Isochronous transfer descriptor */ 134 struct ohci_iso_td { 135 uint32_t flags; 136 uint32_t bp; 137 uint32_t next; 138 uint32_t be; 139 uint16_t offset[8]; 140 }; 141 142 #define USB_HZ 12000000 143 144 /* OHCI Local stuff */ 145 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 146 #define OHCI_CTL_PLE (1<<2) 147 #define OHCI_CTL_IE (1<<3) 148 #define OHCI_CTL_CLE (1<<4) 149 #define OHCI_CTL_BLE (1<<5) 150 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 151 #define OHCI_USB_RESET 0x00 152 #define OHCI_USB_RESUME 0x40 153 #define OHCI_USB_OPERATIONAL 0x80 154 #define OHCI_USB_SUSPEND 0xc0 155 #define OHCI_CTL_IR (1<<8) 156 #define OHCI_CTL_RWC (1<<9) 157 #define OHCI_CTL_RWE (1<<10) 158 159 #define OHCI_STATUS_HCR (1<<0) 160 #define OHCI_STATUS_CLF (1<<1) 161 #define OHCI_STATUS_BLF (1<<2) 162 #define OHCI_STATUS_OCR (1<<3) 163 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 164 165 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ 166 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ 167 #define OHCI_INTR_SF (1U<<2) /* Start of frame */ 168 #define OHCI_INTR_RD (1U<<3) /* Resume detect */ 169 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ 170 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ 171 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ 172 #define OHCI_INTR_OC (1U<<30) /* Ownership change */ 173 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ 174 175 #define OHCI_HCCA_SIZE 0x100 176 #define OHCI_HCCA_MASK 0xffffff00 177 178 #define OHCI_EDPTR_MASK 0xfffffff0 179 180 #define OHCI_FMI_FI 0x00003fff 181 #define OHCI_FMI_FSMPS 0xffff0000 182 #define OHCI_FMI_FIT 0x80000000 183 184 #define OHCI_FR_RT (1U<<31) 185 186 #define OHCI_LS_THRESH 0x628 187 188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 189 #define OHCI_RHA_PSM (1<<8) 190 #define OHCI_RHA_NPS (1<<9) 191 #define OHCI_RHA_DT (1<<10) 192 #define OHCI_RHA_OCPM (1<<11) 193 #define OHCI_RHA_NOCP (1<<12) 194 #define OHCI_RHA_POTPGT_MASK 0xff000000 195 196 #define OHCI_RHS_LPS (1U<<0) 197 #define OHCI_RHS_OCI (1U<<1) 198 #define OHCI_RHS_DRWE (1U<<15) 199 #define OHCI_RHS_LPSC (1U<<16) 200 #define OHCI_RHS_OCIC (1U<<17) 201 #define OHCI_RHS_CRWE (1U<<31) 202 203 #define OHCI_PORT_CCS (1<<0) 204 #define OHCI_PORT_PES (1<<1) 205 #define OHCI_PORT_PSS (1<<2) 206 #define OHCI_PORT_POCI (1<<3) 207 #define OHCI_PORT_PRS (1<<4) 208 #define OHCI_PORT_PPS (1<<8) 209 #define OHCI_PORT_LSDA (1<<9) 210 #define OHCI_PORT_CSC (1<<16) 211 #define OHCI_PORT_PESC (1<<17) 212 #define OHCI_PORT_PSSC (1<<18) 213 #define OHCI_PORT_OCIC (1<<19) 214 #define OHCI_PORT_PRSC (1<<20) 215 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 216 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 217 218 #define OHCI_TD_DIR_SETUP 0x0 219 #define OHCI_TD_DIR_OUT 0x1 220 #define OHCI_TD_DIR_IN 0x2 221 #define OHCI_TD_DIR_RESERVED 0x3 222 223 #define OHCI_CC_NOERROR 0x0 224 #define OHCI_CC_CRC 0x1 225 #define OHCI_CC_BITSTUFFING 0x2 226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 227 #define OHCI_CC_STALL 0x4 228 #define OHCI_CC_DEVICENOTRESPONDING 0x5 229 #define OHCI_CC_PIDCHECKFAILURE 0x6 230 #define OHCI_CC_UNDEXPETEDPID 0x7 231 #define OHCI_CC_DATAOVERRUN 0x8 232 #define OHCI_CC_DATAUNDERRUN 0x9 233 #define OHCI_CC_BUFFEROVERRUN 0xc 234 #define OHCI_CC_BUFFERUNDERRUN 0xd 235 236 #define OHCI_HRESET_FSBIR (1 << 0) 237 238 static void ohci_die(OHCIState *ohci) 239 { 240 ohci->ohci_die(ohci); 241 } 242 243 /* Update IRQ levels */ 244 static inline void ohci_intr_update(OHCIState *ohci) 245 { 246 int level = 0; 247 248 if ((ohci->intr & OHCI_INTR_MIE) && 249 (ohci->intr_status & ohci->intr)) 250 level = 1; 251 252 qemu_set_irq(ohci->irq, level); 253 } 254 255 /* Set an interrupt */ 256 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 257 { 258 ohci->intr_status |= intr; 259 ohci_intr_update(ohci); 260 } 261 262 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 263 { 264 USBDevice *dev; 265 int i; 266 267 for (i = 0; i < ohci->num_ports; i++) { 268 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 269 continue; 270 } 271 dev = usb_find_device(&ohci->rhport[i].port, addr); 272 if (dev != NULL) { 273 return dev; 274 } 275 } 276 return NULL; 277 } 278 279 void ohci_stop_endpoints(OHCIState *ohci) 280 { 281 USBDevice *dev; 282 int i, j; 283 284 if (ohci->async_td) { 285 usb_cancel_packet(&ohci->usb_packet); 286 ohci->async_td = 0; 287 } 288 for (i = 0; i < ohci->num_ports; i++) { 289 dev = ohci->rhport[i].port.dev; 290 if (dev && dev->attached) { 291 usb_device_ep_stopped(dev, &dev->ep_ctl); 292 for (j = 0; j < USB_MAX_ENDPOINTS; j++) { 293 usb_device_ep_stopped(dev, &dev->ep_in[j]); 294 usb_device_ep_stopped(dev, &dev->ep_out[j]); 295 } 296 } 297 } 298 } 299 300 static void ohci_roothub_reset(OHCIState *ohci) 301 { 302 OHCIPort *port; 303 int i; 304 305 ohci_bus_stop(ohci); 306 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 307 ohci->rhdesc_b = 0x0; /* Impl. specific */ 308 ohci->rhstatus = 0; 309 310 for (i = 0; i < ohci->num_ports; i++) { 311 port = &ohci->rhport[i]; 312 port->ctrl = 0; 313 if (port->port.dev && port->port.dev->attached) { 314 usb_port_reset(&port->port); 315 } 316 } 317 ohci_stop_endpoints(ohci); 318 } 319 320 /* Reset the controller */ 321 static void ohci_soft_reset(OHCIState *ohci) 322 { 323 trace_usb_ohci_reset(ohci->name); 324 325 ohci_bus_stop(ohci); 326 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; 327 ohci->old_ctl = 0; 328 ohci->status = 0; 329 ohci->intr_status = 0; 330 ohci->intr = OHCI_INTR_MIE; 331 332 ohci->hcca = 0; 333 ohci->ctrl_head = ohci->ctrl_cur = 0; 334 ohci->bulk_head = ohci->bulk_cur = 0; 335 ohci->per_cur = 0; 336 ohci->done = 0; 337 ohci->done_count = 7; 338 339 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 340 * I took the value linux sets ... 341 */ 342 ohci->fsmps = 0x2778; 343 ohci->fi = 0x2edf; 344 ohci->fit = 0; 345 ohci->frt = 0; 346 ohci->frame_number = 0; 347 ohci->pstart = 0; 348 ohci->lst = OHCI_LS_THRESH; 349 } 350 351 void ohci_hard_reset(OHCIState *ohci) 352 { 353 ohci_soft_reset(ohci); 354 ohci->ctl = 0; 355 ohci_roothub_reset(ohci); 356 } 357 358 /* Get an array of dwords from main memory */ 359 static inline int get_dwords(OHCIState *ohci, 360 dma_addr_t addr, uint32_t *buf, int num) 361 { 362 int i; 363 364 addr += ohci->localmem_base; 365 366 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 367 if (dma_memory_read(ohci->as, addr, 368 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) { 369 return -1; 370 } 371 *buf = le32_to_cpu(*buf); 372 } 373 374 return 0; 375 } 376 377 /* Put an array of dwords in to main memory */ 378 static inline int put_dwords(OHCIState *ohci, 379 dma_addr_t addr, uint32_t *buf, int num) 380 { 381 int i; 382 383 addr += ohci->localmem_base; 384 385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 386 uint32_t tmp = cpu_to_le32(*buf); 387 if (dma_memory_write(ohci->as, addr, 388 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) { 389 return -1; 390 } 391 } 392 393 return 0; 394 } 395 396 /* Get an array of words from main memory */ 397 static inline int get_words(OHCIState *ohci, 398 dma_addr_t addr, uint16_t *buf, int num) 399 { 400 int i; 401 402 addr += ohci->localmem_base; 403 404 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 405 if (dma_memory_read(ohci->as, addr, 406 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) { 407 return -1; 408 } 409 *buf = le16_to_cpu(*buf); 410 } 411 412 return 0; 413 } 414 415 /* Put an array of words in to main memory */ 416 static inline int put_words(OHCIState *ohci, 417 dma_addr_t addr, uint16_t *buf, int num) 418 { 419 int i; 420 421 addr += ohci->localmem_base; 422 423 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 424 uint16_t tmp = cpu_to_le16(*buf); 425 if (dma_memory_write(ohci->as, addr, 426 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) { 427 return -1; 428 } 429 } 430 431 return 0; 432 } 433 434 static inline int ohci_read_ed(OHCIState *ohci, 435 dma_addr_t addr, struct ohci_ed *ed) 436 { 437 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 438 } 439 440 static inline int ohci_read_td(OHCIState *ohci, 441 dma_addr_t addr, struct ohci_td *td) 442 { 443 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 444 } 445 446 static inline int ohci_read_iso_td(OHCIState *ohci, 447 dma_addr_t addr, struct ohci_iso_td *td) 448 { 449 return get_dwords(ohci, addr, (uint32_t *)td, 4) || 450 get_words(ohci, addr + 16, td->offset, 8); 451 } 452 453 static inline int ohci_read_hcca(OHCIState *ohci, 454 dma_addr_t addr, struct ohci_hcca *hcca) 455 { 456 return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca, 457 sizeof(*hcca), MEMTXATTRS_UNSPECIFIED); 458 } 459 460 static inline int ohci_put_ed(OHCIState *ohci, 461 dma_addr_t addr, struct ohci_ed *ed) 462 { 463 /* ed->tail is under control of the HCD. 464 * Since just ed->head is changed by HC, just write back this 465 */ 466 467 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 468 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 469 ED_WBACK_SIZE >> 2); 470 } 471 472 static inline int ohci_put_td(OHCIState *ohci, 473 dma_addr_t addr, struct ohci_td *td) 474 { 475 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 476 } 477 478 static inline int ohci_put_iso_td(OHCIState *ohci, 479 dma_addr_t addr, struct ohci_iso_td *td) 480 { 481 return put_dwords(ohci, addr, (uint32_t *)td, 4) || 482 put_words(ohci, addr + 16, td->offset, 8); 483 } 484 485 static inline int ohci_put_hcca(OHCIState *ohci, 486 dma_addr_t addr, struct ohci_hcca *hcca) 487 { 488 return dma_memory_write(ohci->as, 489 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 490 (char *)hcca + HCCA_WRITEBACK_OFFSET, 491 HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED); 492 } 493 494 /* Read/Write the contents of a TD from/to main memory. */ 495 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 496 uint8_t *buf, int len, DMADirection dir) 497 { 498 dma_addr_t ptr, n; 499 500 ptr = td->cbp; 501 n = 0x1000 - (ptr & 0xfff); 502 if (n > len) 503 n = len; 504 505 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 506 n, dir, MEMTXATTRS_UNSPECIFIED)) { 507 return -1; 508 } 509 if (n == len) { 510 return 0; 511 } 512 ptr = td->be & ~0xfffu; 513 buf += n; 514 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 515 len - n, dir, MEMTXATTRS_UNSPECIFIED)) { 516 return -1; 517 } 518 return 0; 519 } 520 521 /* Read/Write the contents of an ISO TD from/to main memory. */ 522 static int ohci_copy_iso_td(OHCIState *ohci, 523 uint32_t start_addr, uint32_t end_addr, 524 uint8_t *buf, int len, DMADirection dir) 525 { 526 dma_addr_t ptr, n; 527 528 ptr = start_addr; 529 n = 0x1000 - (ptr & 0xfff); 530 if (n > len) 531 n = len; 532 533 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 534 n, dir, MEMTXATTRS_UNSPECIFIED)) { 535 return -1; 536 } 537 if (n == len) { 538 return 0; 539 } 540 ptr = end_addr & ~0xfffu; 541 buf += n; 542 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 543 len - n, dir, MEMTXATTRS_UNSPECIFIED)) { 544 return -1; 545 } 546 return 0; 547 } 548 549 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 550 551 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed) 552 { 553 int dir; 554 size_t len = 0; 555 const char *str = NULL; 556 int pid; 557 int ret; 558 int i; 559 USBDevice *dev; 560 USBEndpoint *ep; 561 USBPacket *pkt; 562 uint8_t buf[8192]; 563 bool int_req; 564 struct ohci_iso_td iso_td; 565 uint32_t addr; 566 uint16_t starting_frame; 567 int16_t relative_frame_number; 568 int frame_count; 569 uint32_t start_offset, next_offset, end_offset = 0; 570 uint32_t start_addr, end_addr; 571 572 addr = ed->head & OHCI_DPTR_MASK; 573 574 if (ohci_read_iso_td(ohci, addr, &iso_td)) { 575 trace_usb_ohci_iso_td_read_failed(addr); 576 ohci_die(ohci); 577 return 1; 578 } 579 580 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 581 frame_count = OHCI_BM(iso_td.flags, TD_FC); 582 relative_frame_number = USUB(ohci->frame_number, starting_frame); 583 584 trace_usb_ohci_iso_td_head( 585 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 586 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 587 ohci->frame_number, starting_frame, 588 frame_count, relative_frame_number); 589 trace_usb_ohci_iso_td_head_offset( 590 iso_td.offset[0], iso_td.offset[1], 591 iso_td.offset[2], iso_td.offset[3], 592 iso_td.offset[4], iso_td.offset[5], 593 iso_td.offset[6], iso_td.offset[7]); 594 595 if (relative_frame_number < 0) { 596 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); 597 return 1; 598 } else if (relative_frame_number > frame_count) { 599 /* ISO TD expired - retire the TD to the Done Queue and continue with 600 the next ISO TD of the same ED */ 601 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, 602 frame_count); 603 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) { 604 /* avoid infinite loop */ 605 return 1; 606 } 607 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 608 ed->head &= ~OHCI_DPTR_MASK; 609 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 610 iso_td.next = ohci->done; 611 ohci->done = addr; 612 i = OHCI_BM(iso_td.flags, TD_DI); 613 if (i < ohci->done_count) 614 ohci->done_count = i; 615 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 616 ohci_die(ohci); 617 return 1; 618 } 619 return 0; 620 } 621 622 dir = OHCI_BM(ed->flags, ED_D); 623 switch (dir) { 624 case OHCI_TD_DIR_IN: 625 str = "in"; 626 pid = USB_TOKEN_IN; 627 break; 628 case OHCI_TD_DIR_OUT: 629 str = "out"; 630 pid = USB_TOKEN_OUT; 631 break; 632 case OHCI_TD_DIR_SETUP: 633 str = "setup"; 634 pid = USB_TOKEN_SETUP; 635 break; 636 default: 637 trace_usb_ohci_iso_td_bad_direction(dir); 638 return 1; 639 } 640 641 if (!iso_td.bp || !iso_td.be) { 642 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); 643 return 1; 644 } 645 646 start_offset = iso_td.offset[relative_frame_number]; 647 if (relative_frame_number < frame_count) { 648 next_offset = iso_td.offset[relative_frame_number + 1]; 649 } else { 650 next_offset = iso_td.be; 651 } 652 653 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 654 ((relative_frame_number < frame_count) && 655 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 656 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); 657 return 1; 658 } 659 660 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 661 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); 662 return 1; 663 } 664 665 if ((start_offset & 0x1000) == 0) { 666 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 667 (start_offset & OHCI_OFFSET_MASK); 668 } else { 669 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 670 (start_offset & OHCI_OFFSET_MASK); 671 } 672 673 if (relative_frame_number < frame_count) { 674 end_offset = next_offset - 1; 675 if ((end_offset & 0x1000) == 0) { 676 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 677 (end_offset & OHCI_OFFSET_MASK); 678 } else { 679 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 680 (end_offset & OHCI_OFFSET_MASK); 681 } 682 } else { 683 /* Last packet in the ISO TD */ 684 end_addr = next_offset; 685 } 686 687 if (start_addr > end_addr) { 688 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr); 689 return 1; 690 } 691 692 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 693 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 694 - (start_addr & OHCI_OFFSET_MASK); 695 } else { 696 len = end_addr - start_addr + 1; 697 } 698 if (len > sizeof(buf)) { 699 len = sizeof(buf); 700 } 701 702 if (len && dir != OHCI_TD_DIR_IN) { 703 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, len, 704 DMA_DIRECTION_TO_DEVICE)) { 705 ohci_die(ohci); 706 return 1; 707 } 708 } 709 710 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 711 if (dev == NULL) { 712 trace_usb_ohci_td_dev_error(); 713 return 1; 714 } 715 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 716 pkt = g_new0(USBPacket, 1); 717 usb_packet_init(pkt); 718 int_req = relative_frame_number == frame_count && 719 OHCI_BM(iso_td.flags, TD_DI) == 0; 720 usb_packet_setup(pkt, pid, ep, 0, addr, false, int_req); 721 usb_packet_addbuf(pkt, buf, len); 722 usb_handle_packet(dev, pkt); 723 if (pkt->status == USB_RET_ASYNC) { 724 usb_device_flush_ep_queue(dev, ep); 725 g_free(pkt); 726 return 1; 727 } 728 if (pkt->status == USB_RET_SUCCESS) { 729 ret = pkt->actual_length; 730 } else { 731 ret = pkt->status; 732 } 733 g_free(pkt); 734 735 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, 736 str, len, ret); 737 738 /* Writeback */ 739 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 740 /* IN transfer succeeded */ 741 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, ret, 742 DMA_DIRECTION_FROM_DEVICE)) { 743 ohci_die(ohci); 744 return 1; 745 } 746 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 747 OHCI_CC_NOERROR); 748 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 749 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 750 /* OUT transfer succeeded */ 751 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 752 OHCI_CC_NOERROR); 753 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 754 } else { 755 if (ret > (ssize_t) len) { 756 trace_usb_ohci_iso_td_data_overrun(ret, len); 757 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 758 OHCI_CC_DATAOVERRUN); 759 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 760 len); 761 } else if (ret >= 0) { 762 trace_usb_ohci_iso_td_data_underrun(ret); 763 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 764 OHCI_CC_DATAUNDERRUN); 765 } else { 766 switch (ret) { 767 case USB_RET_IOERROR: 768 case USB_RET_NODEV: 769 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 770 OHCI_CC_DEVICENOTRESPONDING); 771 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 772 0); 773 break; 774 case USB_RET_NAK: 775 case USB_RET_STALL: 776 trace_usb_ohci_iso_td_nak(ret); 777 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 778 OHCI_CC_STALL); 779 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 780 0); 781 break; 782 default: 783 trace_usb_ohci_iso_td_bad_response(ret); 784 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 785 OHCI_CC_UNDEXPETEDPID); 786 break; 787 } 788 } 789 } 790 791 if (relative_frame_number == frame_count) { 792 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 793 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 794 ed->head &= ~OHCI_DPTR_MASK; 795 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 796 iso_td.next = ohci->done; 797 ohci->done = addr; 798 i = OHCI_BM(iso_td.flags, TD_DI); 799 if (i < ohci->done_count) 800 ohci->done_count = i; 801 } 802 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 803 ohci_die(ohci); 804 } 805 return 1; 806 } 807 808 #define HEX_CHAR_PER_LINE 16 809 810 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 811 { 812 bool print16; 813 bool printall; 814 int i; 815 char tmp[3 * HEX_CHAR_PER_LINE + 1]; 816 char *p = tmp; 817 818 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT); 819 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL); 820 821 if (!printall && !print16) { 822 return; 823 } 824 825 for (i = 0; ; i++) { 826 if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) { 827 if (!printall) { 828 trace_usb_ohci_td_pkt_short(msg, tmp); 829 break; 830 } 831 trace_usb_ohci_td_pkt_full(msg, tmp); 832 p = tmp; 833 *p = 0; 834 } 835 if (i == len) { 836 break; 837 } 838 839 p += sprintf(p, " %.2x", buf[i]); 840 } 841 } 842 843 /* Service a transport descriptor. 844 Returns nonzero to terminate processing of this endpoint. */ 845 846 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 847 { 848 int dir; 849 size_t len = 0, pktlen = 0; 850 const char *str = NULL; 851 int pid; 852 int ret; 853 int i; 854 USBDevice *dev; 855 USBEndpoint *ep; 856 struct ohci_td td; 857 uint32_t addr; 858 int flag_r; 859 int completion; 860 861 addr = ed->head & OHCI_DPTR_MASK; 862 /* See if this TD has already been submitted to the device. */ 863 completion = (addr == ohci->async_td); 864 if (completion && !ohci->async_complete) { 865 trace_usb_ohci_td_skip_async(); 866 return 1; 867 } 868 if (ohci_read_td(ohci, addr, &td)) { 869 trace_usb_ohci_td_read_error(addr); 870 ohci_die(ohci); 871 return 1; 872 } 873 874 dir = OHCI_BM(ed->flags, ED_D); 875 switch (dir) { 876 case OHCI_TD_DIR_OUT: 877 case OHCI_TD_DIR_IN: 878 /* Same value. */ 879 break; 880 default: 881 dir = OHCI_BM(td.flags, TD_DP); 882 break; 883 } 884 885 switch (dir) { 886 case OHCI_TD_DIR_IN: 887 str = "in"; 888 pid = USB_TOKEN_IN; 889 break; 890 case OHCI_TD_DIR_OUT: 891 str = "out"; 892 pid = USB_TOKEN_OUT; 893 break; 894 case OHCI_TD_DIR_SETUP: 895 str = "setup"; 896 pid = USB_TOKEN_SETUP; 897 break; 898 default: 899 trace_usb_ohci_td_bad_direction(dir); 900 return 1; 901 } 902 if (td.cbp && td.be) { 903 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 904 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 905 } else { 906 if (td.cbp > td.be) { 907 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be); 908 ohci_die(ohci); 909 return 1; 910 } 911 len = (td.be - td.cbp) + 1; 912 } 913 if (len > sizeof(ohci->usb_buf)) { 914 len = sizeof(ohci->usb_buf); 915 } 916 917 pktlen = len; 918 if (len && dir != OHCI_TD_DIR_IN) { 919 /* The endpoint may not allow us to transfer it all now */ 920 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 921 if (pktlen > len) { 922 pktlen = len; 923 } 924 if (!completion) { 925 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 926 DMA_DIRECTION_TO_DEVICE)) { 927 ohci_die(ohci); 928 } 929 } 930 } 931 } 932 933 flag_r = (td.flags & OHCI_TD_R) != 0; 934 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, 935 flag_r, td.cbp, td.be); 936 ohci_td_pkt("OUT", ohci->usb_buf, pktlen); 937 938 if (completion) { 939 ohci->async_td = 0; 940 ohci->async_complete = false; 941 } else { 942 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 943 if (dev == NULL) { 944 trace_usb_ohci_td_dev_error(); 945 return 1; 946 } 947 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 948 if (ohci->async_td) { 949 /* ??? The hardware should allow one active packet per 950 endpoint. We only allow one active packet per controller. 951 This should be sufficient as long as devices respond in a 952 timely manner. 953 */ 954 trace_usb_ohci_td_too_many_pending(ep->nr); 955 return 1; 956 } 957 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, 958 OHCI_BM(td.flags, TD_DI) == 0); 959 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 960 usb_handle_packet(dev, &ohci->usb_packet); 961 trace_usb_ohci_td_packet_status(ohci->usb_packet.status); 962 963 if (ohci->usb_packet.status == USB_RET_ASYNC) { 964 usb_device_flush_ep_queue(dev, ep); 965 ohci->async_td = addr; 966 return 1; 967 } 968 } 969 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 970 ret = ohci->usb_packet.actual_length; 971 } else { 972 ret = ohci->usb_packet.status; 973 } 974 975 if (ret >= 0) { 976 if (dir == OHCI_TD_DIR_IN) { 977 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 978 DMA_DIRECTION_FROM_DEVICE)) { 979 ohci_die(ohci); 980 } 981 ohci_td_pkt("IN", ohci->usb_buf, pktlen); 982 } else { 983 ret = pktlen; 984 } 985 } 986 987 /* Writeback */ 988 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 989 /* Transmission succeeded. */ 990 if (ret == len) { 991 td.cbp = 0; 992 } else { 993 if ((td.cbp & 0xfff) + ret > 0xfff) { 994 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 995 } else { 996 td.cbp += ret; 997 } 998 } 999 td.flags |= OHCI_TD_T1; 1000 td.flags ^= OHCI_TD_T0; 1001 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1002 OHCI_SET_BM(td.flags, TD_EC, 0); 1003 1004 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1005 /* Partial packet transfer: TD not ready to retire yet */ 1006 goto exit_no_retire; 1007 } 1008 1009 /* Setting ED_C is part of the TD retirement process */ 1010 ed->head &= ~OHCI_ED_C; 1011 if (td.flags & OHCI_TD_T0) 1012 ed->head |= OHCI_ED_C; 1013 } else { 1014 if (ret >= 0) { 1015 trace_usb_ohci_td_underrun(); 1016 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1017 } else { 1018 switch (ret) { 1019 case USB_RET_IOERROR: 1020 case USB_RET_NODEV: 1021 trace_usb_ohci_td_dev_error(); 1022 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1023 break; 1024 case USB_RET_NAK: 1025 trace_usb_ohci_td_nak(); 1026 return 1; 1027 case USB_RET_STALL: 1028 trace_usb_ohci_td_stall(); 1029 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1030 break; 1031 case USB_RET_BABBLE: 1032 trace_usb_ohci_td_babble(); 1033 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1034 break; 1035 default: 1036 trace_usb_ohci_td_bad_device_response(ret); 1037 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1038 OHCI_SET_BM(td.flags, TD_EC, 3); 1039 break; 1040 } 1041 /* An error occurred so we have to clear the interrupt counter. See 1042 * spec at 6.4.4 on page 104 */ 1043 ohci->done_count = 0; 1044 } 1045 ed->head |= OHCI_ED_H; 1046 } 1047 1048 /* Retire this TD */ 1049 ed->head &= ~OHCI_DPTR_MASK; 1050 ed->head |= td.next & OHCI_DPTR_MASK; 1051 td.next = ohci->done; 1052 ohci->done = addr; 1053 i = OHCI_BM(td.flags, TD_DI); 1054 if (i < ohci->done_count) 1055 ohci->done_count = i; 1056 exit_no_retire: 1057 if (ohci_put_td(ohci, addr, &td)) { 1058 ohci_die(ohci); 1059 return 1; 1060 } 1061 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1062 } 1063 1064 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1065 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head) 1066 { 1067 struct ohci_ed ed; 1068 uint32_t next_ed; 1069 uint32_t cur; 1070 int active; 1071 uint32_t link_cnt = 0; 1072 active = 0; 1073 1074 if (head == 0) 1075 return 0; 1076 1077 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) { 1078 if (ohci_read_ed(ohci, cur, &ed)) { 1079 trace_usb_ohci_ed_read_error(cur); 1080 ohci_die(ohci); 1081 return 0; 1082 } 1083 1084 next_ed = ed.next & OHCI_DPTR_MASK; 1085 1086 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1087 uint32_t addr; 1088 /* Cancel pending packets for ED that have been paused. */ 1089 addr = ed.head & OHCI_DPTR_MASK; 1090 if (ohci->async_td && addr == ohci->async_td) { 1091 usb_cancel_packet(&ohci->usb_packet); 1092 ohci->async_td = 0; 1093 usb_device_ep_stopped(ohci->usb_packet.ep->dev, 1094 ohci->usb_packet.ep); 1095 } 1096 continue; 1097 } 1098 1099 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1100 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, 1101 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1102 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1103 trace_usb_ohci_ed_pkt_flags( 1104 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1105 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1106 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1107 OHCI_BM(ed.flags, ED_MPS)); 1108 1109 active = 1; 1110 1111 if ((ed.flags & OHCI_ED_F) == 0) { 1112 if (ohci_service_td(ohci, &ed)) 1113 break; 1114 } else { 1115 /* Handle isochronous endpoints */ 1116 if (ohci_service_iso_td(ohci, &ed)) { 1117 break; 1118 } 1119 } 1120 } 1121 1122 if (ohci_put_ed(ohci, cur, &ed)) { 1123 ohci_die(ohci); 1124 return 0; 1125 } 1126 } 1127 1128 return active; 1129 } 1130 1131 /* set a timer for EOF */ 1132 static void ohci_eof_timer(OHCIState *ohci) 1133 { 1134 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1135 } 1136 /* Set a timer for EOF and generate a SOF event */ 1137 static void ohci_sof(OHCIState *ohci) 1138 { 1139 ohci->sof_time += usb_frame_time; 1140 ohci_eof_timer(ohci); 1141 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1142 } 1143 1144 /* Process Control and Bulk lists. */ 1145 static void ohci_process_lists(OHCIState *ohci) 1146 { 1147 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1148 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1149 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); 1150 } 1151 if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) { 1152 ohci->ctrl_cur = 0; 1153 ohci->status &= ~OHCI_STATUS_CLF; 1154 } 1155 } 1156 1157 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1158 if (!ohci_service_ed_list(ohci, ohci->bulk_head)) { 1159 ohci->bulk_cur = 0; 1160 ohci->status &= ~OHCI_STATUS_BLF; 1161 } 1162 } 1163 } 1164 1165 /* Do frame processing on frame boundary */ 1166 static void ohci_frame_boundary(void *opaque) 1167 { 1168 OHCIState *ohci = opaque; 1169 struct ohci_hcca hcca; 1170 1171 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { 1172 trace_usb_ohci_hcca_read_error(ohci->hcca); 1173 ohci_die(ohci); 1174 return; 1175 } 1176 1177 /* Process all the lists at the end of the frame */ 1178 if (ohci->ctl & OHCI_CTL_PLE) { 1179 int n; 1180 1181 n = ohci->frame_number & 0x1f; 1182 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n])); 1183 } 1184 1185 /* Cancel all pending packets if either of the lists has been disabled. */ 1186 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1187 ohci_stop_endpoints(ohci); 1188 } 1189 ohci->old_ctl = ohci->ctl; 1190 ohci_process_lists(ohci); 1191 1192 /* Stop if UnrecoverableError happened or ohci_sof will crash */ 1193 if (ohci->intr_status & OHCI_INTR_UE) { 1194 return; 1195 } 1196 1197 /* Frame boundary, so do EOF stuf here */ 1198 ohci->frt = ohci->fit; 1199 1200 /* Increment frame number and take care of endianness. */ 1201 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1202 hcca.frame = cpu_to_le16(ohci->frame_number); 1203 1204 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1205 if (!ohci->done) 1206 abort(); 1207 if (ohci->intr & ohci->intr_status) 1208 ohci->done |= 1; 1209 hcca.done = cpu_to_le32(ohci->done); 1210 ohci->done = 0; 1211 ohci->done_count = 7; 1212 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1213 } 1214 1215 if (ohci->done_count != 7 && ohci->done_count != 0) 1216 ohci->done_count--; 1217 1218 /* Do SOF stuff here */ 1219 ohci_sof(ohci); 1220 1221 /* Writeback HCCA */ 1222 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { 1223 ohci_die(ohci); 1224 } 1225 } 1226 1227 /* Start sending SOF tokens across the USB bus, lists are processed in 1228 * next frame 1229 */ 1230 static int ohci_bus_start(OHCIState *ohci) 1231 { 1232 trace_usb_ohci_start(ohci->name); 1233 1234 /* Delay the first SOF event by one frame time as 1235 * linux driver is not ready to receive it and 1236 * can meet some race conditions 1237 */ 1238 1239 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1240 ohci_eof_timer(ohci); 1241 1242 return 1; 1243 } 1244 1245 /* Stop sending SOF tokens on the bus */ 1246 void ohci_bus_stop(OHCIState *ohci) 1247 { 1248 trace_usb_ohci_stop(ohci->name); 1249 timer_del(ohci->eof_timer); 1250 } 1251 1252 /* Sets a flag in a port status register but only set it if the port is 1253 * connected, if not set ConnectStatusChange flag. If flag is enabled 1254 * return 1. 1255 */ 1256 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1257 { 1258 int ret = 1; 1259 1260 /* writing a 0 has no effect */ 1261 if (val == 0) 1262 return 0; 1263 1264 /* If CurrentConnectStatus is cleared we set 1265 * ConnectStatusChange 1266 */ 1267 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1268 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1269 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1270 /* TODO: CSC is a wakeup event */ 1271 } 1272 return 0; 1273 } 1274 1275 if (ohci->rhport[i].ctrl & val) 1276 ret = 0; 1277 1278 /* set the bit */ 1279 ohci->rhport[i].ctrl |= val; 1280 1281 return ret; 1282 } 1283 1284 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1285 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1286 { 1287 val &= OHCI_FMI_FI; 1288 1289 if (val != ohci->fi) { 1290 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); 1291 } 1292 1293 ohci->fi = val; 1294 } 1295 1296 static void ohci_port_power(OHCIState *ohci, int i, int p) 1297 { 1298 if (p) { 1299 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1300 } else { 1301 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1302 OHCI_PORT_CCS| 1303 OHCI_PORT_PSS| 1304 OHCI_PORT_PRS); 1305 } 1306 } 1307 1308 /* Set HcControlRegister */ 1309 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1310 { 1311 uint32_t old_state; 1312 uint32_t new_state; 1313 1314 old_state = ohci->ctl & OHCI_CTL_HCFS; 1315 ohci->ctl = val; 1316 new_state = ohci->ctl & OHCI_CTL_HCFS; 1317 1318 /* no state change */ 1319 if (old_state == new_state) 1320 return; 1321 1322 trace_usb_ohci_set_ctl(ohci->name, new_state); 1323 switch (new_state) { 1324 case OHCI_USB_OPERATIONAL: 1325 ohci_bus_start(ohci); 1326 break; 1327 case OHCI_USB_SUSPEND: 1328 ohci_bus_stop(ohci); 1329 /* clear pending SF otherwise linux driver loops in ohci_irq() */ 1330 ohci->intr_status &= ~OHCI_INTR_SF; 1331 ohci_intr_update(ohci); 1332 break; 1333 case OHCI_USB_RESUME: 1334 trace_usb_ohci_resume(ohci->name); 1335 break; 1336 case OHCI_USB_RESET: 1337 ohci_roothub_reset(ohci); 1338 break; 1339 } 1340 } 1341 1342 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1343 { 1344 uint16_t fr; 1345 int64_t tks; 1346 1347 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1348 return (ohci->frt << 31); 1349 1350 /* Being in USB operational state guarnatees sof_time was 1351 * set already. 1352 */ 1353 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; 1354 if (tks < 0) { 1355 tks = 0; 1356 } 1357 1358 /* avoid muldiv if possible */ 1359 if (tks >= usb_frame_time) 1360 return (ohci->frt << 31); 1361 1362 tks = tks / usb_bit_time; 1363 fr = (uint16_t)(ohci->fi - tks); 1364 1365 return (ohci->frt << 31) | fr; 1366 } 1367 1368 1369 /* Set root hub status */ 1370 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1371 { 1372 uint32_t old_state; 1373 1374 old_state = ohci->rhstatus; 1375 1376 /* write 1 to clear OCIC */ 1377 if (val & OHCI_RHS_OCIC) 1378 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1379 1380 if (val & OHCI_RHS_LPS) { 1381 int i; 1382 1383 for (i = 0; i < ohci->num_ports; i++) 1384 ohci_port_power(ohci, i, 0); 1385 trace_usb_ohci_hub_power_down(); 1386 } 1387 1388 if (val & OHCI_RHS_LPSC) { 1389 int i; 1390 1391 for (i = 0; i < ohci->num_ports; i++) 1392 ohci_port_power(ohci, i, 1); 1393 trace_usb_ohci_hub_power_up(); 1394 } 1395 1396 if (val & OHCI_RHS_DRWE) 1397 ohci->rhstatus |= OHCI_RHS_DRWE; 1398 1399 if (val & OHCI_RHS_CRWE) 1400 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1401 1402 if (old_state != ohci->rhstatus) 1403 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1404 } 1405 1406 /* Set root hub port status */ 1407 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1408 { 1409 uint32_t old_state; 1410 OHCIPort *port; 1411 1412 port = &ohci->rhport[portnum]; 1413 old_state = port->ctrl; 1414 1415 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1416 if (val & OHCI_PORT_WTC) 1417 port->ctrl &= ~(val & OHCI_PORT_WTC); 1418 1419 if (val & OHCI_PORT_CCS) 1420 port->ctrl &= ~OHCI_PORT_PES; 1421 1422 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1423 1424 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1425 trace_usb_ohci_port_suspend(portnum); 1426 } 1427 1428 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1429 trace_usb_ohci_port_reset(portnum); 1430 usb_device_reset(port->port.dev); 1431 port->ctrl &= ~OHCI_PORT_PRS; 1432 /* ??? Should this also set OHCI_PORT_PESC. */ 1433 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1434 } 1435 1436 /* Invert order here to ensure in ambiguous case, device is 1437 * powered up... 1438 */ 1439 if (val & OHCI_PORT_LSDA) 1440 ohci_port_power(ohci, portnum, 0); 1441 if (val & OHCI_PORT_PPS) 1442 ohci_port_power(ohci, portnum, 1); 1443 1444 if (old_state != port->ctrl) 1445 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1446 } 1447 1448 static uint64_t ohci_mem_read(void *opaque, 1449 hwaddr addr, 1450 unsigned size) 1451 { 1452 OHCIState *ohci = opaque; 1453 uint32_t retval; 1454 1455 /* Only aligned reads are allowed on OHCI */ 1456 if (addr & 3) { 1457 trace_usb_ohci_mem_read_unaligned(addr); 1458 return 0xffffffff; 1459 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1460 /* HcRhPortStatus */ 1461 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1462 } else { 1463 switch (addr >> 2) { 1464 case 0: /* HcRevision */ 1465 retval = 0x10; 1466 break; 1467 1468 case 1: /* HcControl */ 1469 retval = ohci->ctl; 1470 break; 1471 1472 case 2: /* HcCommandStatus */ 1473 retval = ohci->status; 1474 break; 1475 1476 case 3: /* HcInterruptStatus */ 1477 retval = ohci->intr_status; 1478 break; 1479 1480 case 4: /* HcInterruptEnable */ 1481 case 5: /* HcInterruptDisable */ 1482 retval = ohci->intr; 1483 break; 1484 1485 case 6: /* HcHCCA */ 1486 retval = ohci->hcca; 1487 break; 1488 1489 case 7: /* HcPeriodCurrentED */ 1490 retval = ohci->per_cur; 1491 break; 1492 1493 case 8: /* HcControlHeadED */ 1494 retval = ohci->ctrl_head; 1495 break; 1496 1497 case 9: /* HcControlCurrentED */ 1498 retval = ohci->ctrl_cur; 1499 break; 1500 1501 case 10: /* HcBulkHeadED */ 1502 retval = ohci->bulk_head; 1503 break; 1504 1505 case 11: /* HcBulkCurrentED */ 1506 retval = ohci->bulk_cur; 1507 break; 1508 1509 case 12: /* HcDoneHead */ 1510 retval = ohci->done; 1511 break; 1512 1513 case 13: /* HcFmInterretval */ 1514 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1515 break; 1516 1517 case 14: /* HcFmRemaining */ 1518 retval = ohci_get_frame_remaining(ohci); 1519 break; 1520 1521 case 15: /* HcFmNumber */ 1522 retval = ohci->frame_number; 1523 break; 1524 1525 case 16: /* HcPeriodicStart */ 1526 retval = ohci->pstart; 1527 break; 1528 1529 case 17: /* HcLSThreshold */ 1530 retval = ohci->lst; 1531 break; 1532 1533 case 18: /* HcRhDescriptorA */ 1534 retval = ohci->rhdesc_a; 1535 break; 1536 1537 case 19: /* HcRhDescriptorB */ 1538 retval = ohci->rhdesc_b; 1539 break; 1540 1541 case 20: /* HcRhStatus */ 1542 retval = ohci->rhstatus; 1543 break; 1544 1545 /* PXA27x specific registers */ 1546 case 24: /* HcStatus */ 1547 retval = ohci->hstatus & ohci->hmask; 1548 break; 1549 1550 case 25: /* HcHReset */ 1551 retval = ohci->hreset; 1552 break; 1553 1554 case 26: /* HcHInterruptEnable */ 1555 retval = ohci->hmask; 1556 break; 1557 1558 case 27: /* HcHInterruptTest */ 1559 retval = ohci->htest; 1560 break; 1561 1562 default: 1563 trace_usb_ohci_mem_read_bad_offset(addr); 1564 retval = 0xffffffff; 1565 } 1566 } 1567 1568 return retval; 1569 } 1570 1571 static void ohci_mem_write(void *opaque, 1572 hwaddr addr, 1573 uint64_t val, 1574 unsigned size) 1575 { 1576 OHCIState *ohci = opaque; 1577 1578 /* Only aligned reads are allowed on OHCI */ 1579 if (addr & 3) { 1580 trace_usb_ohci_mem_write_unaligned(addr); 1581 return; 1582 } 1583 1584 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1585 /* HcRhPortStatus */ 1586 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1587 return; 1588 } 1589 1590 switch (addr >> 2) { 1591 case 1: /* HcControl */ 1592 ohci_set_ctl(ohci, val); 1593 break; 1594 1595 case 2: /* HcCommandStatus */ 1596 /* SOC is read-only */ 1597 val = (val & ~OHCI_STATUS_SOC); 1598 1599 /* Bits written as '0' remain unchanged in the register */ 1600 ohci->status |= val; 1601 1602 if (ohci->status & OHCI_STATUS_HCR) 1603 ohci_soft_reset(ohci); 1604 break; 1605 1606 case 3: /* HcInterruptStatus */ 1607 ohci->intr_status &= ~val; 1608 ohci_intr_update(ohci); 1609 break; 1610 1611 case 4: /* HcInterruptEnable */ 1612 ohci->intr |= val; 1613 ohci_intr_update(ohci); 1614 break; 1615 1616 case 5: /* HcInterruptDisable */ 1617 ohci->intr &= ~val; 1618 ohci_intr_update(ohci); 1619 break; 1620 1621 case 6: /* HcHCCA */ 1622 ohci->hcca = val & OHCI_HCCA_MASK; 1623 break; 1624 1625 case 7: /* HcPeriodCurrentED */ 1626 /* Ignore writes to this read-only register, Linux does them */ 1627 break; 1628 1629 case 8: /* HcControlHeadED */ 1630 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1631 break; 1632 1633 case 9: /* HcControlCurrentED */ 1634 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1635 break; 1636 1637 case 10: /* HcBulkHeadED */ 1638 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1639 break; 1640 1641 case 11: /* HcBulkCurrentED */ 1642 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1643 break; 1644 1645 case 13: /* HcFmInterval */ 1646 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1647 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1648 ohci_set_frame_interval(ohci, val); 1649 break; 1650 1651 case 15: /* HcFmNumber */ 1652 break; 1653 1654 case 16: /* HcPeriodicStart */ 1655 ohci->pstart = val & 0xffff; 1656 break; 1657 1658 case 17: /* HcLSThreshold */ 1659 ohci->lst = val & 0xffff; 1660 break; 1661 1662 case 18: /* HcRhDescriptorA */ 1663 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1664 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1665 break; 1666 1667 case 19: /* HcRhDescriptorB */ 1668 break; 1669 1670 case 20: /* HcRhStatus */ 1671 ohci_set_hub_status(ohci, val); 1672 break; 1673 1674 /* PXA27x specific registers */ 1675 case 24: /* HcStatus */ 1676 ohci->hstatus &= ~(val & ohci->hmask); 1677 break; 1678 1679 case 25: /* HcHReset */ 1680 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1681 if (val & OHCI_HRESET_FSBIR) 1682 ohci_hard_reset(ohci); 1683 break; 1684 1685 case 26: /* HcHInterruptEnable */ 1686 ohci->hmask = val; 1687 break; 1688 1689 case 27: /* HcHInterruptTest */ 1690 ohci->htest = val; 1691 break; 1692 1693 default: 1694 trace_usb_ohci_mem_write_bad_offset(addr); 1695 break; 1696 } 1697 } 1698 1699 static const MemoryRegionOps ohci_mem_ops = { 1700 .read = ohci_mem_read, 1701 .write = ohci_mem_write, 1702 .endianness = DEVICE_LITTLE_ENDIAN, 1703 }; 1704 1705 /* USBPortOps */ 1706 static void ohci_attach(USBPort *port1) 1707 { 1708 OHCIState *s = port1->opaque; 1709 OHCIPort *port = &s->rhport[port1->index]; 1710 uint32_t old_state = port->ctrl; 1711 1712 /* set connect status */ 1713 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 1714 1715 /* update speed */ 1716 if (port->port.dev->speed == USB_SPEED_LOW) { 1717 port->ctrl |= OHCI_PORT_LSDA; 1718 } else { 1719 port->ctrl &= ~OHCI_PORT_LSDA; 1720 } 1721 1722 /* notify of remote-wakeup */ 1723 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 1724 ohci_set_interrupt(s, OHCI_INTR_RD); 1725 } 1726 1727 trace_usb_ohci_port_attach(port1->index); 1728 1729 if (old_state != port->ctrl) { 1730 ohci_set_interrupt(s, OHCI_INTR_RHSC); 1731 } 1732 } 1733 1734 static void ohci_child_detach(USBPort *port1, USBDevice *dev) 1735 { 1736 OHCIState *ohci = port1->opaque; 1737 1738 if (ohci->async_td && 1739 usb_packet_is_inflight(&ohci->usb_packet) && 1740 ohci->usb_packet.ep->dev == dev) { 1741 usb_cancel_packet(&ohci->usb_packet); 1742 ohci->async_td = 0; 1743 } 1744 } 1745 1746 static void ohci_detach(USBPort *port1) 1747 { 1748 OHCIState *s = port1->opaque; 1749 OHCIPort *port = &s->rhport[port1->index]; 1750 uint32_t old_state = port->ctrl; 1751 1752 ohci_child_detach(port1, port1->dev); 1753 1754 /* set connect status */ 1755 if (port->ctrl & OHCI_PORT_CCS) { 1756 port->ctrl &= ~OHCI_PORT_CCS; 1757 port->ctrl |= OHCI_PORT_CSC; 1758 } 1759 /* disable port */ 1760 if (port->ctrl & OHCI_PORT_PES) { 1761 port->ctrl &= ~OHCI_PORT_PES; 1762 port->ctrl |= OHCI_PORT_PESC; 1763 } 1764 trace_usb_ohci_port_detach(port1->index); 1765 1766 if (old_state != port->ctrl) { 1767 ohci_set_interrupt(s, OHCI_INTR_RHSC); 1768 } 1769 } 1770 1771 static void ohci_wakeup(USBPort *port1) 1772 { 1773 OHCIState *s = port1->opaque; 1774 OHCIPort *port = &s->rhport[port1->index]; 1775 uint32_t intr = 0; 1776 if (port->ctrl & OHCI_PORT_PSS) { 1777 trace_usb_ohci_port_wakeup(port1->index); 1778 port->ctrl |= OHCI_PORT_PSSC; 1779 port->ctrl &= ~OHCI_PORT_PSS; 1780 intr = OHCI_INTR_RHSC; 1781 } 1782 /* Note that the controller can be suspended even if this port is not */ 1783 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 1784 trace_usb_ohci_remote_wakeup(s->name); 1785 /* This is the one state transition the controller can do by itself */ 1786 s->ctl &= ~OHCI_CTL_HCFS; 1787 s->ctl |= OHCI_USB_RESUME; 1788 /* 1789 * In suspend mode only ResumeDetected is possible, not RHSC: 1790 * see the OHCI spec 5.1.2.3. 1791 */ 1792 intr = OHCI_INTR_RD; 1793 } 1794 ohci_set_interrupt(s, intr); 1795 } 1796 1797 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 1798 { 1799 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 1800 1801 trace_usb_ohci_async_complete(); 1802 ohci->async_complete = true; 1803 ohci_process_lists(ohci); 1804 } 1805 1806 static USBPortOps ohci_port_ops = { 1807 .attach = ohci_attach, 1808 .detach = ohci_detach, 1809 .child_detach = ohci_child_detach, 1810 .wakeup = ohci_wakeup, 1811 .complete = ohci_async_complete_packet, 1812 }; 1813 1814 static USBBusOps ohci_bus_ops = { 1815 }; 1816 1817 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports, 1818 dma_addr_t localmem_base, char *masterbus, 1819 uint32_t firstport, AddressSpace *as, 1820 void (*ohci_die_fn)(struct OHCIState *), Error **errp) 1821 { 1822 Error *err = NULL; 1823 int i; 1824 1825 ohci->as = as; 1826 ohci->ohci_die = ohci_die_fn; 1827 1828 if (num_ports > OHCI_MAX_PORTS) { 1829 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)", 1830 num_ports, OHCI_MAX_PORTS); 1831 return; 1832 } 1833 1834 if (usb_frame_time == 0) { 1835 #ifdef OHCI_TIME_WARP 1836 usb_frame_time = NANOSECONDS_PER_SECOND; 1837 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000); 1838 #else 1839 usb_frame_time = NANOSECONDS_PER_SECOND / 1000; 1840 if (NANOSECONDS_PER_SECOND >= USB_HZ) { 1841 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ; 1842 } else { 1843 usb_bit_time = 1; 1844 } 1845 #endif 1846 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); 1847 } 1848 1849 ohci->num_ports = num_ports; 1850 if (masterbus) { 1851 USBPort *ports[OHCI_MAX_PORTS]; 1852 for(i = 0; i < num_ports; i++) { 1853 ports[i] = &ohci->rhport[i].port; 1854 } 1855 usb_register_companion(masterbus, ports, num_ports, 1856 firstport, ohci, &ohci_port_ops, 1857 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1858 &err); 1859 if (err) { 1860 error_propagate(errp, err); 1861 return; 1862 } 1863 } else { 1864 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); 1865 for (i = 0; i < num_ports; i++) { 1866 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1867 ohci, i, &ohci_port_ops, 1868 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1869 } 1870 } 1871 1872 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, 1873 ohci, "ohci", 256); 1874 ohci->localmem_base = localmem_base; 1875 1876 ohci->name = object_get_typename(OBJECT(dev)); 1877 usb_packet_init(&ohci->usb_packet); 1878 1879 ohci->async_td = 0; 1880 1881 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1882 ohci_frame_boundary, ohci); 1883 } 1884 1885 /** 1886 * A typical OHCI will stop operating and set itself into error state 1887 * (which can be queried by MMIO) to signal that it got an error. 1888 */ 1889 void ohci_sysbus_die(struct OHCIState *ohci) 1890 { 1891 trace_usb_ohci_die(); 1892 1893 ohci_set_interrupt(ohci, OHCI_INTR_UE); 1894 ohci_bus_stop(ohci); 1895 } 1896 1897 static void ohci_realize_pxa(DeviceState *dev, Error **errp) 1898 { 1899 OHCISysBusState *s = SYSBUS_OHCI(dev); 1900 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1901 Error *err = NULL; 1902 1903 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, 1904 s->masterbus, s->firstport, 1905 &address_space_memory, ohci_sysbus_die, &err); 1906 if (err) { 1907 error_propagate(errp, err); 1908 return; 1909 } 1910 sysbus_init_irq(sbd, &s->ohci.irq); 1911 sysbus_init_mmio(sbd, &s->ohci.mem); 1912 } 1913 1914 static void usb_ohci_reset_sysbus(DeviceState *dev) 1915 { 1916 OHCISysBusState *s = SYSBUS_OHCI(dev); 1917 OHCIState *ohci = &s->ohci; 1918 1919 ohci_hard_reset(ohci); 1920 } 1921 1922 static const VMStateDescription vmstate_ohci_state_port = { 1923 .name = "ohci-core/port", 1924 .version_id = 1, 1925 .minimum_version_id = 1, 1926 .fields = (VMStateField[]) { 1927 VMSTATE_UINT32(ctrl, OHCIPort), 1928 VMSTATE_END_OF_LIST() 1929 }, 1930 }; 1931 1932 static bool ohci_eof_timer_needed(void *opaque) 1933 { 1934 OHCIState *ohci = opaque; 1935 1936 return timer_pending(ohci->eof_timer); 1937 } 1938 1939 static const VMStateDescription vmstate_ohci_eof_timer = { 1940 .name = "ohci-core/eof-timer", 1941 .version_id = 1, 1942 .minimum_version_id = 1, 1943 .needed = ohci_eof_timer_needed, 1944 .fields = (VMStateField[]) { 1945 VMSTATE_TIMER_PTR(eof_timer, OHCIState), 1946 VMSTATE_END_OF_LIST() 1947 }, 1948 }; 1949 1950 const VMStateDescription vmstate_ohci_state = { 1951 .name = "ohci-core", 1952 .version_id = 1, 1953 .minimum_version_id = 1, 1954 .fields = (VMStateField[]) { 1955 VMSTATE_INT64(sof_time, OHCIState), 1956 VMSTATE_UINT32(ctl, OHCIState), 1957 VMSTATE_UINT32(status, OHCIState), 1958 VMSTATE_UINT32(intr_status, OHCIState), 1959 VMSTATE_UINT32(intr, OHCIState), 1960 VMSTATE_UINT32(hcca, OHCIState), 1961 VMSTATE_UINT32(ctrl_head, OHCIState), 1962 VMSTATE_UINT32(ctrl_cur, OHCIState), 1963 VMSTATE_UINT32(bulk_head, OHCIState), 1964 VMSTATE_UINT32(bulk_cur, OHCIState), 1965 VMSTATE_UINT32(per_cur, OHCIState), 1966 VMSTATE_UINT32(done, OHCIState), 1967 VMSTATE_INT32(done_count, OHCIState), 1968 VMSTATE_UINT16(fsmps, OHCIState), 1969 VMSTATE_UINT8(fit, OHCIState), 1970 VMSTATE_UINT16(fi, OHCIState), 1971 VMSTATE_UINT8(frt, OHCIState), 1972 VMSTATE_UINT16(frame_number, OHCIState), 1973 VMSTATE_UINT16(padding, OHCIState), 1974 VMSTATE_UINT32(pstart, OHCIState), 1975 VMSTATE_UINT32(lst, OHCIState), 1976 VMSTATE_UINT32(rhdesc_a, OHCIState), 1977 VMSTATE_UINT32(rhdesc_b, OHCIState), 1978 VMSTATE_UINT32(rhstatus, OHCIState), 1979 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, 1980 vmstate_ohci_state_port, OHCIPort), 1981 VMSTATE_UINT32(hstatus, OHCIState), 1982 VMSTATE_UINT32(hmask, OHCIState), 1983 VMSTATE_UINT32(hreset, OHCIState), 1984 VMSTATE_UINT32(htest, OHCIState), 1985 VMSTATE_UINT32(old_ctl, OHCIState), 1986 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), 1987 VMSTATE_UINT32(async_td, OHCIState), 1988 VMSTATE_BOOL(async_complete, OHCIState), 1989 VMSTATE_END_OF_LIST() 1990 }, 1991 .subsections = (const VMStateDescription*[]) { 1992 &vmstate_ohci_eof_timer, 1993 NULL 1994 } 1995 }; 1996 1997 static Property ohci_sysbus_properties[] = { 1998 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), 1999 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 2000 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), 2001 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), 2002 DEFINE_PROP_END_OF_LIST(), 2003 }; 2004 2005 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 2006 { 2007 DeviceClass *dc = DEVICE_CLASS(klass); 2008 2009 dc->realize = ohci_realize_pxa; 2010 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2011 dc->desc = "OHCI USB Controller"; 2012 device_class_set_props(dc, ohci_sysbus_properties); 2013 dc->reset = usb_ohci_reset_sysbus; 2014 } 2015 2016 static const TypeInfo ohci_sysbus_info = { 2017 .name = TYPE_SYSBUS_OHCI, 2018 .parent = TYPE_SYS_BUS_DEVICE, 2019 .instance_size = sizeof(OHCISysBusState), 2020 .class_init = ohci_sysbus_class_init, 2021 }; 2022 2023 static void ohci_register_types(void) 2024 { 2025 type_register_static(&ohci_sysbus_info); 2026 } 2027 2028 type_init(ohci_register_types) 2029