1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o BIOS work to boot from USB storage 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/irq.h" 30 #include "qapi/error.h" 31 #include "qemu/module.h" 32 #include "qemu/timer.h" 33 #include "hw/usb.h" 34 #include "migration/vmstate.h" 35 #include "hw/sysbus.h" 36 #include "hw/qdev-dma.h" 37 #include "hw/qdev-properties.h" 38 #include "trace.h" 39 #include "hcd-ohci.h" 40 41 /* This causes frames to occur 1000x slower */ 42 //#define OHCI_TIME_WARP 1 43 44 #define ED_LINK_LIMIT 32 45 46 static int64_t usb_frame_time; 47 static int64_t usb_bit_time; 48 49 /* Host Controller Communications Area */ 50 struct ohci_hcca { 51 uint32_t intr[32]; 52 uint16_t frame, pad; 53 uint32_t done; 54 }; 55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 57 58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 59 #define ED_WBACK_SIZE 4 60 61 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); 62 63 /* Bitfields for the first word of an Endpoint Desciptor. */ 64 #define OHCI_ED_FA_SHIFT 0 65 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 66 #define OHCI_ED_EN_SHIFT 7 67 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 68 #define OHCI_ED_D_SHIFT 11 69 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 70 #define OHCI_ED_S (1<<13) 71 #define OHCI_ED_K (1<<14) 72 #define OHCI_ED_F (1<<15) 73 #define OHCI_ED_MPS_SHIFT 16 74 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 75 76 /* Flags in the head field of an Endpoint Desciptor. */ 77 #define OHCI_ED_H 1 78 #define OHCI_ED_C 2 79 80 /* Bitfields for the first word of a Transfer Desciptor. */ 81 #define OHCI_TD_R (1<<18) 82 #define OHCI_TD_DP_SHIFT 19 83 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 84 #define OHCI_TD_DI_SHIFT 21 85 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 86 #define OHCI_TD_T0 (1<<24) 87 #define OHCI_TD_T1 (1<<25) 88 #define OHCI_TD_EC_SHIFT 26 89 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 90 #define OHCI_TD_CC_SHIFT 28 91 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 92 93 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 94 /* CC & DI - same as in the General Transfer Desciptor */ 95 #define OHCI_TD_SF_SHIFT 0 96 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 97 #define OHCI_TD_FC_SHIFT 24 98 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 99 100 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 101 #define OHCI_TD_PSW_CC_SHIFT 12 102 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 103 #define OHCI_TD_PSW_SIZE_SHIFT 0 104 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 105 106 #define OHCI_PAGE_MASK 0xfffff000 107 #define OHCI_OFFSET_MASK 0xfff 108 109 #define OHCI_DPTR_MASK 0xfffffff0 110 111 #define OHCI_BM(val, field) \ 112 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 113 114 #define OHCI_SET_BM(val, field, newval) do { \ 115 val &= ~OHCI_##field##_MASK; \ 116 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 117 } while(0) 118 119 /* endpoint descriptor */ 120 struct ohci_ed { 121 uint32_t flags; 122 uint32_t tail; 123 uint32_t head; 124 uint32_t next; 125 }; 126 127 /* General transfer descriptor */ 128 struct ohci_td { 129 uint32_t flags; 130 uint32_t cbp; 131 uint32_t next; 132 uint32_t be; 133 }; 134 135 /* Isochronous transfer descriptor */ 136 struct ohci_iso_td { 137 uint32_t flags; 138 uint32_t bp; 139 uint32_t next; 140 uint32_t be; 141 uint16_t offset[8]; 142 }; 143 144 #define USB_HZ 12000000 145 146 /* OHCI Local stuff */ 147 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 148 #define OHCI_CTL_PLE (1<<2) 149 #define OHCI_CTL_IE (1<<3) 150 #define OHCI_CTL_CLE (1<<4) 151 #define OHCI_CTL_BLE (1<<5) 152 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 153 #define OHCI_USB_RESET 0x00 154 #define OHCI_USB_RESUME 0x40 155 #define OHCI_USB_OPERATIONAL 0x80 156 #define OHCI_USB_SUSPEND 0xc0 157 #define OHCI_CTL_IR (1<<8) 158 #define OHCI_CTL_RWC (1<<9) 159 #define OHCI_CTL_RWE (1<<10) 160 161 #define OHCI_STATUS_HCR (1<<0) 162 #define OHCI_STATUS_CLF (1<<1) 163 #define OHCI_STATUS_BLF (1<<2) 164 #define OHCI_STATUS_OCR (1<<3) 165 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 166 167 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ 168 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ 169 #define OHCI_INTR_SF (1U<<2) /* Start of frame */ 170 #define OHCI_INTR_RD (1U<<3) /* Resume detect */ 171 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ 172 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ 173 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ 174 #define OHCI_INTR_OC (1U<<30) /* Ownership change */ 175 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ 176 177 #define OHCI_HCCA_SIZE 0x100 178 #define OHCI_HCCA_MASK 0xffffff00 179 180 #define OHCI_EDPTR_MASK 0xfffffff0 181 182 #define OHCI_FMI_FI 0x00003fff 183 #define OHCI_FMI_FSMPS 0xffff0000 184 #define OHCI_FMI_FIT 0x80000000 185 186 #define OHCI_FR_RT (1U<<31) 187 188 #define OHCI_LS_THRESH 0x628 189 190 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 191 #define OHCI_RHA_PSM (1<<8) 192 #define OHCI_RHA_NPS (1<<9) 193 #define OHCI_RHA_DT (1<<10) 194 #define OHCI_RHA_OCPM (1<<11) 195 #define OHCI_RHA_NOCP (1<<12) 196 #define OHCI_RHA_POTPGT_MASK 0xff000000 197 198 #define OHCI_RHS_LPS (1U<<0) 199 #define OHCI_RHS_OCI (1U<<1) 200 #define OHCI_RHS_DRWE (1U<<15) 201 #define OHCI_RHS_LPSC (1U<<16) 202 #define OHCI_RHS_OCIC (1U<<17) 203 #define OHCI_RHS_CRWE (1U<<31) 204 205 #define OHCI_PORT_CCS (1<<0) 206 #define OHCI_PORT_PES (1<<1) 207 #define OHCI_PORT_PSS (1<<2) 208 #define OHCI_PORT_POCI (1<<3) 209 #define OHCI_PORT_PRS (1<<4) 210 #define OHCI_PORT_PPS (1<<8) 211 #define OHCI_PORT_LSDA (1<<9) 212 #define OHCI_PORT_CSC (1<<16) 213 #define OHCI_PORT_PESC (1<<17) 214 #define OHCI_PORT_PSSC (1<<18) 215 #define OHCI_PORT_OCIC (1<<19) 216 #define OHCI_PORT_PRSC (1<<20) 217 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 218 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 219 220 #define OHCI_TD_DIR_SETUP 0x0 221 #define OHCI_TD_DIR_OUT 0x1 222 #define OHCI_TD_DIR_IN 0x2 223 #define OHCI_TD_DIR_RESERVED 0x3 224 225 #define OHCI_CC_NOERROR 0x0 226 #define OHCI_CC_CRC 0x1 227 #define OHCI_CC_BITSTUFFING 0x2 228 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 229 #define OHCI_CC_STALL 0x4 230 #define OHCI_CC_DEVICENOTRESPONDING 0x5 231 #define OHCI_CC_PIDCHECKFAILURE 0x6 232 #define OHCI_CC_UNDEXPETEDPID 0x7 233 #define OHCI_CC_DATAOVERRUN 0x8 234 #define OHCI_CC_DATAUNDERRUN 0x9 235 #define OHCI_CC_BUFFEROVERRUN 0xc 236 #define OHCI_CC_BUFFERUNDERRUN 0xd 237 238 #define OHCI_HRESET_FSBIR (1 << 0) 239 240 static void ohci_die(OHCIState *ohci) 241 { 242 ohci->ohci_die(ohci); 243 } 244 245 /* Update IRQ levels */ 246 static inline void ohci_intr_update(OHCIState *ohci) 247 { 248 int level = 0; 249 250 if ((ohci->intr & OHCI_INTR_MIE) && 251 (ohci->intr_status & ohci->intr)) 252 level = 1; 253 254 qemu_set_irq(ohci->irq, level); 255 } 256 257 /* Set an interrupt */ 258 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 259 { 260 ohci->intr_status |= intr; 261 ohci_intr_update(ohci); 262 } 263 264 /* Attach or detach a device on a root hub port. */ 265 static void ohci_attach(USBPort *port1) 266 { 267 OHCIState *s = port1->opaque; 268 OHCIPort *port = &s->rhport[port1->index]; 269 uint32_t old_state = port->ctrl; 270 271 /* set connect status */ 272 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 273 274 /* update speed */ 275 if (port->port.dev->speed == USB_SPEED_LOW) { 276 port->ctrl |= OHCI_PORT_LSDA; 277 } else { 278 port->ctrl &= ~OHCI_PORT_LSDA; 279 } 280 281 /* notify of remote-wakeup */ 282 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 283 ohci_set_interrupt(s, OHCI_INTR_RD); 284 } 285 286 trace_usb_ohci_port_attach(port1->index); 287 288 if (old_state != port->ctrl) { 289 ohci_set_interrupt(s, OHCI_INTR_RHSC); 290 } 291 } 292 293 static void ohci_detach(USBPort *port1) 294 { 295 OHCIState *s = port1->opaque; 296 OHCIPort *port = &s->rhport[port1->index]; 297 uint32_t old_state = port->ctrl; 298 299 ohci_async_cancel_device(s, port1->dev); 300 301 /* set connect status */ 302 if (port->ctrl & OHCI_PORT_CCS) { 303 port->ctrl &= ~OHCI_PORT_CCS; 304 port->ctrl |= OHCI_PORT_CSC; 305 } 306 /* disable port */ 307 if (port->ctrl & OHCI_PORT_PES) { 308 port->ctrl &= ~OHCI_PORT_PES; 309 port->ctrl |= OHCI_PORT_PESC; 310 } 311 trace_usb_ohci_port_detach(port1->index); 312 313 if (old_state != port->ctrl) { 314 ohci_set_interrupt(s, OHCI_INTR_RHSC); 315 } 316 } 317 318 static void ohci_wakeup(USBPort *port1) 319 { 320 OHCIState *s = port1->opaque; 321 OHCIPort *port = &s->rhport[port1->index]; 322 uint32_t intr = 0; 323 if (port->ctrl & OHCI_PORT_PSS) { 324 trace_usb_ohci_port_wakeup(port1->index); 325 port->ctrl |= OHCI_PORT_PSSC; 326 port->ctrl &= ~OHCI_PORT_PSS; 327 intr = OHCI_INTR_RHSC; 328 } 329 /* Note that the controller can be suspended even if this port is not */ 330 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 331 trace_usb_ohci_remote_wakeup(s->name); 332 /* This is the one state transition the controller can do by itself */ 333 s->ctl &= ~OHCI_CTL_HCFS; 334 s->ctl |= OHCI_USB_RESUME; 335 /* In suspend mode only ResumeDetected is possible, not RHSC: 336 * see the OHCI spec 5.1.2.3. 337 */ 338 intr = OHCI_INTR_RD; 339 } 340 ohci_set_interrupt(s, intr); 341 } 342 343 static void ohci_child_detach(USBPort *port1, USBDevice *child) 344 { 345 OHCIState *s = port1->opaque; 346 347 ohci_async_cancel_device(s, child); 348 } 349 350 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 351 { 352 USBDevice *dev; 353 int i; 354 355 for (i = 0; i < ohci->num_ports; i++) { 356 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 357 continue; 358 } 359 dev = usb_find_device(&ohci->rhport[i].port, addr); 360 if (dev != NULL) { 361 return dev; 362 } 363 } 364 return NULL; 365 } 366 367 void ohci_stop_endpoints(OHCIState *ohci) 368 { 369 USBDevice *dev; 370 int i, j; 371 372 for (i = 0; i < ohci->num_ports; i++) { 373 dev = ohci->rhport[i].port.dev; 374 if (dev && dev->attached) { 375 usb_device_ep_stopped(dev, &dev->ep_ctl); 376 for (j = 0; j < USB_MAX_ENDPOINTS; j++) { 377 usb_device_ep_stopped(dev, &dev->ep_in[j]); 378 usb_device_ep_stopped(dev, &dev->ep_out[j]); 379 } 380 } 381 } 382 } 383 384 static void ohci_roothub_reset(OHCIState *ohci) 385 { 386 OHCIPort *port; 387 int i; 388 389 ohci_bus_stop(ohci); 390 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 391 ohci->rhdesc_b = 0x0; /* Impl. specific */ 392 ohci->rhstatus = 0; 393 394 for (i = 0; i < ohci->num_ports; i++) { 395 port = &ohci->rhport[i]; 396 port->ctrl = 0; 397 if (port->port.dev && port->port.dev->attached) { 398 usb_port_reset(&port->port); 399 } 400 } 401 if (ohci->async_td) { 402 usb_cancel_packet(&ohci->usb_packet); 403 ohci->async_td = 0; 404 } 405 ohci_stop_endpoints(ohci); 406 } 407 408 /* Reset the controller */ 409 static void ohci_soft_reset(OHCIState *ohci) 410 { 411 trace_usb_ohci_reset(ohci->name); 412 413 ohci_bus_stop(ohci); 414 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; 415 ohci->old_ctl = 0; 416 ohci->status = 0; 417 ohci->intr_status = 0; 418 ohci->intr = OHCI_INTR_MIE; 419 420 ohci->hcca = 0; 421 ohci->ctrl_head = ohci->ctrl_cur = 0; 422 ohci->bulk_head = ohci->bulk_cur = 0; 423 ohci->per_cur = 0; 424 ohci->done = 0; 425 ohci->done_count = 7; 426 427 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 428 * I took the value linux sets ... 429 */ 430 ohci->fsmps = 0x2778; 431 ohci->fi = 0x2edf; 432 ohci->fit = 0; 433 ohci->frt = 0; 434 ohci->frame_number = 0; 435 ohci->pstart = 0; 436 ohci->lst = OHCI_LS_THRESH; 437 } 438 439 void ohci_hard_reset(OHCIState *ohci) 440 { 441 ohci_soft_reset(ohci); 442 ohci->ctl = 0; 443 ohci_roothub_reset(ohci); 444 } 445 446 /* Get an array of dwords from main memory */ 447 static inline int get_dwords(OHCIState *ohci, 448 dma_addr_t addr, uint32_t *buf, int num) 449 { 450 int i; 451 452 addr += ohci->localmem_base; 453 454 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 455 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 456 return -1; 457 } 458 *buf = le32_to_cpu(*buf); 459 } 460 461 return 0; 462 } 463 464 /* Put an array of dwords in to main memory */ 465 static inline int put_dwords(OHCIState *ohci, 466 dma_addr_t addr, uint32_t *buf, int num) 467 { 468 int i; 469 470 addr += ohci->localmem_base; 471 472 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 473 uint32_t tmp = cpu_to_le32(*buf); 474 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 475 return -1; 476 } 477 } 478 479 return 0; 480 } 481 482 /* Get an array of words from main memory */ 483 static inline int get_words(OHCIState *ohci, 484 dma_addr_t addr, uint16_t *buf, int num) 485 { 486 int i; 487 488 addr += ohci->localmem_base; 489 490 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 491 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 492 return -1; 493 } 494 *buf = le16_to_cpu(*buf); 495 } 496 497 return 0; 498 } 499 500 /* Put an array of words in to main memory */ 501 static inline int put_words(OHCIState *ohci, 502 dma_addr_t addr, uint16_t *buf, int num) 503 { 504 int i; 505 506 addr += ohci->localmem_base; 507 508 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 509 uint16_t tmp = cpu_to_le16(*buf); 510 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 511 return -1; 512 } 513 } 514 515 return 0; 516 } 517 518 static inline int ohci_read_ed(OHCIState *ohci, 519 dma_addr_t addr, struct ohci_ed *ed) 520 { 521 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 522 } 523 524 static inline int ohci_read_td(OHCIState *ohci, 525 dma_addr_t addr, struct ohci_td *td) 526 { 527 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 528 } 529 530 static inline int ohci_read_iso_td(OHCIState *ohci, 531 dma_addr_t addr, struct ohci_iso_td *td) 532 { 533 return get_dwords(ohci, addr, (uint32_t *)td, 4) || 534 get_words(ohci, addr + 16, td->offset, 8); 535 } 536 537 static inline int ohci_read_hcca(OHCIState *ohci, 538 dma_addr_t addr, struct ohci_hcca *hcca) 539 { 540 return dma_memory_read(ohci->as, addr + ohci->localmem_base, 541 hcca, sizeof(*hcca)); 542 } 543 544 static inline int ohci_put_ed(OHCIState *ohci, 545 dma_addr_t addr, struct ohci_ed *ed) 546 { 547 /* ed->tail is under control of the HCD. 548 * Since just ed->head is changed by HC, just write back this 549 */ 550 551 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 552 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 553 ED_WBACK_SIZE >> 2); 554 } 555 556 static inline int ohci_put_td(OHCIState *ohci, 557 dma_addr_t addr, struct ohci_td *td) 558 { 559 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 560 } 561 562 static inline int ohci_put_iso_td(OHCIState *ohci, 563 dma_addr_t addr, struct ohci_iso_td *td) 564 { 565 return put_dwords(ohci, addr, (uint32_t *)td, 4) || 566 put_words(ohci, addr + 16, td->offset, 8); 567 } 568 569 static inline int ohci_put_hcca(OHCIState *ohci, 570 dma_addr_t addr, struct ohci_hcca *hcca) 571 { 572 return dma_memory_write(ohci->as, 573 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 574 (char *)hcca + HCCA_WRITEBACK_OFFSET, 575 HCCA_WRITEBACK_SIZE); 576 } 577 578 /* Read/Write the contents of a TD from/to main memory. */ 579 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 580 uint8_t *buf, int len, DMADirection dir) 581 { 582 dma_addr_t ptr, n; 583 584 ptr = td->cbp; 585 n = 0x1000 - (ptr & 0xfff); 586 if (n > len) 587 n = len; 588 589 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 590 n, dir, MEMTXATTRS_UNSPECIFIED)) { 591 return -1; 592 } 593 if (n == len) { 594 return 0; 595 } 596 ptr = td->be & ~0xfffu; 597 buf += n; 598 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 599 len - n, dir, MEMTXATTRS_UNSPECIFIED)) { 600 return -1; 601 } 602 return 0; 603 } 604 605 /* Read/Write the contents of an ISO TD from/to main memory. */ 606 static int ohci_copy_iso_td(OHCIState *ohci, 607 uint32_t start_addr, uint32_t end_addr, 608 uint8_t *buf, int len, DMADirection dir) 609 { 610 dma_addr_t ptr, n; 611 612 ptr = start_addr; 613 n = 0x1000 - (ptr & 0xfff); 614 if (n > len) 615 n = len; 616 617 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 618 n, dir, MEMTXATTRS_UNSPECIFIED)) { 619 return -1; 620 } 621 if (n == len) { 622 return 0; 623 } 624 ptr = end_addr & ~0xfffu; 625 buf += n; 626 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 627 len - n, dir, MEMTXATTRS_UNSPECIFIED)) { 628 return -1; 629 } 630 return 0; 631 } 632 633 static void ohci_process_lists(OHCIState *ohci, int completion); 634 635 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 636 { 637 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 638 639 trace_usb_ohci_async_complete(); 640 ohci->async_complete = true; 641 ohci_process_lists(ohci, 1); 642 } 643 644 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 645 646 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, 647 int completion) 648 { 649 int dir; 650 size_t len = 0; 651 const char *str = NULL; 652 int pid; 653 int ret; 654 int i; 655 USBDevice *dev; 656 USBEndpoint *ep; 657 struct ohci_iso_td iso_td; 658 uint32_t addr; 659 uint16_t starting_frame; 660 int16_t relative_frame_number; 661 int frame_count; 662 uint32_t start_offset, next_offset, end_offset = 0; 663 uint32_t start_addr, end_addr; 664 665 addr = ed->head & OHCI_DPTR_MASK; 666 667 if (ohci_read_iso_td(ohci, addr, &iso_td)) { 668 trace_usb_ohci_iso_td_read_failed(addr); 669 ohci_die(ohci); 670 return 1; 671 } 672 673 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 674 frame_count = OHCI_BM(iso_td.flags, TD_FC); 675 relative_frame_number = USUB(ohci->frame_number, starting_frame); 676 677 trace_usb_ohci_iso_td_head( 678 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 679 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 680 ohci->frame_number, starting_frame, 681 frame_count, relative_frame_number); 682 trace_usb_ohci_iso_td_head_offset( 683 iso_td.offset[0], iso_td.offset[1], 684 iso_td.offset[2], iso_td.offset[3], 685 iso_td.offset[4], iso_td.offset[5], 686 iso_td.offset[6], iso_td.offset[7]); 687 688 if (relative_frame_number < 0) { 689 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); 690 return 1; 691 } else if (relative_frame_number > frame_count) { 692 /* ISO TD expired - retire the TD to the Done Queue and continue with 693 the next ISO TD of the same ED */ 694 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, 695 frame_count); 696 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) { 697 /* avoid infinite loop */ 698 return 1; 699 } 700 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 701 ed->head &= ~OHCI_DPTR_MASK; 702 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 703 iso_td.next = ohci->done; 704 ohci->done = addr; 705 i = OHCI_BM(iso_td.flags, TD_DI); 706 if (i < ohci->done_count) 707 ohci->done_count = i; 708 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 709 ohci_die(ohci); 710 return 1; 711 } 712 return 0; 713 } 714 715 dir = OHCI_BM(ed->flags, ED_D); 716 switch (dir) { 717 case OHCI_TD_DIR_IN: 718 str = "in"; 719 pid = USB_TOKEN_IN; 720 break; 721 case OHCI_TD_DIR_OUT: 722 str = "out"; 723 pid = USB_TOKEN_OUT; 724 break; 725 case OHCI_TD_DIR_SETUP: 726 str = "setup"; 727 pid = USB_TOKEN_SETUP; 728 break; 729 default: 730 trace_usb_ohci_iso_td_bad_direction(dir); 731 return 1; 732 } 733 734 if (!iso_td.bp || !iso_td.be) { 735 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); 736 return 1; 737 } 738 739 start_offset = iso_td.offset[relative_frame_number]; 740 if (relative_frame_number < frame_count) { 741 next_offset = iso_td.offset[relative_frame_number + 1]; 742 } else { 743 next_offset = iso_td.be; 744 } 745 746 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 747 ((relative_frame_number < frame_count) && 748 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 749 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); 750 return 1; 751 } 752 753 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 754 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); 755 return 1; 756 } 757 758 if ((start_offset & 0x1000) == 0) { 759 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 760 (start_offset & OHCI_OFFSET_MASK); 761 } else { 762 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 763 (start_offset & OHCI_OFFSET_MASK); 764 } 765 766 if (relative_frame_number < frame_count) { 767 end_offset = next_offset - 1; 768 if ((end_offset & 0x1000) == 0) { 769 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 770 (end_offset & OHCI_OFFSET_MASK); 771 } else { 772 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 773 (end_offset & OHCI_OFFSET_MASK); 774 } 775 } else { 776 /* Last packet in the ISO TD */ 777 end_addr = next_offset; 778 } 779 780 if (start_addr > end_addr) { 781 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr); 782 return 1; 783 } 784 785 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 786 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 787 - (start_addr & OHCI_OFFSET_MASK); 788 } else { 789 len = end_addr - start_addr + 1; 790 } 791 if (len > sizeof(ohci->usb_buf)) { 792 len = sizeof(ohci->usb_buf); 793 } 794 795 if (len && dir != OHCI_TD_DIR_IN) { 796 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 797 DMA_DIRECTION_TO_DEVICE)) { 798 ohci_die(ohci); 799 return 1; 800 } 801 } 802 803 if (!completion) { 804 bool int_req = relative_frame_number == frame_count && 805 OHCI_BM(iso_td.flags, TD_DI) == 0; 806 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 807 if (dev == NULL) { 808 trace_usb_ohci_td_dev_error(); 809 return 1; 810 } 811 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 812 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); 813 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); 814 usb_handle_packet(dev, &ohci->usb_packet); 815 if (ohci->usb_packet.status == USB_RET_ASYNC) { 816 usb_device_flush_ep_queue(dev, ep); 817 return 1; 818 } 819 } 820 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 821 ret = ohci->usb_packet.actual_length; 822 } else { 823 ret = ohci->usb_packet.status; 824 } 825 826 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, 827 str, len, ret); 828 829 /* Writeback */ 830 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 831 /* IN transfer succeeded */ 832 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 833 DMA_DIRECTION_FROM_DEVICE)) { 834 ohci_die(ohci); 835 return 1; 836 } 837 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 838 OHCI_CC_NOERROR); 839 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 840 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 841 /* OUT transfer succeeded */ 842 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 843 OHCI_CC_NOERROR); 844 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 845 } else { 846 if (ret > (ssize_t) len) { 847 trace_usb_ohci_iso_td_data_overrun(ret, len); 848 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 849 OHCI_CC_DATAOVERRUN); 850 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 851 len); 852 } else if (ret >= 0) { 853 trace_usb_ohci_iso_td_data_underrun(ret); 854 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 855 OHCI_CC_DATAUNDERRUN); 856 } else { 857 switch (ret) { 858 case USB_RET_IOERROR: 859 case USB_RET_NODEV: 860 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 861 OHCI_CC_DEVICENOTRESPONDING); 862 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 863 0); 864 break; 865 case USB_RET_NAK: 866 case USB_RET_STALL: 867 trace_usb_ohci_iso_td_nak(ret); 868 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 869 OHCI_CC_STALL); 870 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 871 0); 872 break; 873 default: 874 trace_usb_ohci_iso_td_bad_response(ret); 875 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 876 OHCI_CC_UNDEXPETEDPID); 877 break; 878 } 879 } 880 } 881 882 if (relative_frame_number == frame_count) { 883 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 884 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 885 ed->head &= ~OHCI_DPTR_MASK; 886 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 887 iso_td.next = ohci->done; 888 ohci->done = addr; 889 i = OHCI_BM(iso_td.flags, TD_DI); 890 if (i < ohci->done_count) 891 ohci->done_count = i; 892 } 893 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 894 ohci_die(ohci); 895 } 896 return 1; 897 } 898 899 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 900 { 901 bool print16; 902 bool printall; 903 const int width = 16; 904 int i; 905 char tmp[3 * width + 1]; 906 char *p = tmp; 907 908 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT); 909 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL); 910 911 if (!printall && !print16) { 912 return; 913 } 914 915 for (i = 0; ; i++) { 916 if (i && (!(i % width) || (i == len))) { 917 if (!printall) { 918 trace_usb_ohci_td_pkt_short(msg, tmp); 919 break; 920 } 921 trace_usb_ohci_td_pkt_full(msg, tmp); 922 p = tmp; 923 *p = 0; 924 } 925 if (i == len) { 926 break; 927 } 928 929 p += sprintf(p, " %.2x", buf[i]); 930 } 931 } 932 933 /* Service a transport descriptor. 934 Returns nonzero to terminate processing of this endpoint. */ 935 936 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 937 { 938 int dir; 939 size_t len = 0, pktlen = 0; 940 const char *str = NULL; 941 int pid; 942 int ret; 943 int i; 944 USBDevice *dev; 945 USBEndpoint *ep; 946 struct ohci_td td; 947 uint32_t addr; 948 int flag_r; 949 int completion; 950 951 addr = ed->head & OHCI_DPTR_MASK; 952 /* See if this TD has already been submitted to the device. */ 953 completion = (addr == ohci->async_td); 954 if (completion && !ohci->async_complete) { 955 trace_usb_ohci_td_skip_async(); 956 return 1; 957 } 958 if (ohci_read_td(ohci, addr, &td)) { 959 trace_usb_ohci_td_read_error(addr); 960 ohci_die(ohci); 961 return 1; 962 } 963 964 dir = OHCI_BM(ed->flags, ED_D); 965 switch (dir) { 966 case OHCI_TD_DIR_OUT: 967 case OHCI_TD_DIR_IN: 968 /* Same value. */ 969 break; 970 default: 971 dir = OHCI_BM(td.flags, TD_DP); 972 break; 973 } 974 975 switch (dir) { 976 case OHCI_TD_DIR_IN: 977 str = "in"; 978 pid = USB_TOKEN_IN; 979 break; 980 case OHCI_TD_DIR_OUT: 981 str = "out"; 982 pid = USB_TOKEN_OUT; 983 break; 984 case OHCI_TD_DIR_SETUP: 985 str = "setup"; 986 pid = USB_TOKEN_SETUP; 987 break; 988 default: 989 trace_usb_ohci_td_bad_direction(dir); 990 return 1; 991 } 992 if (td.cbp && td.be) { 993 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 994 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 995 } else { 996 if (td.cbp > td.be) { 997 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be); 998 ohci_die(ohci); 999 return 1; 1000 } 1001 len = (td.be - td.cbp) + 1; 1002 } 1003 if (len > sizeof(ohci->usb_buf)) { 1004 len = sizeof(ohci->usb_buf); 1005 } 1006 1007 pktlen = len; 1008 if (len && dir != OHCI_TD_DIR_IN) { 1009 /* The endpoint may not allow us to transfer it all now */ 1010 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 1011 if (pktlen > len) { 1012 pktlen = len; 1013 } 1014 if (!completion) { 1015 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 1016 DMA_DIRECTION_TO_DEVICE)) { 1017 ohci_die(ohci); 1018 } 1019 } 1020 } 1021 } 1022 1023 flag_r = (td.flags & OHCI_TD_R) != 0; 1024 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, 1025 flag_r, td.cbp, td.be); 1026 ohci_td_pkt("OUT", ohci->usb_buf, pktlen); 1027 1028 if (completion) { 1029 ohci->async_td = 0; 1030 ohci->async_complete = false; 1031 } else { 1032 if (ohci->async_td) { 1033 /* ??? The hardware should allow one active packet per 1034 endpoint. We only allow one active packet per controller. 1035 This should be sufficient as long as devices respond in a 1036 timely manner. 1037 */ 1038 trace_usb_ohci_td_too_many_pending(); 1039 return 1; 1040 } 1041 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 1042 if (dev == NULL) { 1043 trace_usb_ohci_td_dev_error(); 1044 return 1; 1045 } 1046 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 1047 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, 1048 OHCI_BM(td.flags, TD_DI) == 0); 1049 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 1050 usb_handle_packet(dev, &ohci->usb_packet); 1051 trace_usb_ohci_td_packet_status(ohci->usb_packet.status); 1052 1053 if (ohci->usb_packet.status == USB_RET_ASYNC) { 1054 usb_device_flush_ep_queue(dev, ep); 1055 ohci->async_td = addr; 1056 return 1; 1057 } 1058 } 1059 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 1060 ret = ohci->usb_packet.actual_length; 1061 } else { 1062 ret = ohci->usb_packet.status; 1063 } 1064 1065 if (ret >= 0) { 1066 if (dir == OHCI_TD_DIR_IN) { 1067 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1068 DMA_DIRECTION_FROM_DEVICE)) { 1069 ohci_die(ohci); 1070 } 1071 ohci_td_pkt("IN", ohci->usb_buf, pktlen); 1072 } else { 1073 ret = pktlen; 1074 } 1075 } 1076 1077 /* Writeback */ 1078 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 1079 /* Transmission succeeded. */ 1080 if (ret == len) { 1081 td.cbp = 0; 1082 } else { 1083 if ((td.cbp & 0xfff) + ret > 0xfff) { 1084 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 1085 } else { 1086 td.cbp += ret; 1087 } 1088 } 1089 td.flags |= OHCI_TD_T1; 1090 td.flags ^= OHCI_TD_T0; 1091 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1092 OHCI_SET_BM(td.flags, TD_EC, 0); 1093 1094 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1095 /* Partial packet transfer: TD not ready to retire yet */ 1096 goto exit_no_retire; 1097 } 1098 1099 /* Setting ED_C is part of the TD retirement process */ 1100 ed->head &= ~OHCI_ED_C; 1101 if (td.flags & OHCI_TD_T0) 1102 ed->head |= OHCI_ED_C; 1103 } else { 1104 if (ret >= 0) { 1105 trace_usb_ohci_td_underrun(); 1106 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1107 } else { 1108 switch (ret) { 1109 case USB_RET_IOERROR: 1110 case USB_RET_NODEV: 1111 trace_usb_ohci_td_dev_error(); 1112 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1113 break; 1114 case USB_RET_NAK: 1115 trace_usb_ohci_td_nak(); 1116 return 1; 1117 case USB_RET_STALL: 1118 trace_usb_ohci_td_stall(); 1119 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1120 break; 1121 case USB_RET_BABBLE: 1122 trace_usb_ohci_td_babble(); 1123 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1124 break; 1125 default: 1126 trace_usb_ohci_td_bad_device_response(ret); 1127 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1128 OHCI_SET_BM(td.flags, TD_EC, 3); 1129 break; 1130 } 1131 /* An error occurred so we have to clear the interrupt counter. See 1132 * spec at 6.4.4 on page 104 */ 1133 ohci->done_count = 0; 1134 } 1135 ed->head |= OHCI_ED_H; 1136 } 1137 1138 /* Retire this TD */ 1139 ed->head &= ~OHCI_DPTR_MASK; 1140 ed->head |= td.next & OHCI_DPTR_MASK; 1141 td.next = ohci->done; 1142 ohci->done = addr; 1143 i = OHCI_BM(td.flags, TD_DI); 1144 if (i < ohci->done_count) 1145 ohci->done_count = i; 1146 exit_no_retire: 1147 if (ohci_put_td(ohci, addr, &td)) { 1148 ohci_die(ohci); 1149 return 1; 1150 } 1151 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1152 } 1153 1154 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1155 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) 1156 { 1157 struct ohci_ed ed; 1158 uint32_t next_ed; 1159 uint32_t cur; 1160 int active; 1161 uint32_t link_cnt = 0; 1162 active = 0; 1163 1164 if (head == 0) 1165 return 0; 1166 1167 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) { 1168 if (ohci_read_ed(ohci, cur, &ed)) { 1169 trace_usb_ohci_ed_read_error(cur); 1170 ohci_die(ohci); 1171 return 0; 1172 } 1173 1174 next_ed = ed.next & OHCI_DPTR_MASK; 1175 1176 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1177 uint32_t addr; 1178 /* Cancel pending packets for ED that have been paused. */ 1179 addr = ed.head & OHCI_DPTR_MASK; 1180 if (ohci->async_td && addr == ohci->async_td) { 1181 usb_cancel_packet(&ohci->usb_packet); 1182 ohci->async_td = 0; 1183 usb_device_ep_stopped(ohci->usb_packet.ep->dev, 1184 ohci->usb_packet.ep); 1185 } 1186 continue; 1187 } 1188 1189 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1190 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, 1191 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1192 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1193 trace_usb_ohci_ed_pkt_flags( 1194 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1195 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1196 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1197 OHCI_BM(ed.flags, ED_MPS)); 1198 1199 active = 1; 1200 1201 if ((ed.flags & OHCI_ED_F) == 0) { 1202 if (ohci_service_td(ohci, &ed)) 1203 break; 1204 } else { 1205 /* Handle isochronous endpoints */ 1206 if (ohci_service_iso_td(ohci, &ed, completion)) 1207 break; 1208 } 1209 } 1210 1211 if (ohci_put_ed(ohci, cur, &ed)) { 1212 ohci_die(ohci); 1213 return 0; 1214 } 1215 } 1216 1217 return active; 1218 } 1219 1220 /* set a timer for EOF */ 1221 static void ohci_eof_timer(OHCIState *ohci) 1222 { 1223 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1224 } 1225 /* Set a timer for EOF and generate a SOF event */ 1226 static void ohci_sof(OHCIState *ohci) 1227 { 1228 ohci->sof_time += usb_frame_time; 1229 ohci_eof_timer(ohci); 1230 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1231 } 1232 1233 /* Process Control and Bulk lists. */ 1234 static void ohci_process_lists(OHCIState *ohci, int completion) 1235 { 1236 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1237 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1238 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); 1239 } 1240 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { 1241 ohci->ctrl_cur = 0; 1242 ohci->status &= ~OHCI_STATUS_CLF; 1243 } 1244 } 1245 1246 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1247 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { 1248 ohci->bulk_cur = 0; 1249 ohci->status &= ~OHCI_STATUS_BLF; 1250 } 1251 } 1252 } 1253 1254 /* Do frame processing on frame boundary */ 1255 static void ohci_frame_boundary(void *opaque) 1256 { 1257 OHCIState *ohci = opaque; 1258 struct ohci_hcca hcca; 1259 1260 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { 1261 trace_usb_ohci_hcca_read_error(ohci->hcca); 1262 ohci_die(ohci); 1263 return; 1264 } 1265 1266 /* Process all the lists at the end of the frame */ 1267 if (ohci->ctl & OHCI_CTL_PLE) { 1268 int n; 1269 1270 n = ohci->frame_number & 0x1f; 1271 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); 1272 } 1273 1274 /* Cancel all pending packets if either of the lists has been disabled. */ 1275 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1276 if (ohci->async_td) { 1277 usb_cancel_packet(&ohci->usb_packet); 1278 ohci->async_td = 0; 1279 } 1280 ohci_stop_endpoints(ohci); 1281 } 1282 ohci->old_ctl = ohci->ctl; 1283 ohci_process_lists(ohci, 0); 1284 1285 /* Stop if UnrecoverableError happened or ohci_sof will crash */ 1286 if (ohci->intr_status & OHCI_INTR_UE) { 1287 return; 1288 } 1289 1290 /* Frame boundary, so do EOF stuf here */ 1291 ohci->frt = ohci->fit; 1292 1293 /* Increment frame number and take care of endianness. */ 1294 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1295 hcca.frame = cpu_to_le16(ohci->frame_number); 1296 1297 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1298 if (!ohci->done) 1299 abort(); 1300 if (ohci->intr & ohci->intr_status) 1301 ohci->done |= 1; 1302 hcca.done = cpu_to_le32(ohci->done); 1303 ohci->done = 0; 1304 ohci->done_count = 7; 1305 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1306 } 1307 1308 if (ohci->done_count != 7 && ohci->done_count != 0) 1309 ohci->done_count--; 1310 1311 /* Do SOF stuff here */ 1312 ohci_sof(ohci); 1313 1314 /* Writeback HCCA */ 1315 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { 1316 ohci_die(ohci); 1317 } 1318 } 1319 1320 /* Start sending SOF tokens across the USB bus, lists are processed in 1321 * next frame 1322 */ 1323 static int ohci_bus_start(OHCIState *ohci) 1324 { 1325 trace_usb_ohci_start(ohci->name); 1326 1327 /* Delay the first SOF event by one frame time as 1328 * linux driver is not ready to receive it and 1329 * can meet some race conditions 1330 */ 1331 1332 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1333 ohci_eof_timer(ohci); 1334 1335 return 1; 1336 } 1337 1338 /* Stop sending SOF tokens on the bus */ 1339 void ohci_bus_stop(OHCIState *ohci) 1340 { 1341 trace_usb_ohci_stop(ohci->name); 1342 timer_del(ohci->eof_timer); 1343 } 1344 1345 /* Sets a flag in a port status register but only set it if the port is 1346 * connected, if not set ConnectStatusChange flag. If flag is enabled 1347 * return 1. 1348 */ 1349 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1350 { 1351 int ret = 1; 1352 1353 /* writing a 0 has no effect */ 1354 if (val == 0) 1355 return 0; 1356 1357 /* If CurrentConnectStatus is cleared we set 1358 * ConnectStatusChange 1359 */ 1360 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1361 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1362 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1363 /* TODO: CSC is a wakeup event */ 1364 } 1365 return 0; 1366 } 1367 1368 if (ohci->rhport[i].ctrl & val) 1369 ret = 0; 1370 1371 /* set the bit */ 1372 ohci->rhport[i].ctrl |= val; 1373 1374 return ret; 1375 } 1376 1377 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1378 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1379 { 1380 val &= OHCI_FMI_FI; 1381 1382 if (val != ohci->fi) { 1383 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); 1384 } 1385 1386 ohci->fi = val; 1387 } 1388 1389 static void ohci_port_power(OHCIState *ohci, int i, int p) 1390 { 1391 if (p) { 1392 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1393 } else { 1394 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1395 OHCI_PORT_CCS| 1396 OHCI_PORT_PSS| 1397 OHCI_PORT_PRS); 1398 } 1399 } 1400 1401 /* Set HcControlRegister */ 1402 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1403 { 1404 uint32_t old_state; 1405 uint32_t new_state; 1406 1407 old_state = ohci->ctl & OHCI_CTL_HCFS; 1408 ohci->ctl = val; 1409 new_state = ohci->ctl & OHCI_CTL_HCFS; 1410 1411 /* no state change */ 1412 if (old_state == new_state) 1413 return; 1414 1415 trace_usb_ohci_set_ctl(ohci->name, new_state); 1416 switch (new_state) { 1417 case OHCI_USB_OPERATIONAL: 1418 ohci_bus_start(ohci); 1419 break; 1420 case OHCI_USB_SUSPEND: 1421 ohci_bus_stop(ohci); 1422 /* clear pending SF otherwise linux driver loops in ohci_irq() */ 1423 ohci->intr_status &= ~OHCI_INTR_SF; 1424 ohci_intr_update(ohci); 1425 break; 1426 case OHCI_USB_RESUME: 1427 trace_usb_ohci_resume(ohci->name); 1428 break; 1429 case OHCI_USB_RESET: 1430 ohci_roothub_reset(ohci); 1431 break; 1432 } 1433 } 1434 1435 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1436 { 1437 uint16_t fr; 1438 int64_t tks; 1439 1440 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1441 return (ohci->frt << 31); 1442 1443 /* Being in USB operational state guarnatees sof_time was 1444 * set already. 1445 */ 1446 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; 1447 if (tks < 0) { 1448 tks = 0; 1449 } 1450 1451 /* avoid muldiv if possible */ 1452 if (tks >= usb_frame_time) 1453 return (ohci->frt << 31); 1454 1455 tks = tks / usb_bit_time; 1456 fr = (uint16_t)(ohci->fi - tks); 1457 1458 return (ohci->frt << 31) | fr; 1459 } 1460 1461 1462 /* Set root hub status */ 1463 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1464 { 1465 uint32_t old_state; 1466 1467 old_state = ohci->rhstatus; 1468 1469 /* write 1 to clear OCIC */ 1470 if (val & OHCI_RHS_OCIC) 1471 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1472 1473 if (val & OHCI_RHS_LPS) { 1474 int i; 1475 1476 for (i = 0; i < ohci->num_ports; i++) 1477 ohci_port_power(ohci, i, 0); 1478 trace_usb_ohci_hub_power_down(); 1479 } 1480 1481 if (val & OHCI_RHS_LPSC) { 1482 int i; 1483 1484 for (i = 0; i < ohci->num_ports; i++) 1485 ohci_port_power(ohci, i, 1); 1486 trace_usb_ohci_hub_power_up(); 1487 } 1488 1489 if (val & OHCI_RHS_DRWE) 1490 ohci->rhstatus |= OHCI_RHS_DRWE; 1491 1492 if (val & OHCI_RHS_CRWE) 1493 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1494 1495 if (old_state != ohci->rhstatus) 1496 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1497 } 1498 1499 /* Set root hub port status */ 1500 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1501 { 1502 uint32_t old_state; 1503 OHCIPort *port; 1504 1505 port = &ohci->rhport[portnum]; 1506 old_state = port->ctrl; 1507 1508 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1509 if (val & OHCI_PORT_WTC) 1510 port->ctrl &= ~(val & OHCI_PORT_WTC); 1511 1512 if (val & OHCI_PORT_CCS) 1513 port->ctrl &= ~OHCI_PORT_PES; 1514 1515 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1516 1517 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1518 trace_usb_ohci_port_suspend(portnum); 1519 } 1520 1521 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1522 trace_usb_ohci_port_reset(portnum); 1523 usb_device_reset(port->port.dev); 1524 port->ctrl &= ~OHCI_PORT_PRS; 1525 /* ??? Should this also set OHCI_PORT_PESC. */ 1526 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1527 } 1528 1529 /* Invert order here to ensure in ambiguous case, device is 1530 * powered up... 1531 */ 1532 if (val & OHCI_PORT_LSDA) 1533 ohci_port_power(ohci, portnum, 0); 1534 if (val & OHCI_PORT_PPS) 1535 ohci_port_power(ohci, portnum, 1); 1536 1537 if (old_state != port->ctrl) 1538 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1539 } 1540 1541 static uint64_t ohci_mem_read(void *opaque, 1542 hwaddr addr, 1543 unsigned size) 1544 { 1545 OHCIState *ohci = opaque; 1546 uint32_t retval; 1547 1548 /* Only aligned reads are allowed on OHCI */ 1549 if (addr & 3) { 1550 trace_usb_ohci_mem_read_unaligned(addr); 1551 return 0xffffffff; 1552 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1553 /* HcRhPortStatus */ 1554 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1555 } else { 1556 switch (addr >> 2) { 1557 case 0: /* HcRevision */ 1558 retval = 0x10; 1559 break; 1560 1561 case 1: /* HcControl */ 1562 retval = ohci->ctl; 1563 break; 1564 1565 case 2: /* HcCommandStatus */ 1566 retval = ohci->status; 1567 break; 1568 1569 case 3: /* HcInterruptStatus */ 1570 retval = ohci->intr_status; 1571 break; 1572 1573 case 4: /* HcInterruptEnable */ 1574 case 5: /* HcInterruptDisable */ 1575 retval = ohci->intr; 1576 break; 1577 1578 case 6: /* HcHCCA */ 1579 retval = ohci->hcca; 1580 break; 1581 1582 case 7: /* HcPeriodCurrentED */ 1583 retval = ohci->per_cur; 1584 break; 1585 1586 case 8: /* HcControlHeadED */ 1587 retval = ohci->ctrl_head; 1588 break; 1589 1590 case 9: /* HcControlCurrentED */ 1591 retval = ohci->ctrl_cur; 1592 break; 1593 1594 case 10: /* HcBulkHeadED */ 1595 retval = ohci->bulk_head; 1596 break; 1597 1598 case 11: /* HcBulkCurrentED */ 1599 retval = ohci->bulk_cur; 1600 break; 1601 1602 case 12: /* HcDoneHead */ 1603 retval = ohci->done; 1604 break; 1605 1606 case 13: /* HcFmInterretval */ 1607 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1608 break; 1609 1610 case 14: /* HcFmRemaining */ 1611 retval = ohci_get_frame_remaining(ohci); 1612 break; 1613 1614 case 15: /* HcFmNumber */ 1615 retval = ohci->frame_number; 1616 break; 1617 1618 case 16: /* HcPeriodicStart */ 1619 retval = ohci->pstart; 1620 break; 1621 1622 case 17: /* HcLSThreshold */ 1623 retval = ohci->lst; 1624 break; 1625 1626 case 18: /* HcRhDescriptorA */ 1627 retval = ohci->rhdesc_a; 1628 break; 1629 1630 case 19: /* HcRhDescriptorB */ 1631 retval = ohci->rhdesc_b; 1632 break; 1633 1634 case 20: /* HcRhStatus */ 1635 retval = ohci->rhstatus; 1636 break; 1637 1638 /* PXA27x specific registers */ 1639 case 24: /* HcStatus */ 1640 retval = ohci->hstatus & ohci->hmask; 1641 break; 1642 1643 case 25: /* HcHReset */ 1644 retval = ohci->hreset; 1645 break; 1646 1647 case 26: /* HcHInterruptEnable */ 1648 retval = ohci->hmask; 1649 break; 1650 1651 case 27: /* HcHInterruptTest */ 1652 retval = ohci->htest; 1653 break; 1654 1655 default: 1656 trace_usb_ohci_mem_read_bad_offset(addr); 1657 retval = 0xffffffff; 1658 } 1659 } 1660 1661 return retval; 1662 } 1663 1664 static void ohci_mem_write(void *opaque, 1665 hwaddr addr, 1666 uint64_t val, 1667 unsigned size) 1668 { 1669 OHCIState *ohci = opaque; 1670 1671 /* Only aligned reads are allowed on OHCI */ 1672 if (addr & 3) { 1673 trace_usb_ohci_mem_write_unaligned(addr); 1674 return; 1675 } 1676 1677 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1678 /* HcRhPortStatus */ 1679 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1680 return; 1681 } 1682 1683 switch (addr >> 2) { 1684 case 1: /* HcControl */ 1685 ohci_set_ctl(ohci, val); 1686 break; 1687 1688 case 2: /* HcCommandStatus */ 1689 /* SOC is read-only */ 1690 val = (val & ~OHCI_STATUS_SOC); 1691 1692 /* Bits written as '0' remain unchanged in the register */ 1693 ohci->status |= val; 1694 1695 if (ohci->status & OHCI_STATUS_HCR) 1696 ohci_soft_reset(ohci); 1697 break; 1698 1699 case 3: /* HcInterruptStatus */ 1700 ohci->intr_status &= ~val; 1701 ohci_intr_update(ohci); 1702 break; 1703 1704 case 4: /* HcInterruptEnable */ 1705 ohci->intr |= val; 1706 ohci_intr_update(ohci); 1707 break; 1708 1709 case 5: /* HcInterruptDisable */ 1710 ohci->intr &= ~val; 1711 ohci_intr_update(ohci); 1712 break; 1713 1714 case 6: /* HcHCCA */ 1715 ohci->hcca = val & OHCI_HCCA_MASK; 1716 break; 1717 1718 case 7: /* HcPeriodCurrentED */ 1719 /* Ignore writes to this read-only register, Linux does them */ 1720 break; 1721 1722 case 8: /* HcControlHeadED */ 1723 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1724 break; 1725 1726 case 9: /* HcControlCurrentED */ 1727 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1728 break; 1729 1730 case 10: /* HcBulkHeadED */ 1731 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1732 break; 1733 1734 case 11: /* HcBulkCurrentED */ 1735 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1736 break; 1737 1738 case 13: /* HcFmInterval */ 1739 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1740 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1741 ohci_set_frame_interval(ohci, val); 1742 break; 1743 1744 case 15: /* HcFmNumber */ 1745 break; 1746 1747 case 16: /* HcPeriodicStart */ 1748 ohci->pstart = val & 0xffff; 1749 break; 1750 1751 case 17: /* HcLSThreshold */ 1752 ohci->lst = val & 0xffff; 1753 break; 1754 1755 case 18: /* HcRhDescriptorA */ 1756 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1757 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1758 break; 1759 1760 case 19: /* HcRhDescriptorB */ 1761 break; 1762 1763 case 20: /* HcRhStatus */ 1764 ohci_set_hub_status(ohci, val); 1765 break; 1766 1767 /* PXA27x specific registers */ 1768 case 24: /* HcStatus */ 1769 ohci->hstatus &= ~(val & ohci->hmask); 1770 break; 1771 1772 case 25: /* HcHReset */ 1773 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1774 if (val & OHCI_HRESET_FSBIR) 1775 ohci_hard_reset(ohci); 1776 break; 1777 1778 case 26: /* HcHInterruptEnable */ 1779 ohci->hmask = val; 1780 break; 1781 1782 case 27: /* HcHInterruptTest */ 1783 ohci->htest = val; 1784 break; 1785 1786 default: 1787 trace_usb_ohci_mem_write_bad_offset(addr); 1788 break; 1789 } 1790 } 1791 1792 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) 1793 { 1794 if (ohci->async_td && 1795 usb_packet_is_inflight(&ohci->usb_packet) && 1796 ohci->usb_packet.ep->dev == dev) { 1797 usb_cancel_packet(&ohci->usb_packet); 1798 ohci->async_td = 0; 1799 } 1800 } 1801 1802 static const MemoryRegionOps ohci_mem_ops = { 1803 .read = ohci_mem_read, 1804 .write = ohci_mem_write, 1805 .endianness = DEVICE_LITTLE_ENDIAN, 1806 }; 1807 1808 static USBPortOps ohci_port_ops = { 1809 .attach = ohci_attach, 1810 .detach = ohci_detach, 1811 .child_detach = ohci_child_detach, 1812 .wakeup = ohci_wakeup, 1813 .complete = ohci_async_complete_packet, 1814 }; 1815 1816 static USBBusOps ohci_bus_ops = { 1817 }; 1818 1819 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports, 1820 dma_addr_t localmem_base, char *masterbus, 1821 uint32_t firstport, AddressSpace *as, 1822 void (*ohci_die_fn)(struct OHCIState *), Error **errp) 1823 { 1824 Error *err = NULL; 1825 int i; 1826 1827 ohci->as = as; 1828 ohci->ohci_die = ohci_die_fn; 1829 1830 if (num_ports > OHCI_MAX_PORTS) { 1831 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)", 1832 num_ports, OHCI_MAX_PORTS); 1833 return; 1834 } 1835 1836 if (usb_frame_time == 0) { 1837 #ifdef OHCI_TIME_WARP 1838 usb_frame_time = NANOSECONDS_PER_SECOND; 1839 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000); 1840 #else 1841 usb_frame_time = NANOSECONDS_PER_SECOND / 1000; 1842 if (NANOSECONDS_PER_SECOND >= USB_HZ) { 1843 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ; 1844 } else { 1845 usb_bit_time = 1; 1846 } 1847 #endif 1848 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); 1849 } 1850 1851 ohci->num_ports = num_ports; 1852 if (masterbus) { 1853 USBPort *ports[OHCI_MAX_PORTS]; 1854 for(i = 0; i < num_ports; i++) { 1855 ports[i] = &ohci->rhport[i].port; 1856 } 1857 usb_register_companion(masterbus, ports, num_ports, 1858 firstport, ohci, &ohci_port_ops, 1859 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1860 &err); 1861 if (err) { 1862 error_propagate(errp, err); 1863 return; 1864 } 1865 } else { 1866 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); 1867 for (i = 0; i < num_ports; i++) { 1868 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1869 ohci, i, &ohci_port_ops, 1870 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1871 } 1872 } 1873 1874 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, 1875 ohci, "ohci", 256); 1876 ohci->localmem_base = localmem_base; 1877 1878 ohci->name = object_get_typename(OBJECT(dev)); 1879 usb_packet_init(&ohci->usb_packet); 1880 1881 ohci->async_td = 0; 1882 1883 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1884 ohci_frame_boundary, ohci); 1885 } 1886 1887 /** 1888 * A typical OHCI will stop operating and set itself into error state 1889 * (which can be queried by MMIO) to signal that it got an error. 1890 */ 1891 void ohci_sysbus_die(struct OHCIState *ohci) 1892 { 1893 trace_usb_ohci_die(); 1894 1895 ohci_set_interrupt(ohci, OHCI_INTR_UE); 1896 ohci_bus_stop(ohci); 1897 } 1898 1899 static void ohci_realize_pxa(DeviceState *dev, Error **errp) 1900 { 1901 OHCISysBusState *s = SYSBUS_OHCI(dev); 1902 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1903 Error *err = NULL; 1904 1905 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, 1906 s->masterbus, s->firstport, 1907 &address_space_memory, ohci_sysbus_die, &err); 1908 if (err) { 1909 error_propagate(errp, err); 1910 return; 1911 } 1912 sysbus_init_irq(sbd, &s->ohci.irq); 1913 sysbus_init_mmio(sbd, &s->ohci.mem); 1914 } 1915 1916 static void usb_ohci_reset_sysbus(DeviceState *dev) 1917 { 1918 OHCISysBusState *s = SYSBUS_OHCI(dev); 1919 OHCIState *ohci = &s->ohci; 1920 1921 ohci_hard_reset(ohci); 1922 } 1923 1924 static const VMStateDescription vmstate_ohci_state_port = { 1925 .name = "ohci-core/port", 1926 .version_id = 1, 1927 .minimum_version_id = 1, 1928 .fields = (VMStateField[]) { 1929 VMSTATE_UINT32(ctrl, OHCIPort), 1930 VMSTATE_END_OF_LIST() 1931 }, 1932 }; 1933 1934 static bool ohci_eof_timer_needed(void *opaque) 1935 { 1936 OHCIState *ohci = opaque; 1937 1938 return timer_pending(ohci->eof_timer); 1939 } 1940 1941 static const VMStateDescription vmstate_ohci_eof_timer = { 1942 .name = "ohci-core/eof-timer", 1943 .version_id = 1, 1944 .minimum_version_id = 1, 1945 .needed = ohci_eof_timer_needed, 1946 .fields = (VMStateField[]) { 1947 VMSTATE_TIMER_PTR(eof_timer, OHCIState), 1948 VMSTATE_END_OF_LIST() 1949 }, 1950 }; 1951 1952 const VMStateDescription vmstate_ohci_state = { 1953 .name = "ohci-core", 1954 .version_id = 1, 1955 .minimum_version_id = 1, 1956 .fields = (VMStateField[]) { 1957 VMSTATE_INT64(sof_time, OHCIState), 1958 VMSTATE_UINT32(ctl, OHCIState), 1959 VMSTATE_UINT32(status, OHCIState), 1960 VMSTATE_UINT32(intr_status, OHCIState), 1961 VMSTATE_UINT32(intr, OHCIState), 1962 VMSTATE_UINT32(hcca, OHCIState), 1963 VMSTATE_UINT32(ctrl_head, OHCIState), 1964 VMSTATE_UINT32(ctrl_cur, OHCIState), 1965 VMSTATE_UINT32(bulk_head, OHCIState), 1966 VMSTATE_UINT32(bulk_cur, OHCIState), 1967 VMSTATE_UINT32(per_cur, OHCIState), 1968 VMSTATE_UINT32(done, OHCIState), 1969 VMSTATE_INT32(done_count, OHCIState), 1970 VMSTATE_UINT16(fsmps, OHCIState), 1971 VMSTATE_UINT8(fit, OHCIState), 1972 VMSTATE_UINT16(fi, OHCIState), 1973 VMSTATE_UINT8(frt, OHCIState), 1974 VMSTATE_UINT16(frame_number, OHCIState), 1975 VMSTATE_UINT16(padding, OHCIState), 1976 VMSTATE_UINT32(pstart, OHCIState), 1977 VMSTATE_UINT32(lst, OHCIState), 1978 VMSTATE_UINT32(rhdesc_a, OHCIState), 1979 VMSTATE_UINT32(rhdesc_b, OHCIState), 1980 VMSTATE_UINT32(rhstatus, OHCIState), 1981 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, 1982 vmstate_ohci_state_port, OHCIPort), 1983 VMSTATE_UINT32(hstatus, OHCIState), 1984 VMSTATE_UINT32(hmask, OHCIState), 1985 VMSTATE_UINT32(hreset, OHCIState), 1986 VMSTATE_UINT32(htest, OHCIState), 1987 VMSTATE_UINT32(old_ctl, OHCIState), 1988 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), 1989 VMSTATE_UINT32(async_td, OHCIState), 1990 VMSTATE_BOOL(async_complete, OHCIState), 1991 VMSTATE_END_OF_LIST() 1992 }, 1993 .subsections = (const VMStateDescription*[]) { 1994 &vmstate_ohci_eof_timer, 1995 NULL 1996 } 1997 }; 1998 1999 static Property ohci_sysbus_properties[] = { 2000 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), 2001 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 2002 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), 2003 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), 2004 DEFINE_PROP_END_OF_LIST(), 2005 }; 2006 2007 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 2008 { 2009 DeviceClass *dc = DEVICE_CLASS(klass); 2010 2011 dc->realize = ohci_realize_pxa; 2012 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2013 dc->desc = "OHCI USB Controller"; 2014 device_class_set_props(dc, ohci_sysbus_properties); 2015 dc->reset = usb_ohci_reset_sysbus; 2016 } 2017 2018 static const TypeInfo ohci_sysbus_info = { 2019 .name = TYPE_SYSBUS_OHCI, 2020 .parent = TYPE_SYS_BUS_DEVICE, 2021 .instance_size = sizeof(OHCISysBusState), 2022 .class_init = ohci_sysbus_class_init, 2023 }; 2024 2025 static void ohci_register_types(void) 2026 { 2027 type_register_static(&ohci_sysbus_info); 2028 } 2029 2030 type_init(ohci_register_types) 2031