1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o BIOS work to boot from USB storage 26 */ 27 28 #include "hw/hw.h" 29 #include "qemu/timer.h" 30 #include "hw/usb.h" 31 #include "hw/pci/pci.h" 32 #include "hw/sysbus.h" 33 #include "hw/qdev-dma.h" 34 #include "trace.h" 35 36 /* This causes frames to occur 1000x slower */ 37 //#define OHCI_TIME_WARP 1 38 39 /* Number of Downstream Ports on the root hub. */ 40 41 #define OHCI_MAX_PORTS 15 42 43 static int64_t usb_frame_time; 44 static int64_t usb_bit_time; 45 46 typedef struct OHCIPort { 47 USBPort port; 48 uint32_t ctrl; 49 } OHCIPort; 50 51 typedef struct { 52 USBBus bus; 53 qemu_irq irq; 54 MemoryRegion mem; 55 AddressSpace *as; 56 int num_ports; 57 const char *name; 58 59 QEMUTimer *eof_timer; 60 int64_t sof_time; 61 62 /* OHCI state */ 63 /* Control partition */ 64 uint32_t ctl, status; 65 uint32_t intr_status; 66 uint32_t intr; 67 68 /* memory pointer partition */ 69 uint32_t hcca; 70 uint32_t ctrl_head, ctrl_cur; 71 uint32_t bulk_head, bulk_cur; 72 uint32_t per_cur; 73 uint32_t done; 74 int32_t done_count; 75 76 /* Frame counter partition */ 77 uint16_t fsmps; 78 uint8_t fit; 79 uint16_t fi; 80 uint8_t frt; 81 uint16_t frame_number; 82 uint16_t padding; 83 uint32_t pstart; 84 uint32_t lst; 85 86 /* Root Hub partition */ 87 uint32_t rhdesc_a, rhdesc_b; 88 uint32_t rhstatus; 89 OHCIPort rhport[OHCI_MAX_PORTS]; 90 91 /* PXA27x Non-OHCI events */ 92 uint32_t hstatus; 93 uint32_t hmask; 94 uint32_t hreset; 95 uint32_t htest; 96 97 /* SM501 local memory offset */ 98 dma_addr_t localmem_base; 99 100 /* Active packets. */ 101 uint32_t old_ctl; 102 USBPacket usb_packet; 103 uint8_t usb_buf[8192]; 104 uint32_t async_td; 105 bool async_complete; 106 107 } OHCIState; 108 109 /* Host Controller Communications Area */ 110 struct ohci_hcca { 111 uint32_t intr[32]; 112 uint16_t frame, pad; 113 uint32_t done; 114 }; 115 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 116 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 117 118 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 119 #define ED_WBACK_SIZE 4 120 121 static void ohci_bus_stop(OHCIState *ohci); 122 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); 123 124 /* Bitfields for the first word of an Endpoint Desciptor. */ 125 #define OHCI_ED_FA_SHIFT 0 126 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 127 #define OHCI_ED_EN_SHIFT 7 128 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 129 #define OHCI_ED_D_SHIFT 11 130 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 131 #define OHCI_ED_S (1<<13) 132 #define OHCI_ED_K (1<<14) 133 #define OHCI_ED_F (1<<15) 134 #define OHCI_ED_MPS_SHIFT 16 135 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 136 137 /* Flags in the head field of an Endpoint Desciptor. */ 138 #define OHCI_ED_H 1 139 #define OHCI_ED_C 2 140 141 /* Bitfields for the first word of a Transfer Desciptor. */ 142 #define OHCI_TD_R (1<<18) 143 #define OHCI_TD_DP_SHIFT 19 144 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 145 #define OHCI_TD_DI_SHIFT 21 146 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 147 #define OHCI_TD_T0 (1<<24) 148 #define OHCI_TD_T1 (1<<25) 149 #define OHCI_TD_EC_SHIFT 26 150 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 151 #define OHCI_TD_CC_SHIFT 28 152 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 153 154 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 155 /* CC & DI - same as in the General Transfer Desciptor */ 156 #define OHCI_TD_SF_SHIFT 0 157 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 158 #define OHCI_TD_FC_SHIFT 24 159 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 160 161 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 162 #define OHCI_TD_PSW_CC_SHIFT 12 163 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 164 #define OHCI_TD_PSW_SIZE_SHIFT 0 165 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 166 167 #define OHCI_PAGE_MASK 0xfffff000 168 #define OHCI_OFFSET_MASK 0xfff 169 170 #define OHCI_DPTR_MASK 0xfffffff0 171 172 #define OHCI_BM(val, field) \ 173 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 174 175 #define OHCI_SET_BM(val, field, newval) do { \ 176 val &= ~OHCI_##field##_MASK; \ 177 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 178 } while(0) 179 180 /* endpoint descriptor */ 181 struct ohci_ed { 182 uint32_t flags; 183 uint32_t tail; 184 uint32_t head; 185 uint32_t next; 186 }; 187 188 /* General transfer descriptor */ 189 struct ohci_td { 190 uint32_t flags; 191 uint32_t cbp; 192 uint32_t next; 193 uint32_t be; 194 }; 195 196 /* Isochronous transfer descriptor */ 197 struct ohci_iso_td { 198 uint32_t flags; 199 uint32_t bp; 200 uint32_t next; 201 uint32_t be; 202 uint16_t offset[8]; 203 }; 204 205 #define USB_HZ 12000000 206 207 /* OHCI Local stuff */ 208 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 209 #define OHCI_CTL_PLE (1<<2) 210 #define OHCI_CTL_IE (1<<3) 211 #define OHCI_CTL_CLE (1<<4) 212 #define OHCI_CTL_BLE (1<<5) 213 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 214 #define OHCI_USB_RESET 0x00 215 #define OHCI_USB_RESUME 0x40 216 #define OHCI_USB_OPERATIONAL 0x80 217 #define OHCI_USB_SUSPEND 0xc0 218 #define OHCI_CTL_IR (1<<8) 219 #define OHCI_CTL_RWC (1<<9) 220 #define OHCI_CTL_RWE (1<<10) 221 222 #define OHCI_STATUS_HCR (1<<0) 223 #define OHCI_STATUS_CLF (1<<1) 224 #define OHCI_STATUS_BLF (1<<2) 225 #define OHCI_STATUS_OCR (1<<3) 226 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 227 228 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ 229 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ 230 #define OHCI_INTR_SF (1U<<2) /* Start of frame */ 231 #define OHCI_INTR_RD (1U<<3) /* Resume detect */ 232 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ 233 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ 234 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ 235 #define OHCI_INTR_OC (1U<<30) /* Ownership change */ 236 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ 237 238 #define OHCI_HCCA_SIZE 0x100 239 #define OHCI_HCCA_MASK 0xffffff00 240 241 #define OHCI_EDPTR_MASK 0xfffffff0 242 243 #define OHCI_FMI_FI 0x00003fff 244 #define OHCI_FMI_FSMPS 0xffff0000 245 #define OHCI_FMI_FIT 0x80000000 246 247 #define OHCI_FR_RT (1U<<31) 248 249 #define OHCI_LS_THRESH 0x628 250 251 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 252 #define OHCI_RHA_PSM (1<<8) 253 #define OHCI_RHA_NPS (1<<9) 254 #define OHCI_RHA_DT (1<<10) 255 #define OHCI_RHA_OCPM (1<<11) 256 #define OHCI_RHA_NOCP (1<<12) 257 #define OHCI_RHA_POTPGT_MASK 0xff000000 258 259 #define OHCI_RHS_LPS (1U<<0) 260 #define OHCI_RHS_OCI (1U<<1) 261 #define OHCI_RHS_DRWE (1U<<15) 262 #define OHCI_RHS_LPSC (1U<<16) 263 #define OHCI_RHS_OCIC (1U<<17) 264 #define OHCI_RHS_CRWE (1U<<31) 265 266 #define OHCI_PORT_CCS (1<<0) 267 #define OHCI_PORT_PES (1<<1) 268 #define OHCI_PORT_PSS (1<<2) 269 #define OHCI_PORT_POCI (1<<3) 270 #define OHCI_PORT_PRS (1<<4) 271 #define OHCI_PORT_PPS (1<<8) 272 #define OHCI_PORT_LSDA (1<<9) 273 #define OHCI_PORT_CSC (1<<16) 274 #define OHCI_PORT_PESC (1<<17) 275 #define OHCI_PORT_PSSC (1<<18) 276 #define OHCI_PORT_OCIC (1<<19) 277 #define OHCI_PORT_PRSC (1<<20) 278 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 279 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 280 281 #define OHCI_TD_DIR_SETUP 0x0 282 #define OHCI_TD_DIR_OUT 0x1 283 #define OHCI_TD_DIR_IN 0x2 284 #define OHCI_TD_DIR_RESERVED 0x3 285 286 #define OHCI_CC_NOERROR 0x0 287 #define OHCI_CC_CRC 0x1 288 #define OHCI_CC_BITSTUFFING 0x2 289 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 290 #define OHCI_CC_STALL 0x4 291 #define OHCI_CC_DEVICENOTRESPONDING 0x5 292 #define OHCI_CC_PIDCHECKFAILURE 0x6 293 #define OHCI_CC_UNDEXPETEDPID 0x7 294 #define OHCI_CC_DATAOVERRUN 0x8 295 #define OHCI_CC_DATAUNDERRUN 0x9 296 #define OHCI_CC_BUFFEROVERRUN 0xc 297 #define OHCI_CC_BUFFERUNDERRUN 0xd 298 299 #define OHCI_HRESET_FSBIR (1 << 0) 300 301 static void ohci_die(OHCIState *ohci); 302 303 /* Update IRQ levels */ 304 static inline void ohci_intr_update(OHCIState *ohci) 305 { 306 int level = 0; 307 308 if ((ohci->intr & OHCI_INTR_MIE) && 309 (ohci->intr_status & ohci->intr)) 310 level = 1; 311 312 qemu_set_irq(ohci->irq, level); 313 } 314 315 /* Set an interrupt */ 316 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 317 { 318 ohci->intr_status |= intr; 319 ohci_intr_update(ohci); 320 } 321 322 /* Attach or detach a device on a root hub port. */ 323 static void ohci_attach(USBPort *port1) 324 { 325 OHCIState *s = port1->opaque; 326 OHCIPort *port = &s->rhport[port1->index]; 327 uint32_t old_state = port->ctrl; 328 329 /* set connect status */ 330 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 331 332 /* update speed */ 333 if (port->port.dev->speed == USB_SPEED_LOW) { 334 port->ctrl |= OHCI_PORT_LSDA; 335 } else { 336 port->ctrl &= ~OHCI_PORT_LSDA; 337 } 338 339 /* notify of remote-wakeup */ 340 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 341 ohci_set_interrupt(s, OHCI_INTR_RD); 342 } 343 344 trace_usb_ohci_port_attach(port1->index); 345 346 if (old_state != port->ctrl) { 347 ohci_set_interrupt(s, OHCI_INTR_RHSC); 348 } 349 } 350 351 static void ohci_detach(USBPort *port1) 352 { 353 OHCIState *s = port1->opaque; 354 OHCIPort *port = &s->rhport[port1->index]; 355 uint32_t old_state = port->ctrl; 356 357 ohci_async_cancel_device(s, port1->dev); 358 359 /* set connect status */ 360 if (port->ctrl & OHCI_PORT_CCS) { 361 port->ctrl &= ~OHCI_PORT_CCS; 362 port->ctrl |= OHCI_PORT_CSC; 363 } 364 /* disable port */ 365 if (port->ctrl & OHCI_PORT_PES) { 366 port->ctrl &= ~OHCI_PORT_PES; 367 port->ctrl |= OHCI_PORT_PESC; 368 } 369 trace_usb_ohci_port_detach(port1->index); 370 371 if (old_state != port->ctrl) { 372 ohci_set_interrupt(s, OHCI_INTR_RHSC); 373 } 374 } 375 376 static void ohci_wakeup(USBPort *port1) 377 { 378 OHCIState *s = port1->opaque; 379 OHCIPort *port = &s->rhport[port1->index]; 380 uint32_t intr = 0; 381 if (port->ctrl & OHCI_PORT_PSS) { 382 trace_usb_ohci_port_wakeup(port1->index); 383 port->ctrl |= OHCI_PORT_PSSC; 384 port->ctrl &= ~OHCI_PORT_PSS; 385 intr = OHCI_INTR_RHSC; 386 } 387 /* Note that the controller can be suspended even if this port is not */ 388 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 389 trace_usb_ohci_remote_wakeup(s->name); 390 /* This is the one state transition the controller can do by itself */ 391 s->ctl &= ~OHCI_CTL_HCFS; 392 s->ctl |= OHCI_USB_RESUME; 393 /* In suspend mode only ResumeDetected is possible, not RHSC: 394 * see the OHCI spec 5.1.2.3. 395 */ 396 intr = OHCI_INTR_RD; 397 } 398 ohci_set_interrupt(s, intr); 399 } 400 401 static void ohci_child_detach(USBPort *port1, USBDevice *child) 402 { 403 OHCIState *s = port1->opaque; 404 405 ohci_async_cancel_device(s, child); 406 } 407 408 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 409 { 410 USBDevice *dev; 411 int i; 412 413 for (i = 0; i < ohci->num_ports; i++) { 414 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 415 continue; 416 } 417 dev = usb_find_device(&ohci->rhport[i].port, addr); 418 if (dev != NULL) { 419 return dev; 420 } 421 } 422 return NULL; 423 } 424 425 static void ohci_stop_endpoints(OHCIState *ohci) 426 { 427 USBDevice *dev; 428 int i, j; 429 430 for (i = 0; i < ohci->num_ports; i++) { 431 dev = ohci->rhport[i].port.dev; 432 if (dev && dev->attached) { 433 usb_device_ep_stopped(dev, &dev->ep_ctl); 434 for (j = 0; j < USB_MAX_ENDPOINTS; j++) { 435 usb_device_ep_stopped(dev, &dev->ep_in[j]); 436 usb_device_ep_stopped(dev, &dev->ep_out[j]); 437 } 438 } 439 } 440 } 441 442 /* Reset the controller */ 443 static void ohci_reset(void *opaque) 444 { 445 OHCIState *ohci = opaque; 446 OHCIPort *port; 447 int i; 448 449 ohci_bus_stop(ohci); 450 ohci->ctl = 0; 451 ohci->old_ctl = 0; 452 ohci->status = 0; 453 ohci->intr_status = 0; 454 ohci->intr = OHCI_INTR_MIE; 455 456 ohci->hcca = 0; 457 ohci->ctrl_head = ohci->ctrl_cur = 0; 458 ohci->bulk_head = ohci->bulk_cur = 0; 459 ohci->per_cur = 0; 460 ohci->done = 0; 461 ohci->done_count = 7; 462 463 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 464 * I took the value linux sets ... 465 */ 466 ohci->fsmps = 0x2778; 467 ohci->fi = 0x2edf; 468 ohci->fit = 0; 469 ohci->frt = 0; 470 ohci->frame_number = 0; 471 ohci->pstart = 0; 472 ohci->lst = OHCI_LS_THRESH; 473 474 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 475 ohci->rhdesc_b = 0x0; /* Impl. specific */ 476 ohci->rhstatus = 0; 477 478 for (i = 0; i < ohci->num_ports; i++) 479 { 480 port = &ohci->rhport[i]; 481 port->ctrl = 0; 482 if (port->port.dev && port->port.dev->attached) { 483 usb_port_reset(&port->port); 484 } 485 } 486 if (ohci->async_td) { 487 usb_cancel_packet(&ohci->usb_packet); 488 ohci->async_td = 0; 489 } 490 ohci_stop_endpoints(ohci); 491 trace_usb_ohci_reset(ohci->name); 492 } 493 494 /* Get an array of dwords from main memory */ 495 static inline int get_dwords(OHCIState *ohci, 496 dma_addr_t addr, uint32_t *buf, int num) 497 { 498 int i; 499 500 addr += ohci->localmem_base; 501 502 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 503 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 504 return -1; 505 } 506 *buf = le32_to_cpu(*buf); 507 } 508 509 return 0; 510 } 511 512 /* Put an array of dwords in to main memory */ 513 static inline int put_dwords(OHCIState *ohci, 514 dma_addr_t addr, uint32_t *buf, int num) 515 { 516 int i; 517 518 addr += ohci->localmem_base; 519 520 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 521 uint32_t tmp = cpu_to_le32(*buf); 522 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 523 return -1; 524 } 525 } 526 527 return 0; 528 } 529 530 /* Get an array of words from main memory */ 531 static inline int get_words(OHCIState *ohci, 532 dma_addr_t addr, uint16_t *buf, int num) 533 { 534 int i; 535 536 addr += ohci->localmem_base; 537 538 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 539 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 540 return -1; 541 } 542 *buf = le16_to_cpu(*buf); 543 } 544 545 return 0; 546 } 547 548 /* Put an array of words in to main memory */ 549 static inline int put_words(OHCIState *ohci, 550 dma_addr_t addr, uint16_t *buf, int num) 551 { 552 int i; 553 554 addr += ohci->localmem_base; 555 556 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 557 uint16_t tmp = cpu_to_le16(*buf); 558 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 559 return -1; 560 } 561 } 562 563 return 0; 564 } 565 566 static inline int ohci_read_ed(OHCIState *ohci, 567 dma_addr_t addr, struct ohci_ed *ed) 568 { 569 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 570 } 571 572 static inline int ohci_read_td(OHCIState *ohci, 573 dma_addr_t addr, struct ohci_td *td) 574 { 575 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 576 } 577 578 static inline int ohci_read_iso_td(OHCIState *ohci, 579 dma_addr_t addr, struct ohci_iso_td *td) 580 { 581 return get_dwords(ohci, addr, (uint32_t *)td, 4) || 582 get_words(ohci, addr + 16, td->offset, 8); 583 } 584 585 static inline int ohci_read_hcca(OHCIState *ohci, 586 dma_addr_t addr, struct ohci_hcca *hcca) 587 { 588 return dma_memory_read(ohci->as, addr + ohci->localmem_base, 589 hcca, sizeof(*hcca)); 590 } 591 592 static inline int ohci_put_ed(OHCIState *ohci, 593 dma_addr_t addr, struct ohci_ed *ed) 594 { 595 /* ed->tail is under control of the HCD. 596 * Since just ed->head is changed by HC, just write back this 597 */ 598 599 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 600 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 601 ED_WBACK_SIZE >> 2); 602 } 603 604 static inline int ohci_put_td(OHCIState *ohci, 605 dma_addr_t addr, struct ohci_td *td) 606 { 607 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 608 } 609 610 static inline int ohci_put_iso_td(OHCIState *ohci, 611 dma_addr_t addr, struct ohci_iso_td *td) 612 { 613 return put_dwords(ohci, addr, (uint32_t *)td, 4) || 614 put_words(ohci, addr + 16, td->offset, 8); 615 } 616 617 static inline int ohci_put_hcca(OHCIState *ohci, 618 dma_addr_t addr, struct ohci_hcca *hcca) 619 { 620 return dma_memory_write(ohci->as, 621 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 622 (char *)hcca + HCCA_WRITEBACK_OFFSET, 623 HCCA_WRITEBACK_SIZE); 624 } 625 626 /* Read/Write the contents of a TD from/to main memory. */ 627 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 628 uint8_t *buf, int len, DMADirection dir) 629 { 630 dma_addr_t ptr, n; 631 632 ptr = td->cbp; 633 n = 0x1000 - (ptr & 0xfff); 634 if (n > len) 635 n = len; 636 637 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 638 return -1; 639 } 640 if (n == len) { 641 return 0; 642 } 643 ptr = td->be & ~0xfffu; 644 buf += n; 645 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 646 len - n, dir)) { 647 return -1; 648 } 649 return 0; 650 } 651 652 /* Read/Write the contents of an ISO TD from/to main memory. */ 653 static int ohci_copy_iso_td(OHCIState *ohci, 654 uint32_t start_addr, uint32_t end_addr, 655 uint8_t *buf, int len, DMADirection dir) 656 { 657 dma_addr_t ptr, n; 658 659 ptr = start_addr; 660 n = 0x1000 - (ptr & 0xfff); 661 if (n > len) 662 n = len; 663 664 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 665 return -1; 666 } 667 if (n == len) { 668 return 0; 669 } 670 ptr = end_addr & ~0xfffu; 671 buf += n; 672 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 673 len - n, dir)) { 674 return -1; 675 } 676 return 0; 677 } 678 679 static void ohci_process_lists(OHCIState *ohci, int completion); 680 681 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 682 { 683 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 684 685 trace_usb_ohci_async_complete(); 686 ohci->async_complete = true; 687 ohci_process_lists(ohci, 1); 688 } 689 690 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 691 692 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, 693 int completion) 694 { 695 int dir; 696 size_t len = 0; 697 const char *str = NULL; 698 int pid; 699 int ret; 700 int i; 701 USBDevice *dev; 702 USBEndpoint *ep; 703 struct ohci_iso_td iso_td; 704 uint32_t addr; 705 uint16_t starting_frame; 706 int16_t relative_frame_number; 707 int frame_count; 708 uint32_t start_offset, next_offset, end_offset = 0; 709 uint32_t start_addr, end_addr; 710 711 addr = ed->head & OHCI_DPTR_MASK; 712 713 if (ohci_read_iso_td(ohci, addr, &iso_td)) { 714 trace_usb_ohci_iso_td_read_failed(addr); 715 ohci_die(ohci); 716 return 0; 717 } 718 719 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 720 frame_count = OHCI_BM(iso_td.flags, TD_FC); 721 relative_frame_number = USUB(ohci->frame_number, starting_frame); 722 723 trace_usb_ohci_iso_td_head( 724 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 725 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 726 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], 727 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], 728 ohci->frame_number, starting_frame, 729 frame_count, relative_frame_number, 730 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); 731 732 if (relative_frame_number < 0) { 733 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); 734 return 1; 735 } else if (relative_frame_number > frame_count) { 736 /* ISO TD expired - retire the TD to the Done Queue and continue with 737 the next ISO TD of the same ED */ 738 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, 739 frame_count); 740 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 741 ed->head &= ~OHCI_DPTR_MASK; 742 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 743 iso_td.next = ohci->done; 744 ohci->done = addr; 745 i = OHCI_BM(iso_td.flags, TD_DI); 746 if (i < ohci->done_count) 747 ohci->done_count = i; 748 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 749 ohci_die(ohci); 750 return 1; 751 } 752 return 0; 753 } 754 755 dir = OHCI_BM(ed->flags, ED_D); 756 switch (dir) { 757 case OHCI_TD_DIR_IN: 758 str = "in"; 759 pid = USB_TOKEN_IN; 760 break; 761 case OHCI_TD_DIR_OUT: 762 str = "out"; 763 pid = USB_TOKEN_OUT; 764 break; 765 case OHCI_TD_DIR_SETUP: 766 str = "setup"; 767 pid = USB_TOKEN_SETUP; 768 break; 769 default: 770 trace_usb_ohci_iso_td_bad_direction(dir); 771 return 1; 772 } 773 774 if (!iso_td.bp || !iso_td.be) { 775 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); 776 return 1; 777 } 778 779 start_offset = iso_td.offset[relative_frame_number]; 780 next_offset = iso_td.offset[relative_frame_number + 1]; 781 782 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 783 ((relative_frame_number < frame_count) && 784 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 785 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); 786 return 1; 787 } 788 789 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 790 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); 791 return 1; 792 } 793 794 if ((start_offset & 0x1000) == 0) { 795 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 796 (start_offset & OHCI_OFFSET_MASK); 797 } else { 798 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 799 (start_offset & OHCI_OFFSET_MASK); 800 } 801 802 if (relative_frame_number < frame_count) { 803 end_offset = next_offset - 1; 804 if ((end_offset & 0x1000) == 0) { 805 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 806 (end_offset & OHCI_OFFSET_MASK); 807 } else { 808 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 809 (end_offset & OHCI_OFFSET_MASK); 810 } 811 } else { 812 /* Last packet in the ISO TD */ 813 end_addr = iso_td.be; 814 } 815 816 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 817 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 818 - (start_addr & OHCI_OFFSET_MASK); 819 } else { 820 len = end_addr - start_addr + 1; 821 } 822 823 if (len && dir != OHCI_TD_DIR_IN) { 824 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 825 DMA_DIRECTION_TO_DEVICE)) { 826 ohci_die(ohci); 827 return 1; 828 } 829 } 830 831 if (!completion) { 832 bool int_req = relative_frame_number == frame_count && 833 OHCI_BM(iso_td.flags, TD_DI) == 0; 834 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 835 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 836 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); 837 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); 838 usb_handle_packet(dev, &ohci->usb_packet); 839 if (ohci->usb_packet.status == USB_RET_ASYNC) { 840 usb_device_flush_ep_queue(dev, ep); 841 return 1; 842 } 843 } 844 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 845 ret = ohci->usb_packet.actual_length; 846 } else { 847 ret = ohci->usb_packet.status; 848 } 849 850 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, 851 str, len, ret); 852 853 /* Writeback */ 854 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 855 /* IN transfer succeeded */ 856 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 857 DMA_DIRECTION_FROM_DEVICE)) { 858 ohci_die(ohci); 859 return 1; 860 } 861 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 862 OHCI_CC_NOERROR); 863 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 864 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 865 /* OUT transfer succeeded */ 866 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 867 OHCI_CC_NOERROR); 868 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 869 } else { 870 if (ret > (ssize_t) len) { 871 trace_usb_ohci_iso_td_data_overrun(ret, len); 872 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 873 OHCI_CC_DATAOVERRUN); 874 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 875 len); 876 } else if (ret >= 0) { 877 trace_usb_ohci_iso_td_data_underrun(ret); 878 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 879 OHCI_CC_DATAUNDERRUN); 880 } else { 881 switch (ret) { 882 case USB_RET_IOERROR: 883 case USB_RET_NODEV: 884 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 885 OHCI_CC_DEVICENOTRESPONDING); 886 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 887 0); 888 break; 889 case USB_RET_NAK: 890 case USB_RET_STALL: 891 trace_usb_ohci_iso_td_nak(ret); 892 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 893 OHCI_CC_STALL); 894 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 895 0); 896 break; 897 default: 898 trace_usb_ohci_iso_td_bad_response(ret); 899 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 900 OHCI_CC_UNDEXPETEDPID); 901 break; 902 } 903 } 904 } 905 906 if (relative_frame_number == frame_count) { 907 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 908 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 909 ed->head &= ~OHCI_DPTR_MASK; 910 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 911 iso_td.next = ohci->done; 912 ohci->done = addr; 913 i = OHCI_BM(iso_td.flags, TD_DI); 914 if (i < ohci->done_count) 915 ohci->done_count = i; 916 } 917 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 918 ohci_die(ohci); 919 } 920 return 1; 921 } 922 923 #ifdef trace_event_get_state 924 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 925 { 926 bool print16 = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_SHORT); 927 bool printall = !!trace_event_get_state(TRACE_USB_OHCI_TD_PKT_FULL); 928 const int width = 16; 929 int i; 930 char tmp[3 * width + 1]; 931 char *p = tmp; 932 933 if (!printall && !print16) { 934 return; 935 } 936 937 for (i = 0; ; i++) { 938 if (i && (!(i % width) || (i == len))) { 939 if (!printall) { 940 trace_usb_ohci_td_pkt_short(msg, tmp); 941 break; 942 } 943 trace_usb_ohci_td_pkt_full(msg, tmp); 944 p = tmp; 945 *p = 0; 946 } 947 if (i == len) { 948 break; 949 } 950 951 p += sprintf(p, " %.2x", buf[i]); 952 } 953 } 954 #else 955 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 956 { 957 } 958 #endif 959 960 /* Service a transport descriptor. 961 Returns nonzero to terminate processing of this endpoint. */ 962 963 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 964 { 965 int dir; 966 size_t len = 0, pktlen = 0; 967 const char *str = NULL; 968 int pid; 969 int ret; 970 int i; 971 USBDevice *dev; 972 USBEndpoint *ep; 973 struct ohci_td td; 974 uint32_t addr; 975 int flag_r; 976 int completion; 977 978 addr = ed->head & OHCI_DPTR_MASK; 979 /* See if this TD has already been submitted to the device. */ 980 completion = (addr == ohci->async_td); 981 if (completion && !ohci->async_complete) { 982 trace_usb_ohci_td_skip_async(); 983 return 1; 984 } 985 if (ohci_read_td(ohci, addr, &td)) { 986 trace_usb_ohci_td_read_error(addr); 987 ohci_die(ohci); 988 return 0; 989 } 990 991 dir = OHCI_BM(ed->flags, ED_D); 992 switch (dir) { 993 case OHCI_TD_DIR_OUT: 994 case OHCI_TD_DIR_IN: 995 /* Same value. */ 996 break; 997 default: 998 dir = OHCI_BM(td.flags, TD_DP); 999 break; 1000 } 1001 1002 switch (dir) { 1003 case OHCI_TD_DIR_IN: 1004 str = "in"; 1005 pid = USB_TOKEN_IN; 1006 break; 1007 case OHCI_TD_DIR_OUT: 1008 str = "out"; 1009 pid = USB_TOKEN_OUT; 1010 break; 1011 case OHCI_TD_DIR_SETUP: 1012 str = "setup"; 1013 pid = USB_TOKEN_SETUP; 1014 break; 1015 default: 1016 trace_usb_ohci_td_bad_direction(dir); 1017 return 1; 1018 } 1019 if (td.cbp && td.be) { 1020 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 1021 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 1022 } else { 1023 len = (td.be - td.cbp) + 1; 1024 } 1025 1026 pktlen = len; 1027 if (len && dir != OHCI_TD_DIR_IN) { 1028 /* The endpoint may not allow us to transfer it all now */ 1029 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 1030 if (pktlen > len) { 1031 pktlen = len; 1032 } 1033 if (!completion) { 1034 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 1035 DMA_DIRECTION_TO_DEVICE)) { 1036 ohci_die(ohci); 1037 } 1038 } 1039 } 1040 } 1041 1042 flag_r = (td.flags & OHCI_TD_R) != 0; 1043 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, 1044 flag_r, td.cbp, td.be); 1045 ohci_td_pkt("OUT", ohci->usb_buf, pktlen); 1046 1047 if (completion) { 1048 ohci->async_td = 0; 1049 ohci->async_complete = false; 1050 } else { 1051 if (ohci->async_td) { 1052 /* ??? The hardware should allow one active packet per 1053 endpoint. We only allow one active packet per controller. 1054 This should be sufficient as long as devices respond in a 1055 timely manner. 1056 */ 1057 trace_usb_ohci_td_too_many_pending(); 1058 return 1; 1059 } 1060 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 1061 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 1062 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, 1063 OHCI_BM(td.flags, TD_DI) == 0); 1064 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 1065 usb_handle_packet(dev, &ohci->usb_packet); 1066 trace_usb_ohci_td_packet_status(ohci->usb_packet.status); 1067 1068 if (ohci->usb_packet.status == USB_RET_ASYNC) { 1069 usb_device_flush_ep_queue(dev, ep); 1070 ohci->async_td = addr; 1071 return 1; 1072 } 1073 } 1074 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 1075 ret = ohci->usb_packet.actual_length; 1076 } else { 1077 ret = ohci->usb_packet.status; 1078 } 1079 1080 if (ret >= 0) { 1081 if (dir == OHCI_TD_DIR_IN) { 1082 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1083 DMA_DIRECTION_FROM_DEVICE)) { 1084 ohci_die(ohci); 1085 } 1086 ohci_td_pkt("IN", ohci->usb_buf, pktlen); 1087 } else { 1088 ret = pktlen; 1089 } 1090 } 1091 1092 /* Writeback */ 1093 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 1094 /* Transmission succeeded. */ 1095 if (ret == len) { 1096 td.cbp = 0; 1097 } else { 1098 if ((td.cbp & 0xfff) + ret > 0xfff) { 1099 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 1100 } else { 1101 td.cbp += ret; 1102 } 1103 } 1104 td.flags |= OHCI_TD_T1; 1105 td.flags ^= OHCI_TD_T0; 1106 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1107 OHCI_SET_BM(td.flags, TD_EC, 0); 1108 1109 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1110 /* Partial packet transfer: TD not ready to retire yet */ 1111 goto exit_no_retire; 1112 } 1113 1114 /* Setting ED_C is part of the TD retirement process */ 1115 ed->head &= ~OHCI_ED_C; 1116 if (td.flags & OHCI_TD_T0) 1117 ed->head |= OHCI_ED_C; 1118 } else { 1119 if (ret >= 0) { 1120 trace_usb_ohci_td_underrun(); 1121 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1122 } else { 1123 switch (ret) { 1124 case USB_RET_IOERROR: 1125 case USB_RET_NODEV: 1126 trace_usb_ohci_td_dev_error(); 1127 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1128 break; 1129 case USB_RET_NAK: 1130 trace_usb_ohci_td_nak(); 1131 return 1; 1132 case USB_RET_STALL: 1133 trace_usb_ohci_td_stall(); 1134 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1135 break; 1136 case USB_RET_BABBLE: 1137 trace_usb_ohci_td_babble(); 1138 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1139 break; 1140 default: 1141 trace_usb_ohci_td_bad_device_response(ret); 1142 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1143 OHCI_SET_BM(td.flags, TD_EC, 3); 1144 break; 1145 } 1146 } 1147 ed->head |= OHCI_ED_H; 1148 } 1149 1150 /* Retire this TD */ 1151 ed->head &= ~OHCI_DPTR_MASK; 1152 ed->head |= td.next & OHCI_DPTR_MASK; 1153 td.next = ohci->done; 1154 ohci->done = addr; 1155 i = OHCI_BM(td.flags, TD_DI); 1156 if (i < ohci->done_count) 1157 ohci->done_count = i; 1158 exit_no_retire: 1159 if (ohci_put_td(ohci, addr, &td)) { 1160 ohci_die(ohci); 1161 return 1; 1162 } 1163 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1164 } 1165 1166 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1167 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) 1168 { 1169 struct ohci_ed ed; 1170 uint32_t next_ed; 1171 uint32_t cur; 1172 int active; 1173 1174 active = 0; 1175 1176 if (head == 0) 1177 return 0; 1178 1179 for (cur = head; cur; cur = next_ed) { 1180 if (ohci_read_ed(ohci, cur, &ed)) { 1181 trace_usb_ohci_ed_read_error(cur); 1182 ohci_die(ohci); 1183 return 0; 1184 } 1185 1186 next_ed = ed.next & OHCI_DPTR_MASK; 1187 1188 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1189 uint32_t addr; 1190 /* Cancel pending packets for ED that have been paused. */ 1191 addr = ed.head & OHCI_DPTR_MASK; 1192 if (ohci->async_td && addr == ohci->async_td) { 1193 usb_cancel_packet(&ohci->usb_packet); 1194 ohci->async_td = 0; 1195 usb_device_ep_stopped(ohci->usb_packet.ep->dev, 1196 ohci->usb_packet.ep); 1197 } 1198 continue; 1199 } 1200 1201 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1202 trace_usb_ohci_ed_pkt(cur, 1203 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1204 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1205 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1206 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0, 1207 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1208 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1209 1210 active = 1; 1211 1212 if ((ed.flags & OHCI_ED_F) == 0) { 1213 if (ohci_service_td(ohci, &ed)) 1214 break; 1215 } else { 1216 /* Handle isochronous endpoints */ 1217 if (ohci_service_iso_td(ohci, &ed, completion)) 1218 break; 1219 } 1220 } 1221 1222 if (ohci_put_ed(ohci, cur, &ed)) { 1223 ohci_die(ohci); 1224 return 0; 1225 } 1226 } 1227 1228 return active; 1229 } 1230 1231 /* Generate a SOF event, and set a timer for EOF */ 1232 static void ohci_sof(OHCIState *ohci) 1233 { 1234 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1235 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1236 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1237 } 1238 1239 /* Process Control and Bulk lists. */ 1240 static void ohci_process_lists(OHCIState *ohci, int completion) 1241 { 1242 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1243 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1244 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); 1245 } 1246 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { 1247 ohci->ctrl_cur = 0; 1248 ohci->status &= ~OHCI_STATUS_CLF; 1249 } 1250 } 1251 1252 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1253 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { 1254 ohci->bulk_cur = 0; 1255 ohci->status &= ~OHCI_STATUS_BLF; 1256 } 1257 } 1258 } 1259 1260 /* Do frame processing on frame boundary */ 1261 static void ohci_frame_boundary(void *opaque) 1262 { 1263 OHCIState *ohci = opaque; 1264 struct ohci_hcca hcca; 1265 1266 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { 1267 trace_usb_ohci_hcca_read_error(ohci->hcca); 1268 ohci_die(ohci); 1269 return; 1270 } 1271 1272 /* Process all the lists at the end of the frame */ 1273 if (ohci->ctl & OHCI_CTL_PLE) { 1274 int n; 1275 1276 n = ohci->frame_number & 0x1f; 1277 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); 1278 } 1279 1280 /* Cancel all pending packets if either of the lists has been disabled. */ 1281 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1282 if (ohci->async_td) { 1283 usb_cancel_packet(&ohci->usb_packet); 1284 ohci->async_td = 0; 1285 } 1286 ohci_stop_endpoints(ohci); 1287 } 1288 ohci->old_ctl = ohci->ctl; 1289 ohci_process_lists(ohci, 0); 1290 1291 /* Stop if UnrecoverableError happened or ohci_sof will crash */ 1292 if (ohci->intr_status & OHCI_INTR_UE) { 1293 return; 1294 } 1295 1296 /* Frame boundary, so do EOF stuf here */ 1297 ohci->frt = ohci->fit; 1298 1299 /* Increment frame number and take care of endianness. */ 1300 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1301 hcca.frame = cpu_to_le16(ohci->frame_number); 1302 1303 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1304 if (!ohci->done) 1305 abort(); 1306 if (ohci->intr & ohci->intr_status) 1307 ohci->done |= 1; 1308 hcca.done = cpu_to_le32(ohci->done); 1309 ohci->done = 0; 1310 ohci->done_count = 7; 1311 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1312 } 1313 1314 if (ohci->done_count != 7 && ohci->done_count != 0) 1315 ohci->done_count--; 1316 1317 /* Do SOF stuff here */ 1318 ohci_sof(ohci); 1319 1320 /* Writeback HCCA */ 1321 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { 1322 ohci_die(ohci); 1323 } 1324 } 1325 1326 /* Start sending SOF tokens across the USB bus, lists are processed in 1327 * next frame 1328 */ 1329 static int ohci_bus_start(OHCIState *ohci) 1330 { 1331 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1332 ohci_frame_boundary, 1333 ohci); 1334 1335 if (ohci->eof_timer == NULL) { 1336 trace_usb_ohci_bus_eof_timer_failed(ohci->name); 1337 ohci_die(ohci); 1338 return 0; 1339 } 1340 1341 trace_usb_ohci_start(ohci->name); 1342 1343 ohci_sof(ohci); 1344 1345 return 1; 1346 } 1347 1348 /* Stop sending SOF tokens on the bus */ 1349 static void ohci_bus_stop(OHCIState *ohci) 1350 { 1351 trace_usb_ohci_stop(ohci->name); 1352 if (ohci->eof_timer) { 1353 timer_del(ohci->eof_timer); 1354 timer_free(ohci->eof_timer); 1355 } 1356 ohci->eof_timer = NULL; 1357 } 1358 1359 /* Sets a flag in a port status register but only set it if the port is 1360 * connected, if not set ConnectStatusChange flag. If flag is enabled 1361 * return 1. 1362 */ 1363 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1364 { 1365 int ret = 1; 1366 1367 /* writing a 0 has no effect */ 1368 if (val == 0) 1369 return 0; 1370 1371 /* If CurrentConnectStatus is cleared we set 1372 * ConnectStatusChange 1373 */ 1374 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1375 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1376 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1377 /* TODO: CSC is a wakeup event */ 1378 } 1379 return 0; 1380 } 1381 1382 if (ohci->rhport[i].ctrl & val) 1383 ret = 0; 1384 1385 /* set the bit */ 1386 ohci->rhport[i].ctrl |= val; 1387 1388 return ret; 1389 } 1390 1391 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1392 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1393 { 1394 val &= OHCI_FMI_FI; 1395 1396 if (val != ohci->fi) { 1397 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); 1398 } 1399 1400 ohci->fi = val; 1401 } 1402 1403 static void ohci_port_power(OHCIState *ohci, int i, int p) 1404 { 1405 if (p) { 1406 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1407 } else { 1408 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1409 OHCI_PORT_CCS| 1410 OHCI_PORT_PSS| 1411 OHCI_PORT_PRS); 1412 } 1413 } 1414 1415 /* Set HcControlRegister */ 1416 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1417 { 1418 uint32_t old_state; 1419 uint32_t new_state; 1420 1421 old_state = ohci->ctl & OHCI_CTL_HCFS; 1422 ohci->ctl = val; 1423 new_state = ohci->ctl & OHCI_CTL_HCFS; 1424 1425 /* no state change */ 1426 if (old_state == new_state) 1427 return; 1428 1429 trace_usb_ohci_set_ctl(ohci->name, new_state); 1430 switch (new_state) { 1431 case OHCI_USB_OPERATIONAL: 1432 ohci_bus_start(ohci); 1433 break; 1434 case OHCI_USB_SUSPEND: 1435 ohci_bus_stop(ohci); 1436 break; 1437 case OHCI_USB_RESUME: 1438 trace_usb_ohci_resume(ohci->name); 1439 break; 1440 case OHCI_USB_RESET: 1441 ohci_reset(ohci); 1442 break; 1443 } 1444 } 1445 1446 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1447 { 1448 uint16_t fr; 1449 int64_t tks; 1450 1451 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1452 return (ohci->frt << 31); 1453 1454 /* Being in USB operational state guarnatees sof_time was 1455 * set already. 1456 */ 1457 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; 1458 1459 /* avoid muldiv if possible */ 1460 if (tks >= usb_frame_time) 1461 return (ohci->frt << 31); 1462 1463 tks = muldiv64(1, tks, usb_bit_time); 1464 fr = (uint16_t)(ohci->fi - tks); 1465 1466 return (ohci->frt << 31) | fr; 1467 } 1468 1469 1470 /* Set root hub status */ 1471 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1472 { 1473 uint32_t old_state; 1474 1475 old_state = ohci->rhstatus; 1476 1477 /* write 1 to clear OCIC */ 1478 if (val & OHCI_RHS_OCIC) 1479 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1480 1481 if (val & OHCI_RHS_LPS) { 1482 int i; 1483 1484 for (i = 0; i < ohci->num_ports; i++) 1485 ohci_port_power(ohci, i, 0); 1486 trace_usb_ohci_hub_power_down(); 1487 } 1488 1489 if (val & OHCI_RHS_LPSC) { 1490 int i; 1491 1492 for (i = 0; i < ohci->num_ports; i++) 1493 ohci_port_power(ohci, i, 1); 1494 trace_usb_ohci_hub_power_up(); 1495 } 1496 1497 if (val & OHCI_RHS_DRWE) 1498 ohci->rhstatus |= OHCI_RHS_DRWE; 1499 1500 if (val & OHCI_RHS_CRWE) 1501 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1502 1503 if (old_state != ohci->rhstatus) 1504 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1505 } 1506 1507 /* Set root hub port status */ 1508 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1509 { 1510 uint32_t old_state; 1511 OHCIPort *port; 1512 1513 port = &ohci->rhport[portnum]; 1514 old_state = port->ctrl; 1515 1516 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1517 if (val & OHCI_PORT_WTC) 1518 port->ctrl &= ~(val & OHCI_PORT_WTC); 1519 1520 if (val & OHCI_PORT_CCS) 1521 port->ctrl &= ~OHCI_PORT_PES; 1522 1523 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1524 1525 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1526 trace_usb_ohci_port_suspend(portnum); 1527 } 1528 1529 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1530 trace_usb_ohci_port_reset(portnum); 1531 usb_device_reset(port->port.dev); 1532 port->ctrl &= ~OHCI_PORT_PRS; 1533 /* ??? Should this also set OHCI_PORT_PESC. */ 1534 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1535 } 1536 1537 /* Invert order here to ensure in ambiguous case, device is 1538 * powered up... 1539 */ 1540 if (val & OHCI_PORT_LSDA) 1541 ohci_port_power(ohci, portnum, 0); 1542 if (val & OHCI_PORT_PPS) 1543 ohci_port_power(ohci, portnum, 1); 1544 1545 if (old_state != port->ctrl) 1546 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1547 } 1548 1549 static uint64_t ohci_mem_read(void *opaque, 1550 hwaddr addr, 1551 unsigned size) 1552 { 1553 OHCIState *ohci = opaque; 1554 uint32_t retval; 1555 1556 /* Only aligned reads are allowed on OHCI */ 1557 if (addr & 3) { 1558 trace_usb_ohci_mem_read_unaligned(addr); 1559 return 0xffffffff; 1560 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1561 /* HcRhPortStatus */ 1562 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1563 } else { 1564 switch (addr >> 2) { 1565 case 0: /* HcRevision */ 1566 retval = 0x10; 1567 break; 1568 1569 case 1: /* HcControl */ 1570 retval = ohci->ctl; 1571 break; 1572 1573 case 2: /* HcCommandStatus */ 1574 retval = ohci->status; 1575 break; 1576 1577 case 3: /* HcInterruptStatus */ 1578 retval = ohci->intr_status; 1579 break; 1580 1581 case 4: /* HcInterruptEnable */ 1582 case 5: /* HcInterruptDisable */ 1583 retval = ohci->intr; 1584 break; 1585 1586 case 6: /* HcHCCA */ 1587 retval = ohci->hcca; 1588 break; 1589 1590 case 7: /* HcPeriodCurrentED */ 1591 retval = ohci->per_cur; 1592 break; 1593 1594 case 8: /* HcControlHeadED */ 1595 retval = ohci->ctrl_head; 1596 break; 1597 1598 case 9: /* HcControlCurrentED */ 1599 retval = ohci->ctrl_cur; 1600 break; 1601 1602 case 10: /* HcBulkHeadED */ 1603 retval = ohci->bulk_head; 1604 break; 1605 1606 case 11: /* HcBulkCurrentED */ 1607 retval = ohci->bulk_cur; 1608 break; 1609 1610 case 12: /* HcDoneHead */ 1611 retval = ohci->done; 1612 break; 1613 1614 case 13: /* HcFmInterretval */ 1615 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1616 break; 1617 1618 case 14: /* HcFmRemaining */ 1619 retval = ohci_get_frame_remaining(ohci); 1620 break; 1621 1622 case 15: /* HcFmNumber */ 1623 retval = ohci->frame_number; 1624 break; 1625 1626 case 16: /* HcPeriodicStart */ 1627 retval = ohci->pstart; 1628 break; 1629 1630 case 17: /* HcLSThreshold */ 1631 retval = ohci->lst; 1632 break; 1633 1634 case 18: /* HcRhDescriptorA */ 1635 retval = ohci->rhdesc_a; 1636 break; 1637 1638 case 19: /* HcRhDescriptorB */ 1639 retval = ohci->rhdesc_b; 1640 break; 1641 1642 case 20: /* HcRhStatus */ 1643 retval = ohci->rhstatus; 1644 break; 1645 1646 /* PXA27x specific registers */ 1647 case 24: /* HcStatus */ 1648 retval = ohci->hstatus & ohci->hmask; 1649 break; 1650 1651 case 25: /* HcHReset */ 1652 retval = ohci->hreset; 1653 break; 1654 1655 case 26: /* HcHInterruptEnable */ 1656 retval = ohci->hmask; 1657 break; 1658 1659 case 27: /* HcHInterruptTest */ 1660 retval = ohci->htest; 1661 break; 1662 1663 default: 1664 trace_usb_ohci_mem_read_bad_offset(addr); 1665 retval = 0xffffffff; 1666 } 1667 } 1668 1669 return retval; 1670 } 1671 1672 static void ohci_mem_write(void *opaque, 1673 hwaddr addr, 1674 uint64_t val, 1675 unsigned size) 1676 { 1677 OHCIState *ohci = opaque; 1678 1679 /* Only aligned reads are allowed on OHCI */ 1680 if (addr & 3) { 1681 trace_usb_ohci_mem_write_unaligned(addr); 1682 return; 1683 } 1684 1685 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1686 /* HcRhPortStatus */ 1687 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1688 return; 1689 } 1690 1691 switch (addr >> 2) { 1692 case 1: /* HcControl */ 1693 ohci_set_ctl(ohci, val); 1694 break; 1695 1696 case 2: /* HcCommandStatus */ 1697 /* SOC is read-only */ 1698 val = (val & ~OHCI_STATUS_SOC); 1699 1700 /* Bits written as '0' remain unchanged in the register */ 1701 ohci->status |= val; 1702 1703 if (ohci->status & OHCI_STATUS_HCR) 1704 ohci_reset(ohci); 1705 break; 1706 1707 case 3: /* HcInterruptStatus */ 1708 ohci->intr_status &= ~val; 1709 ohci_intr_update(ohci); 1710 break; 1711 1712 case 4: /* HcInterruptEnable */ 1713 ohci->intr |= val; 1714 ohci_intr_update(ohci); 1715 break; 1716 1717 case 5: /* HcInterruptDisable */ 1718 ohci->intr &= ~val; 1719 ohci_intr_update(ohci); 1720 break; 1721 1722 case 6: /* HcHCCA */ 1723 ohci->hcca = val & OHCI_HCCA_MASK; 1724 break; 1725 1726 case 7: /* HcPeriodCurrentED */ 1727 /* Ignore writes to this read-only register, Linux does them */ 1728 break; 1729 1730 case 8: /* HcControlHeadED */ 1731 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1732 break; 1733 1734 case 9: /* HcControlCurrentED */ 1735 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1736 break; 1737 1738 case 10: /* HcBulkHeadED */ 1739 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1740 break; 1741 1742 case 11: /* HcBulkCurrentED */ 1743 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1744 break; 1745 1746 case 13: /* HcFmInterval */ 1747 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1748 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1749 ohci_set_frame_interval(ohci, val); 1750 break; 1751 1752 case 15: /* HcFmNumber */ 1753 break; 1754 1755 case 16: /* HcPeriodicStart */ 1756 ohci->pstart = val & 0xffff; 1757 break; 1758 1759 case 17: /* HcLSThreshold */ 1760 ohci->lst = val & 0xffff; 1761 break; 1762 1763 case 18: /* HcRhDescriptorA */ 1764 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1765 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1766 break; 1767 1768 case 19: /* HcRhDescriptorB */ 1769 break; 1770 1771 case 20: /* HcRhStatus */ 1772 ohci_set_hub_status(ohci, val); 1773 break; 1774 1775 /* PXA27x specific registers */ 1776 case 24: /* HcStatus */ 1777 ohci->hstatus &= ~(val & ohci->hmask); 1778 break; 1779 1780 case 25: /* HcHReset */ 1781 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1782 if (val & OHCI_HRESET_FSBIR) 1783 ohci_reset(ohci); 1784 break; 1785 1786 case 26: /* HcHInterruptEnable */ 1787 ohci->hmask = val; 1788 break; 1789 1790 case 27: /* HcHInterruptTest */ 1791 ohci->htest = val; 1792 break; 1793 1794 default: 1795 trace_usb_ohci_mem_write_bad_offset(addr); 1796 break; 1797 } 1798 } 1799 1800 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) 1801 { 1802 if (ohci->async_td && 1803 usb_packet_is_inflight(&ohci->usb_packet) && 1804 ohci->usb_packet.ep->dev == dev) { 1805 usb_cancel_packet(&ohci->usb_packet); 1806 ohci->async_td = 0; 1807 } 1808 } 1809 1810 static const MemoryRegionOps ohci_mem_ops = { 1811 .read = ohci_mem_read, 1812 .write = ohci_mem_write, 1813 .endianness = DEVICE_LITTLE_ENDIAN, 1814 }; 1815 1816 static USBPortOps ohci_port_ops = { 1817 .attach = ohci_attach, 1818 .detach = ohci_detach, 1819 .child_detach = ohci_child_detach, 1820 .wakeup = ohci_wakeup, 1821 .complete = ohci_async_complete_packet, 1822 }; 1823 1824 static USBBusOps ohci_bus_ops = { 1825 }; 1826 1827 static int usb_ohci_init(OHCIState *ohci, DeviceState *dev, 1828 int num_ports, dma_addr_t localmem_base, 1829 char *masterbus, uint32_t firstport, 1830 AddressSpace *as) 1831 { 1832 int i; 1833 1834 ohci->as = as; 1835 1836 if (usb_frame_time == 0) { 1837 #ifdef OHCI_TIME_WARP 1838 usb_frame_time = get_ticks_per_sec(); 1839 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); 1840 #else 1841 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); 1842 if (get_ticks_per_sec() >= USB_HZ) { 1843 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ); 1844 } else { 1845 usb_bit_time = 1; 1846 } 1847 #endif 1848 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); 1849 } 1850 1851 ohci->num_ports = num_ports; 1852 if (masterbus) { 1853 USBPort *ports[OHCI_MAX_PORTS]; 1854 for(i = 0; i < num_ports; i++) { 1855 ports[i] = &ohci->rhport[i].port; 1856 } 1857 if (usb_register_companion(masterbus, ports, num_ports, 1858 firstport, ohci, &ohci_port_ops, 1859 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1860 return -1; 1861 } 1862 } else { 1863 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); 1864 for (i = 0; i < num_ports; i++) { 1865 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1866 ohci, i, &ohci_port_ops, 1867 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1868 } 1869 } 1870 1871 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, 1872 ohci, "ohci", 256); 1873 ohci->localmem_base = localmem_base; 1874 1875 ohci->name = object_get_typename(OBJECT(dev)); 1876 usb_packet_init(&ohci->usb_packet); 1877 1878 ohci->async_td = 0; 1879 qemu_register_reset(ohci_reset, ohci); 1880 1881 return 0; 1882 } 1883 1884 #define TYPE_PCI_OHCI "pci-ohci" 1885 #define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI) 1886 1887 typedef struct { 1888 /*< private >*/ 1889 PCIDevice parent_obj; 1890 /*< public >*/ 1891 1892 OHCIState state; 1893 char *masterbus; 1894 uint32_t num_ports; 1895 uint32_t firstport; 1896 } OHCIPCIState; 1897 1898 /** A typical O/EHCI will stop operating, set itself into error state 1899 * (which can be queried by MMIO) and will set PERR in its config 1900 * space to signal that it got an error 1901 */ 1902 static void ohci_die(OHCIState *ohci) 1903 { 1904 OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state); 1905 1906 trace_usb_ohci_die(); 1907 1908 ohci_set_interrupt(ohci, OHCI_INTR_UE); 1909 ohci_bus_stop(ohci); 1910 pci_set_word(dev->parent_obj.config + PCI_STATUS, 1911 PCI_STATUS_DETECTED_PARITY); 1912 } 1913 1914 static int usb_ohci_initfn_pci(PCIDevice *dev) 1915 { 1916 OHCIPCIState *ohci = PCI_OHCI(dev); 1917 1918 dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */ 1919 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1920 1921 if (usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0, 1922 ohci->masterbus, ohci->firstport, 1923 pci_get_address_space(dev)) != 0) { 1924 return -1; 1925 } 1926 ohci->state.irq = pci_allocate_irq(dev); 1927 1928 pci_register_bar(dev, 0, 0, &ohci->state.mem); 1929 return 0; 1930 } 1931 1932 static void usb_ohci_exit(PCIDevice *dev) 1933 { 1934 OHCIPCIState *ohci = PCI_OHCI(dev); 1935 OHCIState *s = &ohci->state; 1936 1937 trace_usb_ohci_exit(s->name); 1938 ohci_bus_stop(s); 1939 1940 if (s->async_td) { 1941 usb_cancel_packet(&s->usb_packet); 1942 s->async_td = 0; 1943 } 1944 ohci_stop_endpoints(s); 1945 1946 if (!ohci->masterbus) { 1947 usb_bus_release(&s->bus); 1948 } 1949 } 1950 1951 #define TYPE_SYSBUS_OHCI "sysbus-ohci" 1952 #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI) 1953 1954 typedef struct { 1955 /*< private >*/ 1956 SysBusDevice parent_obj; 1957 /*< public >*/ 1958 1959 OHCIState ohci; 1960 uint32_t num_ports; 1961 dma_addr_t dma_offset; 1962 } OHCISysBusState; 1963 1964 static void ohci_realize_pxa(DeviceState *dev, Error **errp) 1965 { 1966 OHCISysBusState *s = SYSBUS_OHCI(dev); 1967 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1968 1969 /* Cannot fail as we pass NULL for masterbus */ 1970 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, NULL, 0, 1971 &address_space_memory); 1972 sysbus_init_irq(sbd, &s->ohci.irq); 1973 sysbus_init_mmio(sbd, &s->ohci.mem); 1974 } 1975 1976 static Property ohci_pci_properties[] = { 1977 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), 1978 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), 1979 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), 1980 DEFINE_PROP_END_OF_LIST(), 1981 }; 1982 1983 static const VMStateDescription vmstate_ohci_state_port = { 1984 .name = "ohci-core/port", 1985 .version_id = 1, 1986 .minimum_version_id = 1, 1987 .fields = (VMStateField[]) { 1988 VMSTATE_UINT32(ctrl, OHCIPort), 1989 VMSTATE_END_OF_LIST() 1990 }, 1991 }; 1992 1993 static bool ohci_eof_timer_needed(void *opaque) 1994 { 1995 OHCIState *ohci = opaque; 1996 1997 return ohci->eof_timer != NULL; 1998 } 1999 2000 static int ohci_eof_timer_pre_load(void *opaque) 2001 { 2002 OHCIState *ohci = opaque; 2003 2004 ohci_bus_start(ohci); 2005 2006 return 0; 2007 } 2008 2009 static const VMStateDescription vmstate_ohci_eof_timer = { 2010 .name = "ohci-core/eof-timer", 2011 .version_id = 1, 2012 .minimum_version_id = 1, 2013 .pre_load = ohci_eof_timer_pre_load, 2014 .fields = (VMStateField[]) { 2015 VMSTATE_TIMER(eof_timer, OHCIState), 2016 VMSTATE_END_OF_LIST() 2017 }, 2018 }; 2019 2020 static const VMStateDescription vmstate_ohci_state = { 2021 .name = "ohci-core", 2022 .version_id = 1, 2023 .minimum_version_id = 1, 2024 .fields = (VMStateField[]) { 2025 VMSTATE_INT64(sof_time, OHCIState), 2026 VMSTATE_UINT32(ctl, OHCIState), 2027 VMSTATE_UINT32(status, OHCIState), 2028 VMSTATE_UINT32(intr_status, OHCIState), 2029 VMSTATE_UINT32(intr, OHCIState), 2030 VMSTATE_UINT32(hcca, OHCIState), 2031 VMSTATE_UINT32(ctrl_head, OHCIState), 2032 VMSTATE_UINT32(ctrl_cur, OHCIState), 2033 VMSTATE_UINT32(bulk_head, OHCIState), 2034 VMSTATE_UINT32(bulk_cur, OHCIState), 2035 VMSTATE_UINT32(per_cur, OHCIState), 2036 VMSTATE_UINT32(done, OHCIState), 2037 VMSTATE_INT32(done_count, OHCIState), 2038 VMSTATE_UINT16(fsmps, OHCIState), 2039 VMSTATE_UINT8(fit, OHCIState), 2040 VMSTATE_UINT16(fi, OHCIState), 2041 VMSTATE_UINT8(frt, OHCIState), 2042 VMSTATE_UINT16(frame_number, OHCIState), 2043 VMSTATE_UINT16(padding, OHCIState), 2044 VMSTATE_UINT32(pstart, OHCIState), 2045 VMSTATE_UINT32(lst, OHCIState), 2046 VMSTATE_UINT32(rhdesc_a, OHCIState), 2047 VMSTATE_UINT32(rhdesc_b, OHCIState), 2048 VMSTATE_UINT32(rhstatus, OHCIState), 2049 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, 2050 vmstate_ohci_state_port, OHCIPort), 2051 VMSTATE_UINT32(hstatus, OHCIState), 2052 VMSTATE_UINT32(hmask, OHCIState), 2053 VMSTATE_UINT32(hreset, OHCIState), 2054 VMSTATE_UINT32(htest, OHCIState), 2055 VMSTATE_UINT32(old_ctl, OHCIState), 2056 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), 2057 VMSTATE_UINT32(async_td, OHCIState), 2058 VMSTATE_BOOL(async_complete, OHCIState), 2059 VMSTATE_END_OF_LIST() 2060 }, 2061 .subsections = (VMStateSubsection []) { 2062 { 2063 .vmsd = &vmstate_ohci_eof_timer, 2064 .needed = ohci_eof_timer_needed, 2065 } , { 2066 /* empty */ 2067 } 2068 } 2069 }; 2070 2071 static const VMStateDescription vmstate_ohci = { 2072 .name = "ohci", 2073 .version_id = 1, 2074 .minimum_version_id = 1, 2075 .fields = (VMStateField[]) { 2076 VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState), 2077 VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState), 2078 VMSTATE_END_OF_LIST() 2079 } 2080 }; 2081 2082 static void ohci_pci_class_init(ObjectClass *klass, void *data) 2083 { 2084 DeviceClass *dc = DEVICE_CLASS(klass); 2085 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2086 2087 k->init = usb_ohci_initfn_pci; 2088 k->exit = usb_ohci_exit; 2089 k->vendor_id = PCI_VENDOR_ID_APPLE; 2090 k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB; 2091 k->class_id = PCI_CLASS_SERIAL_USB; 2092 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2093 dc->desc = "Apple USB Controller"; 2094 dc->props = ohci_pci_properties; 2095 dc->hotpluggable = false; 2096 dc->vmsd = &vmstate_ohci; 2097 } 2098 2099 static const TypeInfo ohci_pci_info = { 2100 .name = TYPE_PCI_OHCI, 2101 .parent = TYPE_PCI_DEVICE, 2102 .instance_size = sizeof(OHCIPCIState), 2103 .class_init = ohci_pci_class_init, 2104 }; 2105 2106 static Property ohci_sysbus_properties[] = { 2107 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 2108 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 3), 2109 DEFINE_PROP_END_OF_LIST(), 2110 }; 2111 2112 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 2113 { 2114 DeviceClass *dc = DEVICE_CLASS(klass); 2115 2116 dc->realize = ohci_realize_pxa; 2117 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2118 dc->desc = "OHCI USB Controller"; 2119 dc->props = ohci_sysbus_properties; 2120 } 2121 2122 static const TypeInfo ohci_sysbus_info = { 2123 .name = TYPE_SYSBUS_OHCI, 2124 .parent = TYPE_SYS_BUS_DEVICE, 2125 .instance_size = sizeof(OHCISysBusState), 2126 .class_init = ohci_sysbus_class_init, 2127 }; 2128 2129 static void ohci_register_types(void) 2130 { 2131 type_register_static(&ohci_pci_info); 2132 type_register_static(&ohci_sysbus_info); 2133 } 2134 2135 type_init(ohci_register_types) 2136