1*15f07fb8SPaolo Bonzini /*
2*15f07fb8SPaolo Bonzini * QEMU USB OHCI Emulation
3*15f07fb8SPaolo Bonzini * Copyright (c) 2006 Openedhand Ltd.
4*15f07fb8SPaolo Bonzini * Copyright (c) 2010 CodeSourcery
5*15f07fb8SPaolo Bonzini * Copyright (c) 2024 Red Hat, Inc.
6*15f07fb8SPaolo Bonzini *
7*15f07fb8SPaolo Bonzini * This library is free software; you can redistribute it and/or
8*15f07fb8SPaolo Bonzini * modify it under the terms of the GNU Lesser General Public
9*15f07fb8SPaolo Bonzini * License as published by the Free Software Foundation; either
10*15f07fb8SPaolo Bonzini * version 2.1 of the License, or (at your option) any later version.
11*15f07fb8SPaolo Bonzini *
12*15f07fb8SPaolo Bonzini * This library is distributed in the hope that it will be useful,
13*15f07fb8SPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of
14*15f07fb8SPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15*15f07fb8SPaolo Bonzini * Lesser General Public License for more details.
16*15f07fb8SPaolo Bonzini *
17*15f07fb8SPaolo Bonzini * You should have received a copy of the GNU Lesser General Public
18*15f07fb8SPaolo Bonzini * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19*15f07fb8SPaolo Bonzini */
20*15f07fb8SPaolo Bonzini
21*15f07fb8SPaolo Bonzini #include "qemu/osdep.h"
22*15f07fb8SPaolo Bonzini #include "hw/irq.h"
23*15f07fb8SPaolo Bonzini #include "qapi/error.h"
24*15f07fb8SPaolo Bonzini #include "qemu/module.h"
25*15f07fb8SPaolo Bonzini #include "qemu/timer.h"
26*15f07fb8SPaolo Bonzini #include "hw/usb.h"
27*15f07fb8SPaolo Bonzini #include "migration/vmstate.h"
28*15f07fb8SPaolo Bonzini #include "hw/sysbus.h"
29*15f07fb8SPaolo Bonzini #include "hw/qdev-dma.h"
30*15f07fb8SPaolo Bonzini #include "hw/qdev-properties.h"
31*15f07fb8SPaolo Bonzini #include "trace.h"
32*15f07fb8SPaolo Bonzini #include "hcd-ohci.h"
33*15f07fb8SPaolo Bonzini
34*15f07fb8SPaolo Bonzini
ohci_sysbus_realize(DeviceState * dev,Error ** errp)35*15f07fb8SPaolo Bonzini static void ohci_sysbus_realize(DeviceState *dev, Error **errp)
36*15f07fb8SPaolo Bonzini {
37*15f07fb8SPaolo Bonzini OHCISysBusState *s = SYSBUS_OHCI(dev);
38*15f07fb8SPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
39*15f07fb8SPaolo Bonzini Error *err = NULL;
40*15f07fb8SPaolo Bonzini
41*15f07fb8SPaolo Bonzini usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
42*15f07fb8SPaolo Bonzini s->masterbus, s->firstport,
43*15f07fb8SPaolo Bonzini &address_space_memory, ohci_sysbus_die, &err);
44*15f07fb8SPaolo Bonzini if (err) {
45*15f07fb8SPaolo Bonzini error_propagate(errp, err);
46*15f07fb8SPaolo Bonzini return;
47*15f07fb8SPaolo Bonzini }
48*15f07fb8SPaolo Bonzini sysbus_init_irq(sbd, &s->ohci.irq);
49*15f07fb8SPaolo Bonzini sysbus_init_mmio(sbd, &s->ohci.mem);
50*15f07fb8SPaolo Bonzini }
51*15f07fb8SPaolo Bonzini
ohci_sysbus_reset(DeviceState * dev)52*15f07fb8SPaolo Bonzini static void ohci_sysbus_reset(DeviceState *dev)
53*15f07fb8SPaolo Bonzini {
54*15f07fb8SPaolo Bonzini OHCISysBusState *s = SYSBUS_OHCI(dev);
55*15f07fb8SPaolo Bonzini OHCIState *ohci = &s->ohci;
56*15f07fb8SPaolo Bonzini
57*15f07fb8SPaolo Bonzini ohci_hard_reset(ohci);
58*15f07fb8SPaolo Bonzini }
59*15f07fb8SPaolo Bonzini
60*15f07fb8SPaolo Bonzini static Property ohci_sysbus_properties[] = {
61*15f07fb8SPaolo Bonzini DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
62*15f07fb8SPaolo Bonzini DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
63*15f07fb8SPaolo Bonzini DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
64*15f07fb8SPaolo Bonzini DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
65*15f07fb8SPaolo Bonzini DEFINE_PROP_END_OF_LIST(),
66*15f07fb8SPaolo Bonzini };
67*15f07fb8SPaolo Bonzini
ohci_sysbus_class_init(ObjectClass * klass,void * data)68*15f07fb8SPaolo Bonzini static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
69*15f07fb8SPaolo Bonzini {
70*15f07fb8SPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass);
71*15f07fb8SPaolo Bonzini
72*15f07fb8SPaolo Bonzini dc->realize = ohci_sysbus_realize;
73*15f07fb8SPaolo Bonzini set_bit(DEVICE_CATEGORY_USB, dc->categories);
74*15f07fb8SPaolo Bonzini dc->desc = "OHCI USB Controller";
75*15f07fb8SPaolo Bonzini device_class_set_props(dc, ohci_sysbus_properties);
76*15f07fb8SPaolo Bonzini dc->reset = ohci_sysbus_reset;
77*15f07fb8SPaolo Bonzini }
78*15f07fb8SPaolo Bonzini
79*15f07fb8SPaolo Bonzini static const TypeInfo ohci_sysbus_types[] = {
80*15f07fb8SPaolo Bonzini {
81*15f07fb8SPaolo Bonzini .name = TYPE_SYSBUS_OHCI,
82*15f07fb8SPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE,
83*15f07fb8SPaolo Bonzini .instance_size = sizeof(OHCISysBusState),
84*15f07fb8SPaolo Bonzini .class_init = ohci_sysbus_class_init,
85*15f07fb8SPaolo Bonzini },
86*15f07fb8SPaolo Bonzini };
87*15f07fb8SPaolo Bonzini
88*15f07fb8SPaolo Bonzini DEFINE_TYPES(ohci_sysbus_types);
89