1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * Copyright(c) 2008 Emutex Ltd. (address@hidden) 5 * 6 * EHCI project was started by Mark Burkley, with contributions by 7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, 8 * Jan Kiszka and Vincent Palatin contributed bugfixes. 9 * 10 * 11 * This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU Lesser General Public 13 * License as published by the Free Software Foundation; either 14 * version 2 of the License, or(at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * Lesser General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "hw/hw.h" 26 #include "qemu-timer.h" 27 #include "hw/usb.h" 28 #include "hw/pci.h" 29 #include "monitor.h" 30 #include "trace.h" 31 #include "dma.h" 32 33 #define EHCI_DEBUG 0 34 35 #if EHCI_DEBUG 36 #define DPRINTF printf 37 #else 38 #define DPRINTF(...) 39 #endif 40 41 /* internal processing - reset HC to try and recover */ 42 #define USB_RET_PROCERR (-99) 43 44 #define MMIO_SIZE 0x1000 45 46 /* Capability Registers Base Address - section 2.2 */ 47 #define CAPREGBASE 0x0000 48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved 49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # 50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params 51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params 52 #define EECP HCCPARAMS + 1 53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c 54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 55 56 #define OPREGBASE 0x0020 // Operational Registers Base Address 57 58 #define USBCMD OPREGBASE + 0x0000 59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop 60 #define USBCMD_HCRESET (1 << 1) // HC Reset 61 #define USBCMD_FLS (3 << 2) // Frame List Size 62 #define USBCMD_FLS_SH 2 // Frame List Size Shift 63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable 64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable 65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell 66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset 67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count 68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable 69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control 70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift 71 72 #define USBSTS OPREGBASE + 0x0004 73 #define USBSTS_RO_MASK 0x0000003f 74 #define USBSTS_INT (1 << 0) // USB Interrupt 75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt 76 #define USBSTS_PCD (1 << 2) // Port Change Detect 77 #define USBSTS_FLR (1 << 3) // Frame List Rollover 78 #define USBSTS_HSE (1 << 4) // Host System Error 79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance 80 #define USBSTS_HALT (1 << 12) // HC Halted 81 #define USBSTS_REC (1 << 13) // Reclamation 82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status 83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status 84 85 /* 86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS 87 * so no need to redefine here. 88 */ 89 #define USBINTR OPREGBASE + 0x0008 90 #define USBINTR_MASK 0x0000003f 91 92 #define FRINDEX OPREGBASE + 0x000c 93 #define CTRLDSSEGMENT OPREGBASE + 0x0010 94 #define PERIODICLISTBASE OPREGBASE + 0x0014 95 #define ASYNCLISTADDR OPREGBASE + 0x0018 96 #define ASYNCLISTADDR_MASK 0xffffffe0 97 98 #define CONFIGFLAG OPREGBASE + 0x0040 99 100 #define PORTSC (OPREGBASE + 0x0044) 101 #define PORTSC_BEGIN PORTSC 102 #define PORTSC_END (PORTSC + 4 * NB_PORTS) 103 /* 104 * Bits that are reserved or are read-only are masked out of values 105 * written to us by software 106 */ 107 #define PORTSC_RO_MASK 0x007001c0 108 #define PORTSC_RWC_MASK 0x0000002a 109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable 110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable 111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable 112 #define PORTSC_PTC (15 << 16) // Port Test Control 113 #define PORTSC_PTC_SH 16 // Port Test Control shift 114 #define PORTSC_PIC (3 << 14) // Port Indicator Control 115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift 116 #define PORTSC_POWNER (1 << 13) // Port Owner 117 #define PORTSC_PPOWER (1 << 12) // Port Power 118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status 119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift 120 #define PORTSC_PRESET (1 << 8) // Port Reset 121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend 122 #define PORTSC_FPRES (1 << 6) // Force Port Resume 123 #define PORTSC_OCC (1 << 5) // Over Current Change 124 #define PORTSC_OCA (1 << 4) // Over Current Active 125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change 126 #define PORTSC_PED (1 << 2) // Port Enable/Disable 127 #define PORTSC_CSC (1 << 1) // Connect Status Change 128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status 129 130 #define FRAME_TIMER_FREQ 1000 131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) 132 133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints 134 #define NB_PORTS 6 // Number of downstream ports 135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction 136 #define MAX_QH 100 // Max allowable queue heads in a chain 137 138 /* Internal periodic / asynchronous schedule state machine states 139 */ 140 typedef enum { 141 EST_INACTIVE = 1000, 142 EST_ACTIVE, 143 EST_EXECUTING, 144 EST_SLEEPING, 145 /* The following states are internal to the state machine function 146 */ 147 EST_WAITLISTHEAD, 148 EST_FETCHENTRY, 149 EST_FETCHQH, 150 EST_FETCHITD, 151 EST_FETCHSITD, 152 EST_ADVANCEQUEUE, 153 EST_FETCHQTD, 154 EST_EXECUTE, 155 EST_WRITEBACK, 156 EST_HORIZONTALQH 157 } EHCI_STATES; 158 159 /* macros for accessing fields within next link pointer entry */ 160 #define NLPTR_GET(x) ((x) & 0xffffffe0) 161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) 162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid 163 164 /* link pointer types */ 165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor 166 #define NLPTR_TYPE_QH 1 // queue head 167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor 168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node 169 170 171 /* EHCI spec version 1.0 Section 3.3 172 */ 173 typedef struct EHCIitd { 174 uint32_t next; 175 176 uint32_t transact[8]; 177 #define ITD_XACT_ACTIVE (1 << 31) 178 #define ITD_XACT_DBERROR (1 << 30) 179 #define ITD_XACT_BABBLE (1 << 29) 180 #define ITD_XACT_XACTERR (1 << 28) 181 #define ITD_XACT_LENGTH_MASK 0x0fff0000 182 #define ITD_XACT_LENGTH_SH 16 183 #define ITD_XACT_IOC (1 << 15) 184 #define ITD_XACT_PGSEL_MASK 0x00007000 185 #define ITD_XACT_PGSEL_SH 12 186 #define ITD_XACT_OFFSET_MASK 0x00000fff 187 188 uint32_t bufptr[7]; 189 #define ITD_BUFPTR_MASK 0xfffff000 190 #define ITD_BUFPTR_SH 12 191 #define ITD_BUFPTR_EP_MASK 0x00000f00 192 #define ITD_BUFPTR_EP_SH 8 193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f 194 #define ITD_BUFPTR_DEVADDR_SH 0 195 #define ITD_BUFPTR_DIRECTION (1 << 11) 196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff 197 #define ITD_BUFPTR_MAXPKT_SH 0 198 #define ITD_BUFPTR_MULT_MASK 0x00000003 199 #define ITD_BUFPTR_MULT_SH 0 200 } EHCIitd; 201 202 /* EHCI spec version 1.0 Section 3.4 203 */ 204 typedef struct EHCIsitd { 205 uint32_t next; // Standard next link pointer 206 uint32_t epchar; 207 #define SITD_EPCHAR_IO (1 << 31) 208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 209 #define SITD_EPCHAR_PORTNUM_SH 24 210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 211 #define SITD_EPCHAR_HUBADDR_SH 16 212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 213 #define SITD_EPCHAR_EPNUM_SH 8 214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f 215 216 uint32_t uframe; 217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00 218 #define SITD_UFRAME_CMASK_SH 8 219 #define SITD_UFRAME_SMASK_MASK 0x000000ff 220 221 uint32_t results; 222 #define SITD_RESULTS_IOC (1 << 31) 223 #define SITD_RESULTS_PGSEL (1 << 30) 224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 225 #define SITD_RESULTS_TYBYTES_SH 16 226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 227 #define SITD_RESULTS_CPROGMASK_SH 8 228 #define SITD_RESULTS_ACTIVE (1 << 7) 229 #define SITD_RESULTS_ERR (1 << 6) 230 #define SITD_RESULTS_DBERR (1 << 5) 231 #define SITD_RESULTS_BABBLE (1 << 4) 232 #define SITD_RESULTS_XACTERR (1 << 3) 233 #define SITD_RESULTS_MISSEDUF (1 << 2) 234 #define SITD_RESULTS_SPLITXSTATE (1 << 1) 235 236 uint32_t bufptr[2]; 237 #define SITD_BUFPTR_MASK 0xfffff000 238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff 239 #define SITD_BUFPTR_TPOS_MASK 0x00000018 240 #define SITD_BUFPTR_TPOS_SH 3 241 #define SITD_BUFPTR_TCNT_MASK 0x00000007 242 243 uint32_t backptr; // Standard next link pointer 244 } EHCIsitd; 245 246 /* EHCI spec version 1.0 Section 3.5 247 */ 248 typedef struct EHCIqtd { 249 uint32_t next; // Standard next link pointer 250 uint32_t altnext; // Standard next link pointer 251 uint32_t token; 252 #define QTD_TOKEN_DTOGGLE (1 << 31) 253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 254 #define QTD_TOKEN_TBYTES_SH 16 255 #define QTD_TOKEN_IOC (1 << 15) 256 #define QTD_TOKEN_CPAGE_MASK 0x00007000 257 #define QTD_TOKEN_CPAGE_SH 12 258 #define QTD_TOKEN_CERR_MASK 0x00000c00 259 #define QTD_TOKEN_CERR_SH 10 260 #define QTD_TOKEN_PID_MASK 0x00000300 261 #define QTD_TOKEN_PID_SH 8 262 #define QTD_TOKEN_ACTIVE (1 << 7) 263 #define QTD_TOKEN_HALT (1 << 6) 264 #define QTD_TOKEN_DBERR (1 << 5) 265 #define QTD_TOKEN_BABBLE (1 << 4) 266 #define QTD_TOKEN_XACTERR (1 << 3) 267 #define QTD_TOKEN_MISSEDUF (1 << 2) 268 #define QTD_TOKEN_SPLITXSTATE (1 << 1) 269 #define QTD_TOKEN_PING (1 << 0) 270 271 uint32_t bufptr[5]; // Standard buffer pointer 272 #define QTD_BUFPTR_MASK 0xfffff000 273 #define QTD_BUFPTR_SH 12 274 } EHCIqtd; 275 276 /* EHCI spec version 1.0 Section 3.6 277 */ 278 typedef struct EHCIqh { 279 uint32_t next; // Standard next link pointer 280 281 /* endpoint characteristics */ 282 uint32_t epchar; 283 #define QH_EPCHAR_RL_MASK 0xf0000000 284 #define QH_EPCHAR_RL_SH 28 285 #define QH_EPCHAR_C (1 << 27) 286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 287 #define QH_EPCHAR_MPLEN_SH 16 288 #define QH_EPCHAR_H (1 << 15) 289 #define QH_EPCHAR_DTC (1 << 14) 290 #define QH_EPCHAR_EPS_MASK 0x00003000 291 #define QH_EPCHAR_EPS_SH 12 292 #define EHCI_QH_EPS_FULL 0 293 #define EHCI_QH_EPS_LOW 1 294 #define EHCI_QH_EPS_HIGH 2 295 #define EHCI_QH_EPS_RESERVED 3 296 297 #define QH_EPCHAR_EP_MASK 0x00000f00 298 #define QH_EPCHAR_EP_SH 8 299 #define QH_EPCHAR_I (1 << 7) 300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f 301 #define QH_EPCHAR_DEVADDR_SH 0 302 303 /* endpoint capabilities */ 304 uint32_t epcap; 305 #define QH_EPCAP_MULT_MASK 0xc0000000 306 #define QH_EPCAP_MULT_SH 30 307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000 308 #define QH_EPCAP_PORTNUM_SH 23 309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000 310 #define QH_EPCAP_HUBADDR_SH 16 311 #define QH_EPCAP_CMASK_MASK 0x0000ff00 312 #define QH_EPCAP_CMASK_SH 8 313 #define QH_EPCAP_SMASK_MASK 0x000000ff 314 #define QH_EPCAP_SMASK_SH 0 315 316 uint32_t current_qtd; // Standard next link pointer 317 uint32_t next_qtd; // Standard next link pointer 318 uint32_t altnext_qtd; 319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e 320 #define QH_ALTNEXT_NAKCNT_SH 1 321 322 uint32_t token; // Same as QTD token 323 uint32_t bufptr[5]; // Standard buffer pointer 324 #define BUFPTR_CPROGMASK_MASK 0x000000ff 325 #define BUFPTR_FRAMETAG_MASK 0x0000001f 326 #define BUFPTR_SBYTES_MASK 0x00000fe0 327 #define BUFPTR_SBYTES_SH 5 328 } EHCIqh; 329 330 /* EHCI spec version 1.0 Section 3.7 331 */ 332 typedef struct EHCIfstn { 333 uint32_t next; // Standard next link pointer 334 uint32_t backptr; // Standard next link pointer 335 } EHCIfstn; 336 337 typedef struct EHCIPacket EHCIPacket; 338 typedef struct EHCIQueue EHCIQueue; 339 typedef struct EHCIState EHCIState; 340 341 enum async_state { 342 EHCI_ASYNC_NONE = 0, 343 EHCI_ASYNC_INFLIGHT, 344 EHCI_ASYNC_FINISHED, 345 }; 346 347 struct EHCIPacket { 348 EHCIQueue *queue; 349 QTAILQ_ENTRY(EHCIPacket) next; 350 351 EHCIqtd qtd; /* copy of current QTD (being worked on) */ 352 uint32_t qtdaddr; /* address QTD read from */ 353 354 USBPacket packet; 355 QEMUSGList sgl; 356 int pid; 357 uint32_t tbytes; 358 enum async_state async; 359 int usb_status; 360 }; 361 362 struct EHCIQueue { 363 EHCIState *ehci; 364 QTAILQ_ENTRY(EHCIQueue) next; 365 uint32_t seen; 366 uint64_t ts; 367 int async; 368 int revalidate; 369 370 /* cached data from guest - needs to be flushed 371 * when guest removes an entry (doorbell, handshake sequence) 372 */ 373 EHCIqh qh; /* copy of current QH (being worked on) */ 374 uint32_t qhaddr; /* address QH read from */ 375 uint32_t qtdaddr; /* address QTD read from */ 376 USBDevice *dev; 377 QTAILQ_HEAD(, EHCIPacket) packets; 378 }; 379 380 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; 381 382 struct EHCIState { 383 PCIDevice dev; 384 USBBus bus; 385 qemu_irq irq; 386 MemoryRegion mem; 387 int companion_count; 388 389 /* properties */ 390 uint32_t maxframes; 391 392 /* 393 * EHCI spec version 1.0 Section 2.3 394 * Host Controller Operational Registers 395 */ 396 union { 397 uint8_t mmio[MMIO_SIZE]; 398 struct { 399 uint8_t cap[OPREGBASE]; 400 uint32_t usbcmd; 401 uint32_t usbsts; 402 uint32_t usbintr; 403 uint32_t frindex; 404 uint32_t ctrldssegment; 405 uint32_t periodiclistbase; 406 uint32_t asynclistaddr; 407 uint32_t notused[9]; 408 uint32_t configflag; 409 uint32_t portsc[NB_PORTS]; 410 }; 411 }; 412 413 /* 414 * Internal states, shadow registers, etc 415 */ 416 QEMUTimer *frame_timer; 417 QEMUBH *async_bh; 418 uint32_t astate; /* Current state in asynchronous schedule */ 419 uint32_t pstate; /* Current state in periodic schedule */ 420 USBPort ports[NB_PORTS]; 421 USBPort *companion_ports[NB_PORTS]; 422 uint32_t usbsts_pending; 423 uint32_t usbsts_frindex; 424 EHCIQueueHead aqueues; 425 EHCIQueueHead pqueues; 426 427 /* which address to look at next */ 428 uint32_t a_fetch_addr; 429 uint32_t p_fetch_addr; 430 431 USBPacket ipacket; 432 QEMUSGList isgl; 433 434 uint64_t last_run_ns; 435 uint32_t async_stepdown; 436 }; 437 438 #define SET_LAST_RUN_CLOCK(s) \ 439 (s)->last_run_ns = qemu_get_clock_ns(vm_clock); 440 441 /* nifty macros from Arnon's EHCI version */ 442 #define get_field(data, field) \ 443 (((data) & field##_MASK) >> field##_SH) 444 445 #define set_field(data, newval, field) do { \ 446 uint32_t val = *data; \ 447 val &= ~ field##_MASK; \ 448 val |= ((newval) << field##_SH) & field##_MASK; \ 449 *data = val; \ 450 } while(0) 451 452 static const char *ehci_state_names[] = { 453 [EST_INACTIVE] = "INACTIVE", 454 [EST_ACTIVE] = "ACTIVE", 455 [EST_EXECUTING] = "EXECUTING", 456 [EST_SLEEPING] = "SLEEPING", 457 [EST_WAITLISTHEAD] = "WAITLISTHEAD", 458 [EST_FETCHENTRY] = "FETCH ENTRY", 459 [EST_FETCHQH] = "FETCH QH", 460 [EST_FETCHITD] = "FETCH ITD", 461 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", 462 [EST_FETCHQTD] = "FETCH QTD", 463 [EST_EXECUTE] = "EXECUTE", 464 [EST_WRITEBACK] = "WRITEBACK", 465 [EST_HORIZONTALQH] = "HORIZONTALQH", 466 }; 467 468 static const char *ehci_mmio_names[] = { 469 [CAPLENGTH] = "CAPLENGTH", 470 [HCIVERSION] = "HCIVERSION", 471 [HCSPARAMS] = "HCSPARAMS", 472 [HCCPARAMS] = "HCCPARAMS", 473 [USBCMD] = "USBCMD", 474 [USBSTS] = "USBSTS", 475 [USBINTR] = "USBINTR", 476 [FRINDEX] = "FRINDEX", 477 [PERIODICLISTBASE] = "P-LIST BASE", 478 [ASYNCLISTADDR] = "A-LIST ADDR", 479 [PORTSC_BEGIN] = "PORTSC #0", 480 [PORTSC_BEGIN + 4] = "PORTSC #1", 481 [PORTSC_BEGIN + 8] = "PORTSC #2", 482 [PORTSC_BEGIN + 12] = "PORTSC #3", 483 [PORTSC_BEGIN + 16] = "PORTSC #4", 484 [PORTSC_BEGIN + 20] = "PORTSC #5", 485 [CONFIGFLAG] = "CONFIGFLAG", 486 }; 487 488 static const char *nr2str(const char **n, size_t len, uint32_t nr) 489 { 490 if (nr < len && n[nr] != NULL) { 491 return n[nr]; 492 } else { 493 return "unknown"; 494 } 495 } 496 497 static const char *state2str(uint32_t state) 498 { 499 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); 500 } 501 502 static const char *addr2str(target_phys_addr_t addr) 503 { 504 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); 505 } 506 507 static void ehci_trace_usbsts(uint32_t mask, int state) 508 { 509 /* interrupts */ 510 if (mask & USBSTS_INT) { 511 trace_usb_ehci_usbsts("INT", state); 512 } 513 if (mask & USBSTS_ERRINT) { 514 trace_usb_ehci_usbsts("ERRINT", state); 515 } 516 if (mask & USBSTS_PCD) { 517 trace_usb_ehci_usbsts("PCD", state); 518 } 519 if (mask & USBSTS_FLR) { 520 trace_usb_ehci_usbsts("FLR", state); 521 } 522 if (mask & USBSTS_HSE) { 523 trace_usb_ehci_usbsts("HSE", state); 524 } 525 if (mask & USBSTS_IAA) { 526 trace_usb_ehci_usbsts("IAA", state); 527 } 528 529 /* status */ 530 if (mask & USBSTS_HALT) { 531 trace_usb_ehci_usbsts("HALT", state); 532 } 533 if (mask & USBSTS_REC) { 534 trace_usb_ehci_usbsts("REC", state); 535 } 536 if (mask & USBSTS_PSS) { 537 trace_usb_ehci_usbsts("PSS", state); 538 } 539 if (mask & USBSTS_ASS) { 540 trace_usb_ehci_usbsts("ASS", state); 541 } 542 } 543 544 static inline void ehci_set_usbsts(EHCIState *s, int mask) 545 { 546 if ((s->usbsts & mask) == mask) { 547 return; 548 } 549 ehci_trace_usbsts(mask, 1); 550 s->usbsts |= mask; 551 } 552 553 static inline void ehci_clear_usbsts(EHCIState *s, int mask) 554 { 555 if ((s->usbsts & mask) == 0) { 556 return; 557 } 558 ehci_trace_usbsts(mask, 0); 559 s->usbsts &= ~mask; 560 } 561 562 /* update irq line */ 563 static inline void ehci_update_irq(EHCIState *s) 564 { 565 int level = 0; 566 567 if ((s->usbsts & USBINTR_MASK) & s->usbintr) { 568 level = 1; 569 } 570 571 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); 572 qemu_set_irq(s->irq, level); 573 } 574 575 /* flag interrupt condition */ 576 static inline void ehci_raise_irq(EHCIState *s, int intr) 577 { 578 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { 579 s->usbsts |= intr; 580 ehci_update_irq(s); 581 } else { 582 s->usbsts_pending |= intr; 583 } 584 } 585 586 /* 587 * Commit pending interrupts (added via ehci_raise_irq), 588 * at the rate allowed by "Interrupt Threshold Control". 589 */ 590 static inline void ehci_commit_irq(EHCIState *s) 591 { 592 uint32_t itc; 593 594 if (!s->usbsts_pending) { 595 return; 596 } 597 if (s->usbsts_frindex > s->frindex) { 598 return; 599 } 600 601 itc = (s->usbcmd >> 16) & 0xff; 602 s->usbsts |= s->usbsts_pending; 603 s->usbsts_pending = 0; 604 s->usbsts_frindex = s->frindex + itc; 605 ehci_update_irq(s); 606 } 607 608 static void ehci_update_halt(EHCIState *s) 609 { 610 if (s->usbcmd & USBCMD_RUNSTOP) { 611 ehci_clear_usbsts(s, USBSTS_HALT); 612 } else { 613 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { 614 ehci_set_usbsts(s, USBSTS_HALT); 615 } 616 } 617 } 618 619 static void ehci_set_state(EHCIState *s, int async, int state) 620 { 621 if (async) { 622 trace_usb_ehci_state("async", state2str(state)); 623 s->astate = state; 624 if (s->astate == EST_INACTIVE) { 625 ehci_clear_usbsts(s, USBSTS_ASS); 626 ehci_update_halt(s); 627 } else { 628 ehci_set_usbsts(s, USBSTS_ASS); 629 } 630 } else { 631 trace_usb_ehci_state("periodic", state2str(state)); 632 s->pstate = state; 633 if (s->pstate == EST_INACTIVE) { 634 ehci_clear_usbsts(s, USBSTS_PSS); 635 ehci_update_halt(s); 636 } else { 637 ehci_set_usbsts(s, USBSTS_PSS); 638 } 639 } 640 } 641 642 static int ehci_get_state(EHCIState *s, int async) 643 { 644 return async ? s->astate : s->pstate; 645 } 646 647 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) 648 { 649 if (async) { 650 s->a_fetch_addr = addr; 651 } else { 652 s->p_fetch_addr = addr; 653 } 654 } 655 656 static int ehci_get_fetch_addr(EHCIState *s, int async) 657 { 658 return async ? s->a_fetch_addr : s->p_fetch_addr; 659 } 660 661 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) 662 { 663 /* need three here due to argument count limits */ 664 trace_usb_ehci_qh_ptrs(q, addr, qh->next, 665 qh->current_qtd, qh->next_qtd, qh->altnext_qtd); 666 trace_usb_ehci_qh_fields(addr, 667 get_field(qh->epchar, QH_EPCHAR_RL), 668 get_field(qh->epchar, QH_EPCHAR_MPLEN), 669 get_field(qh->epchar, QH_EPCHAR_EPS), 670 get_field(qh->epchar, QH_EPCHAR_EP), 671 get_field(qh->epchar, QH_EPCHAR_DEVADDR)); 672 trace_usb_ehci_qh_bits(addr, 673 (bool)(qh->epchar & QH_EPCHAR_C), 674 (bool)(qh->epchar & QH_EPCHAR_H), 675 (bool)(qh->epchar & QH_EPCHAR_DTC), 676 (bool)(qh->epchar & QH_EPCHAR_I)); 677 } 678 679 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) 680 { 681 /* need three here due to argument count limits */ 682 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); 683 trace_usb_ehci_qtd_fields(addr, 684 get_field(qtd->token, QTD_TOKEN_TBYTES), 685 get_field(qtd->token, QTD_TOKEN_CPAGE), 686 get_field(qtd->token, QTD_TOKEN_CERR), 687 get_field(qtd->token, QTD_TOKEN_PID)); 688 trace_usb_ehci_qtd_bits(addr, 689 (bool)(qtd->token & QTD_TOKEN_IOC), 690 (bool)(qtd->token & QTD_TOKEN_ACTIVE), 691 (bool)(qtd->token & QTD_TOKEN_HALT), 692 (bool)(qtd->token & QTD_TOKEN_BABBLE), 693 (bool)(qtd->token & QTD_TOKEN_XACTERR)); 694 } 695 696 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) 697 { 698 trace_usb_ehci_itd(addr, itd->next, 699 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), 700 get_field(itd->bufptr[2], ITD_BUFPTR_MULT), 701 get_field(itd->bufptr[0], ITD_BUFPTR_EP), 702 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); 703 } 704 705 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, 706 EHCIsitd *sitd) 707 { 708 trace_usb_ehci_sitd(addr, sitd->next, 709 (bool)(sitd->results & SITD_RESULTS_ACTIVE)); 710 } 711 712 static inline bool ehci_enabled(EHCIState *s) 713 { 714 return s->usbcmd & USBCMD_RUNSTOP; 715 } 716 717 static inline bool ehci_async_enabled(EHCIState *s) 718 { 719 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); 720 } 721 722 static inline bool ehci_periodic_enabled(EHCIState *s) 723 { 724 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); 725 } 726 727 /* packet management */ 728 729 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) 730 { 731 EHCIPacket *p; 732 733 p = g_new0(EHCIPacket, 1); 734 p->queue = q; 735 usb_packet_init(&p->packet); 736 QTAILQ_INSERT_TAIL(&q->packets, p, next); 737 trace_usb_ehci_packet_action(p->queue, p, "alloc"); 738 return p; 739 } 740 741 static void ehci_free_packet(EHCIPacket *p) 742 { 743 trace_usb_ehci_packet_action(p->queue, p, "free"); 744 if (p->async == EHCI_ASYNC_INFLIGHT) { 745 usb_cancel_packet(&p->packet); 746 } 747 QTAILQ_REMOVE(&p->queue->packets, p, next); 748 usb_packet_cleanup(&p->packet); 749 g_free(p); 750 } 751 752 /* queue management */ 753 754 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) 755 { 756 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 757 EHCIQueue *q; 758 759 q = g_malloc0(sizeof(*q)); 760 q->ehci = ehci; 761 q->qhaddr = addr; 762 q->async = async; 763 QTAILQ_INIT(&q->packets); 764 QTAILQ_INSERT_HEAD(head, q, next); 765 trace_usb_ehci_queue_action(q, "alloc"); 766 return q; 767 } 768 769 static void ehci_free_queue(EHCIQueue *q) 770 { 771 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; 772 EHCIPacket *p; 773 774 trace_usb_ehci_queue_action(q, "free"); 775 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { 776 ehci_free_packet(p); 777 } 778 QTAILQ_REMOVE(head, q, next); 779 g_free(q); 780 } 781 782 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, 783 int async) 784 { 785 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 786 EHCIQueue *q; 787 788 QTAILQ_FOREACH(q, head, next) { 789 if (addr == q->qhaddr) { 790 return q; 791 } 792 } 793 return NULL; 794 } 795 796 static void ehci_queues_tag_unused_async(EHCIState *ehci) 797 { 798 EHCIQueue *q; 799 800 QTAILQ_FOREACH(q, &ehci->aqueues, next) { 801 if (!q->seen) { 802 q->revalidate = 1; 803 } 804 } 805 } 806 807 static void ehci_queues_rip_unused(EHCIState *ehci, int async) 808 { 809 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 810 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; 811 EHCIQueue *q, *tmp; 812 813 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 814 if (q->seen) { 815 q->seen = 0; 816 q->ts = ehci->last_run_ns; 817 continue; 818 } 819 if (ehci->last_run_ns < q->ts + maxage) { 820 continue; 821 } 822 ehci_free_queue(q); 823 } 824 } 825 826 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) 827 { 828 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 829 EHCIQueue *q, *tmp; 830 831 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 832 if (q->dev != dev) { 833 continue; 834 } 835 ehci_free_queue(q); 836 } 837 } 838 839 static void ehci_queues_rip_all(EHCIState *ehci, int async) 840 { 841 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 842 EHCIQueue *q, *tmp; 843 844 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 845 ehci_free_queue(q); 846 } 847 } 848 849 /* Attach or detach a device on root hub */ 850 851 static void ehci_attach(USBPort *port) 852 { 853 EHCIState *s = port->opaque; 854 uint32_t *portsc = &s->portsc[port->index]; 855 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 856 857 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); 858 859 if (*portsc & PORTSC_POWNER) { 860 USBPort *companion = s->companion_ports[port->index]; 861 companion->dev = port->dev; 862 companion->ops->attach(companion); 863 return; 864 } 865 866 *portsc |= PORTSC_CONNECT; 867 *portsc |= PORTSC_CSC; 868 869 ehci_raise_irq(s, USBSTS_PCD); 870 ehci_commit_irq(s); 871 } 872 873 static void ehci_detach(USBPort *port) 874 { 875 EHCIState *s = port->opaque; 876 uint32_t *portsc = &s->portsc[port->index]; 877 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 878 879 trace_usb_ehci_port_detach(port->index, owner); 880 881 if (*portsc & PORTSC_POWNER) { 882 USBPort *companion = s->companion_ports[port->index]; 883 companion->ops->detach(companion); 884 companion->dev = NULL; 885 /* 886 * EHCI spec 4.2.2: "When a disconnect occurs... On the event, 887 * the port ownership is returned immediately to the EHCI controller." 888 */ 889 *portsc &= ~PORTSC_POWNER; 890 return; 891 } 892 893 ehci_queues_rip_device(s, port->dev, 0); 894 ehci_queues_rip_device(s, port->dev, 1); 895 896 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); 897 *portsc |= PORTSC_CSC; 898 899 ehci_raise_irq(s, USBSTS_PCD); 900 ehci_commit_irq(s); 901 } 902 903 static void ehci_child_detach(USBPort *port, USBDevice *child) 904 { 905 EHCIState *s = port->opaque; 906 uint32_t portsc = s->portsc[port->index]; 907 908 if (portsc & PORTSC_POWNER) { 909 USBPort *companion = s->companion_ports[port->index]; 910 companion->ops->child_detach(companion, child); 911 return; 912 } 913 914 ehci_queues_rip_device(s, child, 0); 915 ehci_queues_rip_device(s, child, 1); 916 } 917 918 static void ehci_wakeup(USBPort *port) 919 { 920 EHCIState *s = port->opaque; 921 uint32_t portsc = s->portsc[port->index]; 922 923 if (portsc & PORTSC_POWNER) { 924 USBPort *companion = s->companion_ports[port->index]; 925 if (companion->ops->wakeup) { 926 companion->ops->wakeup(companion); 927 } 928 return; 929 } 930 931 qemu_bh_schedule(s->async_bh); 932 } 933 934 static int ehci_register_companion(USBBus *bus, USBPort *ports[], 935 uint32_t portcount, uint32_t firstport) 936 { 937 EHCIState *s = container_of(bus, EHCIState, bus); 938 uint32_t i; 939 940 if (firstport + portcount > NB_PORTS) { 941 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", 942 "firstport on masterbus"); 943 error_printf_unless_qmp( 944 "firstport value of %u makes companion take ports %u - %u, which " 945 "is outside of the valid range of 0 - %u\n", firstport, firstport, 946 firstport + portcount - 1, NB_PORTS - 1); 947 return -1; 948 } 949 950 for (i = 0; i < portcount; i++) { 951 if (s->companion_ports[firstport + i]) { 952 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", 953 "an USB masterbus"); 954 error_printf_unless_qmp( 955 "port %u on masterbus %s already has a companion assigned\n", 956 firstport + i, bus->qbus.name); 957 return -1; 958 } 959 } 960 961 for (i = 0; i < portcount; i++) { 962 s->companion_ports[firstport + i] = ports[i]; 963 s->ports[firstport + i].speedmask |= 964 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; 965 /* Ensure devs attached before the initial reset go to the companion */ 966 s->portsc[firstport + i] = PORTSC_POWNER; 967 } 968 969 s->companion_count++; 970 s->mmio[0x05] = (s->companion_count << 4) | portcount; 971 972 return 0; 973 } 974 975 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) 976 { 977 USBDevice *dev; 978 USBPort *port; 979 int i; 980 981 for (i = 0; i < NB_PORTS; i++) { 982 port = &ehci->ports[i]; 983 if (!(ehci->portsc[i] & PORTSC_PED)) { 984 DPRINTF("Port %d not enabled\n", i); 985 continue; 986 } 987 dev = usb_find_device(port, addr); 988 if (dev != NULL) { 989 return dev; 990 } 991 } 992 return NULL; 993 } 994 995 /* 4.1 host controller initialization */ 996 static void ehci_reset(void *opaque) 997 { 998 EHCIState *s = opaque; 999 int i; 1000 USBDevice *devs[NB_PORTS]; 1001 1002 trace_usb_ehci_reset(); 1003 1004 /* 1005 * Do the detach before touching portsc, so that it correctly gets send to 1006 * us or to our companion based on PORTSC_POWNER before the reset. 1007 */ 1008 for(i = 0; i < NB_PORTS; i++) { 1009 devs[i] = s->ports[i].dev; 1010 if (devs[i] && devs[i]->attached) { 1011 usb_detach(&s->ports[i]); 1012 } 1013 } 1014 1015 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); 1016 1017 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; 1018 s->usbsts = USBSTS_HALT; 1019 s->usbsts_pending = 0; 1020 s->usbsts_frindex = 0; 1021 1022 s->astate = EST_INACTIVE; 1023 s->pstate = EST_INACTIVE; 1024 1025 for(i = 0; i < NB_PORTS; i++) { 1026 if (s->companion_ports[i]) { 1027 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; 1028 } else { 1029 s->portsc[i] = PORTSC_PPOWER; 1030 } 1031 if (devs[i] && devs[i]->attached) { 1032 usb_attach(&s->ports[i]); 1033 usb_device_reset(devs[i]); 1034 } 1035 } 1036 ehci_queues_rip_all(s, 0); 1037 ehci_queues_rip_all(s, 1); 1038 qemu_del_timer(s->frame_timer); 1039 qemu_bh_cancel(s->async_bh); 1040 } 1041 1042 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) 1043 { 1044 EHCIState *s = ptr; 1045 uint32_t val; 1046 1047 val = s->mmio[addr]; 1048 1049 return val; 1050 } 1051 1052 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) 1053 { 1054 EHCIState *s = ptr; 1055 uint32_t val; 1056 1057 val = s->mmio[addr] | (s->mmio[addr+1] << 8); 1058 1059 return val; 1060 } 1061 1062 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) 1063 { 1064 EHCIState *s = ptr; 1065 uint32_t val; 1066 1067 val = s->mmio[addr] | (s->mmio[addr+1] << 8) | 1068 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); 1069 1070 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); 1071 return val; 1072 } 1073 1074 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) 1075 { 1076 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); 1077 exit(1); 1078 } 1079 1080 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) 1081 { 1082 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); 1083 exit(1); 1084 } 1085 1086 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) 1087 { 1088 USBDevice *dev = s->ports[port].dev; 1089 uint32_t *portsc = &s->portsc[port]; 1090 uint32_t orig; 1091 1092 if (s->companion_ports[port] == NULL) 1093 return; 1094 1095 owner = owner & PORTSC_POWNER; 1096 orig = *portsc & PORTSC_POWNER; 1097 1098 if (!(owner ^ orig)) { 1099 return; 1100 } 1101 1102 if (dev && dev->attached) { 1103 usb_detach(&s->ports[port]); 1104 } 1105 1106 *portsc &= ~PORTSC_POWNER; 1107 *portsc |= owner; 1108 1109 if (dev && dev->attached) { 1110 usb_attach(&s->ports[port]); 1111 } 1112 } 1113 1114 static void handle_port_status_write(EHCIState *s, int port, uint32_t val) 1115 { 1116 uint32_t *portsc = &s->portsc[port]; 1117 USBDevice *dev = s->ports[port].dev; 1118 1119 /* Clear rwc bits */ 1120 *portsc &= ~(val & PORTSC_RWC_MASK); 1121 /* The guest may clear, but not set the PED bit */ 1122 *portsc &= val | ~PORTSC_PED; 1123 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ 1124 handle_port_owner_write(s, port, val); 1125 /* And finally apply RO_MASK */ 1126 val &= PORTSC_RO_MASK; 1127 1128 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { 1129 trace_usb_ehci_port_reset(port, 1); 1130 } 1131 1132 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { 1133 trace_usb_ehci_port_reset(port, 0); 1134 if (dev && dev->attached) { 1135 usb_port_reset(&s->ports[port]); 1136 *portsc &= ~PORTSC_CSC; 1137 } 1138 1139 /* 1140 * Table 2.16 Set the enable bit(and enable bit change) to indicate 1141 * to SW that this port has a high speed device attached 1142 */ 1143 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { 1144 val |= PORTSC_PED; 1145 } 1146 } 1147 1148 *portsc &= ~PORTSC_RO_MASK; 1149 *portsc |= val; 1150 } 1151 1152 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) 1153 { 1154 EHCIState *s = ptr; 1155 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); 1156 uint32_t old = *mmio; 1157 int i; 1158 1159 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); 1160 1161 /* Only aligned reads are allowed on OHCI */ 1162 if (addr & 3) { 1163 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" 1164 TARGET_FMT_plx "\n", addr); 1165 return; 1166 } 1167 1168 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { 1169 handle_port_status_write(s, (addr-PORTSC)/4, val); 1170 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); 1171 return; 1172 } 1173 1174 if (addr < OPREGBASE) { 1175 fprintf(stderr, "usb-ehci: write attempt to read-only register" 1176 TARGET_FMT_plx "\n", addr); 1177 return; 1178 } 1179 1180 1181 /* Do any register specific pre-write processing here. */ 1182 switch(addr) { 1183 case USBCMD: 1184 if (val & USBCMD_HCRESET) { 1185 ehci_reset(s); 1186 val = s->usbcmd; 1187 break; 1188 } 1189 1190 /* not supporting dynamic frame list size at the moment */ 1191 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { 1192 fprintf(stderr, "attempt to set frame list size -- value %d\n", 1193 val & USBCMD_FLS); 1194 val &= ~USBCMD_FLS; 1195 } 1196 1197 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != 1198 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { 1199 if (s->pstate == EST_INACTIVE) { 1200 SET_LAST_RUN_CLOCK(s); 1201 } 1202 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ 1203 ehci_update_halt(s); 1204 s->async_stepdown = 0; 1205 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 1206 } 1207 break; 1208 1209 case USBSTS: 1210 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO 1211 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC 1212 val = s->usbsts; 1213 ehci_update_irq(s); 1214 break; 1215 1216 case USBINTR: 1217 val &= USBINTR_MASK; 1218 break; 1219 1220 case FRINDEX: 1221 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ 1222 break; 1223 1224 case CONFIGFLAG: 1225 val &= 0x1; 1226 if (val) { 1227 for(i = 0; i < NB_PORTS; i++) 1228 handle_port_owner_write(s, i, 0); 1229 } 1230 break; 1231 1232 case PERIODICLISTBASE: 1233 if (ehci_periodic_enabled(s)) { 1234 fprintf(stderr, 1235 "ehci: PERIODIC list base register set while periodic schedule\n" 1236 " is enabled and HC is enabled\n"); 1237 } 1238 break; 1239 1240 case ASYNCLISTADDR: 1241 if (ehci_async_enabled(s)) { 1242 fprintf(stderr, 1243 "ehci: ASYNC list address register set while async schedule\n" 1244 " is enabled and HC is enabled\n"); 1245 } 1246 break; 1247 } 1248 1249 *mmio = val; 1250 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); 1251 } 1252 1253 1254 // TODO : Put in common header file, duplication from usb-ohci.c 1255 1256 /* Get an array of dwords from main memory */ 1257 static inline int get_dwords(EHCIState *ehci, uint32_t addr, 1258 uint32_t *buf, int num) 1259 { 1260 int i; 1261 1262 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1263 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); 1264 *buf = le32_to_cpu(*buf); 1265 } 1266 1267 return 1; 1268 } 1269 1270 /* Put an array of dwords in to main memory */ 1271 static inline int put_dwords(EHCIState *ehci, uint32_t addr, 1272 uint32_t *buf, int num) 1273 { 1274 int i; 1275 1276 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1277 uint32_t tmp = cpu_to_le32(*buf); 1278 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); 1279 } 1280 1281 return 1; 1282 } 1283 1284 /* 1285 * Write the qh back to guest physical memory. This step isn't 1286 * in the EHCI spec but we need to do it since we don't share 1287 * physical memory with our guest VM. 1288 * 1289 * The first three dwords are read-only for the EHCI, so skip them 1290 * when writing back the qh. 1291 */ 1292 static void ehci_flush_qh(EHCIQueue *q) 1293 { 1294 uint32_t *qh = (uint32_t *) &q->qh; 1295 uint32_t dwords = sizeof(EHCIqh) >> 2; 1296 uint32_t addr = NLPTR_GET(q->qhaddr); 1297 1298 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); 1299 } 1300 1301 // 4.10.2 1302 1303 static int ehci_qh_do_overlay(EHCIQueue *q) 1304 { 1305 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1306 int i; 1307 int dtoggle; 1308 int ping; 1309 int eps; 1310 int reload; 1311 1312 assert(p != NULL); 1313 assert(p->qtdaddr == q->qtdaddr); 1314 1315 // remember values in fields to preserve in qh after overlay 1316 1317 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; 1318 ping = q->qh.token & QTD_TOKEN_PING; 1319 1320 q->qh.current_qtd = p->qtdaddr; 1321 q->qh.next_qtd = p->qtd.next; 1322 q->qh.altnext_qtd = p->qtd.altnext; 1323 q->qh.token = p->qtd.token; 1324 1325 1326 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); 1327 if (eps == EHCI_QH_EPS_HIGH) { 1328 q->qh.token &= ~QTD_TOKEN_PING; 1329 q->qh.token |= ping; 1330 } 1331 1332 reload = get_field(q->qh.epchar, QH_EPCHAR_RL); 1333 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); 1334 1335 for (i = 0; i < 5; i++) { 1336 q->qh.bufptr[i] = p->qtd.bufptr[i]; 1337 } 1338 1339 if (!(q->qh.epchar & QH_EPCHAR_DTC)) { 1340 // preserve QH DT bit 1341 q->qh.token &= ~QTD_TOKEN_DTOGGLE; 1342 q->qh.token |= dtoggle; 1343 } 1344 1345 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; 1346 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; 1347 1348 ehci_flush_qh(q); 1349 1350 return 0; 1351 } 1352 1353 static int ehci_init_transfer(EHCIPacket *p) 1354 { 1355 uint32_t cpage, offset, bytes, plen; 1356 dma_addr_t page; 1357 1358 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); 1359 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); 1360 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; 1361 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); 1362 1363 while (bytes > 0) { 1364 if (cpage > 4) { 1365 fprintf(stderr, "cpage out of range (%d)\n", cpage); 1366 return USB_RET_PROCERR; 1367 } 1368 1369 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; 1370 page += offset; 1371 plen = bytes; 1372 if (plen > 4096 - offset) { 1373 plen = 4096 - offset; 1374 offset = 0; 1375 cpage++; 1376 } 1377 1378 qemu_sglist_add(&p->sgl, page, plen); 1379 bytes -= plen; 1380 } 1381 return 0; 1382 } 1383 1384 static void ehci_finish_transfer(EHCIQueue *q, int status) 1385 { 1386 uint32_t cpage, offset; 1387 1388 if (status > 0) { 1389 /* update cpage & offset */ 1390 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); 1391 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; 1392 1393 offset += status; 1394 cpage += offset >> QTD_BUFPTR_SH; 1395 offset &= ~QTD_BUFPTR_MASK; 1396 1397 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); 1398 q->qh.bufptr[0] &= QTD_BUFPTR_MASK; 1399 q->qh.bufptr[0] |= offset; 1400 } 1401 } 1402 1403 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) 1404 { 1405 EHCIPacket *p; 1406 EHCIState *s = port->opaque; 1407 uint32_t portsc = s->portsc[port->index]; 1408 1409 if (portsc & PORTSC_POWNER) { 1410 USBPort *companion = s->companion_ports[port->index]; 1411 companion->ops->complete(companion, packet); 1412 return; 1413 } 1414 1415 p = container_of(packet, EHCIPacket, packet); 1416 trace_usb_ehci_packet_action(p->queue, p, "wakeup"); 1417 assert(p->async == EHCI_ASYNC_INFLIGHT); 1418 p->async = EHCI_ASYNC_FINISHED; 1419 p->usb_status = packet->result; 1420 1421 if (p->queue->async) { 1422 qemu_bh_schedule(p->queue->ehci->async_bh); 1423 } 1424 } 1425 1426 static void ehci_execute_complete(EHCIQueue *q) 1427 { 1428 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1429 1430 assert(p != NULL); 1431 assert(p->qtdaddr == q->qtdaddr); 1432 assert(p->async != EHCI_ASYNC_INFLIGHT); 1433 p->async = EHCI_ASYNC_NONE; 1434 1435 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", 1436 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); 1437 1438 if (p->usb_status < 0) { 1439 switch (p->usb_status) { 1440 case USB_RET_IOERROR: 1441 case USB_RET_NODEV: 1442 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); 1443 set_field(&q->qh.token, 0, QTD_TOKEN_CERR); 1444 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1445 break; 1446 case USB_RET_STALL: 1447 q->qh.token |= QTD_TOKEN_HALT; 1448 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1449 break; 1450 case USB_RET_NAK: 1451 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); 1452 return; /* We're not done yet with this transaction */ 1453 case USB_RET_BABBLE: 1454 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); 1455 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1456 break; 1457 default: 1458 /* should not be triggerable */ 1459 fprintf(stderr, "USB invalid response %d\n", p->usb_status); 1460 assert(0); 1461 break; 1462 } 1463 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) { 1464 p->usb_status = USB_RET_BABBLE; 1465 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); 1466 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1467 } else { 1468 // TODO check 4.12 for splits 1469 1470 if (p->tbytes && p->pid == USB_TOKEN_IN) { 1471 p->tbytes -= p->usb_status; 1472 } else { 1473 p->tbytes = 0; 1474 } 1475 1476 DPRINTF("updating tbytes to %d\n", p->tbytes); 1477 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); 1478 } 1479 ehci_finish_transfer(q, p->usb_status); 1480 usb_packet_unmap(&p->packet, &p->sgl); 1481 qemu_sglist_destroy(&p->sgl); 1482 1483 q->qh.token ^= QTD_TOKEN_DTOGGLE; 1484 q->qh.token &= ~QTD_TOKEN_ACTIVE; 1485 1486 if (q->qh.token & QTD_TOKEN_IOC) { 1487 ehci_raise_irq(q->ehci, USBSTS_INT); 1488 } 1489 } 1490 1491 // 4.10.3 1492 1493 static int ehci_execute(EHCIPacket *p, const char *action) 1494 { 1495 USBEndpoint *ep; 1496 int ret; 1497 int endp; 1498 1499 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { 1500 fprintf(stderr, "Attempting to execute inactive qtd\n"); 1501 return USB_RET_PROCERR; 1502 } 1503 1504 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; 1505 if (p->tbytes > BUFF_SIZE) { 1506 fprintf(stderr, "Request for more bytes than allowed\n"); 1507 return USB_RET_PROCERR; 1508 } 1509 1510 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; 1511 switch (p->pid) { 1512 case 0: 1513 p->pid = USB_TOKEN_OUT; 1514 break; 1515 case 1: 1516 p->pid = USB_TOKEN_IN; 1517 break; 1518 case 2: 1519 p->pid = USB_TOKEN_SETUP; 1520 break; 1521 default: 1522 fprintf(stderr, "bad token\n"); 1523 break; 1524 } 1525 1526 if (ehci_init_transfer(p) != 0) { 1527 return USB_RET_PROCERR; 1528 } 1529 1530 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); 1531 ep = usb_ep_get(p->queue->dev, p->pid, endp); 1532 1533 usb_packet_setup(&p->packet, p->pid, ep); 1534 usb_packet_map(&p->packet, &p->sgl); 1535 1536 trace_usb_ehci_packet_action(p->queue, p, action); 1537 ret = usb_handle_packet(p->queue->dev, &p->packet); 1538 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " 1539 "(total %d) endp %x ret %d\n", 1540 q->qhaddr, q->qh.next, q->qtdaddr, q->pid, 1541 q->packet.iov.size, q->tbytes, endp, ret); 1542 1543 if (ret > BUFF_SIZE) { 1544 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); 1545 return USB_RET_PROCERR; 1546 } 1547 1548 return ret; 1549 } 1550 1551 /* 4.7.2 1552 */ 1553 1554 static int ehci_process_itd(EHCIState *ehci, 1555 EHCIitd *itd) 1556 { 1557 USBDevice *dev; 1558 USBEndpoint *ep; 1559 int ret; 1560 uint32_t i, len, pid, dir, devaddr, endp; 1561 uint32_t pg, off, ptr1, ptr2, max, mult; 1562 1563 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); 1564 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); 1565 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); 1566 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); 1567 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); 1568 1569 for(i = 0; i < 8; i++) { 1570 if (itd->transact[i] & ITD_XACT_ACTIVE) { 1571 pg = get_field(itd->transact[i], ITD_XACT_PGSEL); 1572 off = itd->transact[i] & ITD_XACT_OFFSET_MASK; 1573 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); 1574 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); 1575 len = get_field(itd->transact[i], ITD_XACT_LENGTH); 1576 1577 if (len > max * mult) { 1578 len = max * mult; 1579 } 1580 1581 if (len > BUFF_SIZE) { 1582 return USB_RET_PROCERR; 1583 } 1584 1585 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); 1586 if (off + len > 4096) { 1587 /* transfer crosses page border */ 1588 uint32_t len2 = off + len - 4096; 1589 uint32_t len1 = len - len2; 1590 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); 1591 qemu_sglist_add(&ehci->isgl, ptr2, len2); 1592 } else { 1593 qemu_sglist_add(&ehci->isgl, ptr1 + off, len); 1594 } 1595 1596 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; 1597 1598 dev = ehci_find_device(ehci, devaddr); 1599 ep = usb_ep_get(dev, pid, endp); 1600 if (ep->type == USB_ENDPOINT_XFER_ISOC) { 1601 usb_packet_setup(&ehci->ipacket, pid, ep); 1602 usb_packet_map(&ehci->ipacket, &ehci->isgl); 1603 ret = usb_handle_packet(dev, &ehci->ipacket); 1604 assert(ret != USB_RET_ASYNC); 1605 usb_packet_unmap(&ehci->ipacket, &ehci->isgl); 1606 } else { 1607 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); 1608 ret = USB_RET_NAK; 1609 } 1610 qemu_sglist_destroy(&ehci->isgl); 1611 1612 if (ret < 0) { 1613 switch (ret) { 1614 default: 1615 fprintf(stderr, "Unexpected iso usb result: %d\n", ret); 1616 /* Fall through */ 1617 case USB_RET_IOERROR: 1618 case USB_RET_NODEV: 1619 /* 3.3.2: XACTERR is only allowed on IN transactions */ 1620 if (dir) { 1621 itd->transact[i] |= ITD_XACT_XACTERR; 1622 ehci_raise_irq(ehci, USBSTS_ERRINT); 1623 } 1624 break; 1625 case USB_RET_BABBLE: 1626 itd->transact[i] |= ITD_XACT_BABBLE; 1627 ehci_raise_irq(ehci, USBSTS_ERRINT); 1628 break; 1629 case USB_RET_NAK: 1630 /* no data for us, so do a zero-length transfer */ 1631 ret = 0; 1632 break; 1633 } 1634 } 1635 if (ret >= 0) { 1636 if (!dir) { 1637 /* OUT */ 1638 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); 1639 } else { 1640 /* IN */ 1641 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); 1642 } 1643 } 1644 if (itd->transact[i] & ITD_XACT_IOC) { 1645 ehci_raise_irq(ehci, USBSTS_INT); 1646 } 1647 itd->transact[i] &= ~ITD_XACT_ACTIVE; 1648 } 1649 } 1650 return 0; 1651 } 1652 1653 1654 /* This state is the entry point for asynchronous schedule 1655 * processing. Entry here consitutes a EHCI start event state (4.8.5) 1656 */ 1657 static int ehci_state_waitlisthead(EHCIState *ehci, int async) 1658 { 1659 EHCIqh qh; 1660 int i = 0; 1661 int again = 0; 1662 uint32_t entry = ehci->asynclistaddr; 1663 1664 /* set reclamation flag at start event (4.8.6) */ 1665 if (async) { 1666 ehci_set_usbsts(ehci, USBSTS_REC); 1667 } 1668 1669 ehci_queues_rip_unused(ehci, async); 1670 1671 /* Find the head of the list (4.9.1.1) */ 1672 for(i = 0; i < MAX_QH; i++) { 1673 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, 1674 sizeof(EHCIqh) >> 2); 1675 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); 1676 1677 if (qh.epchar & QH_EPCHAR_H) { 1678 if (async) { 1679 entry |= (NLPTR_TYPE_QH << 1); 1680 } 1681 1682 ehci_set_fetch_addr(ehci, async, entry); 1683 ehci_set_state(ehci, async, EST_FETCHENTRY); 1684 again = 1; 1685 goto out; 1686 } 1687 1688 entry = qh.next; 1689 if (entry == ehci->asynclistaddr) { 1690 break; 1691 } 1692 } 1693 1694 /* no head found for list. */ 1695 1696 ehci_set_state(ehci, async, EST_ACTIVE); 1697 1698 out: 1699 return again; 1700 } 1701 1702 1703 /* This state is the entry point for periodic schedule processing as 1704 * well as being a continuation state for async processing. 1705 */ 1706 static int ehci_state_fetchentry(EHCIState *ehci, int async) 1707 { 1708 int again = 0; 1709 uint32_t entry = ehci_get_fetch_addr(ehci, async); 1710 1711 if (NLPTR_TBIT(entry)) { 1712 ehci_set_state(ehci, async, EST_ACTIVE); 1713 goto out; 1714 } 1715 1716 /* section 4.8, only QH in async schedule */ 1717 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { 1718 fprintf(stderr, "non queue head request in async schedule\n"); 1719 return -1; 1720 } 1721 1722 switch (NLPTR_TYPE_GET(entry)) { 1723 case NLPTR_TYPE_QH: 1724 ehci_set_state(ehci, async, EST_FETCHQH); 1725 again = 1; 1726 break; 1727 1728 case NLPTR_TYPE_ITD: 1729 ehci_set_state(ehci, async, EST_FETCHITD); 1730 again = 1; 1731 break; 1732 1733 case NLPTR_TYPE_STITD: 1734 ehci_set_state(ehci, async, EST_FETCHSITD); 1735 again = 1; 1736 break; 1737 1738 default: 1739 /* TODO: handle FSTN type */ 1740 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " 1741 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); 1742 return -1; 1743 } 1744 1745 out: 1746 return again; 1747 } 1748 1749 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) 1750 { 1751 EHCIPacket *p; 1752 uint32_t entry, devaddr; 1753 EHCIQueue *q; 1754 EHCIqh qh; 1755 1756 entry = ehci_get_fetch_addr(ehci, async); 1757 q = ehci_find_queue_by_qh(ehci, entry, async); 1758 if (NULL == q) { 1759 q = ehci_alloc_queue(ehci, entry, async); 1760 } 1761 p = QTAILQ_FIRST(&q->packets); 1762 1763 q->seen++; 1764 if (q->seen > 1) { 1765 /* we are going in circles -- stop processing */ 1766 ehci_set_state(ehci, async, EST_ACTIVE); 1767 q = NULL; 1768 goto out; 1769 } 1770 1771 get_dwords(ehci, NLPTR_GET(q->qhaddr), 1772 (uint32_t *) &qh, sizeof(EHCIqh) >> 2); 1773 if (q->revalidate && (q->qh.epchar != qh.epchar || 1774 q->qh.epcap != qh.epcap || 1775 q->qh.current_qtd != qh.current_qtd)) { 1776 ehci_free_queue(q); 1777 q = ehci_alloc_queue(ehci, entry, async); 1778 q->seen++; 1779 p = NULL; 1780 } 1781 q->qh = qh; 1782 q->revalidate = 0; 1783 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); 1784 1785 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); 1786 if (q->dev != NULL && q->dev->addr != devaddr) { 1787 if (!QTAILQ_EMPTY(&q->packets)) { 1788 /* should not happen (guest bug) */ 1789 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { 1790 ehci_free_packet(p); 1791 } 1792 } 1793 q->dev = NULL; 1794 } 1795 if (q->dev == NULL) { 1796 q->dev = ehci_find_device(q->ehci, devaddr); 1797 } 1798 1799 if (p && p->async == EHCI_ASYNC_INFLIGHT) { 1800 /* I/O still in progress -- skip queue */ 1801 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1802 goto out; 1803 } 1804 if (p && p->async == EHCI_ASYNC_FINISHED) { 1805 /* I/O finished -- continue processing queue */ 1806 trace_usb_ehci_packet_action(p->queue, p, "complete"); 1807 ehci_set_state(ehci, async, EST_EXECUTING); 1808 goto out; 1809 } 1810 1811 if (async && (q->qh.epchar & QH_EPCHAR_H)) { 1812 1813 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ 1814 if (ehci->usbsts & USBSTS_REC) { 1815 ehci_clear_usbsts(ehci, USBSTS_REC); 1816 } else { 1817 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" 1818 " - done processing\n", q->qhaddr); 1819 ehci_set_state(ehci, async, EST_ACTIVE); 1820 q = NULL; 1821 goto out; 1822 } 1823 } 1824 1825 #if EHCI_DEBUG 1826 if (q->qhaddr != q->qh.next) { 1827 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", 1828 q->qhaddr, 1829 q->qh.epchar & QH_EPCHAR_H, 1830 q->qh.token & QTD_TOKEN_HALT, 1831 q->qh.token & QTD_TOKEN_ACTIVE, 1832 q->qh.next); 1833 } 1834 #endif 1835 1836 if (q->qh.token & QTD_TOKEN_HALT) { 1837 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1838 1839 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && 1840 (NLPTR_TBIT(q->qh.current_qtd) == 0)) { 1841 q->qtdaddr = q->qh.current_qtd; 1842 ehci_set_state(ehci, async, EST_FETCHQTD); 1843 1844 } else { 1845 /* EHCI spec version 1.0 Section 4.10.2 */ 1846 ehci_set_state(ehci, async, EST_ADVANCEQUEUE); 1847 } 1848 1849 out: 1850 return q; 1851 } 1852 1853 static int ehci_state_fetchitd(EHCIState *ehci, int async) 1854 { 1855 uint32_t entry; 1856 EHCIitd itd; 1857 1858 assert(!async); 1859 entry = ehci_get_fetch_addr(ehci, async); 1860 1861 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1862 sizeof(EHCIitd) >> 2); 1863 ehci_trace_itd(ehci, entry, &itd); 1864 1865 if (ehci_process_itd(ehci, &itd) != 0) { 1866 return -1; 1867 } 1868 1869 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1870 sizeof(EHCIitd) >> 2); 1871 ehci_set_fetch_addr(ehci, async, itd.next); 1872 ehci_set_state(ehci, async, EST_FETCHENTRY); 1873 1874 return 1; 1875 } 1876 1877 static int ehci_state_fetchsitd(EHCIState *ehci, int async) 1878 { 1879 uint32_t entry; 1880 EHCIsitd sitd; 1881 1882 assert(!async); 1883 entry = ehci_get_fetch_addr(ehci, async); 1884 1885 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, 1886 sizeof(EHCIsitd) >> 2); 1887 ehci_trace_sitd(ehci, entry, &sitd); 1888 1889 if (!(sitd.results & SITD_RESULTS_ACTIVE)) { 1890 /* siTD is not active, nothing to do */; 1891 } else { 1892 /* TODO: split transfers are not implemented */ 1893 fprintf(stderr, "WARNING: Skipping active siTD\n"); 1894 } 1895 1896 ehci_set_fetch_addr(ehci, async, sitd.next); 1897 ehci_set_state(ehci, async, EST_FETCHENTRY); 1898 return 1; 1899 } 1900 1901 /* Section 4.10.2 - paragraph 3 */ 1902 static int ehci_state_advqueue(EHCIQueue *q) 1903 { 1904 #if 0 1905 /* TO-DO: 4.10.2 - paragraph 2 1906 * if I-bit is set to 1 and QH is not active 1907 * go to horizontal QH 1908 */ 1909 if (I-bit set) { 1910 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1911 goto out; 1912 } 1913 #endif 1914 1915 /* 1916 * want data and alt-next qTD is valid 1917 */ 1918 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && 1919 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { 1920 q->qtdaddr = q->qh.altnext_qtd; 1921 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1922 1923 /* 1924 * next qTD is valid 1925 */ 1926 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { 1927 q->qtdaddr = q->qh.next_qtd; 1928 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1929 1930 /* 1931 * no valid qTD, try next QH 1932 */ 1933 } else { 1934 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1935 } 1936 1937 return 1; 1938 } 1939 1940 /* Section 4.10.2 - paragraph 4 */ 1941 static int ehci_state_fetchqtd(EHCIQueue *q) 1942 { 1943 EHCIqtd qtd; 1944 EHCIPacket *p; 1945 int again = 0; 1946 1947 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, 1948 sizeof(EHCIqtd) >> 2); 1949 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); 1950 1951 p = QTAILQ_FIRST(&q->packets); 1952 while (p != NULL && p->qtdaddr != q->qtdaddr) { 1953 /* should not happen (guest bug) */ 1954 ehci_free_packet(p); 1955 p = QTAILQ_FIRST(&q->packets); 1956 } 1957 if (p != NULL) { 1958 ehci_qh_do_overlay(q); 1959 ehci_flush_qh(q); 1960 if (p->async == EHCI_ASYNC_INFLIGHT) { 1961 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1962 } else { 1963 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 1964 } 1965 again = 1; 1966 } else if (qtd.token & QTD_TOKEN_ACTIVE) { 1967 p = ehci_alloc_packet(q); 1968 p->qtdaddr = q->qtdaddr; 1969 p->qtd = qtd; 1970 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 1971 again = 1; 1972 } else { 1973 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1974 again = 1; 1975 } 1976 1977 return again; 1978 } 1979 1980 static int ehci_state_horizqh(EHCIQueue *q) 1981 { 1982 int again = 0; 1983 1984 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { 1985 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); 1986 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); 1987 again = 1; 1988 } else { 1989 ehci_set_state(q->ehci, q->async, EST_ACTIVE); 1990 } 1991 1992 return again; 1993 } 1994 1995 static void ehci_fill_queue(EHCIPacket *p) 1996 { 1997 EHCIQueue *q = p->queue; 1998 EHCIqtd qtd = p->qtd; 1999 uint32_t qtdaddr; 2000 2001 for (;;) { 2002 if (NLPTR_TBIT(qtd.altnext) == 0) { 2003 break; 2004 } 2005 if (NLPTR_TBIT(qtd.next) != 0) { 2006 break; 2007 } 2008 qtdaddr = qtd.next; 2009 get_dwords(q->ehci, NLPTR_GET(qtdaddr), 2010 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); 2011 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); 2012 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 2013 break; 2014 } 2015 p = ehci_alloc_packet(q); 2016 p->qtdaddr = qtdaddr; 2017 p->qtd = qtd; 2018 p->usb_status = ehci_execute(p, "queue"); 2019 assert(p->usb_status == USB_RET_ASYNC); 2020 p->async = EHCI_ASYNC_INFLIGHT; 2021 } 2022 } 2023 2024 static int ehci_state_execute(EHCIQueue *q) 2025 { 2026 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2027 int again = 0; 2028 2029 assert(p != NULL); 2030 assert(p->qtdaddr == q->qtdaddr); 2031 2032 if (ehci_qh_do_overlay(q) != 0) { 2033 return -1; 2034 } 2035 2036 // TODO verify enough time remains in the uframe as in 4.4.1.1 2037 // TODO write back ptr to async list when done or out of time 2038 // TODO Windows does not seem to ever set the MULT field 2039 2040 if (!q->async) { 2041 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); 2042 if (!transactCtr) { 2043 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2044 again = 1; 2045 goto out; 2046 } 2047 } 2048 2049 if (q->async) { 2050 ehci_set_usbsts(q->ehci, USBSTS_REC); 2051 } 2052 2053 p->usb_status = ehci_execute(p, "process"); 2054 if (p->usb_status == USB_RET_PROCERR) { 2055 again = -1; 2056 goto out; 2057 } 2058 if (p->usb_status == USB_RET_ASYNC) { 2059 ehci_flush_qh(q); 2060 trace_usb_ehci_packet_action(p->queue, p, "async"); 2061 p->async = EHCI_ASYNC_INFLIGHT; 2062 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2063 again = 1; 2064 ehci_fill_queue(p); 2065 goto out; 2066 } 2067 2068 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 2069 again = 1; 2070 2071 out: 2072 return again; 2073 } 2074 2075 static int ehci_state_executing(EHCIQueue *q) 2076 { 2077 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2078 int again = 0; 2079 2080 assert(p != NULL); 2081 assert(p->qtdaddr == q->qtdaddr); 2082 2083 ehci_execute_complete(q); 2084 if (p->usb_status == USB_RET_ASYNC) { 2085 goto out; 2086 } 2087 if (p->usb_status == USB_RET_PROCERR) { 2088 again = -1; 2089 goto out; 2090 } 2091 2092 // 4.10.3 2093 if (!q->async) { 2094 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); 2095 transactCtr--; 2096 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); 2097 // 4.10.3, bottom of page 82, should exit this state when transaction 2098 // counter decrements to 0 2099 } 2100 2101 /* 4.10.5 */ 2102 if (p->usb_status == USB_RET_NAK) { 2103 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2104 } else { 2105 ehci_set_state(q->ehci, q->async, EST_WRITEBACK); 2106 } 2107 2108 again = 1; 2109 2110 out: 2111 ehci_flush_qh(q); 2112 return again; 2113 } 2114 2115 2116 static int ehci_state_writeback(EHCIQueue *q) 2117 { 2118 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2119 uint32_t *qtd, addr; 2120 int again = 0; 2121 2122 /* Write back the QTD from the QH area */ 2123 assert(p != NULL); 2124 assert(p->qtdaddr == q->qtdaddr); 2125 2126 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); 2127 qtd = (uint32_t *) &q->qh.next_qtd; 2128 addr = NLPTR_GET(p->qtdaddr); 2129 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); 2130 ehci_free_packet(p); 2131 2132 /* 2133 * EHCI specs say go horizontal here. 2134 * 2135 * We can also advance the queue here for performance reasons. We 2136 * need to take care to only take that shortcut in case we've 2137 * processed the qtd just written back without errors, i.e. halt 2138 * bit is clear. 2139 */ 2140 if (q->qh.token & QTD_TOKEN_HALT) { 2141 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2142 again = 1; 2143 } else { 2144 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); 2145 again = 1; 2146 } 2147 return again; 2148 } 2149 2150 /* 2151 * This is the state machine that is common to both async and periodic 2152 */ 2153 2154 static void ehci_advance_state(EHCIState *ehci, int async) 2155 { 2156 EHCIQueue *q = NULL; 2157 int again; 2158 2159 do { 2160 switch(ehci_get_state(ehci, async)) { 2161 case EST_WAITLISTHEAD: 2162 again = ehci_state_waitlisthead(ehci, async); 2163 break; 2164 2165 case EST_FETCHENTRY: 2166 again = ehci_state_fetchentry(ehci, async); 2167 break; 2168 2169 case EST_FETCHQH: 2170 q = ehci_state_fetchqh(ehci, async); 2171 if (q != NULL) { 2172 assert(q->async == async); 2173 again = 1; 2174 } else { 2175 again = 0; 2176 } 2177 break; 2178 2179 case EST_FETCHITD: 2180 again = ehci_state_fetchitd(ehci, async); 2181 break; 2182 2183 case EST_FETCHSITD: 2184 again = ehci_state_fetchsitd(ehci, async); 2185 break; 2186 2187 case EST_ADVANCEQUEUE: 2188 again = ehci_state_advqueue(q); 2189 break; 2190 2191 case EST_FETCHQTD: 2192 again = ehci_state_fetchqtd(q); 2193 break; 2194 2195 case EST_HORIZONTALQH: 2196 again = ehci_state_horizqh(q); 2197 break; 2198 2199 case EST_EXECUTE: 2200 again = ehci_state_execute(q); 2201 if (async) { 2202 ehci->async_stepdown = 0; 2203 } 2204 break; 2205 2206 case EST_EXECUTING: 2207 assert(q != NULL); 2208 if (async) { 2209 ehci->async_stepdown = 0; 2210 } 2211 again = ehci_state_executing(q); 2212 break; 2213 2214 case EST_WRITEBACK: 2215 assert(q != NULL); 2216 again = ehci_state_writeback(q); 2217 break; 2218 2219 default: 2220 fprintf(stderr, "Bad state!\n"); 2221 again = -1; 2222 assert(0); 2223 break; 2224 } 2225 2226 if (again < 0) { 2227 fprintf(stderr, "processing error - resetting ehci HC\n"); 2228 ehci_reset(ehci); 2229 again = 0; 2230 } 2231 } 2232 while (again); 2233 } 2234 2235 static void ehci_advance_async_state(EHCIState *ehci) 2236 { 2237 const int async = 1; 2238 2239 switch(ehci_get_state(ehci, async)) { 2240 case EST_INACTIVE: 2241 if (!ehci_async_enabled(ehci)) { 2242 break; 2243 } 2244 ehci_set_state(ehci, async, EST_ACTIVE); 2245 // No break, fall through to ACTIVE 2246 2247 case EST_ACTIVE: 2248 if (!ehci_async_enabled(ehci)) { 2249 ehci_queues_rip_all(ehci, async); 2250 ehci_set_state(ehci, async, EST_INACTIVE); 2251 break; 2252 } 2253 2254 /* make sure guest has acknowledged the doorbell interrupt */ 2255 /* TO-DO: is this really needed? */ 2256 if (ehci->usbsts & USBSTS_IAA) { 2257 DPRINTF("IAA status bit still set.\n"); 2258 break; 2259 } 2260 2261 /* check that address register has been set */ 2262 if (ehci->asynclistaddr == 0) { 2263 break; 2264 } 2265 2266 ehci_set_state(ehci, async, EST_WAITLISTHEAD); 2267 ehci_advance_state(ehci, async); 2268 2269 /* If the doorbell is set, the guest wants to make a change to the 2270 * schedule. The host controller needs to release cached data. 2271 * (section 4.8.2) 2272 */ 2273 if (ehci->usbcmd & USBCMD_IAAD) { 2274 /* Remove all unseen qhs from the async qhs queue */ 2275 ehci_queues_tag_unused_async(ehci); 2276 DPRINTF("ASYNC: doorbell request acknowledged\n"); 2277 ehci->usbcmd &= ~USBCMD_IAAD; 2278 ehci_raise_irq(ehci, USBSTS_IAA); 2279 } 2280 break; 2281 2282 default: 2283 /* this should only be due to a developer mistake */ 2284 fprintf(stderr, "ehci: Bad asynchronous state %d. " 2285 "Resetting to active\n", ehci->astate); 2286 assert(0); 2287 } 2288 } 2289 2290 static void ehci_advance_periodic_state(EHCIState *ehci) 2291 { 2292 uint32_t entry; 2293 uint32_t list; 2294 const int async = 0; 2295 2296 // 4.6 2297 2298 switch(ehci_get_state(ehci, async)) { 2299 case EST_INACTIVE: 2300 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { 2301 ehci_set_state(ehci, async, EST_ACTIVE); 2302 // No break, fall through to ACTIVE 2303 } else 2304 break; 2305 2306 case EST_ACTIVE: 2307 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { 2308 ehci_queues_rip_all(ehci, async); 2309 ehci_set_state(ehci, async, EST_INACTIVE); 2310 break; 2311 } 2312 2313 list = ehci->periodiclistbase & 0xfffff000; 2314 /* check that register has been set */ 2315 if (list == 0) { 2316 break; 2317 } 2318 list |= ((ehci->frindex & 0x1ff8) >> 1); 2319 2320 pci_dma_read(&ehci->dev, list, &entry, sizeof entry); 2321 entry = le32_to_cpu(entry); 2322 2323 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", 2324 ehci->frindex / 8, list, entry); 2325 ehci_set_fetch_addr(ehci, async,entry); 2326 ehci_set_state(ehci, async, EST_FETCHENTRY); 2327 ehci_advance_state(ehci, async); 2328 ehci_queues_rip_unused(ehci, async); 2329 break; 2330 2331 default: 2332 /* this should only be due to a developer mistake */ 2333 fprintf(stderr, "ehci: Bad periodic state %d. " 2334 "Resetting to active\n", ehci->pstate); 2335 assert(0); 2336 } 2337 } 2338 2339 static void ehci_update_frindex(EHCIState *ehci, int frames) 2340 { 2341 int i; 2342 2343 if (!ehci_enabled(ehci)) { 2344 return; 2345 } 2346 2347 for (i = 0; i < frames; i++) { 2348 ehci->frindex += 8; 2349 2350 if (ehci->frindex == 0x00002000) { 2351 ehci_raise_irq(ehci, USBSTS_FLR); 2352 } 2353 2354 if (ehci->frindex == 0x00004000) { 2355 ehci_raise_irq(ehci, USBSTS_FLR); 2356 ehci->frindex = 0; 2357 if (ehci->usbsts_frindex > 0x00004000) { 2358 ehci->usbsts_frindex -= 0x00004000; 2359 } else { 2360 ehci->usbsts_frindex = 0; 2361 } 2362 } 2363 } 2364 } 2365 2366 static void ehci_frame_timer(void *opaque) 2367 { 2368 EHCIState *ehci = opaque; 2369 int need_timer = 0; 2370 int64_t expire_time, t_now; 2371 uint64_t ns_elapsed; 2372 int frames, skipped_frames; 2373 int i; 2374 2375 t_now = qemu_get_clock_ns(vm_clock); 2376 ns_elapsed = t_now - ehci->last_run_ns; 2377 frames = ns_elapsed / FRAME_TIMER_NS; 2378 2379 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { 2380 need_timer++; 2381 ehci->async_stepdown = 0; 2382 2383 if (frames > ehci->maxframes) { 2384 skipped_frames = frames - ehci->maxframes; 2385 ehci_update_frindex(ehci, skipped_frames); 2386 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; 2387 frames -= skipped_frames; 2388 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); 2389 } 2390 2391 for (i = 0; i < frames; i++) { 2392 ehci_update_frindex(ehci, 1); 2393 ehci_advance_periodic_state(ehci); 2394 ehci->last_run_ns += FRAME_TIMER_NS; 2395 } 2396 } else { 2397 if (ehci->async_stepdown < ehci->maxframes / 2) { 2398 ehci->async_stepdown++; 2399 } 2400 ehci_update_frindex(ehci, frames); 2401 ehci->last_run_ns += FRAME_TIMER_NS * frames; 2402 } 2403 2404 /* Async is not inside loop since it executes everything it can once 2405 * called 2406 */ 2407 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { 2408 need_timer++; 2409 ehci_advance_async_state(ehci); 2410 } 2411 2412 ehci_commit_irq(ehci); 2413 if (ehci->usbsts_pending) { 2414 need_timer++; 2415 ehci->async_stepdown = 0; 2416 } 2417 2418 if (need_timer) { 2419 expire_time = t_now + (get_ticks_per_sec() 2420 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); 2421 qemu_mod_timer(ehci->frame_timer, expire_time); 2422 } 2423 } 2424 2425 static void ehci_async_bh(void *opaque) 2426 { 2427 EHCIState *ehci = opaque; 2428 ehci_advance_async_state(ehci); 2429 } 2430 2431 static const MemoryRegionOps ehci_mem_ops = { 2432 .old_mmio = { 2433 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, 2434 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, 2435 }, 2436 .endianness = DEVICE_LITTLE_ENDIAN, 2437 }; 2438 2439 static int usb_ehci_initfn(PCIDevice *dev); 2440 2441 static USBPortOps ehci_port_ops = { 2442 .attach = ehci_attach, 2443 .detach = ehci_detach, 2444 .child_detach = ehci_child_detach, 2445 .wakeup = ehci_wakeup, 2446 .complete = ehci_async_complete_packet, 2447 }; 2448 2449 static USBBusOps ehci_bus_ops = { 2450 .register_companion = ehci_register_companion, 2451 }; 2452 2453 static int usb_ehci_post_load(void *opaque, int version_id) 2454 { 2455 EHCIState *s = opaque; 2456 int i; 2457 2458 for (i = 0; i < NB_PORTS; i++) { 2459 USBPort *companion = s->companion_ports[i]; 2460 if (companion == NULL) { 2461 continue; 2462 } 2463 if (s->portsc[i] & PORTSC_POWNER) { 2464 companion->dev = s->ports[i].dev; 2465 } else { 2466 companion->dev = NULL; 2467 } 2468 } 2469 2470 return 0; 2471 } 2472 2473 static const VMStateDescription vmstate_ehci = { 2474 .name = "ehci", 2475 .version_id = 2, 2476 .minimum_version_id = 1, 2477 .post_load = usb_ehci_post_load, 2478 .fields = (VMStateField[]) { 2479 VMSTATE_PCI_DEVICE(dev, EHCIState), 2480 /* mmio registers */ 2481 VMSTATE_UINT32(usbcmd, EHCIState), 2482 VMSTATE_UINT32(usbsts, EHCIState), 2483 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), 2484 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), 2485 VMSTATE_UINT32(usbintr, EHCIState), 2486 VMSTATE_UINT32(frindex, EHCIState), 2487 VMSTATE_UINT32(ctrldssegment, EHCIState), 2488 VMSTATE_UINT32(periodiclistbase, EHCIState), 2489 VMSTATE_UINT32(asynclistaddr, EHCIState), 2490 VMSTATE_UINT32(configflag, EHCIState), 2491 VMSTATE_UINT32(portsc[0], EHCIState), 2492 VMSTATE_UINT32(portsc[1], EHCIState), 2493 VMSTATE_UINT32(portsc[2], EHCIState), 2494 VMSTATE_UINT32(portsc[3], EHCIState), 2495 VMSTATE_UINT32(portsc[4], EHCIState), 2496 VMSTATE_UINT32(portsc[5], EHCIState), 2497 /* frame timer */ 2498 VMSTATE_TIMER(frame_timer, EHCIState), 2499 VMSTATE_UINT64(last_run_ns, EHCIState), 2500 VMSTATE_UINT32(async_stepdown, EHCIState), 2501 /* schedule state */ 2502 VMSTATE_UINT32(astate, EHCIState), 2503 VMSTATE_UINT32(pstate, EHCIState), 2504 VMSTATE_UINT32(a_fetch_addr, EHCIState), 2505 VMSTATE_UINT32(p_fetch_addr, EHCIState), 2506 VMSTATE_END_OF_LIST() 2507 } 2508 }; 2509 2510 static Property ehci_properties[] = { 2511 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), 2512 DEFINE_PROP_END_OF_LIST(), 2513 }; 2514 2515 static void ehci_class_init(ObjectClass *klass, void *data) 2516 { 2517 DeviceClass *dc = DEVICE_CLASS(klass); 2518 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2519 2520 k->init = usb_ehci_initfn; 2521 k->vendor_id = PCI_VENDOR_ID_INTEL; 2522 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ 2523 k->revision = 0x10; 2524 k->class_id = PCI_CLASS_SERIAL_USB; 2525 dc->vmsd = &vmstate_ehci; 2526 dc->props = ehci_properties; 2527 } 2528 2529 static TypeInfo ehci_info = { 2530 .name = "usb-ehci", 2531 .parent = TYPE_PCI_DEVICE, 2532 .instance_size = sizeof(EHCIState), 2533 .class_init = ehci_class_init, 2534 }; 2535 2536 static void ich9_ehci_class_init(ObjectClass *klass, void *data) 2537 { 2538 DeviceClass *dc = DEVICE_CLASS(klass); 2539 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2540 2541 k->init = usb_ehci_initfn; 2542 k->vendor_id = PCI_VENDOR_ID_INTEL; 2543 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; 2544 k->revision = 0x03; 2545 k->class_id = PCI_CLASS_SERIAL_USB; 2546 dc->vmsd = &vmstate_ehci; 2547 dc->props = ehci_properties; 2548 } 2549 2550 static TypeInfo ich9_ehci_info = { 2551 .name = "ich9-usb-ehci1", 2552 .parent = TYPE_PCI_DEVICE, 2553 .instance_size = sizeof(EHCIState), 2554 .class_init = ich9_ehci_class_init, 2555 }; 2556 2557 static int usb_ehci_initfn(PCIDevice *dev) 2558 { 2559 EHCIState *s = DO_UPCAST(EHCIState, dev, dev); 2560 uint8_t *pci_conf = s->dev.config; 2561 int i; 2562 2563 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); 2564 2565 /* capabilities pointer */ 2566 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); 2567 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); 2568 2569 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ 2570 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); 2571 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); 2572 2573 // pci_conf[0x50] = 0x01; // power management caps 2574 2575 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) 2576 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) 2577 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) 2578 2579 pci_conf[0x64] = 0x00; 2580 pci_conf[0x65] = 0x00; 2581 pci_conf[0x66] = 0x00; 2582 pci_conf[0x67] = 0x00; 2583 pci_conf[0x68] = 0x01; 2584 pci_conf[0x69] = 0x00; 2585 pci_conf[0x6a] = 0x00; 2586 pci_conf[0x6b] = 0x00; // USBLEGSUP 2587 pci_conf[0x6c] = 0x00; 2588 pci_conf[0x6d] = 0x00; 2589 pci_conf[0x6e] = 0x00; 2590 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS 2591 2592 // 2.2 host controller interface version 2593 s->mmio[0x00] = (uint8_t) OPREGBASE; 2594 s->mmio[0x01] = 0x00; 2595 s->mmio[0x02] = 0x00; 2596 s->mmio[0x03] = 0x01; // HC version 2597 s->mmio[0x04] = NB_PORTS; // Number of downstream ports 2598 s->mmio[0x05] = 0x00; // No companion ports at present 2599 s->mmio[0x06] = 0x00; 2600 s->mmio[0x07] = 0x00; 2601 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable 2602 s->mmio[0x09] = 0x68; // EECP 2603 s->mmio[0x0a] = 0x00; 2604 s->mmio[0x0b] = 0x00; 2605 2606 s->irq = s->dev.irq[3]; 2607 2608 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); 2609 for(i = 0; i < NB_PORTS; i++) { 2610 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, 2611 USB_SPEED_MASK_HIGH); 2612 s->ports[i].dev = 0; 2613 } 2614 2615 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); 2616 s->async_bh = qemu_bh_new(ehci_async_bh, s); 2617 QTAILQ_INIT(&s->aqueues); 2618 QTAILQ_INIT(&s->pqueues); 2619 usb_packet_init(&s->ipacket); 2620 2621 qemu_register_reset(ehci_reset, s); 2622 2623 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); 2624 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); 2625 2626 return 0; 2627 } 2628 2629 static void ehci_register_types(void) 2630 { 2631 type_register_static(&ehci_info); 2632 type_register_static(&ich9_ehci_info); 2633 } 2634 2635 type_init(ehci_register_types) 2636 2637 /* 2638 * vim: expandtab ts=4 2639 */ 2640