1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * Copyright(c) 2008 Emutex Ltd. (address@hidden) 5 * Copyright(c) 2011-2012 Red Hat, Inc. 6 * 7 * Red Hat Authors: 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * Hans de Goede <hdegoede@redhat.com> 10 * 11 * EHCI project was started by Mark Burkley, with contributions by 12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, 13 * Jan Kiszka and Vincent Palatin contributed bugfixes. 14 * 15 * 16 * This library is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU Lesser General Public 18 * License as published by the Free Software Foundation; either 19 * version 2 of the License, or(at your option) any later version. 20 * 21 * This library is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * Lesser General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, see <http://www.gnu.org/licenses/>. 28 */ 29 30 #include "hw/hw.h" 31 #include "qemu-timer.h" 32 #include "hw/usb.h" 33 #include "hw/pci.h" 34 #include "monitor.h" 35 #include "trace.h" 36 #include "dma.h" 37 #include "sysemu.h" 38 39 #define EHCI_DEBUG 0 40 41 #if EHCI_DEBUG 42 #define DPRINTF printf 43 #else 44 #define DPRINTF(...) 45 #endif 46 47 /* internal processing - reset HC to try and recover */ 48 #define USB_RET_PROCERR (-99) 49 50 #define MMIO_SIZE 0x1000 51 52 /* Capability Registers Base Address - section 2.2 */ 53 #define CAPREGBASE 0x0000 54 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved 55 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # 56 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params 57 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params 58 #define EECP HCCPARAMS + 1 59 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c 60 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 61 62 #define OPREGBASE 0x0020 // Operational Registers Base Address 63 64 #define USBCMD OPREGBASE + 0x0000 65 #define USBCMD_RUNSTOP (1 << 0) // run / Stop 66 #define USBCMD_HCRESET (1 << 1) // HC Reset 67 #define USBCMD_FLS (3 << 2) // Frame List Size 68 #define USBCMD_FLS_SH 2 // Frame List Size Shift 69 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable 70 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable 71 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell 72 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset 73 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count 74 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable 75 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control 76 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift 77 78 #define USBSTS OPREGBASE + 0x0004 79 #define USBSTS_RO_MASK 0x0000003f 80 #define USBSTS_INT (1 << 0) // USB Interrupt 81 #define USBSTS_ERRINT (1 << 1) // Error Interrupt 82 #define USBSTS_PCD (1 << 2) // Port Change Detect 83 #define USBSTS_FLR (1 << 3) // Frame List Rollover 84 #define USBSTS_HSE (1 << 4) // Host System Error 85 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance 86 #define USBSTS_HALT (1 << 12) // HC Halted 87 #define USBSTS_REC (1 << 13) // Reclamation 88 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status 89 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status 90 91 /* 92 * Interrupt enable bits correspond to the interrupt active bits in USBSTS 93 * so no need to redefine here. 94 */ 95 #define USBINTR OPREGBASE + 0x0008 96 #define USBINTR_MASK 0x0000003f 97 98 #define FRINDEX OPREGBASE + 0x000c 99 #define CTRLDSSEGMENT OPREGBASE + 0x0010 100 #define PERIODICLISTBASE OPREGBASE + 0x0014 101 #define ASYNCLISTADDR OPREGBASE + 0x0018 102 #define ASYNCLISTADDR_MASK 0xffffffe0 103 104 #define CONFIGFLAG OPREGBASE + 0x0040 105 106 #define PORTSC (OPREGBASE + 0x0044) 107 #define PORTSC_BEGIN PORTSC 108 #define PORTSC_END (PORTSC + 4 * NB_PORTS) 109 /* 110 * Bits that are reserved or are read-only are masked out of values 111 * written to us by software 112 */ 113 #define PORTSC_RO_MASK 0x007001c0 114 #define PORTSC_RWC_MASK 0x0000002a 115 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable 116 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable 117 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable 118 #define PORTSC_PTC (15 << 16) // Port Test Control 119 #define PORTSC_PTC_SH 16 // Port Test Control shift 120 #define PORTSC_PIC (3 << 14) // Port Indicator Control 121 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift 122 #define PORTSC_POWNER (1 << 13) // Port Owner 123 #define PORTSC_PPOWER (1 << 12) // Port Power 124 #define PORTSC_LINESTAT (3 << 10) // Port Line Status 125 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift 126 #define PORTSC_PRESET (1 << 8) // Port Reset 127 #define PORTSC_SUSPEND (1 << 7) // Port Suspend 128 #define PORTSC_FPRES (1 << 6) // Force Port Resume 129 #define PORTSC_OCC (1 << 5) // Over Current Change 130 #define PORTSC_OCA (1 << 4) // Over Current Active 131 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change 132 #define PORTSC_PED (1 << 2) // Port Enable/Disable 133 #define PORTSC_CSC (1 << 1) // Connect Status Change 134 #define PORTSC_CONNECT (1 << 0) // Current Connect Status 135 136 #define FRAME_TIMER_FREQ 1000 137 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) 138 139 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints 140 #define NB_PORTS 6 // Number of downstream ports 141 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction 142 #define MAX_QH 100 // Max allowable queue heads in a chain 143 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up 144 145 /* Internal periodic / asynchronous schedule state machine states 146 */ 147 typedef enum { 148 EST_INACTIVE = 1000, 149 EST_ACTIVE, 150 EST_EXECUTING, 151 EST_SLEEPING, 152 /* The following states are internal to the state machine function 153 */ 154 EST_WAITLISTHEAD, 155 EST_FETCHENTRY, 156 EST_FETCHQH, 157 EST_FETCHITD, 158 EST_FETCHSITD, 159 EST_ADVANCEQUEUE, 160 EST_FETCHQTD, 161 EST_EXECUTE, 162 EST_WRITEBACK, 163 EST_HORIZONTALQH 164 } EHCI_STATES; 165 166 /* macros for accessing fields within next link pointer entry */ 167 #define NLPTR_GET(x) ((x) & 0xffffffe0) 168 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) 169 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid 170 171 /* link pointer types */ 172 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor 173 #define NLPTR_TYPE_QH 1 // queue head 174 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor 175 #define NLPTR_TYPE_FSTN 3 // frame span traversal node 176 177 178 /* EHCI spec version 1.0 Section 3.3 179 */ 180 typedef struct EHCIitd { 181 uint32_t next; 182 183 uint32_t transact[8]; 184 #define ITD_XACT_ACTIVE (1 << 31) 185 #define ITD_XACT_DBERROR (1 << 30) 186 #define ITD_XACT_BABBLE (1 << 29) 187 #define ITD_XACT_XACTERR (1 << 28) 188 #define ITD_XACT_LENGTH_MASK 0x0fff0000 189 #define ITD_XACT_LENGTH_SH 16 190 #define ITD_XACT_IOC (1 << 15) 191 #define ITD_XACT_PGSEL_MASK 0x00007000 192 #define ITD_XACT_PGSEL_SH 12 193 #define ITD_XACT_OFFSET_MASK 0x00000fff 194 195 uint32_t bufptr[7]; 196 #define ITD_BUFPTR_MASK 0xfffff000 197 #define ITD_BUFPTR_SH 12 198 #define ITD_BUFPTR_EP_MASK 0x00000f00 199 #define ITD_BUFPTR_EP_SH 8 200 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f 201 #define ITD_BUFPTR_DEVADDR_SH 0 202 #define ITD_BUFPTR_DIRECTION (1 << 11) 203 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff 204 #define ITD_BUFPTR_MAXPKT_SH 0 205 #define ITD_BUFPTR_MULT_MASK 0x00000003 206 #define ITD_BUFPTR_MULT_SH 0 207 } EHCIitd; 208 209 /* EHCI spec version 1.0 Section 3.4 210 */ 211 typedef struct EHCIsitd { 212 uint32_t next; // Standard next link pointer 213 uint32_t epchar; 214 #define SITD_EPCHAR_IO (1 << 31) 215 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 216 #define SITD_EPCHAR_PORTNUM_SH 24 217 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 218 #define SITD_EPCHAR_HUBADDR_SH 16 219 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 220 #define SITD_EPCHAR_EPNUM_SH 8 221 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f 222 223 uint32_t uframe; 224 #define SITD_UFRAME_CMASK_MASK 0x0000ff00 225 #define SITD_UFRAME_CMASK_SH 8 226 #define SITD_UFRAME_SMASK_MASK 0x000000ff 227 228 uint32_t results; 229 #define SITD_RESULTS_IOC (1 << 31) 230 #define SITD_RESULTS_PGSEL (1 << 30) 231 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 232 #define SITD_RESULTS_TYBYTES_SH 16 233 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 234 #define SITD_RESULTS_CPROGMASK_SH 8 235 #define SITD_RESULTS_ACTIVE (1 << 7) 236 #define SITD_RESULTS_ERR (1 << 6) 237 #define SITD_RESULTS_DBERR (1 << 5) 238 #define SITD_RESULTS_BABBLE (1 << 4) 239 #define SITD_RESULTS_XACTERR (1 << 3) 240 #define SITD_RESULTS_MISSEDUF (1 << 2) 241 #define SITD_RESULTS_SPLITXSTATE (1 << 1) 242 243 uint32_t bufptr[2]; 244 #define SITD_BUFPTR_MASK 0xfffff000 245 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff 246 #define SITD_BUFPTR_TPOS_MASK 0x00000018 247 #define SITD_BUFPTR_TPOS_SH 3 248 #define SITD_BUFPTR_TCNT_MASK 0x00000007 249 250 uint32_t backptr; // Standard next link pointer 251 } EHCIsitd; 252 253 /* EHCI spec version 1.0 Section 3.5 254 */ 255 typedef struct EHCIqtd { 256 uint32_t next; // Standard next link pointer 257 uint32_t altnext; // Standard next link pointer 258 uint32_t token; 259 #define QTD_TOKEN_DTOGGLE (1 << 31) 260 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 261 #define QTD_TOKEN_TBYTES_SH 16 262 #define QTD_TOKEN_IOC (1 << 15) 263 #define QTD_TOKEN_CPAGE_MASK 0x00007000 264 #define QTD_TOKEN_CPAGE_SH 12 265 #define QTD_TOKEN_CERR_MASK 0x00000c00 266 #define QTD_TOKEN_CERR_SH 10 267 #define QTD_TOKEN_PID_MASK 0x00000300 268 #define QTD_TOKEN_PID_SH 8 269 #define QTD_TOKEN_ACTIVE (1 << 7) 270 #define QTD_TOKEN_HALT (1 << 6) 271 #define QTD_TOKEN_DBERR (1 << 5) 272 #define QTD_TOKEN_BABBLE (1 << 4) 273 #define QTD_TOKEN_XACTERR (1 << 3) 274 #define QTD_TOKEN_MISSEDUF (1 << 2) 275 #define QTD_TOKEN_SPLITXSTATE (1 << 1) 276 #define QTD_TOKEN_PING (1 << 0) 277 278 uint32_t bufptr[5]; // Standard buffer pointer 279 #define QTD_BUFPTR_MASK 0xfffff000 280 #define QTD_BUFPTR_SH 12 281 } EHCIqtd; 282 283 /* EHCI spec version 1.0 Section 3.6 284 */ 285 typedef struct EHCIqh { 286 uint32_t next; // Standard next link pointer 287 288 /* endpoint characteristics */ 289 uint32_t epchar; 290 #define QH_EPCHAR_RL_MASK 0xf0000000 291 #define QH_EPCHAR_RL_SH 28 292 #define QH_EPCHAR_C (1 << 27) 293 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 294 #define QH_EPCHAR_MPLEN_SH 16 295 #define QH_EPCHAR_H (1 << 15) 296 #define QH_EPCHAR_DTC (1 << 14) 297 #define QH_EPCHAR_EPS_MASK 0x00003000 298 #define QH_EPCHAR_EPS_SH 12 299 #define EHCI_QH_EPS_FULL 0 300 #define EHCI_QH_EPS_LOW 1 301 #define EHCI_QH_EPS_HIGH 2 302 #define EHCI_QH_EPS_RESERVED 3 303 304 #define QH_EPCHAR_EP_MASK 0x00000f00 305 #define QH_EPCHAR_EP_SH 8 306 #define QH_EPCHAR_I (1 << 7) 307 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f 308 #define QH_EPCHAR_DEVADDR_SH 0 309 310 /* endpoint capabilities */ 311 uint32_t epcap; 312 #define QH_EPCAP_MULT_MASK 0xc0000000 313 #define QH_EPCAP_MULT_SH 30 314 #define QH_EPCAP_PORTNUM_MASK 0x3f800000 315 #define QH_EPCAP_PORTNUM_SH 23 316 #define QH_EPCAP_HUBADDR_MASK 0x007f0000 317 #define QH_EPCAP_HUBADDR_SH 16 318 #define QH_EPCAP_CMASK_MASK 0x0000ff00 319 #define QH_EPCAP_CMASK_SH 8 320 #define QH_EPCAP_SMASK_MASK 0x000000ff 321 #define QH_EPCAP_SMASK_SH 0 322 323 uint32_t current_qtd; // Standard next link pointer 324 uint32_t next_qtd; // Standard next link pointer 325 uint32_t altnext_qtd; 326 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e 327 #define QH_ALTNEXT_NAKCNT_SH 1 328 329 uint32_t token; // Same as QTD token 330 uint32_t bufptr[5]; // Standard buffer pointer 331 #define BUFPTR_CPROGMASK_MASK 0x000000ff 332 #define BUFPTR_FRAMETAG_MASK 0x0000001f 333 #define BUFPTR_SBYTES_MASK 0x00000fe0 334 #define BUFPTR_SBYTES_SH 5 335 } EHCIqh; 336 337 /* EHCI spec version 1.0 Section 3.7 338 */ 339 typedef struct EHCIfstn { 340 uint32_t next; // Standard next link pointer 341 uint32_t backptr; // Standard next link pointer 342 } EHCIfstn; 343 344 typedef struct EHCIPacket EHCIPacket; 345 typedef struct EHCIQueue EHCIQueue; 346 typedef struct EHCIState EHCIState; 347 348 enum async_state { 349 EHCI_ASYNC_NONE = 0, 350 EHCI_ASYNC_INITIALIZED, 351 EHCI_ASYNC_INFLIGHT, 352 EHCI_ASYNC_FINISHED, 353 }; 354 355 struct EHCIPacket { 356 EHCIQueue *queue; 357 QTAILQ_ENTRY(EHCIPacket) next; 358 359 EHCIqtd qtd; /* copy of current QTD (being worked on) */ 360 uint32_t qtdaddr; /* address QTD read from */ 361 362 USBPacket packet; 363 QEMUSGList sgl; 364 int pid; 365 uint32_t tbytes; 366 enum async_state async; 367 int usb_status; 368 }; 369 370 struct EHCIQueue { 371 EHCIState *ehci; 372 QTAILQ_ENTRY(EHCIQueue) next; 373 uint32_t seen; 374 uint64_t ts; 375 int async; 376 int transact_ctr; 377 378 /* cached data from guest - needs to be flushed 379 * when guest removes an entry (doorbell, handshake sequence) 380 */ 381 EHCIqh qh; /* copy of current QH (being worked on) */ 382 uint32_t qhaddr; /* address QH read from */ 383 uint32_t qtdaddr; /* address QTD read from */ 384 USBDevice *dev; 385 QTAILQ_HEAD(, EHCIPacket) packets; 386 }; 387 388 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; 389 390 struct EHCIState { 391 PCIDevice dev; 392 USBBus bus; 393 qemu_irq irq; 394 MemoryRegion mem; 395 MemoryRegion mem_caps; 396 MemoryRegion mem_opreg; 397 MemoryRegion mem_ports; 398 int companion_count; 399 400 /* properties */ 401 uint32_t maxframes; 402 403 /* 404 * EHCI spec version 1.0 Section 2.3 405 * Host Controller Operational Registers 406 */ 407 uint8_t caps[OPREGBASE]; 408 union { 409 uint32_t opreg[(PORTSC_BEGIN-OPREGBASE)/sizeof(uint32_t)]; 410 struct { 411 uint32_t usbcmd; 412 uint32_t usbsts; 413 uint32_t usbintr; 414 uint32_t frindex; 415 uint32_t ctrldssegment; 416 uint32_t periodiclistbase; 417 uint32_t asynclistaddr; 418 uint32_t notused[9]; 419 uint32_t configflag; 420 }; 421 }; 422 uint32_t portsc[NB_PORTS]; 423 424 /* 425 * Internal states, shadow registers, etc 426 */ 427 QEMUTimer *frame_timer; 428 QEMUBH *async_bh; 429 uint32_t astate; /* Current state in asynchronous schedule */ 430 uint32_t pstate; /* Current state in periodic schedule */ 431 USBPort ports[NB_PORTS]; 432 USBPort *companion_ports[NB_PORTS]; 433 uint32_t usbsts_pending; 434 uint32_t usbsts_frindex; 435 EHCIQueueHead aqueues; 436 EHCIQueueHead pqueues; 437 438 /* which address to look at next */ 439 uint32_t a_fetch_addr; 440 uint32_t p_fetch_addr; 441 442 USBPacket ipacket; 443 QEMUSGList isgl; 444 445 uint64_t last_run_ns; 446 uint32_t async_stepdown; 447 }; 448 449 #define SET_LAST_RUN_CLOCK(s) \ 450 (s)->last_run_ns = qemu_get_clock_ns(vm_clock); 451 452 /* nifty macros from Arnon's EHCI version */ 453 #define get_field(data, field) \ 454 (((data) & field##_MASK) >> field##_SH) 455 456 #define set_field(data, newval, field) do { \ 457 uint32_t val = *data; \ 458 val &= ~ field##_MASK; \ 459 val |= ((newval) << field##_SH) & field##_MASK; \ 460 *data = val; \ 461 } while(0) 462 463 static const char *ehci_state_names[] = { 464 [EST_INACTIVE] = "INACTIVE", 465 [EST_ACTIVE] = "ACTIVE", 466 [EST_EXECUTING] = "EXECUTING", 467 [EST_SLEEPING] = "SLEEPING", 468 [EST_WAITLISTHEAD] = "WAITLISTHEAD", 469 [EST_FETCHENTRY] = "FETCH ENTRY", 470 [EST_FETCHQH] = "FETCH QH", 471 [EST_FETCHITD] = "FETCH ITD", 472 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", 473 [EST_FETCHQTD] = "FETCH QTD", 474 [EST_EXECUTE] = "EXECUTE", 475 [EST_WRITEBACK] = "WRITEBACK", 476 [EST_HORIZONTALQH] = "HORIZONTALQH", 477 }; 478 479 static const char *ehci_mmio_names[] = { 480 [USBCMD] = "USBCMD", 481 [USBSTS] = "USBSTS", 482 [USBINTR] = "USBINTR", 483 [FRINDEX] = "FRINDEX", 484 [PERIODICLISTBASE] = "P-LIST BASE", 485 [ASYNCLISTADDR] = "A-LIST ADDR", 486 [CONFIGFLAG] = "CONFIGFLAG", 487 }; 488 489 static int ehci_state_executing(EHCIQueue *q); 490 static int ehci_state_writeback(EHCIQueue *q); 491 492 static const char *nr2str(const char **n, size_t len, uint32_t nr) 493 { 494 if (nr < len && n[nr] != NULL) { 495 return n[nr]; 496 } else { 497 return "unknown"; 498 } 499 } 500 501 static const char *state2str(uint32_t state) 502 { 503 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); 504 } 505 506 static const char *addr2str(hwaddr addr) 507 { 508 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), 509 addr + OPREGBASE); 510 } 511 512 static void ehci_trace_usbsts(uint32_t mask, int state) 513 { 514 /* interrupts */ 515 if (mask & USBSTS_INT) { 516 trace_usb_ehci_usbsts("INT", state); 517 } 518 if (mask & USBSTS_ERRINT) { 519 trace_usb_ehci_usbsts("ERRINT", state); 520 } 521 if (mask & USBSTS_PCD) { 522 trace_usb_ehci_usbsts("PCD", state); 523 } 524 if (mask & USBSTS_FLR) { 525 trace_usb_ehci_usbsts("FLR", state); 526 } 527 if (mask & USBSTS_HSE) { 528 trace_usb_ehci_usbsts("HSE", state); 529 } 530 if (mask & USBSTS_IAA) { 531 trace_usb_ehci_usbsts("IAA", state); 532 } 533 534 /* status */ 535 if (mask & USBSTS_HALT) { 536 trace_usb_ehci_usbsts("HALT", state); 537 } 538 if (mask & USBSTS_REC) { 539 trace_usb_ehci_usbsts("REC", state); 540 } 541 if (mask & USBSTS_PSS) { 542 trace_usb_ehci_usbsts("PSS", state); 543 } 544 if (mask & USBSTS_ASS) { 545 trace_usb_ehci_usbsts("ASS", state); 546 } 547 } 548 549 static inline void ehci_set_usbsts(EHCIState *s, int mask) 550 { 551 if ((s->usbsts & mask) == mask) { 552 return; 553 } 554 ehci_trace_usbsts(mask, 1); 555 s->usbsts |= mask; 556 } 557 558 static inline void ehci_clear_usbsts(EHCIState *s, int mask) 559 { 560 if ((s->usbsts & mask) == 0) { 561 return; 562 } 563 ehci_trace_usbsts(mask, 0); 564 s->usbsts &= ~mask; 565 } 566 567 /* update irq line */ 568 static inline void ehci_update_irq(EHCIState *s) 569 { 570 int level = 0; 571 572 if ((s->usbsts & USBINTR_MASK) & s->usbintr) { 573 level = 1; 574 } 575 576 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); 577 qemu_set_irq(s->irq, level); 578 } 579 580 /* flag interrupt condition */ 581 static inline void ehci_raise_irq(EHCIState *s, int intr) 582 { 583 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { 584 s->usbsts |= intr; 585 ehci_update_irq(s); 586 } else { 587 s->usbsts_pending |= intr; 588 } 589 } 590 591 /* 592 * Commit pending interrupts (added via ehci_raise_irq), 593 * at the rate allowed by "Interrupt Threshold Control". 594 */ 595 static inline void ehci_commit_irq(EHCIState *s) 596 { 597 uint32_t itc; 598 599 if (!s->usbsts_pending) { 600 return; 601 } 602 if (s->usbsts_frindex > s->frindex) { 603 return; 604 } 605 606 itc = (s->usbcmd >> 16) & 0xff; 607 s->usbsts |= s->usbsts_pending; 608 s->usbsts_pending = 0; 609 s->usbsts_frindex = s->frindex + itc; 610 ehci_update_irq(s); 611 } 612 613 static void ehci_update_halt(EHCIState *s) 614 { 615 if (s->usbcmd & USBCMD_RUNSTOP) { 616 ehci_clear_usbsts(s, USBSTS_HALT); 617 } else { 618 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { 619 ehci_set_usbsts(s, USBSTS_HALT); 620 } 621 } 622 } 623 624 static void ehci_set_state(EHCIState *s, int async, int state) 625 { 626 if (async) { 627 trace_usb_ehci_state("async", state2str(state)); 628 s->astate = state; 629 if (s->astate == EST_INACTIVE) { 630 ehci_clear_usbsts(s, USBSTS_ASS); 631 ehci_update_halt(s); 632 } else { 633 ehci_set_usbsts(s, USBSTS_ASS); 634 } 635 } else { 636 trace_usb_ehci_state("periodic", state2str(state)); 637 s->pstate = state; 638 if (s->pstate == EST_INACTIVE) { 639 ehci_clear_usbsts(s, USBSTS_PSS); 640 ehci_update_halt(s); 641 } else { 642 ehci_set_usbsts(s, USBSTS_PSS); 643 } 644 } 645 } 646 647 static int ehci_get_state(EHCIState *s, int async) 648 { 649 return async ? s->astate : s->pstate; 650 } 651 652 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) 653 { 654 if (async) { 655 s->a_fetch_addr = addr; 656 } else { 657 s->p_fetch_addr = addr; 658 } 659 } 660 661 static int ehci_get_fetch_addr(EHCIState *s, int async) 662 { 663 return async ? s->a_fetch_addr : s->p_fetch_addr; 664 } 665 666 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) 667 { 668 /* need three here due to argument count limits */ 669 trace_usb_ehci_qh_ptrs(q, addr, qh->next, 670 qh->current_qtd, qh->next_qtd, qh->altnext_qtd); 671 trace_usb_ehci_qh_fields(addr, 672 get_field(qh->epchar, QH_EPCHAR_RL), 673 get_field(qh->epchar, QH_EPCHAR_MPLEN), 674 get_field(qh->epchar, QH_EPCHAR_EPS), 675 get_field(qh->epchar, QH_EPCHAR_EP), 676 get_field(qh->epchar, QH_EPCHAR_DEVADDR)); 677 trace_usb_ehci_qh_bits(addr, 678 (bool)(qh->epchar & QH_EPCHAR_C), 679 (bool)(qh->epchar & QH_EPCHAR_H), 680 (bool)(qh->epchar & QH_EPCHAR_DTC), 681 (bool)(qh->epchar & QH_EPCHAR_I)); 682 } 683 684 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) 685 { 686 /* need three here due to argument count limits */ 687 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); 688 trace_usb_ehci_qtd_fields(addr, 689 get_field(qtd->token, QTD_TOKEN_TBYTES), 690 get_field(qtd->token, QTD_TOKEN_CPAGE), 691 get_field(qtd->token, QTD_TOKEN_CERR), 692 get_field(qtd->token, QTD_TOKEN_PID)); 693 trace_usb_ehci_qtd_bits(addr, 694 (bool)(qtd->token & QTD_TOKEN_IOC), 695 (bool)(qtd->token & QTD_TOKEN_ACTIVE), 696 (bool)(qtd->token & QTD_TOKEN_HALT), 697 (bool)(qtd->token & QTD_TOKEN_BABBLE), 698 (bool)(qtd->token & QTD_TOKEN_XACTERR)); 699 } 700 701 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) 702 { 703 trace_usb_ehci_itd(addr, itd->next, 704 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), 705 get_field(itd->bufptr[2], ITD_BUFPTR_MULT), 706 get_field(itd->bufptr[0], ITD_BUFPTR_EP), 707 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); 708 } 709 710 static void ehci_trace_sitd(EHCIState *s, hwaddr addr, 711 EHCIsitd *sitd) 712 { 713 trace_usb_ehci_sitd(addr, sitd->next, 714 (bool)(sitd->results & SITD_RESULTS_ACTIVE)); 715 } 716 717 static void ehci_trace_guest_bug(EHCIState *s, const char *message) 718 { 719 trace_usb_ehci_guest_bug(message); 720 fprintf(stderr, "ehci warning: %s\n", message); 721 } 722 723 static inline bool ehci_enabled(EHCIState *s) 724 { 725 return s->usbcmd & USBCMD_RUNSTOP; 726 } 727 728 static inline bool ehci_async_enabled(EHCIState *s) 729 { 730 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); 731 } 732 733 static inline bool ehci_periodic_enabled(EHCIState *s) 734 { 735 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); 736 } 737 738 /* packet management */ 739 740 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) 741 { 742 EHCIPacket *p; 743 744 p = g_new0(EHCIPacket, 1); 745 p->queue = q; 746 usb_packet_init(&p->packet); 747 QTAILQ_INSERT_TAIL(&q->packets, p, next); 748 trace_usb_ehci_packet_action(p->queue, p, "alloc"); 749 return p; 750 } 751 752 static void ehci_free_packet(EHCIPacket *p) 753 { 754 if (p->async == EHCI_ASYNC_FINISHED) { 755 int state = ehci_get_state(p->queue->ehci, p->queue->async); 756 /* This is a normal, but rare condition (cancel racing completion) */ 757 fprintf(stderr, "EHCI: Warning packet completed but not processed\n"); 758 ehci_state_executing(p->queue); 759 ehci_state_writeback(p->queue); 760 ehci_set_state(p->queue->ehci, p->queue->async, state); 761 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */ 762 return; 763 } 764 trace_usb_ehci_packet_action(p->queue, p, "free"); 765 if (p->async == EHCI_ASYNC_INITIALIZED) { 766 usb_packet_unmap(&p->packet, &p->sgl); 767 qemu_sglist_destroy(&p->sgl); 768 } 769 if (p->async == EHCI_ASYNC_INFLIGHT) { 770 usb_cancel_packet(&p->packet); 771 usb_packet_unmap(&p->packet, &p->sgl); 772 qemu_sglist_destroy(&p->sgl); 773 } 774 QTAILQ_REMOVE(&p->queue->packets, p, next); 775 usb_packet_cleanup(&p->packet); 776 g_free(p); 777 } 778 779 /* queue management */ 780 781 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) 782 { 783 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 784 EHCIQueue *q; 785 786 q = g_malloc0(sizeof(*q)); 787 q->ehci = ehci; 788 q->qhaddr = addr; 789 q->async = async; 790 QTAILQ_INIT(&q->packets); 791 QTAILQ_INSERT_HEAD(head, q, next); 792 trace_usb_ehci_queue_action(q, "alloc"); 793 return q; 794 } 795 796 static int ehci_cancel_queue(EHCIQueue *q) 797 { 798 EHCIPacket *p; 799 int packets = 0; 800 801 p = QTAILQ_FIRST(&q->packets); 802 if (p == NULL) { 803 return 0; 804 } 805 806 trace_usb_ehci_queue_action(q, "cancel"); 807 do { 808 ehci_free_packet(p); 809 packets++; 810 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL); 811 return packets; 812 } 813 814 static int ehci_reset_queue(EHCIQueue *q) 815 { 816 int packets; 817 818 trace_usb_ehci_queue_action(q, "reset"); 819 packets = ehci_cancel_queue(q); 820 q->dev = NULL; 821 q->qtdaddr = 0; 822 return packets; 823 } 824 825 static void ehci_free_queue(EHCIQueue *q, const char *warn) 826 { 827 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; 828 int cancelled; 829 830 trace_usb_ehci_queue_action(q, "free"); 831 cancelled = ehci_cancel_queue(q); 832 if (warn && cancelled > 0) { 833 ehci_trace_guest_bug(q->ehci, warn); 834 } 835 QTAILQ_REMOVE(head, q, next); 836 g_free(q); 837 } 838 839 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, 840 int async) 841 { 842 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 843 EHCIQueue *q; 844 845 QTAILQ_FOREACH(q, head, next) { 846 if (addr == q->qhaddr) { 847 return q; 848 } 849 } 850 return NULL; 851 } 852 853 static void ehci_queues_rip_unused(EHCIState *ehci, int async) 854 { 855 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 856 const char *warn = async ? "guest unlinked busy QH" : NULL; 857 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; 858 EHCIQueue *q, *tmp; 859 860 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 861 if (q->seen) { 862 q->seen = 0; 863 q->ts = ehci->last_run_ns; 864 continue; 865 } 866 if (ehci->last_run_ns < q->ts + maxage) { 867 continue; 868 } 869 ehci_free_queue(q, warn); 870 } 871 } 872 873 static void ehci_queues_rip_unseen(EHCIState *ehci, int async) 874 { 875 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 876 EHCIQueue *q, *tmp; 877 878 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 879 if (!q->seen) { 880 ehci_free_queue(q, NULL); 881 } 882 } 883 } 884 885 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) 886 { 887 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 888 EHCIQueue *q, *tmp; 889 890 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 891 if (q->dev != dev) { 892 continue; 893 } 894 ehci_free_queue(q, NULL); 895 } 896 } 897 898 static void ehci_queues_rip_all(EHCIState *ehci, int async) 899 { 900 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 901 const char *warn = async ? "guest stopped busy async schedule" : NULL; 902 EHCIQueue *q, *tmp; 903 904 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 905 ehci_free_queue(q, warn); 906 } 907 } 908 909 /* Attach or detach a device on root hub */ 910 911 static void ehci_attach(USBPort *port) 912 { 913 EHCIState *s = port->opaque; 914 uint32_t *portsc = &s->portsc[port->index]; 915 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 916 917 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); 918 919 if (*portsc & PORTSC_POWNER) { 920 USBPort *companion = s->companion_ports[port->index]; 921 companion->dev = port->dev; 922 companion->ops->attach(companion); 923 return; 924 } 925 926 *portsc |= PORTSC_CONNECT; 927 *portsc |= PORTSC_CSC; 928 929 ehci_raise_irq(s, USBSTS_PCD); 930 ehci_commit_irq(s); 931 } 932 933 static void ehci_detach(USBPort *port) 934 { 935 EHCIState *s = port->opaque; 936 uint32_t *portsc = &s->portsc[port->index]; 937 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 938 939 trace_usb_ehci_port_detach(port->index, owner); 940 941 if (*portsc & PORTSC_POWNER) { 942 USBPort *companion = s->companion_ports[port->index]; 943 companion->ops->detach(companion); 944 companion->dev = NULL; 945 /* 946 * EHCI spec 4.2.2: "When a disconnect occurs... On the event, 947 * the port ownership is returned immediately to the EHCI controller." 948 */ 949 *portsc &= ~PORTSC_POWNER; 950 return; 951 } 952 953 ehci_queues_rip_device(s, port->dev, 0); 954 ehci_queues_rip_device(s, port->dev, 1); 955 956 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); 957 *portsc |= PORTSC_CSC; 958 959 ehci_raise_irq(s, USBSTS_PCD); 960 ehci_commit_irq(s); 961 } 962 963 static void ehci_child_detach(USBPort *port, USBDevice *child) 964 { 965 EHCIState *s = port->opaque; 966 uint32_t portsc = s->portsc[port->index]; 967 968 if (portsc & PORTSC_POWNER) { 969 USBPort *companion = s->companion_ports[port->index]; 970 companion->ops->child_detach(companion, child); 971 return; 972 } 973 974 ehci_queues_rip_device(s, child, 0); 975 ehci_queues_rip_device(s, child, 1); 976 } 977 978 static void ehci_wakeup(USBPort *port) 979 { 980 EHCIState *s = port->opaque; 981 uint32_t portsc = s->portsc[port->index]; 982 983 if (portsc & PORTSC_POWNER) { 984 USBPort *companion = s->companion_ports[port->index]; 985 if (companion->ops->wakeup) { 986 companion->ops->wakeup(companion); 987 } 988 return; 989 } 990 991 qemu_bh_schedule(s->async_bh); 992 } 993 994 static int ehci_register_companion(USBBus *bus, USBPort *ports[], 995 uint32_t portcount, uint32_t firstport) 996 { 997 EHCIState *s = container_of(bus, EHCIState, bus); 998 uint32_t i; 999 1000 if (firstport + portcount > NB_PORTS) { 1001 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", 1002 "firstport on masterbus"); 1003 error_printf_unless_qmp( 1004 "firstport value of %u makes companion take ports %u - %u, which " 1005 "is outside of the valid range of 0 - %u\n", firstport, firstport, 1006 firstport + portcount - 1, NB_PORTS - 1); 1007 return -1; 1008 } 1009 1010 for (i = 0; i < portcount; i++) { 1011 if (s->companion_ports[firstport + i]) { 1012 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", 1013 "an USB masterbus"); 1014 error_printf_unless_qmp( 1015 "port %u on masterbus %s already has a companion assigned\n", 1016 firstport + i, bus->qbus.name); 1017 return -1; 1018 } 1019 } 1020 1021 for (i = 0; i < portcount; i++) { 1022 s->companion_ports[firstport + i] = ports[i]; 1023 s->ports[firstport + i].speedmask |= 1024 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; 1025 /* Ensure devs attached before the initial reset go to the companion */ 1026 s->portsc[firstport + i] = PORTSC_POWNER; 1027 } 1028 1029 s->companion_count++; 1030 s->caps[0x05] = (s->companion_count << 4) | portcount; 1031 1032 return 0; 1033 } 1034 1035 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) 1036 { 1037 USBDevice *dev; 1038 USBPort *port; 1039 int i; 1040 1041 for (i = 0; i < NB_PORTS; i++) { 1042 port = &ehci->ports[i]; 1043 if (!(ehci->portsc[i] & PORTSC_PED)) { 1044 DPRINTF("Port %d not enabled\n", i); 1045 continue; 1046 } 1047 dev = usb_find_device(port, addr); 1048 if (dev != NULL) { 1049 return dev; 1050 } 1051 } 1052 return NULL; 1053 } 1054 1055 /* 4.1 host controller initialization */ 1056 static void ehci_reset(void *opaque) 1057 { 1058 EHCIState *s = opaque; 1059 int i; 1060 USBDevice *devs[NB_PORTS]; 1061 1062 trace_usb_ehci_reset(); 1063 1064 /* 1065 * Do the detach before touching portsc, so that it correctly gets send to 1066 * us or to our companion based on PORTSC_POWNER before the reset. 1067 */ 1068 for(i = 0; i < NB_PORTS; i++) { 1069 devs[i] = s->ports[i].dev; 1070 if (devs[i] && devs[i]->attached) { 1071 usb_detach(&s->ports[i]); 1072 } 1073 } 1074 1075 memset(&s->opreg, 0x00, sizeof(s->opreg)); 1076 memset(&s->portsc, 0x00, sizeof(s->portsc)); 1077 1078 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; 1079 s->usbsts = USBSTS_HALT; 1080 s->usbsts_pending = 0; 1081 s->usbsts_frindex = 0; 1082 1083 s->astate = EST_INACTIVE; 1084 s->pstate = EST_INACTIVE; 1085 1086 for(i = 0; i < NB_PORTS; i++) { 1087 if (s->companion_ports[i]) { 1088 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; 1089 } else { 1090 s->portsc[i] = PORTSC_PPOWER; 1091 } 1092 if (devs[i] && devs[i]->attached) { 1093 usb_attach(&s->ports[i]); 1094 usb_device_reset(devs[i]); 1095 } 1096 } 1097 ehci_queues_rip_all(s, 0); 1098 ehci_queues_rip_all(s, 1); 1099 qemu_del_timer(s->frame_timer); 1100 qemu_bh_cancel(s->async_bh); 1101 } 1102 1103 static uint64_t ehci_caps_read(void *ptr, hwaddr addr, 1104 unsigned size) 1105 { 1106 EHCIState *s = ptr; 1107 return s->caps[addr]; 1108 } 1109 1110 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, 1111 unsigned size) 1112 { 1113 EHCIState *s = ptr; 1114 uint32_t val; 1115 1116 val = s->opreg[addr >> 2]; 1117 trace_usb_ehci_opreg_read(addr + OPREGBASE, addr2str(addr), val); 1118 return val; 1119 } 1120 1121 static uint64_t ehci_port_read(void *ptr, hwaddr addr, 1122 unsigned size) 1123 { 1124 EHCIState *s = ptr; 1125 uint32_t val; 1126 1127 val = s->portsc[addr >> 2]; 1128 trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val); 1129 return val; 1130 } 1131 1132 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) 1133 { 1134 USBDevice *dev = s->ports[port].dev; 1135 uint32_t *portsc = &s->portsc[port]; 1136 uint32_t orig; 1137 1138 if (s->companion_ports[port] == NULL) 1139 return; 1140 1141 owner = owner & PORTSC_POWNER; 1142 orig = *portsc & PORTSC_POWNER; 1143 1144 if (!(owner ^ orig)) { 1145 return; 1146 } 1147 1148 if (dev && dev->attached) { 1149 usb_detach(&s->ports[port]); 1150 } 1151 1152 *portsc &= ~PORTSC_POWNER; 1153 *portsc |= owner; 1154 1155 if (dev && dev->attached) { 1156 usb_attach(&s->ports[port]); 1157 } 1158 } 1159 1160 static void ehci_port_write(void *ptr, hwaddr addr, 1161 uint64_t val, unsigned size) 1162 { 1163 EHCIState *s = ptr; 1164 int port = addr >> 2; 1165 uint32_t *portsc = &s->portsc[port]; 1166 uint32_t old = *portsc; 1167 USBDevice *dev = s->ports[port].dev; 1168 1169 trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val); 1170 1171 /* Clear rwc bits */ 1172 *portsc &= ~(val & PORTSC_RWC_MASK); 1173 /* The guest may clear, but not set the PED bit */ 1174 *portsc &= val | ~PORTSC_PED; 1175 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ 1176 handle_port_owner_write(s, port, val); 1177 /* And finally apply RO_MASK */ 1178 val &= PORTSC_RO_MASK; 1179 1180 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { 1181 trace_usb_ehci_port_reset(port, 1); 1182 } 1183 1184 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { 1185 trace_usb_ehci_port_reset(port, 0); 1186 if (dev && dev->attached) { 1187 usb_port_reset(&s->ports[port]); 1188 *portsc &= ~PORTSC_CSC; 1189 } 1190 1191 /* 1192 * Table 2.16 Set the enable bit(and enable bit change) to indicate 1193 * to SW that this port has a high speed device attached 1194 */ 1195 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { 1196 val |= PORTSC_PED; 1197 } 1198 } 1199 1200 *portsc &= ~PORTSC_RO_MASK; 1201 *portsc |= val; 1202 trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old); 1203 } 1204 1205 static void ehci_opreg_write(void *ptr, hwaddr addr, 1206 uint64_t val, unsigned size) 1207 { 1208 EHCIState *s = ptr; 1209 uint32_t *mmio = s->opreg + (addr >> 2); 1210 uint32_t old = *mmio; 1211 int i; 1212 1213 trace_usb_ehci_opreg_write(addr + OPREGBASE, addr2str(addr), val); 1214 1215 switch (addr + OPREGBASE) { 1216 case USBCMD: 1217 if (val & USBCMD_HCRESET) { 1218 ehci_reset(s); 1219 val = s->usbcmd; 1220 break; 1221 } 1222 1223 /* not supporting dynamic frame list size at the moment */ 1224 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { 1225 fprintf(stderr, "attempt to set frame list size -- value %d\n", 1226 (int)val & USBCMD_FLS); 1227 val &= ~USBCMD_FLS; 1228 } 1229 1230 if (val & USBCMD_IAAD) { 1231 /* 1232 * Process IAAD immediately, otherwise the Linux IAAD watchdog may 1233 * trigger and re-use a qh without us seeing the unlink. 1234 */ 1235 s->async_stepdown = 0; 1236 qemu_bh_schedule(s->async_bh); 1237 trace_usb_ehci_doorbell_ring(); 1238 } 1239 1240 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != 1241 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { 1242 if (s->pstate == EST_INACTIVE) { 1243 SET_LAST_RUN_CLOCK(s); 1244 } 1245 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ 1246 ehci_update_halt(s); 1247 s->async_stepdown = 0; 1248 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 1249 } 1250 break; 1251 1252 case USBSTS: 1253 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO 1254 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC 1255 val = s->usbsts; 1256 ehci_update_irq(s); 1257 break; 1258 1259 case USBINTR: 1260 val &= USBINTR_MASK; 1261 break; 1262 1263 case FRINDEX: 1264 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ 1265 break; 1266 1267 case CONFIGFLAG: 1268 val &= 0x1; 1269 if (val) { 1270 for(i = 0; i < NB_PORTS; i++) 1271 handle_port_owner_write(s, i, 0); 1272 } 1273 break; 1274 1275 case PERIODICLISTBASE: 1276 if (ehci_periodic_enabled(s)) { 1277 fprintf(stderr, 1278 "ehci: PERIODIC list base register set while periodic schedule\n" 1279 " is enabled and HC is enabled\n"); 1280 } 1281 break; 1282 1283 case ASYNCLISTADDR: 1284 if (ehci_async_enabled(s)) { 1285 fprintf(stderr, 1286 "ehci: ASYNC list address register set while async schedule\n" 1287 " is enabled and HC is enabled\n"); 1288 } 1289 break; 1290 } 1291 1292 *mmio = val; 1293 trace_usb_ehci_opreg_change(addr + OPREGBASE, addr2str(addr), *mmio, old); 1294 } 1295 1296 1297 // TODO : Put in common header file, duplication from usb-ohci.c 1298 1299 /* Get an array of dwords from main memory */ 1300 static inline int get_dwords(EHCIState *ehci, uint32_t addr, 1301 uint32_t *buf, int num) 1302 { 1303 int i; 1304 1305 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1306 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); 1307 *buf = le32_to_cpu(*buf); 1308 } 1309 1310 return 1; 1311 } 1312 1313 /* Put an array of dwords in to main memory */ 1314 static inline int put_dwords(EHCIState *ehci, uint32_t addr, 1315 uint32_t *buf, int num) 1316 { 1317 int i; 1318 1319 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 1320 uint32_t tmp = cpu_to_le32(*buf); 1321 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); 1322 } 1323 1324 return 1; 1325 } 1326 1327 /* 1328 * Write the qh back to guest physical memory. This step isn't 1329 * in the EHCI spec but we need to do it since we don't share 1330 * physical memory with our guest VM. 1331 * 1332 * The first three dwords are read-only for the EHCI, so skip them 1333 * when writing back the qh. 1334 */ 1335 static void ehci_flush_qh(EHCIQueue *q) 1336 { 1337 uint32_t *qh = (uint32_t *) &q->qh; 1338 uint32_t dwords = sizeof(EHCIqh) >> 2; 1339 uint32_t addr = NLPTR_GET(q->qhaddr); 1340 1341 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); 1342 } 1343 1344 // 4.10.2 1345 1346 static int ehci_qh_do_overlay(EHCIQueue *q) 1347 { 1348 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1349 int i; 1350 int dtoggle; 1351 int ping; 1352 int eps; 1353 int reload; 1354 1355 assert(p != NULL); 1356 assert(p->qtdaddr == q->qtdaddr); 1357 1358 // remember values in fields to preserve in qh after overlay 1359 1360 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; 1361 ping = q->qh.token & QTD_TOKEN_PING; 1362 1363 q->qh.current_qtd = p->qtdaddr; 1364 q->qh.next_qtd = p->qtd.next; 1365 q->qh.altnext_qtd = p->qtd.altnext; 1366 q->qh.token = p->qtd.token; 1367 1368 1369 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); 1370 if (eps == EHCI_QH_EPS_HIGH) { 1371 q->qh.token &= ~QTD_TOKEN_PING; 1372 q->qh.token |= ping; 1373 } 1374 1375 reload = get_field(q->qh.epchar, QH_EPCHAR_RL); 1376 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); 1377 1378 for (i = 0; i < 5; i++) { 1379 q->qh.bufptr[i] = p->qtd.bufptr[i]; 1380 } 1381 1382 if (!(q->qh.epchar & QH_EPCHAR_DTC)) { 1383 // preserve QH DT bit 1384 q->qh.token &= ~QTD_TOKEN_DTOGGLE; 1385 q->qh.token |= dtoggle; 1386 } 1387 1388 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; 1389 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; 1390 1391 ehci_flush_qh(q); 1392 1393 return 0; 1394 } 1395 1396 static int ehci_init_transfer(EHCIPacket *p) 1397 { 1398 uint32_t cpage, offset, bytes, plen; 1399 dma_addr_t page; 1400 1401 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); 1402 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); 1403 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; 1404 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); 1405 1406 while (bytes > 0) { 1407 if (cpage > 4) { 1408 fprintf(stderr, "cpage out of range (%d)\n", cpage); 1409 return USB_RET_PROCERR; 1410 } 1411 1412 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; 1413 page += offset; 1414 plen = bytes; 1415 if (plen > 4096 - offset) { 1416 plen = 4096 - offset; 1417 offset = 0; 1418 cpage++; 1419 } 1420 1421 qemu_sglist_add(&p->sgl, page, plen); 1422 bytes -= plen; 1423 } 1424 return 0; 1425 } 1426 1427 static void ehci_finish_transfer(EHCIQueue *q, int status) 1428 { 1429 uint32_t cpage, offset; 1430 1431 if (status > 0) { 1432 /* update cpage & offset */ 1433 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); 1434 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; 1435 1436 offset += status; 1437 cpage += offset >> QTD_BUFPTR_SH; 1438 offset &= ~QTD_BUFPTR_MASK; 1439 1440 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); 1441 q->qh.bufptr[0] &= QTD_BUFPTR_MASK; 1442 q->qh.bufptr[0] |= offset; 1443 } 1444 } 1445 1446 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) 1447 { 1448 EHCIPacket *p; 1449 EHCIState *s = port->opaque; 1450 uint32_t portsc = s->portsc[port->index]; 1451 1452 if (portsc & PORTSC_POWNER) { 1453 USBPort *companion = s->companion_ports[port->index]; 1454 companion->ops->complete(companion, packet); 1455 return; 1456 } 1457 1458 p = container_of(packet, EHCIPacket, packet); 1459 trace_usb_ehci_packet_action(p->queue, p, "wakeup"); 1460 assert(p->async == EHCI_ASYNC_INFLIGHT); 1461 p->async = EHCI_ASYNC_FINISHED; 1462 p->usb_status = packet->result; 1463 1464 if (p->queue->async) { 1465 qemu_bh_schedule(p->queue->ehci->async_bh); 1466 } 1467 } 1468 1469 static void ehci_execute_complete(EHCIQueue *q) 1470 { 1471 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1472 1473 assert(p != NULL); 1474 assert(p->qtdaddr == q->qtdaddr); 1475 assert(p->async == EHCI_ASYNC_INITIALIZED || 1476 p->async == EHCI_ASYNC_FINISHED); 1477 1478 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", 1479 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); 1480 1481 if (p->usb_status < 0) { 1482 switch (p->usb_status) { 1483 case USB_RET_IOERROR: 1484 case USB_RET_NODEV: 1485 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); 1486 set_field(&q->qh.token, 0, QTD_TOKEN_CERR); 1487 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1488 break; 1489 case USB_RET_STALL: 1490 q->qh.token |= QTD_TOKEN_HALT; 1491 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1492 break; 1493 case USB_RET_NAK: 1494 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); 1495 return; /* We're not done yet with this transaction */ 1496 case USB_RET_BABBLE: 1497 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); 1498 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1499 break; 1500 default: 1501 /* should not be triggerable */ 1502 fprintf(stderr, "USB invalid response %d\n", p->usb_status); 1503 assert(0); 1504 break; 1505 } 1506 } else { 1507 // TODO check 4.12 for splits 1508 1509 if (p->tbytes && p->pid == USB_TOKEN_IN) { 1510 p->tbytes -= p->usb_status; 1511 } else { 1512 p->tbytes = 0; 1513 } 1514 1515 DPRINTF("updating tbytes to %d\n", p->tbytes); 1516 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); 1517 } 1518 ehci_finish_transfer(q, p->usb_status); 1519 usb_packet_unmap(&p->packet, &p->sgl); 1520 qemu_sglist_destroy(&p->sgl); 1521 p->async = EHCI_ASYNC_NONE; 1522 1523 q->qh.token ^= QTD_TOKEN_DTOGGLE; 1524 q->qh.token &= ~QTD_TOKEN_ACTIVE; 1525 1526 if (q->qh.token & QTD_TOKEN_IOC) { 1527 ehci_raise_irq(q->ehci, USBSTS_INT); 1528 } 1529 } 1530 1531 // 4.10.3 1532 1533 static int ehci_execute(EHCIPacket *p, const char *action) 1534 { 1535 USBEndpoint *ep; 1536 int ret; 1537 int endp; 1538 1539 assert(p->async == EHCI_ASYNC_NONE || 1540 p->async == EHCI_ASYNC_INITIALIZED); 1541 1542 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { 1543 fprintf(stderr, "Attempting to execute inactive qtd\n"); 1544 return USB_RET_PROCERR; 1545 } 1546 1547 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; 1548 if (p->tbytes > BUFF_SIZE) { 1549 ehci_trace_guest_bug(p->queue->ehci, 1550 "guest requested more bytes than allowed"); 1551 return USB_RET_PROCERR; 1552 } 1553 1554 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; 1555 switch (p->pid) { 1556 case 0: 1557 p->pid = USB_TOKEN_OUT; 1558 break; 1559 case 1: 1560 p->pid = USB_TOKEN_IN; 1561 break; 1562 case 2: 1563 p->pid = USB_TOKEN_SETUP; 1564 break; 1565 default: 1566 fprintf(stderr, "bad token\n"); 1567 break; 1568 } 1569 1570 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); 1571 ep = usb_ep_get(p->queue->dev, p->pid, endp); 1572 1573 if (p->async == EHCI_ASYNC_NONE) { 1574 if (ehci_init_transfer(p) != 0) { 1575 return USB_RET_PROCERR; 1576 } 1577 1578 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr); 1579 usb_packet_map(&p->packet, &p->sgl); 1580 p->async = EHCI_ASYNC_INITIALIZED; 1581 } 1582 1583 trace_usb_ehci_packet_action(p->queue, p, action); 1584 ret = usb_handle_packet(p->queue->dev, &p->packet); 1585 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " 1586 "(total %d) endp %x ret %d\n", 1587 q->qhaddr, q->qh.next, q->qtdaddr, q->pid, 1588 q->packet.iov.size, q->tbytes, endp, ret); 1589 1590 if (ret > BUFF_SIZE) { 1591 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); 1592 return USB_RET_PROCERR; 1593 } 1594 1595 return ret; 1596 } 1597 1598 /* 4.7.2 1599 */ 1600 1601 static int ehci_process_itd(EHCIState *ehci, 1602 EHCIitd *itd, 1603 uint32_t addr) 1604 { 1605 USBDevice *dev; 1606 USBEndpoint *ep; 1607 int ret; 1608 uint32_t i, len, pid, dir, devaddr, endp; 1609 uint32_t pg, off, ptr1, ptr2, max, mult; 1610 1611 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); 1612 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); 1613 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); 1614 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); 1615 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); 1616 1617 for(i = 0; i < 8; i++) { 1618 if (itd->transact[i] & ITD_XACT_ACTIVE) { 1619 pg = get_field(itd->transact[i], ITD_XACT_PGSEL); 1620 off = itd->transact[i] & ITD_XACT_OFFSET_MASK; 1621 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); 1622 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); 1623 len = get_field(itd->transact[i], ITD_XACT_LENGTH); 1624 1625 if (len > max * mult) { 1626 len = max * mult; 1627 } 1628 1629 if (len > BUFF_SIZE) { 1630 return USB_RET_PROCERR; 1631 } 1632 1633 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); 1634 if (off + len > 4096) { 1635 /* transfer crosses page border */ 1636 uint32_t len2 = off + len - 4096; 1637 uint32_t len1 = len - len2; 1638 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); 1639 qemu_sglist_add(&ehci->isgl, ptr2, len2); 1640 } else { 1641 qemu_sglist_add(&ehci->isgl, ptr1 + off, len); 1642 } 1643 1644 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; 1645 1646 dev = ehci_find_device(ehci, devaddr); 1647 ep = usb_ep_get(dev, pid, endp); 1648 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { 1649 usb_packet_setup(&ehci->ipacket, pid, ep, addr); 1650 usb_packet_map(&ehci->ipacket, &ehci->isgl); 1651 ret = usb_handle_packet(dev, &ehci->ipacket); 1652 assert(ret != USB_RET_ASYNC); 1653 usb_packet_unmap(&ehci->ipacket, &ehci->isgl); 1654 } else { 1655 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); 1656 ret = USB_RET_NAK; 1657 } 1658 qemu_sglist_destroy(&ehci->isgl); 1659 1660 if (ret < 0) { 1661 switch (ret) { 1662 default: 1663 fprintf(stderr, "Unexpected iso usb result: %d\n", ret); 1664 /* Fall through */ 1665 case USB_RET_IOERROR: 1666 case USB_RET_NODEV: 1667 /* 3.3.2: XACTERR is only allowed on IN transactions */ 1668 if (dir) { 1669 itd->transact[i] |= ITD_XACT_XACTERR; 1670 ehci_raise_irq(ehci, USBSTS_ERRINT); 1671 } 1672 break; 1673 case USB_RET_BABBLE: 1674 itd->transact[i] |= ITD_XACT_BABBLE; 1675 ehci_raise_irq(ehci, USBSTS_ERRINT); 1676 break; 1677 case USB_RET_NAK: 1678 /* no data for us, so do a zero-length transfer */ 1679 ret = 0; 1680 break; 1681 } 1682 } 1683 if (ret >= 0) { 1684 if (!dir) { 1685 /* OUT */ 1686 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); 1687 } else { 1688 /* IN */ 1689 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); 1690 } 1691 } 1692 if (itd->transact[i] & ITD_XACT_IOC) { 1693 ehci_raise_irq(ehci, USBSTS_INT); 1694 } 1695 itd->transact[i] &= ~ITD_XACT_ACTIVE; 1696 } 1697 } 1698 return 0; 1699 } 1700 1701 1702 /* This state is the entry point for asynchronous schedule 1703 * processing. Entry here consitutes a EHCI start event state (4.8.5) 1704 */ 1705 static int ehci_state_waitlisthead(EHCIState *ehci, int async) 1706 { 1707 EHCIqh qh; 1708 int i = 0; 1709 int again = 0; 1710 uint32_t entry = ehci->asynclistaddr; 1711 1712 /* set reclamation flag at start event (4.8.6) */ 1713 if (async) { 1714 ehci_set_usbsts(ehci, USBSTS_REC); 1715 } 1716 1717 ehci_queues_rip_unused(ehci, async); 1718 1719 /* Find the head of the list (4.9.1.1) */ 1720 for(i = 0; i < MAX_QH; i++) { 1721 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, 1722 sizeof(EHCIqh) >> 2); 1723 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); 1724 1725 if (qh.epchar & QH_EPCHAR_H) { 1726 if (async) { 1727 entry |= (NLPTR_TYPE_QH << 1); 1728 } 1729 1730 ehci_set_fetch_addr(ehci, async, entry); 1731 ehci_set_state(ehci, async, EST_FETCHENTRY); 1732 again = 1; 1733 goto out; 1734 } 1735 1736 entry = qh.next; 1737 if (entry == ehci->asynclistaddr) { 1738 break; 1739 } 1740 } 1741 1742 /* no head found for list. */ 1743 1744 ehci_set_state(ehci, async, EST_ACTIVE); 1745 1746 out: 1747 return again; 1748 } 1749 1750 1751 /* This state is the entry point for periodic schedule processing as 1752 * well as being a continuation state for async processing. 1753 */ 1754 static int ehci_state_fetchentry(EHCIState *ehci, int async) 1755 { 1756 int again = 0; 1757 uint32_t entry = ehci_get_fetch_addr(ehci, async); 1758 1759 if (NLPTR_TBIT(entry)) { 1760 ehci_set_state(ehci, async, EST_ACTIVE); 1761 goto out; 1762 } 1763 1764 /* section 4.8, only QH in async schedule */ 1765 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { 1766 fprintf(stderr, "non queue head request in async schedule\n"); 1767 return -1; 1768 } 1769 1770 switch (NLPTR_TYPE_GET(entry)) { 1771 case NLPTR_TYPE_QH: 1772 ehci_set_state(ehci, async, EST_FETCHQH); 1773 again = 1; 1774 break; 1775 1776 case NLPTR_TYPE_ITD: 1777 ehci_set_state(ehci, async, EST_FETCHITD); 1778 again = 1; 1779 break; 1780 1781 case NLPTR_TYPE_STITD: 1782 ehci_set_state(ehci, async, EST_FETCHSITD); 1783 again = 1; 1784 break; 1785 1786 default: 1787 /* TODO: handle FSTN type */ 1788 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " 1789 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); 1790 return -1; 1791 } 1792 1793 out: 1794 return again; 1795 } 1796 1797 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) 1798 { 1799 EHCIPacket *p; 1800 uint32_t entry, devaddr, endp; 1801 EHCIQueue *q; 1802 EHCIqh qh; 1803 1804 entry = ehci_get_fetch_addr(ehci, async); 1805 q = ehci_find_queue_by_qh(ehci, entry, async); 1806 if (NULL == q) { 1807 q = ehci_alloc_queue(ehci, entry, async); 1808 } 1809 p = QTAILQ_FIRST(&q->packets); 1810 1811 q->seen++; 1812 if (q->seen > 1) { 1813 /* we are going in circles -- stop processing */ 1814 ehci_set_state(ehci, async, EST_ACTIVE); 1815 q = NULL; 1816 goto out; 1817 } 1818 1819 get_dwords(ehci, NLPTR_GET(q->qhaddr), 1820 (uint32_t *) &qh, sizeof(EHCIqh) >> 2); 1821 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); 1822 1823 /* 1824 * The overlay area of the qh should never be changed by the guest, 1825 * except when idle, in which case the reset is a nop. 1826 */ 1827 devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR); 1828 endp = get_field(qh.epchar, QH_EPCHAR_EP); 1829 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) || 1830 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || 1831 (memcmp(&qh.current_qtd, &q->qh.current_qtd, 1832 9 * sizeof(uint32_t)) != 0) || 1833 (q->dev != NULL && q->dev->addr != devaddr)) { 1834 if (ehci_reset_queue(q) > 0) { 1835 ehci_trace_guest_bug(ehci, "guest updated active QH"); 1836 } 1837 p = NULL; 1838 } 1839 q->qh = qh; 1840 1841 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); 1842 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ 1843 q->transact_ctr = 4; 1844 } 1845 1846 if (q->dev == NULL) { 1847 q->dev = ehci_find_device(q->ehci, devaddr); 1848 } 1849 1850 if (p && p->async == EHCI_ASYNC_FINISHED) { 1851 /* I/O finished -- continue processing queue */ 1852 trace_usb_ehci_packet_action(p->queue, p, "complete"); 1853 ehci_set_state(ehci, async, EST_EXECUTING); 1854 goto out; 1855 } 1856 1857 if (async && (q->qh.epchar & QH_EPCHAR_H)) { 1858 1859 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ 1860 if (ehci->usbsts & USBSTS_REC) { 1861 ehci_clear_usbsts(ehci, USBSTS_REC); 1862 } else { 1863 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" 1864 " - done processing\n", q->qhaddr); 1865 ehci_set_state(ehci, async, EST_ACTIVE); 1866 q = NULL; 1867 goto out; 1868 } 1869 } 1870 1871 #if EHCI_DEBUG 1872 if (q->qhaddr != q->qh.next) { 1873 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", 1874 q->qhaddr, 1875 q->qh.epchar & QH_EPCHAR_H, 1876 q->qh.token & QTD_TOKEN_HALT, 1877 q->qh.token & QTD_TOKEN_ACTIVE, 1878 q->qh.next); 1879 } 1880 #endif 1881 1882 if (q->qh.token & QTD_TOKEN_HALT) { 1883 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1884 1885 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && 1886 (NLPTR_TBIT(q->qh.current_qtd) == 0)) { 1887 q->qtdaddr = q->qh.current_qtd; 1888 ehci_set_state(ehci, async, EST_FETCHQTD); 1889 1890 } else { 1891 /* EHCI spec version 1.0 Section 4.10.2 */ 1892 ehci_set_state(ehci, async, EST_ADVANCEQUEUE); 1893 } 1894 1895 out: 1896 return q; 1897 } 1898 1899 static int ehci_state_fetchitd(EHCIState *ehci, int async) 1900 { 1901 uint32_t entry; 1902 EHCIitd itd; 1903 1904 assert(!async); 1905 entry = ehci_get_fetch_addr(ehci, async); 1906 1907 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1908 sizeof(EHCIitd) >> 2); 1909 ehci_trace_itd(ehci, entry, &itd); 1910 1911 if (ehci_process_itd(ehci, &itd, entry) != 0) { 1912 return -1; 1913 } 1914 1915 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1916 sizeof(EHCIitd) >> 2); 1917 ehci_set_fetch_addr(ehci, async, itd.next); 1918 ehci_set_state(ehci, async, EST_FETCHENTRY); 1919 1920 return 1; 1921 } 1922 1923 static int ehci_state_fetchsitd(EHCIState *ehci, int async) 1924 { 1925 uint32_t entry; 1926 EHCIsitd sitd; 1927 1928 assert(!async); 1929 entry = ehci_get_fetch_addr(ehci, async); 1930 1931 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, 1932 sizeof(EHCIsitd) >> 2); 1933 ehci_trace_sitd(ehci, entry, &sitd); 1934 1935 if (!(sitd.results & SITD_RESULTS_ACTIVE)) { 1936 /* siTD is not active, nothing to do */; 1937 } else { 1938 /* TODO: split transfers are not implemented */ 1939 fprintf(stderr, "WARNING: Skipping active siTD\n"); 1940 } 1941 1942 ehci_set_fetch_addr(ehci, async, sitd.next); 1943 ehci_set_state(ehci, async, EST_FETCHENTRY); 1944 return 1; 1945 } 1946 1947 /* Section 4.10.2 - paragraph 3 */ 1948 static int ehci_state_advqueue(EHCIQueue *q) 1949 { 1950 #if 0 1951 /* TO-DO: 4.10.2 - paragraph 2 1952 * if I-bit is set to 1 and QH is not active 1953 * go to horizontal QH 1954 */ 1955 if (I-bit set) { 1956 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1957 goto out; 1958 } 1959 #endif 1960 1961 /* 1962 * want data and alt-next qTD is valid 1963 */ 1964 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && 1965 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { 1966 q->qtdaddr = q->qh.altnext_qtd; 1967 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1968 1969 /* 1970 * next qTD is valid 1971 */ 1972 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { 1973 q->qtdaddr = q->qh.next_qtd; 1974 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1975 1976 /* 1977 * no valid qTD, try next QH 1978 */ 1979 } else { 1980 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1981 } 1982 1983 return 1; 1984 } 1985 1986 /* Section 4.10.2 - paragraph 4 */ 1987 static int ehci_state_fetchqtd(EHCIQueue *q) 1988 { 1989 EHCIqtd qtd; 1990 EHCIPacket *p; 1991 int again = 0; 1992 1993 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, 1994 sizeof(EHCIqtd) >> 2); 1995 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); 1996 1997 p = QTAILQ_FIRST(&q->packets); 1998 if (p != NULL) { 1999 if (p->qtdaddr != q->qtdaddr || 2000 (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) || 2001 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) || 2002 p->qtd.bufptr[0] != qtd.bufptr[0]) { 2003 ehci_cancel_queue(q); 2004 ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD"); 2005 p = NULL; 2006 } else { 2007 p->qtd = qtd; 2008 ehci_qh_do_overlay(q); 2009 } 2010 } 2011 2012 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 2013 if (p != NULL) { 2014 /* transfer canceled by guest (clear active) */ 2015 ehci_cancel_queue(q); 2016 p = NULL; 2017 } 2018 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2019 again = 1; 2020 } else if (p != NULL) { 2021 switch (p->async) { 2022 case EHCI_ASYNC_NONE: 2023 case EHCI_ASYNC_INITIALIZED: 2024 /* Not yet executed (MULT), or previously nacked (int) packet */ 2025 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 2026 break; 2027 case EHCI_ASYNC_INFLIGHT: 2028 /* Unfinished async handled packet, go horizontal */ 2029 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2030 break; 2031 case EHCI_ASYNC_FINISHED: 2032 /* 2033 * We get here when advqueue moves to a packet which is already 2034 * finished, which can happen with packets queued up by fill_queue 2035 */ 2036 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 2037 break; 2038 } 2039 again = 1; 2040 } else { 2041 p = ehci_alloc_packet(q); 2042 p->qtdaddr = q->qtdaddr; 2043 p->qtd = qtd; 2044 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 2045 again = 1; 2046 } 2047 2048 return again; 2049 } 2050 2051 static int ehci_state_horizqh(EHCIQueue *q) 2052 { 2053 int again = 0; 2054 2055 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { 2056 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); 2057 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); 2058 again = 1; 2059 } else { 2060 ehci_set_state(q->ehci, q->async, EST_ACTIVE); 2061 } 2062 2063 return again; 2064 } 2065 2066 static int ehci_fill_queue(EHCIPacket *p) 2067 { 2068 EHCIQueue *q = p->queue; 2069 EHCIqtd qtd = p->qtd; 2070 uint32_t qtdaddr; 2071 2072 for (;;) { 2073 if (NLPTR_TBIT(qtd.altnext) == 0) { 2074 break; 2075 } 2076 if (NLPTR_TBIT(qtd.next) != 0) { 2077 break; 2078 } 2079 qtdaddr = qtd.next; 2080 get_dwords(q->ehci, NLPTR_GET(qtdaddr), 2081 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); 2082 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); 2083 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 2084 break; 2085 } 2086 p = ehci_alloc_packet(q); 2087 p->qtdaddr = qtdaddr; 2088 p->qtd = qtd; 2089 p->usb_status = ehci_execute(p, "queue"); 2090 if (p->usb_status == USB_RET_PROCERR) { 2091 break; 2092 } 2093 assert(p->usb_status == USB_RET_ASYNC); 2094 p->async = EHCI_ASYNC_INFLIGHT; 2095 } 2096 return p->usb_status; 2097 } 2098 2099 static int ehci_state_execute(EHCIQueue *q) 2100 { 2101 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2102 int again = 0; 2103 2104 assert(p != NULL); 2105 assert(p->qtdaddr == q->qtdaddr); 2106 2107 if (ehci_qh_do_overlay(q) != 0) { 2108 return -1; 2109 } 2110 2111 // TODO verify enough time remains in the uframe as in 4.4.1.1 2112 // TODO write back ptr to async list when done or out of time 2113 2114 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */ 2115 if (!q->async && q->transact_ctr == 0) { 2116 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2117 again = 1; 2118 goto out; 2119 } 2120 2121 if (q->async) { 2122 ehci_set_usbsts(q->ehci, USBSTS_REC); 2123 } 2124 2125 p->usb_status = ehci_execute(p, "process"); 2126 if (p->usb_status == USB_RET_PROCERR) { 2127 again = -1; 2128 goto out; 2129 } 2130 if (p->usb_status == USB_RET_ASYNC) { 2131 ehci_flush_qh(q); 2132 trace_usb_ehci_packet_action(p->queue, p, "async"); 2133 p->async = EHCI_ASYNC_INFLIGHT; 2134 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2135 if (q->async) { 2136 again = (ehci_fill_queue(p) == USB_RET_PROCERR) ? -1 : 1; 2137 } else { 2138 again = 1; 2139 } 2140 goto out; 2141 } 2142 2143 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 2144 again = 1; 2145 2146 out: 2147 return again; 2148 } 2149 2150 static int ehci_state_executing(EHCIQueue *q) 2151 { 2152 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2153 2154 assert(p != NULL); 2155 assert(p->qtdaddr == q->qtdaddr); 2156 2157 ehci_execute_complete(q); 2158 2159 /* 4.10.3 */ 2160 if (!q->async && q->transact_ctr > 0) { 2161 q->transact_ctr--; 2162 } 2163 2164 /* 4.10.5 */ 2165 if (p->usb_status == USB_RET_NAK) { 2166 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2167 } else { 2168 ehci_set_state(q->ehci, q->async, EST_WRITEBACK); 2169 } 2170 2171 ehci_flush_qh(q); 2172 return 1; 2173 } 2174 2175 2176 static int ehci_state_writeback(EHCIQueue *q) 2177 { 2178 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 2179 uint32_t *qtd, addr; 2180 int again = 0; 2181 2182 /* Write back the QTD from the QH area */ 2183 assert(p != NULL); 2184 assert(p->qtdaddr == q->qtdaddr); 2185 2186 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); 2187 qtd = (uint32_t *) &q->qh.next_qtd; 2188 addr = NLPTR_GET(p->qtdaddr); 2189 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); 2190 ehci_free_packet(p); 2191 2192 /* 2193 * EHCI specs say go horizontal here. 2194 * 2195 * We can also advance the queue here for performance reasons. We 2196 * need to take care to only take that shortcut in case we've 2197 * processed the qtd just written back without errors, i.e. halt 2198 * bit is clear. 2199 */ 2200 if (q->qh.token & QTD_TOKEN_HALT) { 2201 /* 2202 * We should not do any further processing on a halted queue! 2203 * This is esp. important for bulk endpoints with pipelining enabled 2204 * (redirection to a real USB device), where we must cancel all the 2205 * transfers after this one so that: 2206 * 1) If they've completed already, they are not processed further 2207 * causing more stalls, originating from the same failed transfer 2208 * 2) If still in flight, they are cancelled before the guest does 2209 * a clear stall, otherwise the guest and device can loose sync! 2210 */ 2211 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { 2212 ehci_free_packet(p); 2213 } 2214 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2215 again = 1; 2216 } else { 2217 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); 2218 again = 1; 2219 } 2220 return again; 2221 } 2222 2223 /* 2224 * This is the state machine that is common to both async and periodic 2225 */ 2226 2227 static void ehci_advance_state(EHCIState *ehci, int async) 2228 { 2229 EHCIQueue *q = NULL; 2230 int again; 2231 2232 do { 2233 switch(ehci_get_state(ehci, async)) { 2234 case EST_WAITLISTHEAD: 2235 again = ehci_state_waitlisthead(ehci, async); 2236 break; 2237 2238 case EST_FETCHENTRY: 2239 again = ehci_state_fetchentry(ehci, async); 2240 break; 2241 2242 case EST_FETCHQH: 2243 q = ehci_state_fetchqh(ehci, async); 2244 if (q != NULL) { 2245 assert(q->async == async); 2246 again = 1; 2247 } else { 2248 again = 0; 2249 } 2250 break; 2251 2252 case EST_FETCHITD: 2253 again = ehci_state_fetchitd(ehci, async); 2254 break; 2255 2256 case EST_FETCHSITD: 2257 again = ehci_state_fetchsitd(ehci, async); 2258 break; 2259 2260 case EST_ADVANCEQUEUE: 2261 again = ehci_state_advqueue(q); 2262 break; 2263 2264 case EST_FETCHQTD: 2265 again = ehci_state_fetchqtd(q); 2266 break; 2267 2268 case EST_HORIZONTALQH: 2269 again = ehci_state_horizqh(q); 2270 break; 2271 2272 case EST_EXECUTE: 2273 again = ehci_state_execute(q); 2274 if (async) { 2275 ehci->async_stepdown = 0; 2276 } 2277 break; 2278 2279 case EST_EXECUTING: 2280 assert(q != NULL); 2281 if (async) { 2282 ehci->async_stepdown = 0; 2283 } 2284 again = ehci_state_executing(q); 2285 break; 2286 2287 case EST_WRITEBACK: 2288 assert(q != NULL); 2289 again = ehci_state_writeback(q); 2290 break; 2291 2292 default: 2293 fprintf(stderr, "Bad state!\n"); 2294 again = -1; 2295 assert(0); 2296 break; 2297 } 2298 2299 if (again < 0) { 2300 fprintf(stderr, "processing error - resetting ehci HC\n"); 2301 ehci_reset(ehci); 2302 again = 0; 2303 } 2304 } 2305 while (again); 2306 } 2307 2308 static void ehci_advance_async_state(EHCIState *ehci) 2309 { 2310 const int async = 1; 2311 2312 switch(ehci_get_state(ehci, async)) { 2313 case EST_INACTIVE: 2314 if (!ehci_async_enabled(ehci)) { 2315 break; 2316 } 2317 ehci_set_state(ehci, async, EST_ACTIVE); 2318 // No break, fall through to ACTIVE 2319 2320 case EST_ACTIVE: 2321 if (!ehci_async_enabled(ehci)) { 2322 ehci_queues_rip_all(ehci, async); 2323 ehci_set_state(ehci, async, EST_INACTIVE); 2324 break; 2325 } 2326 2327 /* make sure guest has acknowledged the doorbell interrupt */ 2328 /* TO-DO: is this really needed? */ 2329 if (ehci->usbsts & USBSTS_IAA) { 2330 DPRINTF("IAA status bit still set.\n"); 2331 break; 2332 } 2333 2334 /* check that address register has been set */ 2335 if (ehci->asynclistaddr == 0) { 2336 break; 2337 } 2338 2339 ehci_set_state(ehci, async, EST_WAITLISTHEAD); 2340 ehci_advance_state(ehci, async); 2341 2342 /* If the doorbell is set, the guest wants to make a change to the 2343 * schedule. The host controller needs to release cached data. 2344 * (section 4.8.2) 2345 */ 2346 if (ehci->usbcmd & USBCMD_IAAD) { 2347 /* Remove all unseen qhs from the async qhs queue */ 2348 ehci_queues_rip_unseen(ehci, async); 2349 trace_usb_ehci_doorbell_ack(); 2350 ehci->usbcmd &= ~USBCMD_IAAD; 2351 ehci_raise_irq(ehci, USBSTS_IAA); 2352 } 2353 break; 2354 2355 default: 2356 /* this should only be due to a developer mistake */ 2357 fprintf(stderr, "ehci: Bad asynchronous state %d. " 2358 "Resetting to active\n", ehci->astate); 2359 assert(0); 2360 } 2361 } 2362 2363 static void ehci_advance_periodic_state(EHCIState *ehci) 2364 { 2365 uint32_t entry; 2366 uint32_t list; 2367 const int async = 0; 2368 2369 // 4.6 2370 2371 switch(ehci_get_state(ehci, async)) { 2372 case EST_INACTIVE: 2373 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { 2374 ehci_set_state(ehci, async, EST_ACTIVE); 2375 // No break, fall through to ACTIVE 2376 } else 2377 break; 2378 2379 case EST_ACTIVE: 2380 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { 2381 ehci_queues_rip_all(ehci, async); 2382 ehci_set_state(ehci, async, EST_INACTIVE); 2383 break; 2384 } 2385 2386 list = ehci->periodiclistbase & 0xfffff000; 2387 /* check that register has been set */ 2388 if (list == 0) { 2389 break; 2390 } 2391 list |= ((ehci->frindex & 0x1ff8) >> 1); 2392 2393 pci_dma_read(&ehci->dev, list, &entry, sizeof entry); 2394 entry = le32_to_cpu(entry); 2395 2396 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", 2397 ehci->frindex / 8, list, entry); 2398 ehci_set_fetch_addr(ehci, async,entry); 2399 ehci_set_state(ehci, async, EST_FETCHENTRY); 2400 ehci_advance_state(ehci, async); 2401 ehci_queues_rip_unused(ehci, async); 2402 break; 2403 2404 default: 2405 /* this should only be due to a developer mistake */ 2406 fprintf(stderr, "ehci: Bad periodic state %d. " 2407 "Resetting to active\n", ehci->pstate); 2408 assert(0); 2409 } 2410 } 2411 2412 static void ehci_update_frindex(EHCIState *ehci, int frames) 2413 { 2414 int i; 2415 2416 if (!ehci_enabled(ehci)) { 2417 return; 2418 } 2419 2420 for (i = 0; i < frames; i++) { 2421 ehci->frindex += 8; 2422 2423 if (ehci->frindex == 0x00002000) { 2424 ehci_raise_irq(ehci, USBSTS_FLR); 2425 } 2426 2427 if (ehci->frindex == 0x00004000) { 2428 ehci_raise_irq(ehci, USBSTS_FLR); 2429 ehci->frindex = 0; 2430 if (ehci->usbsts_frindex >= 0x00004000) { 2431 ehci->usbsts_frindex -= 0x00004000; 2432 } else { 2433 ehci->usbsts_frindex = 0; 2434 } 2435 } 2436 } 2437 } 2438 2439 static void ehci_frame_timer(void *opaque) 2440 { 2441 EHCIState *ehci = opaque; 2442 int need_timer = 0; 2443 int64_t expire_time, t_now; 2444 uint64_t ns_elapsed; 2445 int frames, skipped_frames; 2446 int i; 2447 2448 t_now = qemu_get_clock_ns(vm_clock); 2449 ns_elapsed = t_now - ehci->last_run_ns; 2450 frames = ns_elapsed / FRAME_TIMER_NS; 2451 2452 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { 2453 need_timer++; 2454 ehci->async_stepdown = 0; 2455 2456 if (frames > ehci->maxframes) { 2457 skipped_frames = frames - ehci->maxframes; 2458 ehci_update_frindex(ehci, skipped_frames); 2459 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames; 2460 frames -= skipped_frames; 2461 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); 2462 } 2463 2464 for (i = 0; i < frames; i++) { 2465 /* 2466 * If we're running behind schedule, we should not catch up 2467 * too fast, as that will make some guests unhappy: 2468 * 1) We must process a minimum of MIN_FR_PER_TICK frames, 2469 * otherwise we will never catch up 2470 * 2) Process frames until the guest has requested an irq (IOC) 2471 */ 2472 if (i >= MIN_FR_PER_TICK) { 2473 ehci_commit_irq(ehci); 2474 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) { 2475 break; 2476 } 2477 } 2478 ehci_update_frindex(ehci, 1); 2479 ehci_advance_periodic_state(ehci); 2480 ehci->last_run_ns += FRAME_TIMER_NS; 2481 } 2482 } else { 2483 if (ehci->async_stepdown < ehci->maxframes / 2) { 2484 ehci->async_stepdown++; 2485 } 2486 ehci_update_frindex(ehci, frames); 2487 ehci->last_run_ns += FRAME_TIMER_NS * frames; 2488 } 2489 2490 /* Async is not inside loop since it executes everything it can once 2491 * called 2492 */ 2493 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { 2494 need_timer++; 2495 ehci_advance_async_state(ehci); 2496 } 2497 2498 ehci_commit_irq(ehci); 2499 if (ehci->usbsts_pending) { 2500 need_timer++; 2501 ehci->async_stepdown = 0; 2502 } 2503 2504 if (need_timer) { 2505 expire_time = t_now + (get_ticks_per_sec() 2506 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); 2507 qemu_mod_timer(ehci->frame_timer, expire_time); 2508 } 2509 } 2510 2511 static void ehci_async_bh(void *opaque) 2512 { 2513 EHCIState *ehci = opaque; 2514 ehci_advance_async_state(ehci); 2515 } 2516 2517 static const MemoryRegionOps ehci_mmio_caps_ops = { 2518 .read = ehci_caps_read, 2519 .valid.min_access_size = 1, 2520 .valid.max_access_size = 4, 2521 .impl.min_access_size = 1, 2522 .impl.max_access_size = 1, 2523 .endianness = DEVICE_LITTLE_ENDIAN, 2524 }; 2525 2526 static const MemoryRegionOps ehci_mmio_opreg_ops = { 2527 .read = ehci_opreg_read, 2528 .write = ehci_opreg_write, 2529 .valid.min_access_size = 4, 2530 .valid.max_access_size = 4, 2531 .endianness = DEVICE_LITTLE_ENDIAN, 2532 }; 2533 2534 static const MemoryRegionOps ehci_mmio_port_ops = { 2535 .read = ehci_port_read, 2536 .write = ehci_port_write, 2537 .valid.min_access_size = 4, 2538 .valid.max_access_size = 4, 2539 .endianness = DEVICE_LITTLE_ENDIAN, 2540 }; 2541 2542 static int usb_ehci_initfn(PCIDevice *dev); 2543 2544 static USBPortOps ehci_port_ops = { 2545 .attach = ehci_attach, 2546 .detach = ehci_detach, 2547 .child_detach = ehci_child_detach, 2548 .wakeup = ehci_wakeup, 2549 .complete = ehci_async_complete_packet, 2550 }; 2551 2552 static USBBusOps ehci_bus_ops = { 2553 .register_companion = ehci_register_companion, 2554 }; 2555 2556 static int usb_ehci_post_load(void *opaque, int version_id) 2557 { 2558 EHCIState *s = opaque; 2559 int i; 2560 2561 for (i = 0; i < NB_PORTS; i++) { 2562 USBPort *companion = s->companion_ports[i]; 2563 if (companion == NULL) { 2564 continue; 2565 } 2566 if (s->portsc[i] & PORTSC_POWNER) { 2567 companion->dev = s->ports[i].dev; 2568 } else { 2569 companion->dev = NULL; 2570 } 2571 } 2572 2573 return 0; 2574 } 2575 2576 static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) 2577 { 2578 EHCIState *ehci = opaque; 2579 2580 /* 2581 * We don't migrate the EHCIQueue-s, instead we rebuild them for the 2582 * schedule in guest memory. We must do the rebuilt ASAP, so that 2583 * USB-devices which have async handled packages have a packet in the 2584 * ep queue to match the completion with. 2585 */ 2586 if (state == RUN_STATE_RUNNING) { 2587 ehci_advance_async_state(ehci); 2588 } 2589 2590 /* 2591 * The schedule rebuilt from guest memory could cause the migration dest 2592 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH 2593 * will never have existed on the destination. Therefor we must flush the 2594 * async schedule on savevm to catch any not yet noticed unlinks. 2595 */ 2596 if (state == RUN_STATE_SAVE_VM) { 2597 ehci_advance_async_state(ehci); 2598 ehci_queues_rip_unseen(ehci, 1); 2599 } 2600 } 2601 2602 static const VMStateDescription vmstate_ehci = { 2603 .name = "ehci", 2604 .version_id = 2, 2605 .minimum_version_id = 1, 2606 .post_load = usb_ehci_post_load, 2607 .fields = (VMStateField[]) { 2608 VMSTATE_PCI_DEVICE(dev, EHCIState), 2609 /* mmio registers */ 2610 VMSTATE_UINT32(usbcmd, EHCIState), 2611 VMSTATE_UINT32(usbsts, EHCIState), 2612 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), 2613 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), 2614 VMSTATE_UINT32(usbintr, EHCIState), 2615 VMSTATE_UINT32(frindex, EHCIState), 2616 VMSTATE_UINT32(ctrldssegment, EHCIState), 2617 VMSTATE_UINT32(periodiclistbase, EHCIState), 2618 VMSTATE_UINT32(asynclistaddr, EHCIState), 2619 VMSTATE_UINT32(configflag, EHCIState), 2620 VMSTATE_UINT32(portsc[0], EHCIState), 2621 VMSTATE_UINT32(portsc[1], EHCIState), 2622 VMSTATE_UINT32(portsc[2], EHCIState), 2623 VMSTATE_UINT32(portsc[3], EHCIState), 2624 VMSTATE_UINT32(portsc[4], EHCIState), 2625 VMSTATE_UINT32(portsc[5], EHCIState), 2626 /* frame timer */ 2627 VMSTATE_TIMER(frame_timer, EHCIState), 2628 VMSTATE_UINT64(last_run_ns, EHCIState), 2629 VMSTATE_UINT32(async_stepdown, EHCIState), 2630 /* schedule state */ 2631 VMSTATE_UINT32(astate, EHCIState), 2632 VMSTATE_UINT32(pstate, EHCIState), 2633 VMSTATE_UINT32(a_fetch_addr, EHCIState), 2634 VMSTATE_UINT32(p_fetch_addr, EHCIState), 2635 VMSTATE_END_OF_LIST() 2636 } 2637 }; 2638 2639 static Property ehci_properties[] = { 2640 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), 2641 DEFINE_PROP_END_OF_LIST(), 2642 }; 2643 2644 static void ehci_class_init(ObjectClass *klass, void *data) 2645 { 2646 DeviceClass *dc = DEVICE_CLASS(klass); 2647 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2648 2649 k->init = usb_ehci_initfn; 2650 k->vendor_id = PCI_VENDOR_ID_INTEL; 2651 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ 2652 k->revision = 0x10; 2653 k->class_id = PCI_CLASS_SERIAL_USB; 2654 dc->vmsd = &vmstate_ehci; 2655 dc->props = ehci_properties; 2656 } 2657 2658 static TypeInfo ehci_info = { 2659 .name = "usb-ehci", 2660 .parent = TYPE_PCI_DEVICE, 2661 .instance_size = sizeof(EHCIState), 2662 .class_init = ehci_class_init, 2663 }; 2664 2665 static void ich9_ehci_class_init(ObjectClass *klass, void *data) 2666 { 2667 DeviceClass *dc = DEVICE_CLASS(klass); 2668 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 2669 2670 k->init = usb_ehci_initfn; 2671 k->vendor_id = PCI_VENDOR_ID_INTEL; 2672 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; 2673 k->revision = 0x03; 2674 k->class_id = PCI_CLASS_SERIAL_USB; 2675 dc->vmsd = &vmstate_ehci; 2676 dc->props = ehci_properties; 2677 } 2678 2679 static TypeInfo ich9_ehci_info = { 2680 .name = "ich9-usb-ehci1", 2681 .parent = TYPE_PCI_DEVICE, 2682 .instance_size = sizeof(EHCIState), 2683 .class_init = ich9_ehci_class_init, 2684 }; 2685 2686 static int usb_ehci_initfn(PCIDevice *dev) 2687 { 2688 EHCIState *s = DO_UPCAST(EHCIState, dev, dev); 2689 uint8_t *pci_conf = s->dev.config; 2690 int i; 2691 2692 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); 2693 2694 /* capabilities pointer */ 2695 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); 2696 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); 2697 2698 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ 2699 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); 2700 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); 2701 2702 // pci_conf[0x50] = 0x01; // power management caps 2703 2704 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) 2705 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) 2706 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) 2707 2708 pci_conf[0x64] = 0x00; 2709 pci_conf[0x65] = 0x00; 2710 pci_conf[0x66] = 0x00; 2711 pci_conf[0x67] = 0x00; 2712 pci_conf[0x68] = 0x01; 2713 pci_conf[0x69] = 0x00; 2714 pci_conf[0x6a] = 0x00; 2715 pci_conf[0x6b] = 0x00; // USBLEGSUP 2716 pci_conf[0x6c] = 0x00; 2717 pci_conf[0x6d] = 0x00; 2718 pci_conf[0x6e] = 0x00; 2719 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS 2720 2721 /* 2.2 host controller interface version */ 2722 s->caps[0x00] = (uint8_t) OPREGBASE; 2723 s->caps[0x01] = 0x00; 2724 s->caps[0x02] = 0x00; 2725 s->caps[0x03] = 0x01; /* HC version */ 2726 s->caps[0x04] = NB_PORTS; /* Number of downstream ports */ 2727 s->caps[0x05] = 0x00; /* No companion ports at present */ 2728 s->caps[0x06] = 0x00; 2729 s->caps[0x07] = 0x00; 2730 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ 2731 s->caps[0x09] = 0x68; /* EECP */ 2732 s->caps[0x0a] = 0x00; 2733 s->caps[0x0b] = 0x00; 2734 2735 s->irq = s->dev.irq[3]; 2736 2737 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); 2738 for(i = 0; i < NB_PORTS; i++) { 2739 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, 2740 USB_SPEED_MASK_HIGH); 2741 s->ports[i].dev = 0; 2742 } 2743 2744 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); 2745 s->async_bh = qemu_bh_new(ehci_async_bh, s); 2746 QTAILQ_INIT(&s->aqueues); 2747 QTAILQ_INIT(&s->pqueues); 2748 usb_packet_init(&s->ipacket); 2749 2750 qemu_register_reset(ehci_reset, s); 2751 qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); 2752 2753 memory_region_init(&s->mem, "ehci", MMIO_SIZE); 2754 memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, 2755 "capabilities", OPREGBASE); 2756 memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, 2757 "operational", PORTSC_BEGIN - OPREGBASE); 2758 memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, 2759 "ports", PORTSC_END - PORTSC_BEGIN); 2760 2761 memory_region_add_subregion(&s->mem, 0, &s->mem_caps); 2762 memory_region_add_subregion(&s->mem, OPREGBASE, &s->mem_opreg); 2763 memory_region_add_subregion(&s->mem, PORTSC_BEGIN, &s->mem_ports); 2764 2765 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); 2766 2767 return 0; 2768 } 2769 2770 static void ehci_register_types(void) 2771 { 2772 type_register_static(&ehci_info); 2773 type_register_static(&ich9_ehci_info); 2774 } 2775 2776 type_init(ehci_register_types) 2777 2778 /* 2779 * vim: expandtab ts=4 2780 */ 2781