1 /* 2 * QEMU USB EHCI Emulation 3 * 4 * Copyright(c) 2008 Emutex Ltd. (address@hidden) 5 * Copyright(c) 2011-2012 Red Hat, Inc. 6 * 7 * Red Hat Authors: 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * Hans de Goede <hdegoede@redhat.com> 10 * 11 * EHCI project was started by Mark Burkley, with contributions by 12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, 13 * Jan Kiszka and Vincent Palatin contributed bugfixes. 14 * 15 * This library is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU Lesser General Public 17 * License as published by the Free Software Foundation; either 18 * version 2.1 of the License, or (at your option) any later version. 19 * 20 * This library is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23 * Lesser General Public License for more details. 24 * 25 * You should have received a copy of the GNU Lesser General Public License 26 * along with this program; if not, see <http://www.gnu.org/licenses/>. 27 */ 28 29 #include "qemu/osdep.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/usb/ehci-regs.h" 33 #include "hw/usb/hcd-ehci.h" 34 #include "migration/vmstate.h" 35 #include "trace.h" 36 #include "qemu/error-report.h" 37 #include "qemu/main-loop.h" 38 39 #define FRAME_TIMER_FREQ 1000 40 #define FRAME_TIMER_NS (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ) 41 #define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8) 42 43 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints 44 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction 45 #define MAX_QH 100 // Max allowable queue heads in a chain 46 #define MIN_UFR_PER_TICK 24 /* Min frames to process when catching up */ 47 #define PERIODIC_ACTIVE 512 /* Micro-frames */ 48 49 /* Internal periodic / asynchronous schedule state machine states 50 */ 51 typedef enum { 52 EST_INACTIVE = 1000, 53 EST_ACTIVE, 54 EST_EXECUTING, 55 EST_SLEEPING, 56 /* The following states are internal to the state machine function 57 */ 58 EST_WAITLISTHEAD, 59 EST_FETCHENTRY, 60 EST_FETCHQH, 61 EST_FETCHITD, 62 EST_FETCHSITD, 63 EST_ADVANCEQUEUE, 64 EST_FETCHQTD, 65 EST_EXECUTE, 66 EST_WRITEBACK, 67 EST_HORIZONTALQH 68 } EHCI_STATES; 69 70 /* macros for accessing fields within next link pointer entry */ 71 #define NLPTR_GET(x) ((x) & 0xffffffe0) 72 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) 73 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid 74 75 /* link pointer types */ 76 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor 77 #define NLPTR_TYPE_QH 1 // queue head 78 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor 79 #define NLPTR_TYPE_FSTN 3 // frame span traversal node 80 81 #define SET_LAST_RUN_CLOCK(s) \ 82 (s)->last_run_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 83 84 /* nifty macros from Arnon's EHCI version */ 85 #define get_field(data, field) \ 86 (((data) & field##_MASK) >> field##_SH) 87 88 #define set_field(data, newval, field) do { \ 89 uint32_t val = *data; \ 90 val &= ~ field##_MASK; \ 91 val |= ((newval) << field##_SH) & field##_MASK; \ 92 *data = val; \ 93 } while(0) 94 95 static const char *ehci_state_names[] = { 96 [EST_INACTIVE] = "INACTIVE", 97 [EST_ACTIVE] = "ACTIVE", 98 [EST_EXECUTING] = "EXECUTING", 99 [EST_SLEEPING] = "SLEEPING", 100 [EST_WAITLISTHEAD] = "WAITLISTHEAD", 101 [EST_FETCHENTRY] = "FETCH ENTRY", 102 [EST_FETCHQH] = "FETCH QH", 103 [EST_FETCHITD] = "FETCH ITD", 104 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", 105 [EST_FETCHQTD] = "FETCH QTD", 106 [EST_EXECUTE] = "EXECUTE", 107 [EST_WRITEBACK] = "WRITEBACK", 108 [EST_HORIZONTALQH] = "HORIZONTALQH", 109 }; 110 111 static const char *ehci_mmio_names[] = { 112 [USBCMD] = "USBCMD", 113 [USBSTS] = "USBSTS", 114 [USBINTR] = "USBINTR", 115 [FRINDEX] = "FRINDEX", 116 [PERIODICLISTBASE] = "P-LIST BASE", 117 [ASYNCLISTADDR] = "A-LIST ADDR", 118 [CONFIGFLAG] = "CONFIGFLAG", 119 }; 120 121 static int ehci_state_executing(EHCIQueue *q); 122 static int ehci_state_writeback(EHCIQueue *q); 123 static int ehci_state_advqueue(EHCIQueue *q); 124 static int ehci_fill_queue(EHCIPacket *p); 125 static void ehci_free_packet(EHCIPacket *p); 126 127 static const char *nr2str(const char **n, size_t len, uint32_t nr) 128 { 129 if (nr < len && n[nr] != NULL) { 130 return n[nr]; 131 } else { 132 return "unknown"; 133 } 134 } 135 136 static const char *state2str(uint32_t state) 137 { 138 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); 139 } 140 141 static const char *addr2str(hwaddr addr) 142 { 143 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); 144 } 145 146 static void ehci_trace_usbsts(uint32_t mask, int state) 147 { 148 /* interrupts */ 149 if (mask & USBSTS_INT) { 150 trace_usb_ehci_usbsts("INT", state); 151 } 152 if (mask & USBSTS_ERRINT) { 153 trace_usb_ehci_usbsts("ERRINT", state); 154 } 155 if (mask & USBSTS_PCD) { 156 trace_usb_ehci_usbsts("PCD", state); 157 } 158 if (mask & USBSTS_FLR) { 159 trace_usb_ehci_usbsts("FLR", state); 160 } 161 if (mask & USBSTS_HSE) { 162 trace_usb_ehci_usbsts("HSE", state); 163 } 164 if (mask & USBSTS_IAA) { 165 trace_usb_ehci_usbsts("IAA", state); 166 } 167 168 /* status */ 169 if (mask & USBSTS_HALT) { 170 trace_usb_ehci_usbsts("HALT", state); 171 } 172 if (mask & USBSTS_REC) { 173 trace_usb_ehci_usbsts("REC", state); 174 } 175 if (mask & USBSTS_PSS) { 176 trace_usb_ehci_usbsts("PSS", state); 177 } 178 if (mask & USBSTS_ASS) { 179 trace_usb_ehci_usbsts("ASS", state); 180 } 181 } 182 183 static inline void ehci_set_usbsts(EHCIState *s, int mask) 184 { 185 if ((s->usbsts & mask) == mask) { 186 return; 187 } 188 ehci_trace_usbsts(mask, 1); 189 s->usbsts |= mask; 190 } 191 192 static inline void ehci_clear_usbsts(EHCIState *s, int mask) 193 { 194 if ((s->usbsts & mask) == 0) { 195 return; 196 } 197 ehci_trace_usbsts(mask, 0); 198 s->usbsts &= ~mask; 199 } 200 201 /* update irq line */ 202 static inline void ehci_update_irq(EHCIState *s) 203 { 204 int level = 0; 205 206 if ((s->usbsts & USBINTR_MASK) & s->usbintr) { 207 level = 1; 208 } 209 210 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr); 211 qemu_set_irq(s->irq, level); 212 } 213 214 /* flag interrupt condition */ 215 static inline void ehci_raise_irq(EHCIState *s, int intr) 216 { 217 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) { 218 s->usbsts |= intr; 219 ehci_update_irq(s); 220 } else { 221 s->usbsts_pending |= intr; 222 } 223 } 224 225 /* 226 * Commit pending interrupts (added via ehci_raise_irq), 227 * at the rate allowed by "Interrupt Threshold Control". 228 */ 229 static inline void ehci_commit_irq(EHCIState *s) 230 { 231 uint32_t itc; 232 233 if (!s->usbsts_pending) { 234 return; 235 } 236 if (s->usbsts_frindex > s->frindex) { 237 return; 238 } 239 240 itc = (s->usbcmd >> 16) & 0xff; 241 s->usbsts |= s->usbsts_pending; 242 s->usbsts_pending = 0; 243 s->usbsts_frindex = s->frindex + itc; 244 ehci_update_irq(s); 245 } 246 247 static void ehci_update_halt(EHCIState *s) 248 { 249 if (s->usbcmd & USBCMD_RUNSTOP) { 250 ehci_clear_usbsts(s, USBSTS_HALT); 251 } else { 252 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) { 253 ehci_set_usbsts(s, USBSTS_HALT); 254 } 255 } 256 } 257 258 static void ehci_set_state(EHCIState *s, int async, int state) 259 { 260 if (async) { 261 trace_usb_ehci_state("async", state2str(state)); 262 s->astate = state; 263 if (s->astate == EST_INACTIVE) { 264 ehci_clear_usbsts(s, USBSTS_ASS); 265 ehci_update_halt(s); 266 } else { 267 ehci_set_usbsts(s, USBSTS_ASS); 268 } 269 } else { 270 trace_usb_ehci_state("periodic", state2str(state)); 271 s->pstate = state; 272 if (s->pstate == EST_INACTIVE) { 273 ehci_clear_usbsts(s, USBSTS_PSS); 274 ehci_update_halt(s); 275 } else { 276 ehci_set_usbsts(s, USBSTS_PSS); 277 } 278 } 279 } 280 281 static int ehci_get_state(EHCIState *s, int async) 282 { 283 return async ? s->astate : s->pstate; 284 } 285 286 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) 287 { 288 if (async) { 289 s->a_fetch_addr = addr; 290 } else { 291 s->p_fetch_addr = addr; 292 } 293 } 294 295 static int ehci_get_fetch_addr(EHCIState *s, int async) 296 { 297 return async ? s->a_fetch_addr : s->p_fetch_addr; 298 } 299 300 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh) 301 { 302 /* need three here due to argument count limits */ 303 trace_usb_ehci_qh_ptrs(q, addr, qh->next, 304 qh->current_qtd, qh->next_qtd, qh->altnext_qtd); 305 trace_usb_ehci_qh_fields(addr, 306 get_field(qh->epchar, QH_EPCHAR_RL), 307 get_field(qh->epchar, QH_EPCHAR_MPLEN), 308 get_field(qh->epchar, QH_EPCHAR_EPS), 309 get_field(qh->epchar, QH_EPCHAR_EP), 310 get_field(qh->epchar, QH_EPCHAR_DEVADDR)); 311 trace_usb_ehci_qh_bits(addr, 312 (bool)(qh->epchar & QH_EPCHAR_C), 313 (bool)(qh->epchar & QH_EPCHAR_H), 314 (bool)(qh->epchar & QH_EPCHAR_DTC), 315 (bool)(qh->epchar & QH_EPCHAR_I)); 316 } 317 318 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd) 319 { 320 /* need three here due to argument count limits */ 321 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); 322 trace_usb_ehci_qtd_fields(addr, 323 get_field(qtd->token, QTD_TOKEN_TBYTES), 324 get_field(qtd->token, QTD_TOKEN_CPAGE), 325 get_field(qtd->token, QTD_TOKEN_CERR), 326 get_field(qtd->token, QTD_TOKEN_PID)); 327 trace_usb_ehci_qtd_bits(addr, 328 (bool)(qtd->token & QTD_TOKEN_IOC), 329 (bool)(qtd->token & QTD_TOKEN_ACTIVE), 330 (bool)(qtd->token & QTD_TOKEN_HALT), 331 (bool)(qtd->token & QTD_TOKEN_BABBLE), 332 (bool)(qtd->token & QTD_TOKEN_XACTERR)); 333 } 334 335 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd) 336 { 337 trace_usb_ehci_itd(addr, itd->next, 338 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), 339 get_field(itd->bufptr[2], ITD_BUFPTR_MULT), 340 get_field(itd->bufptr[0], ITD_BUFPTR_EP), 341 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); 342 } 343 344 static void ehci_trace_sitd(EHCIState *s, hwaddr addr, 345 EHCIsitd *sitd) 346 { 347 trace_usb_ehci_sitd(addr, sitd->next, 348 (bool)(sitd->results & SITD_RESULTS_ACTIVE)); 349 } 350 351 static void ehci_trace_guest_bug(EHCIState *s, const char *message) 352 { 353 trace_usb_ehci_guest_bug(message); 354 warn_report("%s", message); 355 } 356 357 static inline bool ehci_enabled(EHCIState *s) 358 { 359 return s->usbcmd & USBCMD_RUNSTOP; 360 } 361 362 static inline bool ehci_async_enabled(EHCIState *s) 363 { 364 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE); 365 } 366 367 static inline bool ehci_periodic_enabled(EHCIState *s) 368 { 369 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE); 370 } 371 372 /* Get an array of dwords from main memory */ 373 static inline int get_dwords(EHCIState *ehci, uint32_t addr, 374 uint32_t *buf, int num) 375 { 376 int i; 377 378 if (!ehci->as) { 379 ehci_raise_irq(ehci, USBSTS_HSE); 380 ehci->usbcmd &= ~USBCMD_RUNSTOP; 381 trace_usb_ehci_dma_error(); 382 return -1; 383 } 384 385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 386 dma_memory_read(ehci->as, addr, buf, sizeof(*buf)); 387 *buf = le32_to_cpu(*buf); 388 } 389 390 return num; 391 } 392 393 /* Put an array of dwords in to main memory */ 394 static inline int put_dwords(EHCIState *ehci, uint32_t addr, 395 uint32_t *buf, int num) 396 { 397 int i; 398 399 if (!ehci->as) { 400 ehci_raise_irq(ehci, USBSTS_HSE); 401 ehci->usbcmd &= ~USBCMD_RUNSTOP; 402 trace_usb_ehci_dma_error(); 403 return -1; 404 } 405 406 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 407 uint32_t tmp = cpu_to_le32(*buf); 408 dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp)); 409 } 410 411 return num; 412 } 413 414 static int ehci_get_pid(EHCIqtd *qtd) 415 { 416 switch (get_field(qtd->token, QTD_TOKEN_PID)) { 417 case 0: 418 return USB_TOKEN_OUT; 419 case 1: 420 return USB_TOKEN_IN; 421 case 2: 422 return USB_TOKEN_SETUP; 423 default: 424 fprintf(stderr, "bad token\n"); 425 return 0; 426 } 427 } 428 429 static bool ehci_verify_qh(EHCIQueue *q, EHCIqh *qh) 430 { 431 uint32_t devaddr = get_field(qh->epchar, QH_EPCHAR_DEVADDR); 432 uint32_t endp = get_field(qh->epchar, QH_EPCHAR_EP); 433 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) || 434 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) || 435 (qh->current_qtd != q->qh.current_qtd) || 436 (q->async && qh->next_qtd != q->qh.next_qtd) || 437 (memcmp(&qh->altnext_qtd, &q->qh.altnext_qtd, 438 7 * sizeof(uint32_t)) != 0) || 439 (q->dev != NULL && q->dev->addr != devaddr)) { 440 return false; 441 } else { 442 return true; 443 } 444 } 445 446 static bool ehci_verify_qtd(EHCIPacket *p, EHCIqtd *qtd) 447 { 448 if (p->qtdaddr != p->queue->qtdaddr || 449 (p->queue->async && !NLPTR_TBIT(p->qtd.next) && 450 (p->qtd.next != qtd->next)) || 451 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd->altnext)) || 452 p->qtd.token != qtd->token || 453 p->qtd.bufptr[0] != qtd->bufptr[0]) { 454 return false; 455 } else { 456 return true; 457 } 458 } 459 460 static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd) 461 { 462 int ep = get_field(q->qh.epchar, QH_EPCHAR_EP); 463 int pid = ehci_get_pid(qtd); 464 465 /* Note the pid changing is normal for ep 0 (the control ep) */ 466 if (q->last_pid && ep != 0 && pid != q->last_pid) { 467 return false; 468 } else { 469 return true; 470 } 471 } 472 473 /* Finish executing and writeback a packet outside of the regular 474 fetchqh -> fetchqtd -> execute -> writeback cycle */ 475 static void ehci_writeback_async_complete_packet(EHCIPacket *p) 476 { 477 EHCIQueue *q = p->queue; 478 EHCIqtd qtd; 479 EHCIqh qh; 480 int state; 481 482 /* Verify the qh + qtd, like we do when going through fetchqh & fetchqtd */ 483 get_dwords(q->ehci, NLPTR_GET(q->qhaddr), 484 (uint32_t *) &qh, sizeof(EHCIqh) >> 2); 485 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), 486 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2); 487 if (!ehci_verify_qh(q, &qh) || !ehci_verify_qtd(p, &qtd)) { 488 p->async = EHCI_ASYNC_INITIALIZED; 489 ehci_free_packet(p); 490 return; 491 } 492 493 state = ehci_get_state(q->ehci, q->async); 494 ehci_state_executing(q); 495 ehci_state_writeback(q); /* Frees the packet! */ 496 if (!(q->qh.token & QTD_TOKEN_HALT)) { 497 ehci_state_advqueue(q); 498 } 499 ehci_set_state(q->ehci, q->async, state); 500 } 501 502 /* packet management */ 503 504 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) 505 { 506 EHCIPacket *p; 507 508 p = g_new0(EHCIPacket, 1); 509 p->queue = q; 510 usb_packet_init(&p->packet); 511 QTAILQ_INSERT_TAIL(&q->packets, p, next); 512 trace_usb_ehci_packet_action(p->queue, p, "alloc"); 513 return p; 514 } 515 516 static void ehci_free_packet(EHCIPacket *p) 517 { 518 if (p->async == EHCI_ASYNC_FINISHED && 519 !(p->queue->qh.token & QTD_TOKEN_HALT)) { 520 ehci_writeback_async_complete_packet(p); 521 return; 522 } 523 trace_usb_ehci_packet_action(p->queue, p, "free"); 524 if (p->async == EHCI_ASYNC_INFLIGHT) { 525 usb_cancel_packet(&p->packet); 526 } 527 if (p->async == EHCI_ASYNC_FINISHED && 528 p->packet.status == USB_RET_SUCCESS) { 529 fprintf(stderr, 530 "EHCI: Dropping completed packet from halted %s ep %02X\n", 531 (p->pid == USB_TOKEN_IN) ? "in" : "out", 532 get_field(p->queue->qh.epchar, QH_EPCHAR_EP)); 533 } 534 if (p->async != EHCI_ASYNC_NONE) { 535 usb_packet_unmap(&p->packet, &p->sgl); 536 qemu_sglist_destroy(&p->sgl); 537 } 538 QTAILQ_REMOVE(&p->queue->packets, p, next); 539 usb_packet_cleanup(&p->packet); 540 g_free(p); 541 } 542 543 /* queue management */ 544 545 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async) 546 { 547 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 548 EHCIQueue *q; 549 550 q = g_malloc0(sizeof(*q)); 551 q->ehci = ehci; 552 q->qhaddr = addr; 553 q->async = async; 554 QTAILQ_INIT(&q->packets); 555 QTAILQ_INSERT_HEAD(head, q, next); 556 trace_usb_ehci_queue_action(q, "alloc"); 557 return q; 558 } 559 560 static void ehci_queue_stopped(EHCIQueue *q) 561 { 562 int endp = get_field(q->qh.epchar, QH_EPCHAR_EP); 563 564 if (!q->last_pid || !q->dev) { 565 return; 566 } 567 568 usb_device_ep_stopped(q->dev, usb_ep_get(q->dev, q->last_pid, endp)); 569 } 570 571 static int ehci_cancel_queue(EHCIQueue *q) 572 { 573 EHCIPacket *p; 574 int packets = 0; 575 576 p = QTAILQ_FIRST(&q->packets); 577 if (p == NULL) { 578 goto leave; 579 } 580 581 trace_usb_ehci_queue_action(q, "cancel"); 582 do { 583 ehci_free_packet(p); 584 packets++; 585 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL); 586 587 leave: 588 ehci_queue_stopped(q); 589 return packets; 590 } 591 592 static int ehci_reset_queue(EHCIQueue *q) 593 { 594 int packets; 595 596 trace_usb_ehci_queue_action(q, "reset"); 597 packets = ehci_cancel_queue(q); 598 q->dev = NULL; 599 q->qtdaddr = 0; 600 q->last_pid = 0; 601 return packets; 602 } 603 604 static void ehci_free_queue(EHCIQueue *q, const char *warn) 605 { 606 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues; 607 int cancelled; 608 609 trace_usb_ehci_queue_action(q, "free"); 610 cancelled = ehci_cancel_queue(q); 611 if (warn && cancelled > 0) { 612 ehci_trace_guest_bug(q->ehci, warn); 613 } 614 QTAILQ_REMOVE(head, q, next); 615 g_free(q); 616 } 617 618 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, 619 int async) 620 { 621 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 622 EHCIQueue *q; 623 624 QTAILQ_FOREACH(q, head, next) { 625 if (addr == q->qhaddr) { 626 return q; 627 } 628 } 629 return NULL; 630 } 631 632 static void ehci_queues_rip_unused(EHCIState *ehci, int async) 633 { 634 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 635 const char *warn = async ? "guest unlinked busy QH" : NULL; 636 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4; 637 EHCIQueue *q, *tmp; 638 639 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 640 if (q->seen) { 641 q->seen = 0; 642 q->ts = ehci->last_run_ns; 643 continue; 644 } 645 if (ehci->last_run_ns < q->ts + maxage) { 646 continue; 647 } 648 ehci_free_queue(q, warn); 649 } 650 } 651 652 static void ehci_queues_rip_unseen(EHCIState *ehci, int async) 653 { 654 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 655 EHCIQueue *q, *tmp; 656 657 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 658 if (!q->seen) { 659 ehci_free_queue(q, NULL); 660 } 661 } 662 } 663 664 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) 665 { 666 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 667 EHCIQueue *q, *tmp; 668 669 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 670 if (q->dev != dev) { 671 continue; 672 } 673 ehci_free_queue(q, NULL); 674 } 675 } 676 677 static void ehci_queues_rip_all(EHCIState *ehci, int async) 678 { 679 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; 680 const char *warn = async ? "guest stopped busy async schedule" : NULL; 681 EHCIQueue *q, *tmp; 682 683 QTAILQ_FOREACH_SAFE(q, head, next, tmp) { 684 ehci_free_queue(q, warn); 685 } 686 } 687 688 /* Attach or detach a device on root hub */ 689 690 static void ehci_attach(USBPort *port) 691 { 692 EHCIState *s = port->opaque; 693 uint32_t *portsc = &s->portsc[port->index]; 694 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 695 696 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc); 697 698 if (*portsc & PORTSC_POWNER) { 699 USBPort *companion = s->companion_ports[port->index]; 700 companion->dev = port->dev; 701 companion->ops->attach(companion); 702 return; 703 } 704 705 *portsc |= PORTSC_CONNECT; 706 *portsc |= PORTSC_CSC; 707 708 ehci_raise_irq(s, USBSTS_PCD); 709 } 710 711 static void ehci_detach(USBPort *port) 712 { 713 EHCIState *s = port->opaque; 714 uint32_t *portsc = &s->portsc[port->index]; 715 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci"; 716 717 trace_usb_ehci_port_detach(port->index, owner); 718 719 if (*portsc & PORTSC_POWNER) { 720 USBPort *companion = s->companion_ports[port->index]; 721 companion->ops->detach(companion); 722 companion->dev = NULL; 723 /* 724 * EHCI spec 4.2.2: "When a disconnect occurs... On the event, 725 * the port ownership is returned immediately to the EHCI controller." 726 */ 727 *portsc &= ~PORTSC_POWNER; 728 return; 729 } 730 731 ehci_queues_rip_device(s, port->dev, 0); 732 ehci_queues_rip_device(s, port->dev, 1); 733 734 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED|PORTSC_SUSPEND); 735 *portsc |= PORTSC_CSC; 736 737 ehci_raise_irq(s, USBSTS_PCD); 738 } 739 740 static void ehci_child_detach(USBPort *port, USBDevice *child) 741 { 742 EHCIState *s = port->opaque; 743 uint32_t portsc = s->portsc[port->index]; 744 745 if (portsc & PORTSC_POWNER) { 746 USBPort *companion = s->companion_ports[port->index]; 747 companion->ops->child_detach(companion, child); 748 return; 749 } 750 751 ehci_queues_rip_device(s, child, 0); 752 ehci_queues_rip_device(s, child, 1); 753 } 754 755 static void ehci_wakeup(USBPort *port) 756 { 757 EHCIState *s = port->opaque; 758 uint32_t *portsc = &s->portsc[port->index]; 759 760 if (*portsc & PORTSC_POWNER) { 761 USBPort *companion = s->companion_ports[port->index]; 762 if (companion->ops->wakeup) { 763 companion->ops->wakeup(companion); 764 } 765 return; 766 } 767 768 if (*portsc & PORTSC_SUSPEND) { 769 trace_usb_ehci_port_wakeup(port->index); 770 *portsc |= PORTSC_FPRES; 771 ehci_raise_irq(s, USBSTS_PCD); 772 } 773 774 qemu_bh_schedule(s->async_bh); 775 } 776 777 static void ehci_register_companion(USBBus *bus, USBPort *ports[], 778 uint32_t portcount, uint32_t firstport, 779 Error **errp) 780 { 781 EHCIState *s = container_of(bus, EHCIState, bus); 782 uint32_t i; 783 784 if (firstport + portcount > NB_PORTS) { 785 error_setg(errp, "firstport must be between 0 and %u", 786 NB_PORTS - portcount); 787 return; 788 } 789 790 for (i = 0; i < portcount; i++) { 791 if (s->companion_ports[firstport + i]) { 792 error_setg(errp, "firstport %u asks for ports %u-%u," 793 " but port %u has a companion assigned already", 794 firstport, firstport, firstport + portcount - 1, 795 firstport + i); 796 return; 797 } 798 } 799 800 for (i = 0; i < portcount; i++) { 801 s->companion_ports[firstport + i] = ports[i]; 802 s->ports[firstport + i].speedmask |= 803 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; 804 /* Ensure devs attached before the initial reset go to the companion */ 805 s->portsc[firstport + i] = PORTSC_POWNER; 806 } 807 808 s->companion_count++; 809 s->caps[0x05] = (s->companion_count << 4) | portcount; 810 } 811 812 static void ehci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 813 unsigned int stream) 814 { 815 EHCIState *s = container_of(bus, EHCIState, bus); 816 uint32_t portsc = s->portsc[ep->dev->port->index]; 817 818 if (portsc & PORTSC_POWNER) { 819 return; 820 } 821 822 s->periodic_sched_active = PERIODIC_ACTIVE; 823 qemu_bh_schedule(s->async_bh); 824 } 825 826 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) 827 { 828 USBDevice *dev; 829 USBPort *port; 830 int i; 831 832 for (i = 0; i < NB_PORTS; i++) { 833 port = &ehci->ports[i]; 834 if (!(ehci->portsc[i] & PORTSC_PED)) { 835 DPRINTF("Port %d not enabled\n", i); 836 continue; 837 } 838 dev = usb_find_device(port, addr); 839 if (dev != NULL) { 840 return dev; 841 } 842 } 843 return NULL; 844 } 845 846 /* 4.1 host controller initialization */ 847 void ehci_reset(void *opaque) 848 { 849 EHCIState *s = opaque; 850 int i; 851 USBDevice *devs[NB_PORTS]; 852 853 trace_usb_ehci_reset(); 854 855 /* 856 * Do the detach before touching portsc, so that it correctly gets send to 857 * us or to our companion based on PORTSC_POWNER before the reset. 858 */ 859 for(i = 0; i < NB_PORTS; i++) { 860 devs[i] = s->ports[i].dev; 861 if (devs[i] && devs[i]->attached) { 862 usb_detach(&s->ports[i]); 863 } 864 } 865 866 memset(&s->opreg, 0x00, sizeof(s->opreg)); 867 memset(&s->portsc, 0x00, sizeof(s->portsc)); 868 869 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; 870 s->usbsts = USBSTS_HALT; 871 s->usbsts_pending = 0; 872 s->usbsts_frindex = 0; 873 ehci_update_irq(s); 874 875 s->astate = EST_INACTIVE; 876 s->pstate = EST_INACTIVE; 877 878 for(i = 0; i < NB_PORTS; i++) { 879 if (s->companion_ports[i]) { 880 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; 881 } else { 882 s->portsc[i] = PORTSC_PPOWER; 883 } 884 if (devs[i] && devs[i]->attached) { 885 usb_attach(&s->ports[i]); 886 usb_device_reset(devs[i]); 887 } 888 } 889 ehci_queues_rip_all(s, 0); 890 ehci_queues_rip_all(s, 1); 891 timer_del(s->frame_timer); 892 qemu_bh_cancel(s->async_bh); 893 } 894 895 static uint64_t ehci_caps_read(void *ptr, hwaddr addr, 896 unsigned size) 897 { 898 EHCIState *s = ptr; 899 return s->caps[addr]; 900 } 901 902 static void ehci_caps_write(void *ptr, hwaddr addr, 903 uint64_t val, unsigned size) 904 { 905 } 906 907 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, 908 unsigned size) 909 { 910 EHCIState *s = ptr; 911 uint32_t val; 912 913 switch (addr) { 914 case FRINDEX: 915 /* Round down to mult of 8, else it can go backwards on migration */ 916 val = s->frindex & ~7; 917 break; 918 default: 919 val = s->opreg[addr >> 2]; 920 } 921 922 trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); 923 return val; 924 } 925 926 static uint64_t ehci_port_read(void *ptr, hwaddr addr, 927 unsigned size) 928 { 929 EHCIState *s = ptr; 930 uint32_t val; 931 932 val = s->portsc[addr >> 2]; 933 trace_usb_ehci_portsc_read(addr + s->portscbase, addr >> 2, val); 934 return val; 935 } 936 937 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) 938 { 939 USBDevice *dev = s->ports[port].dev; 940 uint32_t *portsc = &s->portsc[port]; 941 uint32_t orig; 942 943 if (s->companion_ports[port] == NULL) 944 return; 945 946 owner = owner & PORTSC_POWNER; 947 orig = *portsc & PORTSC_POWNER; 948 949 if (!(owner ^ orig)) { 950 return; 951 } 952 953 if (dev && dev->attached) { 954 usb_detach(&s->ports[port]); 955 } 956 957 *portsc &= ~PORTSC_POWNER; 958 *portsc |= owner; 959 960 if (dev && dev->attached) { 961 usb_attach(&s->ports[port]); 962 } 963 } 964 965 static void ehci_port_write(void *ptr, hwaddr addr, 966 uint64_t val, unsigned size) 967 { 968 EHCIState *s = ptr; 969 int port = addr >> 2; 970 uint32_t *portsc = &s->portsc[port]; 971 uint32_t old = *portsc; 972 USBDevice *dev = s->ports[port].dev; 973 974 trace_usb_ehci_portsc_write(addr + s->portscbase, addr >> 2, val); 975 976 /* Clear rwc bits */ 977 *portsc &= ~(val & PORTSC_RWC_MASK); 978 /* The guest may clear, but not set the PED bit */ 979 *portsc &= val | ~PORTSC_PED; 980 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ 981 handle_port_owner_write(s, port, val); 982 /* And finally apply RO_MASK */ 983 val &= PORTSC_RO_MASK; 984 985 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { 986 trace_usb_ehci_port_reset(port, 1); 987 } 988 989 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { 990 trace_usb_ehci_port_reset(port, 0); 991 if (dev && dev->attached) { 992 usb_port_reset(&s->ports[port]); 993 *portsc &= ~PORTSC_CSC; 994 } 995 996 /* 997 * Table 2.16 Set the enable bit(and enable bit change) to indicate 998 * to SW that this port has a high speed device attached 999 */ 1000 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { 1001 val |= PORTSC_PED; 1002 } 1003 } 1004 1005 if ((val & PORTSC_SUSPEND) && !(*portsc & PORTSC_SUSPEND)) { 1006 trace_usb_ehci_port_suspend(port); 1007 } 1008 if (!(val & PORTSC_FPRES) && (*portsc & PORTSC_FPRES)) { 1009 trace_usb_ehci_port_resume(port); 1010 val &= ~PORTSC_SUSPEND; 1011 } 1012 1013 *portsc &= ~PORTSC_RO_MASK; 1014 *portsc |= val; 1015 trace_usb_ehci_portsc_change(addr + s->portscbase, addr >> 2, *portsc, old); 1016 } 1017 1018 static void ehci_opreg_write(void *ptr, hwaddr addr, 1019 uint64_t val, unsigned size) 1020 { 1021 EHCIState *s = ptr; 1022 uint32_t *mmio = s->opreg + (addr >> 2); 1023 uint32_t old = *mmio; 1024 int i; 1025 1026 trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); 1027 1028 switch (addr) { 1029 case USBCMD: 1030 if (val & USBCMD_HCRESET) { 1031 ehci_reset(s); 1032 val = s->usbcmd; 1033 break; 1034 } 1035 1036 /* not supporting dynamic frame list size at the moment */ 1037 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { 1038 fprintf(stderr, "attempt to set frame list size -- value %d\n", 1039 (int)val & USBCMD_FLS); 1040 val &= ~USBCMD_FLS; 1041 } 1042 1043 if (val & USBCMD_IAAD) { 1044 /* 1045 * Process IAAD immediately, otherwise the Linux IAAD watchdog may 1046 * trigger and re-use a qh without us seeing the unlink. 1047 */ 1048 s->async_stepdown = 0; 1049 qemu_bh_schedule(s->async_bh); 1050 trace_usb_ehci_doorbell_ring(); 1051 } 1052 1053 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) != 1054 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) { 1055 if (s->pstate == EST_INACTIVE) { 1056 SET_LAST_RUN_CLOCK(s); 1057 } 1058 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */ 1059 ehci_update_halt(s); 1060 s->async_stepdown = 0; 1061 qemu_bh_schedule(s->async_bh); 1062 } 1063 break; 1064 1065 case USBSTS: 1066 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO 1067 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC 1068 val = s->usbsts; 1069 ehci_update_irq(s); 1070 break; 1071 1072 case USBINTR: 1073 val &= USBINTR_MASK; 1074 if (ehci_enabled(s) && (USBSTS_FLR & val)) { 1075 qemu_bh_schedule(s->async_bh); 1076 } 1077 break; 1078 1079 case FRINDEX: 1080 val &= 0x00003fff; /* frindex is 14bits */ 1081 s->usbsts_frindex = val; 1082 break; 1083 1084 case CONFIGFLAG: 1085 val &= 0x1; 1086 if (val) { 1087 for(i = 0; i < NB_PORTS; i++) 1088 handle_port_owner_write(s, i, 0); 1089 } 1090 break; 1091 1092 case PERIODICLISTBASE: 1093 if (ehci_periodic_enabled(s)) { 1094 fprintf(stderr, 1095 "ehci: PERIODIC list base register set while periodic schedule\n" 1096 " is enabled and HC is enabled\n"); 1097 } 1098 break; 1099 1100 case ASYNCLISTADDR: 1101 if (ehci_async_enabled(s)) { 1102 fprintf(stderr, 1103 "ehci: ASYNC list address register set while async schedule\n" 1104 " is enabled and HC is enabled\n"); 1105 } 1106 break; 1107 } 1108 1109 *mmio = val; 1110 trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), 1111 *mmio, old); 1112 } 1113 1114 /* 1115 * Write the qh back to guest physical memory. This step isn't 1116 * in the EHCI spec but we need to do it since we don't share 1117 * physical memory with our guest VM. 1118 * 1119 * The first three dwords are read-only for the EHCI, so skip them 1120 * when writing back the qh. 1121 */ 1122 static void ehci_flush_qh(EHCIQueue *q) 1123 { 1124 uint32_t *qh = (uint32_t *) &q->qh; 1125 uint32_t dwords = sizeof(EHCIqh) >> 2; 1126 uint32_t addr = NLPTR_GET(q->qhaddr); 1127 1128 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); 1129 } 1130 1131 // 4.10.2 1132 1133 static int ehci_qh_do_overlay(EHCIQueue *q) 1134 { 1135 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1136 int i; 1137 int dtoggle; 1138 int ping; 1139 int eps; 1140 int reload; 1141 1142 assert(p != NULL); 1143 assert(p->qtdaddr == q->qtdaddr); 1144 1145 // remember values in fields to preserve in qh after overlay 1146 1147 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; 1148 ping = q->qh.token & QTD_TOKEN_PING; 1149 1150 q->qh.current_qtd = p->qtdaddr; 1151 q->qh.next_qtd = p->qtd.next; 1152 q->qh.altnext_qtd = p->qtd.altnext; 1153 q->qh.token = p->qtd.token; 1154 1155 1156 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); 1157 if (eps == EHCI_QH_EPS_HIGH) { 1158 q->qh.token &= ~QTD_TOKEN_PING; 1159 q->qh.token |= ping; 1160 } 1161 1162 reload = get_field(q->qh.epchar, QH_EPCHAR_RL); 1163 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); 1164 1165 for (i = 0; i < 5; i++) { 1166 q->qh.bufptr[i] = p->qtd.bufptr[i]; 1167 } 1168 1169 if (!(q->qh.epchar & QH_EPCHAR_DTC)) { 1170 // preserve QH DT bit 1171 q->qh.token &= ~QTD_TOKEN_DTOGGLE; 1172 q->qh.token |= dtoggle; 1173 } 1174 1175 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; 1176 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; 1177 1178 ehci_flush_qh(q); 1179 1180 return 0; 1181 } 1182 1183 static int ehci_init_transfer(EHCIPacket *p) 1184 { 1185 uint32_t cpage, offset, bytes, plen; 1186 dma_addr_t page; 1187 1188 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); 1189 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); 1190 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; 1191 qemu_sglist_init(&p->sgl, p->queue->ehci->device, 5, p->queue->ehci->as); 1192 1193 while (bytes > 0) { 1194 if (cpage > 4) { 1195 fprintf(stderr, "cpage out of range (%d)\n", cpage); 1196 qemu_sglist_destroy(&p->sgl); 1197 return -1; 1198 } 1199 1200 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; 1201 page += offset; 1202 plen = bytes; 1203 if (plen > 4096 - offset) { 1204 plen = 4096 - offset; 1205 offset = 0; 1206 cpage++; 1207 } 1208 1209 qemu_sglist_add(&p->sgl, page, plen); 1210 bytes -= plen; 1211 } 1212 return 0; 1213 } 1214 1215 static void ehci_finish_transfer(EHCIQueue *q, int len) 1216 { 1217 uint32_t cpage, offset; 1218 1219 if (len > 0) { 1220 /* update cpage & offset */ 1221 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); 1222 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; 1223 1224 offset += len; 1225 cpage += offset >> QTD_BUFPTR_SH; 1226 offset &= ~QTD_BUFPTR_MASK; 1227 1228 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); 1229 q->qh.bufptr[0] &= QTD_BUFPTR_MASK; 1230 q->qh.bufptr[0] |= offset; 1231 } 1232 } 1233 1234 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) 1235 { 1236 EHCIPacket *p; 1237 EHCIState *s = port->opaque; 1238 uint32_t portsc = s->portsc[port->index]; 1239 1240 if (portsc & PORTSC_POWNER) { 1241 USBPort *companion = s->companion_ports[port->index]; 1242 companion->ops->complete(companion, packet); 1243 return; 1244 } 1245 1246 p = container_of(packet, EHCIPacket, packet); 1247 assert(p->async == EHCI_ASYNC_INFLIGHT); 1248 1249 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 1250 trace_usb_ehci_packet_action(p->queue, p, "remove"); 1251 ehci_free_packet(p); 1252 return; 1253 } 1254 1255 trace_usb_ehci_packet_action(p->queue, p, "wakeup"); 1256 p->async = EHCI_ASYNC_FINISHED; 1257 1258 if (!p->queue->async) { 1259 s->periodic_sched_active = PERIODIC_ACTIVE; 1260 } 1261 qemu_bh_schedule(s->async_bh); 1262 } 1263 1264 static void ehci_execute_complete(EHCIQueue *q) 1265 { 1266 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1267 uint32_t tbytes; 1268 1269 assert(p != NULL); 1270 assert(p->qtdaddr == q->qtdaddr); 1271 assert(p->async == EHCI_ASYNC_INITIALIZED || 1272 p->async == EHCI_ASYNC_FINISHED); 1273 1274 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, " 1275 "status %d, actual_length %d\n", 1276 q->qhaddr, q->qh.next, q->qtdaddr, 1277 p->packet.status, p->packet.actual_length); 1278 1279 switch (p->packet.status) { 1280 case USB_RET_SUCCESS: 1281 break; 1282 case USB_RET_IOERROR: 1283 case USB_RET_NODEV: 1284 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); 1285 set_field(&q->qh.token, 0, QTD_TOKEN_CERR); 1286 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1287 break; 1288 case USB_RET_STALL: 1289 q->qh.token |= QTD_TOKEN_HALT; 1290 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1291 break; 1292 case USB_RET_NAK: 1293 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); 1294 return; /* We're not done yet with this transaction */ 1295 case USB_RET_BABBLE: 1296 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); 1297 ehci_raise_irq(q->ehci, USBSTS_ERRINT); 1298 break; 1299 default: 1300 /* should not be triggerable */ 1301 fprintf(stderr, "USB invalid response %d\n", p->packet.status); 1302 g_assert_not_reached(); 1303 break; 1304 } 1305 1306 /* TODO check 4.12 for splits */ 1307 tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); 1308 if (tbytes && p->pid == USB_TOKEN_IN) { 1309 tbytes -= p->packet.actual_length; 1310 if (tbytes) { 1311 /* 4.15.1.2 must raise int on a short input packet */ 1312 ehci_raise_irq(q->ehci, USBSTS_INT); 1313 if (q->async) { 1314 q->ehci->int_req_by_async = true; 1315 } 1316 } 1317 } else { 1318 tbytes = 0; 1319 } 1320 DPRINTF("updating tbytes to %d\n", tbytes); 1321 set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES); 1322 1323 ehci_finish_transfer(q, p->packet.actual_length); 1324 usb_packet_unmap(&p->packet, &p->sgl); 1325 qemu_sglist_destroy(&p->sgl); 1326 p->async = EHCI_ASYNC_NONE; 1327 1328 q->qh.token ^= QTD_TOKEN_DTOGGLE; 1329 q->qh.token &= ~QTD_TOKEN_ACTIVE; 1330 1331 if (q->qh.token & QTD_TOKEN_IOC) { 1332 ehci_raise_irq(q->ehci, USBSTS_INT); 1333 if (q->async) { 1334 q->ehci->int_req_by_async = true; 1335 } 1336 } 1337 } 1338 1339 /* 4.10.3 returns "again" */ 1340 static int ehci_execute(EHCIPacket *p, const char *action) 1341 { 1342 USBEndpoint *ep; 1343 int endp; 1344 bool spd; 1345 1346 assert(p->async == EHCI_ASYNC_NONE || 1347 p->async == EHCI_ASYNC_INITIALIZED); 1348 1349 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) { 1350 fprintf(stderr, "Attempting to execute inactive qtd\n"); 1351 return -1; 1352 } 1353 1354 if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) { 1355 ehci_trace_guest_bug(p->queue->ehci, 1356 "guest requested more bytes than allowed"); 1357 return -1; 1358 } 1359 1360 if (!ehci_verify_pid(p->queue, &p->qtd)) { 1361 ehci_queue_stopped(p->queue); /* Mark the ep in the prev dir stopped */ 1362 } 1363 p->pid = ehci_get_pid(&p->qtd); 1364 p->queue->last_pid = p->pid; 1365 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP); 1366 ep = usb_ep_get(p->queue->dev, p->pid, endp); 1367 1368 if (p->async == EHCI_ASYNC_NONE) { 1369 if (ehci_init_transfer(p) != 0) { 1370 return -1; 1371 } 1372 1373 spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0); 1374 usb_packet_setup(&p->packet, p->pid, ep, 0, p->qtdaddr, spd, 1375 (p->qtd.token & QTD_TOKEN_IOC) != 0); 1376 usb_packet_map(&p->packet, &p->sgl); 1377 p->async = EHCI_ASYNC_INITIALIZED; 1378 } 1379 1380 trace_usb_ehci_packet_action(p->queue, p, action); 1381 usb_handle_packet(p->queue->dev, &p->packet); 1382 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x " 1383 "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next, 1384 p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status, 1385 p->packet.actual_length); 1386 1387 if (p->packet.actual_length > BUFF_SIZE) { 1388 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); 1389 return -1; 1390 } 1391 1392 return 1; 1393 } 1394 1395 /* 4.7.2 1396 */ 1397 1398 static int ehci_process_itd(EHCIState *ehci, 1399 EHCIitd *itd, 1400 uint32_t addr) 1401 { 1402 USBDevice *dev; 1403 USBEndpoint *ep; 1404 uint32_t i, len, pid, dir, devaddr, endp; 1405 uint32_t pg, off, ptr1, ptr2, max, mult; 1406 1407 ehci->periodic_sched_active = PERIODIC_ACTIVE; 1408 1409 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); 1410 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); 1411 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); 1412 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); 1413 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); 1414 1415 for(i = 0; i < 8; i++) { 1416 if (itd->transact[i] & ITD_XACT_ACTIVE) { 1417 pg = get_field(itd->transact[i], ITD_XACT_PGSEL); 1418 off = itd->transact[i] & ITD_XACT_OFFSET_MASK; 1419 len = get_field(itd->transact[i], ITD_XACT_LENGTH); 1420 1421 if (len > max * mult) { 1422 len = max * mult; 1423 } 1424 if (len > BUFF_SIZE || pg > 6) { 1425 return -1; 1426 } 1427 1428 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); 1429 qemu_sglist_init(&ehci->isgl, ehci->device, 2, ehci->as); 1430 if (off + len > 4096) { 1431 /* transfer crosses page border */ 1432 if (pg == 6) { 1433 qemu_sglist_destroy(&ehci->isgl); 1434 return -1; /* avoid page pg + 1 */ 1435 } 1436 ptr2 = (itd->bufptr[pg + 1] & ITD_BUFPTR_MASK); 1437 uint32_t len2 = off + len - 4096; 1438 uint32_t len1 = len - len2; 1439 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); 1440 qemu_sglist_add(&ehci->isgl, ptr2, len2); 1441 } else { 1442 qemu_sglist_add(&ehci->isgl, ptr1 + off, len); 1443 } 1444 1445 dev = ehci_find_device(ehci, devaddr); 1446 if (dev == NULL) { 1447 ehci_trace_guest_bug(ehci, "no device found"); 1448 return -1; 1449 } 1450 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; 1451 ep = usb_ep_get(dev, pid, endp); 1452 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) { 1453 usb_packet_setup(&ehci->ipacket, pid, ep, 0, addr, false, 1454 (itd->transact[i] & ITD_XACT_IOC) != 0); 1455 usb_packet_map(&ehci->ipacket, &ehci->isgl); 1456 usb_handle_packet(dev, &ehci->ipacket); 1457 usb_packet_unmap(&ehci->ipacket, &ehci->isgl); 1458 } else { 1459 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); 1460 ehci->ipacket.status = USB_RET_NAK; 1461 ehci->ipacket.actual_length = 0; 1462 } 1463 qemu_sglist_destroy(&ehci->isgl); 1464 1465 switch (ehci->ipacket.status) { 1466 case USB_RET_SUCCESS: 1467 break; 1468 default: 1469 fprintf(stderr, "Unexpected iso usb result: %d\n", 1470 ehci->ipacket.status); 1471 /* Fall through */ 1472 case USB_RET_IOERROR: 1473 case USB_RET_NODEV: 1474 /* 3.3.2: XACTERR is only allowed on IN transactions */ 1475 if (dir) { 1476 itd->transact[i] |= ITD_XACT_XACTERR; 1477 ehci_raise_irq(ehci, USBSTS_ERRINT); 1478 } 1479 break; 1480 case USB_RET_BABBLE: 1481 itd->transact[i] |= ITD_XACT_BABBLE; 1482 ehci_raise_irq(ehci, USBSTS_ERRINT); 1483 break; 1484 case USB_RET_NAK: 1485 /* no data for us, so do a zero-length transfer */ 1486 ehci->ipacket.actual_length = 0; 1487 break; 1488 } 1489 if (!dir) { 1490 set_field(&itd->transact[i], len - ehci->ipacket.actual_length, 1491 ITD_XACT_LENGTH); /* OUT */ 1492 } else { 1493 set_field(&itd->transact[i], ehci->ipacket.actual_length, 1494 ITD_XACT_LENGTH); /* IN */ 1495 } 1496 if (itd->transact[i] & ITD_XACT_IOC) { 1497 ehci_raise_irq(ehci, USBSTS_INT); 1498 } 1499 itd->transact[i] &= ~ITD_XACT_ACTIVE; 1500 } 1501 } 1502 return 0; 1503 } 1504 1505 1506 /* This state is the entry point for asynchronous schedule 1507 * processing. Entry here consitutes a EHCI start event state (4.8.5) 1508 */ 1509 static int ehci_state_waitlisthead(EHCIState *ehci, int async) 1510 { 1511 EHCIqh qh; 1512 int i = 0; 1513 int again = 0; 1514 uint32_t entry = ehci->asynclistaddr; 1515 1516 /* set reclamation flag at start event (4.8.6) */ 1517 if (async) { 1518 ehci_set_usbsts(ehci, USBSTS_REC); 1519 } 1520 1521 ehci_queues_rip_unused(ehci, async); 1522 1523 /* Find the head of the list (4.9.1.1) */ 1524 for(i = 0; i < MAX_QH; i++) { 1525 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, 1526 sizeof(EHCIqh) >> 2) < 0) { 1527 return 0; 1528 } 1529 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); 1530 1531 if (qh.epchar & QH_EPCHAR_H) { 1532 if (async) { 1533 entry |= (NLPTR_TYPE_QH << 1); 1534 } 1535 1536 ehci_set_fetch_addr(ehci, async, entry); 1537 ehci_set_state(ehci, async, EST_FETCHENTRY); 1538 again = 1; 1539 goto out; 1540 } 1541 1542 entry = qh.next; 1543 if (entry == ehci->asynclistaddr) { 1544 break; 1545 } 1546 } 1547 1548 /* no head found for list. */ 1549 1550 ehci_set_state(ehci, async, EST_ACTIVE); 1551 1552 out: 1553 return again; 1554 } 1555 1556 1557 /* This state is the entry point for periodic schedule processing as 1558 * well as being a continuation state for async processing. 1559 */ 1560 static int ehci_state_fetchentry(EHCIState *ehci, int async) 1561 { 1562 int again = 0; 1563 uint32_t entry = ehci_get_fetch_addr(ehci, async); 1564 1565 if (NLPTR_TBIT(entry)) { 1566 ehci_set_state(ehci, async, EST_ACTIVE); 1567 goto out; 1568 } 1569 1570 /* section 4.8, only QH in async schedule */ 1571 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { 1572 fprintf(stderr, "non queue head request in async schedule\n"); 1573 return -1; 1574 } 1575 1576 switch (NLPTR_TYPE_GET(entry)) { 1577 case NLPTR_TYPE_QH: 1578 ehci_set_state(ehci, async, EST_FETCHQH); 1579 again = 1; 1580 break; 1581 1582 case NLPTR_TYPE_ITD: 1583 ehci_set_state(ehci, async, EST_FETCHITD); 1584 again = 1; 1585 break; 1586 1587 case NLPTR_TYPE_STITD: 1588 ehci_set_state(ehci, async, EST_FETCHSITD); 1589 again = 1; 1590 break; 1591 1592 default: 1593 /* TODO: handle FSTN type */ 1594 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " 1595 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); 1596 return -1; 1597 } 1598 1599 out: 1600 return again; 1601 } 1602 1603 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) 1604 { 1605 uint32_t entry; 1606 EHCIQueue *q; 1607 EHCIqh qh; 1608 1609 entry = ehci_get_fetch_addr(ehci, async); 1610 q = ehci_find_queue_by_qh(ehci, entry, async); 1611 if (q == NULL) { 1612 q = ehci_alloc_queue(ehci, entry, async); 1613 } 1614 1615 q->seen++; 1616 if (q->seen > 1) { 1617 /* we are going in circles -- stop processing */ 1618 ehci_set_state(ehci, async, EST_ACTIVE); 1619 q = NULL; 1620 goto out; 1621 } 1622 1623 if (get_dwords(ehci, NLPTR_GET(q->qhaddr), 1624 (uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) { 1625 q = NULL; 1626 goto out; 1627 } 1628 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh); 1629 1630 /* 1631 * The overlay area of the qh should never be changed by the guest, 1632 * except when idle, in which case the reset is a nop. 1633 */ 1634 if (!ehci_verify_qh(q, &qh)) { 1635 if (ehci_reset_queue(q) > 0) { 1636 ehci_trace_guest_bug(ehci, "guest updated active QH"); 1637 } 1638 } 1639 q->qh = qh; 1640 1641 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT); 1642 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */ 1643 q->transact_ctr = 4; 1644 } 1645 1646 if (q->dev == NULL) { 1647 q->dev = ehci_find_device(q->ehci, 1648 get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)); 1649 } 1650 1651 if (async && (q->qh.epchar & QH_EPCHAR_H)) { 1652 1653 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ 1654 if (ehci->usbsts & USBSTS_REC) { 1655 ehci_clear_usbsts(ehci, USBSTS_REC); 1656 } else { 1657 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" 1658 " - done processing\n", q->qhaddr); 1659 ehci_set_state(ehci, async, EST_ACTIVE); 1660 q = NULL; 1661 goto out; 1662 } 1663 } 1664 1665 #if EHCI_DEBUG 1666 if (q->qhaddr != q->qh.next) { 1667 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", 1668 q->qhaddr, 1669 q->qh.epchar & QH_EPCHAR_H, 1670 q->qh.token & QTD_TOKEN_HALT, 1671 q->qh.token & QTD_TOKEN_ACTIVE, 1672 q->qh.next); 1673 } 1674 #endif 1675 1676 if (q->qh.token & QTD_TOKEN_HALT) { 1677 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1678 1679 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && 1680 (NLPTR_TBIT(q->qh.current_qtd) == 0) && 1681 (q->qh.current_qtd != 0)) { 1682 q->qtdaddr = q->qh.current_qtd; 1683 ehci_set_state(ehci, async, EST_FETCHQTD); 1684 1685 } else { 1686 /* EHCI spec version 1.0 Section 4.10.2 */ 1687 ehci_set_state(ehci, async, EST_ADVANCEQUEUE); 1688 } 1689 1690 out: 1691 return q; 1692 } 1693 1694 static int ehci_state_fetchitd(EHCIState *ehci, int async) 1695 { 1696 uint32_t entry; 1697 EHCIitd itd; 1698 1699 assert(!async); 1700 entry = ehci_get_fetch_addr(ehci, async); 1701 1702 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1703 sizeof(EHCIitd) >> 2) < 0) { 1704 return -1; 1705 } 1706 ehci_trace_itd(ehci, entry, &itd); 1707 1708 if (ehci_process_itd(ehci, &itd, entry) != 0) { 1709 return -1; 1710 } 1711 1712 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, 1713 sizeof(EHCIitd) >> 2); 1714 ehci_set_fetch_addr(ehci, async, itd.next); 1715 ehci_set_state(ehci, async, EST_FETCHENTRY); 1716 1717 return 1; 1718 } 1719 1720 static int ehci_state_fetchsitd(EHCIState *ehci, int async) 1721 { 1722 uint32_t entry; 1723 EHCIsitd sitd; 1724 1725 assert(!async); 1726 entry = ehci_get_fetch_addr(ehci, async); 1727 1728 if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, 1729 sizeof(EHCIsitd) >> 2) < 0) { 1730 return 0; 1731 } 1732 ehci_trace_sitd(ehci, entry, &sitd); 1733 1734 if (!(sitd.results & SITD_RESULTS_ACTIVE)) { 1735 /* siTD is not active, nothing to do */; 1736 } else { 1737 /* TODO: split transfers are not implemented */ 1738 warn_report("Skipping active siTD"); 1739 } 1740 1741 ehci_set_fetch_addr(ehci, async, sitd.next); 1742 ehci_set_state(ehci, async, EST_FETCHENTRY); 1743 return 1; 1744 } 1745 1746 /* Section 4.10.2 - paragraph 3 */ 1747 static int ehci_state_advqueue(EHCIQueue *q) 1748 { 1749 #if 0 1750 /* TO-DO: 4.10.2 - paragraph 2 1751 * if I-bit is set to 1 and QH is not active 1752 * go to horizontal QH 1753 */ 1754 if (I-bit set) { 1755 ehci_set_state(ehci, async, EST_HORIZONTALQH); 1756 goto out; 1757 } 1758 #endif 1759 1760 /* 1761 * want data and alt-next qTD is valid 1762 */ 1763 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && 1764 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { 1765 q->qtdaddr = q->qh.altnext_qtd; 1766 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1767 1768 /* 1769 * next qTD is valid 1770 */ 1771 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { 1772 q->qtdaddr = q->qh.next_qtd; 1773 ehci_set_state(q->ehci, q->async, EST_FETCHQTD); 1774 1775 /* 1776 * no valid qTD, try next QH 1777 */ 1778 } else { 1779 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1780 } 1781 1782 return 1; 1783 } 1784 1785 /* Section 4.10.2 - paragraph 4 */ 1786 static int ehci_state_fetchqtd(EHCIQueue *q) 1787 { 1788 EHCIqtd qtd; 1789 EHCIPacket *p; 1790 int again = 1; 1791 uint32_t addr; 1792 1793 addr = NLPTR_GET(q->qtdaddr); 1794 if (get_dwords(q->ehci, addr + 8, &qtd.token, 1) < 0) { 1795 return 0; 1796 } 1797 barrier(); 1798 if (get_dwords(q->ehci, addr + 0, &qtd.next, 1) < 0 || 1799 get_dwords(q->ehci, addr + 4, &qtd.altnext, 1) < 0 || 1800 get_dwords(q->ehci, addr + 12, qtd.bufptr, 1801 ARRAY_SIZE(qtd.bufptr)) < 0) { 1802 return 0; 1803 } 1804 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); 1805 1806 p = QTAILQ_FIRST(&q->packets); 1807 if (p != NULL) { 1808 if (!ehci_verify_qtd(p, &qtd)) { 1809 ehci_cancel_queue(q); 1810 if (qtd.token & QTD_TOKEN_ACTIVE) { 1811 ehci_trace_guest_bug(q->ehci, "guest updated active qTD"); 1812 } 1813 p = NULL; 1814 } else { 1815 p->qtd = qtd; 1816 ehci_qh_do_overlay(q); 1817 } 1818 } 1819 1820 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 1821 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1822 } else if (p != NULL) { 1823 switch (p->async) { 1824 case EHCI_ASYNC_NONE: 1825 case EHCI_ASYNC_INITIALIZED: 1826 /* Not yet executed (MULT), or previously nacked (int) packet */ 1827 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 1828 break; 1829 case EHCI_ASYNC_INFLIGHT: 1830 /* Check if the guest has added new tds to the queue */ 1831 again = ehci_fill_queue(QTAILQ_LAST(&q->packets)); 1832 /* Unfinished async handled packet, go horizontal */ 1833 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1834 break; 1835 case EHCI_ASYNC_FINISHED: 1836 /* Complete executing of the packet */ 1837 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 1838 break; 1839 } 1840 } else { 1841 p = ehci_alloc_packet(q); 1842 p->qtdaddr = q->qtdaddr; 1843 p->qtd = qtd; 1844 ehci_set_state(q->ehci, q->async, EST_EXECUTE); 1845 } 1846 1847 return again; 1848 } 1849 1850 static int ehci_state_horizqh(EHCIQueue *q) 1851 { 1852 int again = 0; 1853 1854 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) { 1855 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next); 1856 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY); 1857 again = 1; 1858 } else { 1859 ehci_set_state(q->ehci, q->async, EST_ACTIVE); 1860 } 1861 1862 return again; 1863 } 1864 1865 /* Returns "again" */ 1866 static int ehci_fill_queue(EHCIPacket *p) 1867 { 1868 USBEndpoint *ep = p->packet.ep; 1869 EHCIQueue *q = p->queue; 1870 EHCIqtd qtd = p->qtd; 1871 uint32_t qtdaddr; 1872 1873 for (;;) { 1874 if (NLPTR_TBIT(qtd.next) != 0) { 1875 break; 1876 } 1877 qtdaddr = qtd.next; 1878 /* 1879 * Detect circular td lists, Windows creates these, counting on the 1880 * active bit going low after execution to make the queue stop. 1881 */ 1882 QTAILQ_FOREACH(p, &q->packets, next) { 1883 if (p->qtdaddr == qtdaddr) { 1884 goto leave; 1885 } 1886 } 1887 if (get_dwords(q->ehci, NLPTR_GET(qtdaddr), 1888 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2) < 0) { 1889 return -1; 1890 } 1891 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd); 1892 if (!(qtd.token & QTD_TOKEN_ACTIVE)) { 1893 break; 1894 } 1895 if (!ehci_verify_pid(q, &qtd)) { 1896 ehci_trace_guest_bug(q->ehci, "guest queued token with wrong pid"); 1897 break; 1898 } 1899 p = ehci_alloc_packet(q); 1900 p->qtdaddr = qtdaddr; 1901 p->qtd = qtd; 1902 if (ehci_execute(p, "queue") == -1) { 1903 return -1; 1904 } 1905 assert(p->packet.status == USB_RET_ASYNC); 1906 p->async = EHCI_ASYNC_INFLIGHT; 1907 } 1908 leave: 1909 usb_device_flush_ep_queue(ep->dev, ep); 1910 return 1; 1911 } 1912 1913 static int ehci_state_execute(EHCIQueue *q) 1914 { 1915 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1916 int again = 0; 1917 1918 assert(p != NULL); 1919 assert(p->qtdaddr == q->qtdaddr); 1920 1921 if (ehci_qh_do_overlay(q) != 0) { 1922 return -1; 1923 } 1924 1925 // TODO verify enough time remains in the uframe as in 4.4.1.1 1926 // TODO write back ptr to async list when done or out of time 1927 1928 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */ 1929 if (!q->async && q->transact_ctr == 0) { 1930 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1931 again = 1; 1932 goto out; 1933 } 1934 1935 if (q->async) { 1936 ehci_set_usbsts(q->ehci, USBSTS_REC); 1937 } 1938 1939 again = ehci_execute(p, "process"); 1940 if (again == -1) { 1941 goto out; 1942 } 1943 if (p->packet.status == USB_RET_ASYNC) { 1944 ehci_flush_qh(q); 1945 trace_usb_ehci_packet_action(p->queue, p, "async"); 1946 p->async = EHCI_ASYNC_INFLIGHT; 1947 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1948 if (q->async) { 1949 again = ehci_fill_queue(p); 1950 } else { 1951 again = 1; 1952 } 1953 goto out; 1954 } 1955 1956 ehci_set_state(q->ehci, q->async, EST_EXECUTING); 1957 again = 1; 1958 1959 out: 1960 return again; 1961 } 1962 1963 static int ehci_state_executing(EHCIQueue *q) 1964 { 1965 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1966 1967 assert(p != NULL); 1968 assert(p->qtdaddr == q->qtdaddr); 1969 1970 ehci_execute_complete(q); 1971 1972 /* 4.10.3 */ 1973 if (!q->async && q->transact_ctr > 0) { 1974 q->transact_ctr--; 1975 } 1976 1977 /* 4.10.5 */ 1978 if (p->packet.status == USB_RET_NAK) { 1979 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 1980 } else { 1981 ehci_set_state(q->ehci, q->async, EST_WRITEBACK); 1982 } 1983 1984 ehci_flush_qh(q); 1985 return 1; 1986 } 1987 1988 1989 static int ehci_state_writeback(EHCIQueue *q) 1990 { 1991 EHCIPacket *p = QTAILQ_FIRST(&q->packets); 1992 uint32_t *qtd, addr; 1993 int again = 0; 1994 1995 /* Write back the QTD from the QH area */ 1996 assert(p != NULL); 1997 assert(p->qtdaddr == q->qtdaddr); 1998 1999 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); 2000 qtd = (uint32_t *) &q->qh.next_qtd; 2001 addr = NLPTR_GET(p->qtdaddr); 2002 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2); 2003 ehci_free_packet(p); 2004 2005 /* 2006 * EHCI specs say go horizontal here. 2007 * 2008 * We can also advance the queue here for performance reasons. We 2009 * need to take care to only take that shortcut in case we've 2010 * processed the qtd just written back without errors, i.e. halt 2011 * bit is clear. 2012 */ 2013 if (q->qh.token & QTD_TOKEN_HALT) { 2014 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH); 2015 again = 1; 2016 } else { 2017 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE); 2018 again = 1; 2019 } 2020 return again; 2021 } 2022 2023 /* 2024 * This is the state machine that is common to both async and periodic 2025 */ 2026 2027 static void ehci_advance_state(EHCIState *ehci, int async) 2028 { 2029 EHCIQueue *q = NULL; 2030 int itd_count = 0; 2031 int again; 2032 2033 do { 2034 switch(ehci_get_state(ehci, async)) { 2035 case EST_WAITLISTHEAD: 2036 again = ehci_state_waitlisthead(ehci, async); 2037 break; 2038 2039 case EST_FETCHENTRY: 2040 again = ehci_state_fetchentry(ehci, async); 2041 break; 2042 2043 case EST_FETCHQH: 2044 q = ehci_state_fetchqh(ehci, async); 2045 if (q != NULL) { 2046 assert(q->async == async); 2047 again = 1; 2048 } else { 2049 again = 0; 2050 } 2051 break; 2052 2053 case EST_FETCHITD: 2054 again = ehci_state_fetchitd(ehci, async); 2055 itd_count++; 2056 break; 2057 2058 case EST_FETCHSITD: 2059 again = ehci_state_fetchsitd(ehci, async); 2060 itd_count++; 2061 break; 2062 2063 case EST_ADVANCEQUEUE: 2064 assert(q != NULL); 2065 again = ehci_state_advqueue(q); 2066 break; 2067 2068 case EST_FETCHQTD: 2069 assert(q != NULL); 2070 again = ehci_state_fetchqtd(q); 2071 break; 2072 2073 case EST_HORIZONTALQH: 2074 assert(q != NULL); 2075 again = ehci_state_horizqh(q); 2076 break; 2077 2078 case EST_EXECUTE: 2079 assert(q != NULL); 2080 again = ehci_state_execute(q); 2081 if (async) { 2082 ehci->async_stepdown = 0; 2083 } 2084 break; 2085 2086 case EST_EXECUTING: 2087 assert(q != NULL); 2088 if (async) { 2089 ehci->async_stepdown = 0; 2090 } 2091 again = ehci_state_executing(q); 2092 break; 2093 2094 case EST_WRITEBACK: 2095 assert(q != NULL); 2096 again = ehci_state_writeback(q); 2097 if (!async) { 2098 ehci->periodic_sched_active = PERIODIC_ACTIVE; 2099 } 2100 break; 2101 2102 default: 2103 fprintf(stderr, "Bad state!\n"); 2104 again = -1; 2105 g_assert_not_reached(); 2106 break; 2107 } 2108 2109 if (again < 0 || itd_count > 16) { 2110 /* TODO: notify guest (raise HSE irq?) */ 2111 fprintf(stderr, "processing error - resetting ehci HC\n"); 2112 ehci_reset(ehci); 2113 again = 0; 2114 } 2115 } 2116 while (again); 2117 } 2118 2119 static void ehci_advance_async_state(EHCIState *ehci) 2120 { 2121 const int async = 1; 2122 2123 switch(ehci_get_state(ehci, async)) { 2124 case EST_INACTIVE: 2125 if (!ehci_async_enabled(ehci)) { 2126 break; 2127 } 2128 ehci_set_state(ehci, async, EST_ACTIVE); 2129 // No break, fall through to ACTIVE 2130 2131 case EST_ACTIVE: 2132 if (!ehci_async_enabled(ehci)) { 2133 ehci_queues_rip_all(ehci, async); 2134 ehci_set_state(ehci, async, EST_INACTIVE); 2135 break; 2136 } 2137 2138 /* make sure guest has acknowledged the doorbell interrupt */ 2139 /* TO-DO: is this really needed? */ 2140 if (ehci->usbsts & USBSTS_IAA) { 2141 DPRINTF("IAA status bit still set.\n"); 2142 break; 2143 } 2144 2145 /* check that address register has been set */ 2146 if (ehci->asynclistaddr == 0) { 2147 break; 2148 } 2149 2150 ehci_set_state(ehci, async, EST_WAITLISTHEAD); 2151 ehci_advance_state(ehci, async); 2152 2153 /* If the doorbell is set, the guest wants to make a change to the 2154 * schedule. The host controller needs to release cached data. 2155 * (section 4.8.2) 2156 */ 2157 if (ehci->usbcmd & USBCMD_IAAD) { 2158 /* Remove all unseen qhs from the async qhs queue */ 2159 ehci_queues_rip_unseen(ehci, async); 2160 trace_usb_ehci_doorbell_ack(); 2161 ehci->usbcmd &= ~USBCMD_IAAD; 2162 ehci_raise_irq(ehci, USBSTS_IAA); 2163 } 2164 break; 2165 2166 default: 2167 /* this should only be due to a developer mistake */ 2168 fprintf(stderr, "ehci: Bad asynchronous state %d. " 2169 "Resetting to active\n", ehci->astate); 2170 g_assert_not_reached(); 2171 } 2172 } 2173 2174 static void ehci_advance_periodic_state(EHCIState *ehci) 2175 { 2176 uint32_t entry; 2177 uint32_t list; 2178 const int async = 0; 2179 2180 // 4.6 2181 2182 switch(ehci_get_state(ehci, async)) { 2183 case EST_INACTIVE: 2184 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { 2185 ehci_set_state(ehci, async, EST_ACTIVE); 2186 // No break, fall through to ACTIVE 2187 } else 2188 break; 2189 2190 case EST_ACTIVE: 2191 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) { 2192 ehci_queues_rip_all(ehci, async); 2193 ehci_set_state(ehci, async, EST_INACTIVE); 2194 break; 2195 } 2196 2197 list = ehci->periodiclistbase & 0xfffff000; 2198 /* check that register has been set */ 2199 if (list == 0) { 2200 break; 2201 } 2202 list |= ((ehci->frindex & 0x1ff8) >> 1); 2203 2204 if (get_dwords(ehci, list, &entry, 1) < 0) { 2205 break; 2206 } 2207 2208 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", 2209 ehci->frindex / 8, list, entry); 2210 ehci_set_fetch_addr(ehci, async,entry); 2211 ehci_set_state(ehci, async, EST_FETCHENTRY); 2212 ehci_advance_state(ehci, async); 2213 ehci_queues_rip_unused(ehci, async); 2214 break; 2215 2216 default: 2217 /* this should only be due to a developer mistake */ 2218 fprintf(stderr, "ehci: Bad periodic state %d. " 2219 "Resetting to active\n", ehci->pstate); 2220 g_assert_not_reached(); 2221 } 2222 } 2223 2224 static void ehci_update_frindex(EHCIState *ehci, int uframes) 2225 { 2226 if (!ehci_enabled(ehci) && ehci->pstate == EST_INACTIVE) { 2227 return; 2228 } 2229 2230 /* Generate FLR interrupt if frame index rolls over 0x2000 */ 2231 if ((ehci->frindex % 0x2000) + uframes >= 0x2000) { 2232 ehci_raise_irq(ehci, USBSTS_FLR); 2233 } 2234 2235 /* How many times will frindex roll over 0x4000 with this frame count? 2236 * usbsts_frindex is decremented by 0x4000 on rollover until it reaches 0 2237 */ 2238 int rollovers = (ehci->frindex + uframes) / 0x4000; 2239 if (rollovers > 0) { 2240 if (ehci->usbsts_frindex >= (rollovers * 0x4000)) { 2241 ehci->usbsts_frindex -= 0x4000 * rollovers; 2242 } else { 2243 ehci->usbsts_frindex = 0; 2244 } 2245 } 2246 2247 ehci->frindex = (ehci->frindex + uframes) % 0x4000; 2248 } 2249 2250 static void ehci_work_bh(void *opaque) 2251 { 2252 EHCIState *ehci = opaque; 2253 int need_timer = 0; 2254 int64_t expire_time, t_now; 2255 uint64_t ns_elapsed; 2256 uint64_t uframes, skipped_uframes; 2257 int i; 2258 2259 if (ehci->working) { 2260 return; 2261 } 2262 ehci->working = true; 2263 2264 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2265 ns_elapsed = t_now - ehci->last_run_ns; 2266 uframes = ns_elapsed / UFRAME_TIMER_NS; 2267 2268 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) { 2269 need_timer++; 2270 2271 if (uframes > (ehci->maxframes * 8)) { 2272 skipped_uframes = uframes - (ehci->maxframes * 8); 2273 ehci_update_frindex(ehci, skipped_uframes); 2274 ehci->last_run_ns += UFRAME_TIMER_NS * skipped_uframes; 2275 uframes -= skipped_uframes; 2276 DPRINTF("WARNING - EHCI skipped %d uframes\n", skipped_uframes); 2277 } 2278 2279 for (i = 0; i < uframes; i++) { 2280 /* 2281 * If we're running behind schedule, we should not catch up 2282 * too fast, as that will make some guests unhappy: 2283 * 1) We must process a minimum of MIN_UFR_PER_TICK frames, 2284 * otherwise we will never catch up 2285 * 2) Process frames until the guest has requested an irq (IOC) 2286 */ 2287 if (i >= MIN_UFR_PER_TICK) { 2288 ehci_commit_irq(ehci); 2289 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) { 2290 break; 2291 } 2292 } 2293 if (ehci->periodic_sched_active) { 2294 ehci->periodic_sched_active--; 2295 } 2296 ehci_update_frindex(ehci, 1); 2297 if ((ehci->frindex & 7) == 0) { 2298 ehci_advance_periodic_state(ehci); 2299 } 2300 ehci->last_run_ns += UFRAME_TIMER_NS; 2301 } 2302 } else { 2303 ehci->periodic_sched_active = 0; 2304 ehci_update_frindex(ehci, uframes); 2305 ehci->last_run_ns += UFRAME_TIMER_NS * uframes; 2306 } 2307 2308 if (ehci->periodic_sched_active) { 2309 ehci->async_stepdown = 0; 2310 } else if (ehci->async_stepdown < ehci->maxframes / 2) { 2311 ehci->async_stepdown++; 2312 } 2313 2314 /* Async is not inside loop since it executes everything it can once 2315 * called 2316 */ 2317 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) { 2318 need_timer++; 2319 ehci_advance_async_state(ehci); 2320 } 2321 2322 ehci_commit_irq(ehci); 2323 if (ehci->usbsts_pending) { 2324 need_timer++; 2325 ehci->async_stepdown = 0; 2326 } 2327 2328 if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) { 2329 need_timer++; 2330 } 2331 2332 if (need_timer) { 2333 /* If we've raised int, we speed up the timer, so that we quickly 2334 * notice any new packets queued up in response */ 2335 if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) { 2336 expire_time = t_now + 2337 NANOSECONDS_PER_SECOND / (FRAME_TIMER_FREQ * 4); 2338 ehci->int_req_by_async = false; 2339 } else { 2340 expire_time = t_now + (NANOSECONDS_PER_SECOND 2341 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ); 2342 } 2343 timer_mod(ehci->frame_timer, expire_time); 2344 } 2345 2346 ehci->working = false; 2347 } 2348 2349 static void ehci_work_timer(void *opaque) 2350 { 2351 EHCIState *ehci = opaque; 2352 2353 qemu_bh_schedule(ehci->async_bh); 2354 } 2355 2356 static const MemoryRegionOps ehci_mmio_caps_ops = { 2357 .read = ehci_caps_read, 2358 .write = ehci_caps_write, 2359 .valid.min_access_size = 1, 2360 .valid.max_access_size = 4, 2361 .impl.min_access_size = 1, 2362 .impl.max_access_size = 1, 2363 .endianness = DEVICE_LITTLE_ENDIAN, 2364 }; 2365 2366 static const MemoryRegionOps ehci_mmio_opreg_ops = { 2367 .read = ehci_opreg_read, 2368 .write = ehci_opreg_write, 2369 .valid.min_access_size = 4, 2370 .valid.max_access_size = 4, 2371 .endianness = DEVICE_LITTLE_ENDIAN, 2372 }; 2373 2374 static const MemoryRegionOps ehci_mmio_port_ops = { 2375 .read = ehci_port_read, 2376 .write = ehci_port_write, 2377 .valid.min_access_size = 4, 2378 .valid.max_access_size = 4, 2379 .endianness = DEVICE_LITTLE_ENDIAN, 2380 }; 2381 2382 static USBPortOps ehci_port_ops = { 2383 .attach = ehci_attach, 2384 .detach = ehci_detach, 2385 .child_detach = ehci_child_detach, 2386 .wakeup = ehci_wakeup, 2387 .complete = ehci_async_complete_packet, 2388 }; 2389 2390 static USBBusOps ehci_bus_ops_companion = { 2391 .register_companion = ehci_register_companion, 2392 .wakeup_endpoint = ehci_wakeup_endpoint, 2393 }; 2394 static USBBusOps ehci_bus_ops_standalone = { 2395 .wakeup_endpoint = ehci_wakeup_endpoint, 2396 }; 2397 2398 static int usb_ehci_pre_save(void *opaque) 2399 { 2400 EHCIState *ehci = opaque; 2401 uint32_t new_frindex; 2402 2403 /* Round down frindex to a multiple of 8 for migration compatibility */ 2404 new_frindex = ehci->frindex & ~7; 2405 ehci->last_run_ns -= (ehci->frindex - new_frindex) * UFRAME_TIMER_NS; 2406 ehci->frindex = new_frindex; 2407 2408 return 0; 2409 } 2410 2411 static int usb_ehci_post_load(void *opaque, int version_id) 2412 { 2413 EHCIState *s = opaque; 2414 int i; 2415 2416 for (i = 0; i < NB_PORTS; i++) { 2417 USBPort *companion = s->companion_ports[i]; 2418 if (companion == NULL) { 2419 continue; 2420 } 2421 if (s->portsc[i] & PORTSC_POWNER) { 2422 companion->dev = s->ports[i].dev; 2423 } else { 2424 companion->dev = NULL; 2425 } 2426 } 2427 2428 return 0; 2429 } 2430 2431 static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) 2432 { 2433 EHCIState *ehci = opaque; 2434 2435 /* 2436 * We don't migrate the EHCIQueue-s, instead we rebuild them for the 2437 * schedule in guest memory. We must do the rebuilt ASAP, so that 2438 * USB-devices which have async handled packages have a packet in the 2439 * ep queue to match the completion with. 2440 */ 2441 if (state == RUN_STATE_RUNNING) { 2442 ehci_advance_async_state(ehci); 2443 } 2444 2445 /* 2446 * The schedule rebuilt from guest memory could cause the migration dest 2447 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH 2448 * will never have existed on the destination. Therefor we must flush the 2449 * async schedule on savevm to catch any not yet noticed unlinks. 2450 */ 2451 if (state == RUN_STATE_SAVE_VM) { 2452 ehci_advance_async_state(ehci); 2453 ehci_queues_rip_unseen(ehci, 1); 2454 } 2455 } 2456 2457 const VMStateDescription vmstate_ehci = { 2458 .name = "ehci-core", 2459 .version_id = 2, 2460 .minimum_version_id = 1, 2461 .pre_save = usb_ehci_pre_save, 2462 .post_load = usb_ehci_post_load, 2463 .fields = (VMStateField[]) { 2464 /* mmio registers */ 2465 VMSTATE_UINT32(usbcmd, EHCIState), 2466 VMSTATE_UINT32(usbsts, EHCIState), 2467 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2), 2468 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2), 2469 VMSTATE_UINT32(usbintr, EHCIState), 2470 VMSTATE_UINT32(frindex, EHCIState), 2471 VMSTATE_UINT32(ctrldssegment, EHCIState), 2472 VMSTATE_UINT32(periodiclistbase, EHCIState), 2473 VMSTATE_UINT32(asynclistaddr, EHCIState), 2474 VMSTATE_UINT32(configflag, EHCIState), 2475 VMSTATE_UINT32(portsc[0], EHCIState), 2476 VMSTATE_UINT32(portsc[1], EHCIState), 2477 VMSTATE_UINT32(portsc[2], EHCIState), 2478 VMSTATE_UINT32(portsc[3], EHCIState), 2479 VMSTATE_UINT32(portsc[4], EHCIState), 2480 VMSTATE_UINT32(portsc[5], EHCIState), 2481 /* frame timer */ 2482 VMSTATE_TIMER_PTR(frame_timer, EHCIState), 2483 VMSTATE_UINT64(last_run_ns, EHCIState), 2484 VMSTATE_UINT32(async_stepdown, EHCIState), 2485 /* schedule state */ 2486 VMSTATE_UINT32(astate, EHCIState), 2487 VMSTATE_UINT32(pstate, EHCIState), 2488 VMSTATE_UINT32(a_fetch_addr, EHCIState), 2489 VMSTATE_UINT32(p_fetch_addr, EHCIState), 2490 VMSTATE_END_OF_LIST() 2491 } 2492 }; 2493 2494 void usb_ehci_realize(EHCIState *s, DeviceState *dev, Error **errp) 2495 { 2496 int i; 2497 2498 if (s->portnr > NB_PORTS) { 2499 error_setg(errp, "Too many ports! Max. port number is %d.", 2500 NB_PORTS); 2501 return; 2502 } 2503 if (s->maxframes < 8 || s->maxframes > 512) { 2504 error_setg(errp, "maxframes %d out if range (8 .. 512)", 2505 s->maxframes); 2506 return; 2507 } 2508 2509 usb_bus_new(&s->bus, sizeof(s->bus), s->companion_enable ? 2510 &ehci_bus_ops_companion : &ehci_bus_ops_standalone, dev); 2511 for (i = 0; i < s->portnr; i++) { 2512 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, 2513 USB_SPEED_MASK_HIGH); 2514 s->ports[i].dev = 0; 2515 } 2516 2517 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ehci_work_timer, s); 2518 s->async_bh = qemu_bh_new(ehci_work_bh, s); 2519 s->device = dev; 2520 2521 s->vmstate = qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s); 2522 } 2523 2524 void usb_ehci_unrealize(EHCIState *s, DeviceState *dev, Error **errp) 2525 { 2526 trace_usb_ehci_unrealize(); 2527 2528 if (s->frame_timer) { 2529 timer_del(s->frame_timer); 2530 timer_free(s->frame_timer); 2531 s->frame_timer = NULL; 2532 } 2533 if (s->async_bh) { 2534 qemu_bh_delete(s->async_bh); 2535 } 2536 2537 ehci_queues_rip_all(s, 0); 2538 ehci_queues_rip_all(s, 1); 2539 2540 memory_region_del_subregion(&s->mem, &s->mem_caps); 2541 memory_region_del_subregion(&s->mem, &s->mem_opreg); 2542 memory_region_del_subregion(&s->mem, &s->mem_ports); 2543 2544 usb_bus_release(&s->bus); 2545 2546 if (s->vmstate) { 2547 qemu_del_vm_change_state_handler(s->vmstate); 2548 } 2549 } 2550 2551 void usb_ehci_init(EHCIState *s, DeviceState *dev) 2552 { 2553 /* 2.2 host controller interface version */ 2554 s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase); 2555 s->caps[0x01] = 0x00; 2556 s->caps[0x02] = 0x00; 2557 s->caps[0x03] = 0x01; /* HC version */ 2558 s->caps[0x04] = s->portnr; /* Number of downstream ports */ 2559 s->caps[0x05] = 0x00; /* No companion ports at present */ 2560 s->caps[0x06] = 0x00; 2561 s->caps[0x07] = 0x00; 2562 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ 2563 s->caps[0x0a] = 0x00; 2564 s->caps[0x0b] = 0x00; 2565 2566 QTAILQ_INIT(&s->aqueues); 2567 QTAILQ_INIT(&s->pqueues); 2568 usb_packet_init(&s->ipacket); 2569 2570 memory_region_init(&s->mem, OBJECT(dev), "ehci", MMIO_SIZE); 2571 memory_region_init_io(&s->mem_caps, OBJECT(dev), &ehci_mmio_caps_ops, s, 2572 "capabilities", CAPA_SIZE); 2573 memory_region_init_io(&s->mem_opreg, OBJECT(dev), &ehci_mmio_opreg_ops, s, 2574 "operational", s->portscbase); 2575 memory_region_init_io(&s->mem_ports, OBJECT(dev), &ehci_mmio_port_ops, s, 2576 "ports", 4 * s->portnr); 2577 2578 memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); 2579 memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); 2580 memory_region_add_subregion(&s->mem, s->opregbase + s->portscbase, 2581 &s->mem_ports); 2582 } 2583 2584 void usb_ehci_finalize(EHCIState *s) 2585 { 2586 usb_packet_cleanup(&s->ipacket); 2587 } 2588 2589 /* 2590 * vim: expandtab ts=4 2591 */ 2592